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Searched refs:ADC_IPDR_ID_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h4860 #define ADC_IPDR_ID_Pos (0U) macro
4861 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
4863 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
4864 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
4865 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
4866 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
4867 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
4868 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
4869 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
4870 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
[all …]
Dstm32mp151fxx_cm4.h4878 #define ADC_IPDR_ID_Pos (0U) macro
4879 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
4881 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
4882 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
4883 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
4884 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
4885 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
4886 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
4887 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
4888 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
[all …]
Dstm32mp151axx_ca7.h4860 #define ADC_IPDR_ID_Pos (0U) macro
4861 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
4863 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
4864 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
4865 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
4866 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
4867 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
4868 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
4869 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
4870 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
[all …]
Dstm32mp151axx_cm4.h4826 #define ADC_IPDR_ID_Pos (0U) macro
4827 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
4829 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
4830 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
4831 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
4832 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
4833 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
4834 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
4835 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
4836 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
[all …]
Dstm32mp151dxx_cm4.h4826 #define ADC_IPDR_ID_Pos (0U) macro
4827 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
4829 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
4830 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
4831 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
4832 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
4833 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
4834 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
4835 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
4836 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
[all …]
Dstm32mp151cxx_ca7.h4912 #define ADC_IPDR_ID_Pos (0U) macro
4913 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
4915 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
4916 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
4917 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
4918 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
4919 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
4920 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
4921 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
4922 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
[all …]
Dstm32mp151cxx_cm4.h4878 #define ADC_IPDR_ID_Pos (0U) macro
4879 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
4881 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
4882 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
4883 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
4884 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
4885 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
4886 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
4887 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
4888 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
[all …]
Dstm32mp151fxx_ca7.h4912 #define ADC_IPDR_ID_Pos (0U) macro
4913 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
4915 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
4916 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
4917 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
4918 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
4919 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
4920 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
4921 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
4922 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
[all …]
Dstm32mp153axx_ca7.h4970 #define ADC_IPDR_ID_Pos (0U) macro
4971 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
4973 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
4974 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
4975 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
4976 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
4977 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
4978 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
4979 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
4980 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
[all …]
Dstm32mp153axx_cm4.h4936 #define ADC_IPDR_ID_Pos (0U) macro
4937 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
4939 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
4940 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
4941 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
4942 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
4943 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
4944 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
4945 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
4946 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
[all …]
Dstm32mp153cxx_ca7.h5022 #define ADC_IPDR_ID_Pos (0U) macro
5023 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
5025 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
5026 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
5027 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
5028 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
5029 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
5030 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
5031 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
5032 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
[all …]
Dstm32mp153cxx_cm4.h4988 #define ADC_IPDR_ID_Pos (0U) macro
4989 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
4991 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
4992 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
4993 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
4994 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
4995 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
4996 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
4997 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
4998 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
[all …]
Dstm32mp153dxx_ca7.h4970 #define ADC_IPDR_ID_Pos (0U) macro
4971 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
4973 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
4974 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
4975 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
4976 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
4977 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
4978 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
4979 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
4980 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
[all …]
Dstm32mp153dxx_cm4.h4936 #define ADC_IPDR_ID_Pos (0U) macro
4937 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
4939 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
4940 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
4941 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
4942 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
4943 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
4944 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
4945 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
4946 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
[all …]
Dstm32mp153fxx_ca7.h5022 #define ADC_IPDR_ID_Pos (0U) macro
5023 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
5025 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
5026 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
5027 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
5028 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
5029 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
5030 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
5031 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
5032 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
[all …]
Dstm32mp153fxx_cm4.h4988 #define ADC_IPDR_ID_Pos (0U) macro
4989 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
4991 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
4992 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
4993 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
4994 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
4995 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
4996 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
4997 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
4998 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
[all …]
Dstm32mp157axx_ca7.h5085 #define ADC_IPDR_ID_Pos (0U) macro
5086 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
5088 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
5089 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
5090 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
5091 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
5092 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
5093 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
5094 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
5095 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
[all …]
Dstm32mp157axx_cm4.h5051 #define ADC_IPDR_ID_Pos (0U) macro
5052 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
5054 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
5055 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
5056 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
5057 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
5058 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
5059 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
5060 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
5061 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
[all …]
Dstm32mp157cxx_ca7.h5137 #define ADC_IPDR_ID_Pos (0U) macro
5138 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
5140 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
5141 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
5142 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
5143 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
5144 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
5145 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
5146 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
5147 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
[all …]
Dstm32mp157cxx_cm4.h5103 #define ADC_IPDR_ID_Pos (0U) macro
5104 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
5106 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
5107 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
5108 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
5109 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
5110 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
5111 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
5112 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
5113 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
[all …]
Dstm32mp157dxx_ca7.h5085 #define ADC_IPDR_ID_Pos (0U) macro
5086 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
5088 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
5089 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
5090 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
5091 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
5092 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
5093 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
5094 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
5095 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
[all …]
Dstm32mp157dxx_cm4.h5051 #define ADC_IPDR_ID_Pos (0U) macro
5052 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
5054 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
5055 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
5056 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
5057 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
5058 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
5059 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
5060 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
5061 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
[all …]
Dstm32mp157fxx_ca7.h5137 #define ADC_IPDR_ID_Pos (0U) macro
5138 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
5140 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
5141 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
5142 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
5143 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
5144 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
5145 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
5146 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
5147 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
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Dstm32mp157fxx_cm4.h5103 #define ADC_IPDR_ID_Pos (0U) macro
5104 #define ADC_IPDR_ID_Msk (0xFFFFFFFFUL << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */
5106 #define ADC_IPDR_ID_0 (0x1UL << ADC_IPDR_ID_Pos) /*!< 0x00000001 */
5107 #define ADC_IPDR_ID_1 (0x2UL << ADC_IPDR_ID_Pos) /*!< 0x00000002 */
5108 #define ADC_IPDR_ID_2 (0x4UL << ADC_IPDR_ID_Pos) /*!< 0x00000004 */
5109 #define ADC_IPDR_ID_3 (0x8UL << ADC_IPDR_ID_Pos) /*!< 0x00000008 */
5110 #define ADC_IPDR_ID_4 (0x10UL << ADC_IPDR_ID_Pos) /*!< 0x00000010 */
5111 #define ADC_IPDR_ID_5 (0x20UL << ADC_IPDR_ID_Pos) /*!< 0x00000020 */
5112 #define ADC_IPDR_ID_6 (0x40UL << ADC_IPDR_ID_Pos) /*!< 0x00000040 */
5113 #define ADC_IPDR_ID_7 (0x80UL << ADC_IPDR_ID_Pos) /*!< 0x00000080 */
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