1 /** 2 ****************************************************************************** 3 * @file stm32n6xx_hal_adc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32N6xx_HAL_ADC_EX_H 21 #define STM32N6xx_HAL_ADC_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32n6xx_hal_def.h" 29 30 /** @addtogroup STM32N6xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup ADCEx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief ADC Injected Conversion Oversampling structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Ratio; /*!< Configures the oversampling ratio. 49 This parameter can be a value from 1 to 1024 */ 50 51 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 52 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 53 } ADC_InjOversamplingTypeDef; 54 55 /** 56 * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected 57 * @note Parameters of this structure are shared within 2 scopes: 58 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, 59 * InjectedOffsetNumber, InjectedOffset 60 * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, 61 * InjectedDiscontinuousConvMode, AutoInjectedConv, ExternalTrigInjecConv, 62 * ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling. 63 * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. 64 * ADC state can be either: 65 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 66 * 'InjectedSingleDiff') 67 * - For parameters 'InjectedDiscontinuousConvMode', 'InjecOversampling': 68 * ADC enabled without conversion on going on injected group. 69 * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': 70 * ADC enabled without conversion on going on regular and injected groups. 71 * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 72 * 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going on ADC groups 73 * regular and injected. 74 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 75 * without error reporting (as it can be the expected behavior in case of intended action to update another 76 * parameter (which fulfills the ADC state condition) on the fly). 77 */ 78 typedef struct 79 { 80 uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. 81 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 82 Note: Depending on devices and ADC instances, some channels may not be 83 available on device package pins. Refer to device datasheet for 84 channels availability. */ 85 86 uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. 87 This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. 88 Note: to disable a channel or change order of conversion sequencer, 89 rank containing a previous channel setting can be overwritten by 90 the new channel setting (or parameter number of conversions 91 adjusted) */ 92 93 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. 94 Unit: ADC clock cycles. 95 Conversion time is the addition of sampling time and processing time 96 (13.5 ADC clock cycles at ADC resolution 12 bits, 11.5 cycles at 10 bits, 97 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 98 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. 99 Caution: This parameter applies to a channel that can be used in a 100 regular and/or injected group. 101 It overwrites the last setting. 102 Note: In case of usage of internal measurement channels 103 (VrefInt/Vbat/TempSensor), sampling time constraints must be 104 respected (sampling time can be adjusted in function of ADC clock 105 frequency and sampling time setting); 106 Refer to device datasheet for timings values. */ 107 uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. 108 In differential mode: Differential measurement is carried out between 109 the selected channel (positive input) and 110 another channel (negative input). Refer to 111 reference manual for corresponding channel. 112 Only channel of positive input has to be 113 configured, the other channel is configured 114 automatically. 115 This parameter must be a value of: 116 @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. 117 Caution: This parameter applies to a channel that can be used in a 118 regular and/or injected group. It overwrites the last setting. 119 Note: Refer to Reference Manual to ensure the selected channel is 120 available in differential mode. 121 Note: This parameter must be modified when ADC is disabled (before ADC 122 start conversion or after ADC stop conversion). 123 If ADC is enabled, this parameter setting is bypassed without error 124 reporting (as it can be the expected behavior in case of another 125 parameter update on the fly) */ 126 127 uint32_t InjectedOffsetNumber; /*!< Selects the offset number. 128 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB. 129 Caution: Only one offset is allowed per channel. This parameter 130 overwrites the last setting. */ 131 132 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data. 133 Offset value must be a positive number. 134 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this 135 parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 136 0x3FF, 0xFF or 0x3F respectively. 137 Note: This parameter must be modified when no conversion is on going on 138 both regular and injected groups (ADC disabled, or ADC enabled 139 without continuous mode or external trigger that could launch a 140 conversion). */ 141 142 FunctionalState InjectedOffsetSignedSaturation; /*!< Specifies whether the Signed saturation feature is used or not. 143 This parameter is applied only for 14-bit or 8-bit resolution. 144 This parameter can be set to ENABLE or DISABLE. */ 145 146 uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added 147 (positive sign) from or to the raw converted data. 148 This parameter can be a value of @ref ADCEx_OffsetSign. 149 Note: 150 - This parameter must be modified when no conversion is on going on 151 both regular and injected groups (ADC disabled or ADC enabled without 152 continuous mode or external trigger that could launch a conversion). 153 - This parameter is specific to ADC1 only. */ 154 155 FunctionalState InjectedOffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. 156 This parameter value can be ENABLE or DISABLE. 157 Note: This parameter must be modified when no conversion is on going 158 on both regular and injected groups (ADC disabled, or ADC enabled 159 without continuous mode or external trigger that could launch 160 a conversion). */ 161 162 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within 163 the ADC group injected sequencer. 164 To use the injected group sequencer and convert several ranks, 165 parameter 'ScanConvMode' must be enabled. 166 This parameter must be a number between Min_Data = 1 and Max_Data = 4. 167 Caution: this setting impacts the entire injected group. 168 Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 169 configure a channel on injected group can impact the 170 configuration of other channels previously set. */ 171 172 FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected 173 is performed in Complete-sequence/Discontinuous-sequence 174 (main sequence subdivided in successive parts). 175 Discontinuous mode is used only if sequencer is enabled 176 (parameter 'ScanConvMode'). 177 If sequencer is disabled, this parameter is discarded. 178 Discontinuous mode can be enabled only if continuous 179 mode is disabled. 180 This parameter can be set to ENABLE or DISABLE. 181 Note: This parameter must be modified when ADC is disabled 182 (before ADC start conversion or after ADC stop conversion). 183 Note: For injected group, discontinuous mode converts the 184 sequence channel by channel (discontinuous length 185 fixed to 1 rank). 186 Caution: this setting impacts the entire injected group. 187 Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 188 configure a channel on injected group can impact the 189 configuration of other channels previously set. */ 190 191 FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion 192 after regular one 193 This parameter can be set to ENABLE or DISABLE. 194 Note: To use Automatic injected conversion, discontinuous mode must be 195 disabled ('DiscontinuousConvMode' and 196 'InjectedDiscontinuousConvMode' set to DISABLE) 197 Note: To use Automatic injected conversion, injected group external 198 triggers must be disabled ('ExternalTrigInjecConv' set to 199 ADC_INJECTED_SOFTWARE_START) 200 Note: In case of DMA used with regular group: if DMA configured in normal 201 mode (single shot) JAUTO will be stopped upon DMA transfer 202 complete. To maintain JAUTO always enabled, 203 DMA must be configured in circular mode. 204 Caution: this setting impacts the entire injected group. 205 Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 206 configure a channel on injected group can impact the 207 configuration of other channels previously set. */ 208 209 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of 210 injected group. 211 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled 212 and software trigger is used instead. 213 This parameter can be a value of 214 @ref ADC_injected_external_trigger_source. 215 Caution: this setting impacts the entire injected group. Therefore, 216 call of HAL_ADCEx_InjectedConfigChannel() to configure a channel 217 on injected group can impact the configuration of other channels 218 previously set. */ 219 220 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. 221 This parameter can be a value of @ref ADC_injected_external_trigger_edge. 222 If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter 223 is discarded. 224 Caution: this setting impacts the entire injected group. Therefore, 225 call of HAL_ADCEx_InjectedConfigChannel() to configure a 226 channel on injected group can impact the configuration of other 227 channels previously set. */ 228 229 FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. 230 This parameter can be set to ENABLE or DISABLE. 231 Note: This parameter can be modified only if there is no conversion 232 is ongoing (both ADSTART and JADSTART cleared). */ 233 234 ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. 235 Caution: this setting overwrites the previous oversampling 236 configuration if oversampling already enabled. 237 Note: This parameter can be modified only if there is no 238 conversion is ongoing (both ADSTART and 239 JADSTART cleared).*/ 240 } ADC_InjectionConfTypeDef; 241 242 #if defined(ADC_MULTIMODE_SUPPORT) 243 /** 244 * @brief Structure definition of ADC multimode 245 * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs 246 * state (both Master and Slave ADCs). 247 * Both Master and Slave ADCs must be disabled. 248 */ 249 typedef struct 250 { 251 uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. 252 This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ 253 254 uint32_t DualModeData; /*!< Configures the Dual ADC Mode Data Format: 255 This parameter can be a value of @ref ADCEx_Dual_Mode_Data_Format */ 256 257 uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. 258 This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY */ 259 } ADC_MultiModeTypeDef; 260 #endif /* ADC_MULTIMODE_SUPPORT */ 261 262 /** 263 * @} 264 */ 265 266 /* Exported constants --------------------------------------------------------*/ 267 268 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants 269 * @{ 270 */ 271 272 /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source 273 * @{ 274 */ 275 /* ADC group regular trigger sources for all ADC instances */ 276 #define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< ADC group injected conversion 277 trigger internal: SW start. */ 278 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion 279 trigger from external peripheral: external interrupt line 15. */ 280 #define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion 281 trigger from external peripheral: TIM1 channel 4 event (capture compare). */ 282 #define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion 283 trigger from external peripheral: TIM1 TRGO event. */ 284 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion 285 trigger from external peripheral: TIM1 TRGO2 event. */ 286 #define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion 287 trigger from external peripheral: TIM2 channel 1 event (capture compare). */ 288 #define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion 289 trigger from external peripheral: TIM2 TRGO event. */ 290 #define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion 291 trigger from external peripheral: TIM3 channel 1 event (capture compare). */ 292 #define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion 293 trigger from external peripheral: TIM3 channel 3 event (capture compare). */ 294 #define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion 295 trigger from external peripheral: TIM3 channel 4 event (capture compare). */ 296 #define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion 297 trigger from external peripheral: TIM3 TRGO event. */ 298 #define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion 299 trigger from external peripheral: TIM4 TRGO event. */ 300 #define ADC_EXTERNALTRIGINJEC_T5_TRGO (LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) /*!< ADC group injected conversion 301 trigger from external peripheral: TIM5 TRGO event. */ 302 #define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion 303 trigger from external peripheral: TIM6 TRGO event. */ 304 #define ADC_EXTERNALTRIGINJEC_T7_TRGO (LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) /*!< ADC group injected conversion 305 trigger from external peripheral: TIM7 TRGO event. */ 306 #define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion 307 trigger from external peripheral: TIM8 TRGO event. */ 308 #define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion 309 trigger from external peripheral: TIM8 TRGO2 event. */ 310 #define ADC_EXTERNALTRIGINJEC_T9_CC2 (LL_ADC_INJ_TRIG_EXT_TIM9_CH2) /*!< ADC group injected conversion 311 trigger from external peripheral: TIM9 channel 2 event (capture compare). */ 312 #define ADC_EXTERNALTRIGINJEC_T9_TRGO (LL_ADC_INJ_TRIG_EXT_TIM9_TRGO) /*!< ADC group injected conversion 313 trigger from external peripheral: TIM9 TRGO event. */ 314 #define ADC_EXTERNALTRIGINJEC_T12_TRGO (LL_ADC_INJ_TRIG_EXT_TIM12_TRGO) /*!< ADC group injected conversion 315 trigger from external peripheral: TIM12 TRGO event. */ 316 #define ADC_EXTERNALTRIGINJEC_T12_CC4 (LL_ADC_INJ_TRIG_EXT_TIM12_CH4) /*!< ADC group injected conversion 317 trigger from external peripheral: TIM12 channel 4 event (capture compare). */ 318 #define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion 319 trigger from external peripheral: TIM12 TRGO event. */ 320 #define ADC_EXTERNALTRIGINJEC_T18_TRGO (LL_ADC_INJ_TRIG_EXT_TIM18_TRGO) /*!< ADC group injected conversion 321 trigger from external peripheral: TIM12 TRGO event. */ 322 #define ADC_EXTERNALTRIGINJEC_LPTIM1_CH2 (LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2) /*!< ADC group injected conversion 323 trigger from external peripheral: LPTIM1 channel 2 event. */ 324 #define ADC_EXTERNALTRIGINJEC_LPTIM2_CH2 (LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2) /*!< ADC group injected conversion 325 trigger from external peripheral: LPTIM2 channel 2 event. */ 326 #define ADC_EXTERNALTRIGINJEC_LPTIM3_CH2 (LL_ADC_INJ_TRIG_EXT_LPTIM3_CH2) /*!< ADC group injected conversion 327 trigger from external peripheral: LPTIM3 channel 2 event. */ 328 /** 329 * @} 330 */ 331 332 /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) 333 * @{ 334 */ 335 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions trigger 336 disabled (SW start)*/ 337 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions trigger 338 polarity set to rising edge */ 339 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions trigger 340 polarity set to falling edge */ 341 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions trigger 342 polarity set to both rising and falling edges */ 343 /** 344 * @} 345 */ 346 347 /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending 348 * @{ 349 */ 350 #define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended */ 351 #define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential */ 352 /** 353 * @} 354 */ 355 356 /** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number 357 * @{ 358 */ 359 #define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected 360 ADC channel */ 361 #define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which 362 the offset programmed will be applied (independently of channel mapped 363 on ADC group regular or group injected) */ 364 #define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which 365 the offset programmed will be applied (independently of channel mapped 366 on ADC group regular or group injected) */ 367 #define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which 368 the offset programmed will be applied (independently of channel mapped 369 on ADC group regular or group injected) */ 370 #define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which 371 the offset programmed will be applied (independently of channel mapped 372 on ADC group regular or group injected) */ 373 /** 374 * @} 375 */ 376 377 /** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign 378 * @{ 379 */ 380 #define ADC_OFFSET_SIGN_NEGATIVE LL_ADC_OFFSET_SIGN_NEGATIVE /*!< Offset sign negative, offset is subtracted */ 381 #define ADC_OFFSET_SIGN_POSITIVE LL_ADC_OFFSET_SIGN_POSITIVE /*!< Offset sign positive, offset is added */ 382 /** 383 * @} 384 */ 385 386 /** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks 387 * @{ 388 */ 389 #define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ 390 #define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */ 391 #define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */ 392 #define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */ 393 /** 394 * @} 395 */ 396 397 #if defined(ADC_MULTIMODE_SUPPORT) 398 /** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode 399 * @{ 400 */ 401 #define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled 402 (ADC independent mode) */ 403 #define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular 404 simultaneous */ 405 #define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined 406 group regular interleaved */ 407 #define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group 408 injected simultaneous */ 409 #define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group 410 injected alternate trigger. Works only with external triggers (not internal 411 SW start) */ 412 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined 413 group regular simultaneous + group injected simultaneous */ 414 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined 415 group regular simultaneous + group injected alternate trigger */ 416 #define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined 417 group regular interleaved + group injected simultaneous */ 418 /** 419 * @} 420 */ 421 422 /** @defgroup ADCEx_Dual_Mode_Data_Format ADC Extended Dual Mode Data Formatting 423 * @{ 424 */ 425 426 #define ADC_DUALMODEDATAFORMAT_DISABLED (LL_ADC_MULTI_REG_DATA_EACH_ADC) /*!< ADC multimode group regular data 427 format: conversion data in data register of each ADC instance. 428 If ADC data transfer by DMA is used: each ADC uses its own DMA channel, 429 with its individual DMA transfer settings. */ 430 #define ADC_DUALMODEDATAFORMAT_32_BIT (LL_ADC_MULTI_REG_DATA_COMMON_32B) /*!< ADC multimode group regular data 431 format: conversion data in two ADC common instance data registers (CDR, CDR2) 432 with packing option on 32 bit. In register CDR, data packing on 32 bit: 433 ADC master and slave data are concatenated (data master in [15; 0], 434 data slave in [31; 16]), therefore data width must be lower than 16 bit 435 (even with ADC resolution 12 bit, higher width reachable by post processing: 436 oversampling, offset, ...). In register CDR2, data of master and slave are 437 alternatively set in full register width 32 bit, therefore no constraint on 438 data width. In case of usage with DMA, CDR generate ones transfer request 439 and CDR2 two transfer requests per conversion. */ 440 #define ADC_DUALMODEDATAFORMAT_8_BIT (LL_ADC_MULTI_REG_DATA_COMMON_16B) /*!< ADC multimode group regular data 441 format: conversion data in two ADC common instance data registers (CDR, CDR2) 442 with packing option on 16 bit. In register CDR, data packing on 16 bit: 443 ADC master and slave data are concatenated (data master in [7; 0], 444 data slave in [15; 8]), therefore data width must be lower than 8 bit 445 (even with ADC resolution 8 bit, higher width reachable by post processing: 446 oversampling, offset, ...). In register CDR2, data of master and slave are 447 alternatively set in full register width 32 bit, therefore no constraint on 448 data width. In case of usage with DMA, CDR generate ones transfer request 449 and CDR2 two transfer requests per conversion. */ 450 451 /* Legacy literals */ 452 #define ADC_DUALMODEDATAFORMAT_32_10_BITS ADC_DUALMODEDATAFORMAT_32_BIT 453 #define ADC_DUALMODEDATAFORMAT_8_BITS ADC_DUALMODEDATAFORMAT_8_BIT 454 /** 455 * @} 456 */ 457 458 /** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases 459 * @{ 460 */ 461 #define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two 462 sampling phases: 1 ADC clock cycle */ 463 #define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two 464 sampling phases: 2 ADC clock cycles */ 465 #define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two 466 sampling phases: 3 ADC clock cycles */ 467 #define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two 468 sampling phases: 4 ADC clock cycles */ 469 #define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two 470 sampling phases: 5 ADC clock cycles */ 471 #define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two 472 sampling phases: 6 ADC clock cycles */ 473 #define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two 474 sampling phases: 7 ADC clock cycles */ 475 #define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two 476 sampling phases: 8 ADC clock cycles */ 477 #define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two 478 sampling phases: 9 ADC clock cycles */ 479 #define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two 480 sampling phases: 10 ADC clock cycles */ 481 #define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two 482 sampling phases: 11 ADC clock cycles */ 483 #define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two 484 sampling phases: 12 ADC clock cycles */ 485 #define ADC_TWOSAMPLINGDELAY_13CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) /*!< ADC multimode delay between two 486 sampling phases: 13 ADC clock cycles */ 487 /** 488 * @} 489 */ 490 491 #endif /* ADC_MULTIMODE_SUPPORT */ 492 493 /** 494 * @} 495 */ 496 497 /** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups 498 * @{ 499 */ 500 #define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on 501 all STM32 devices) */ 502 #define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on 503 all STM32 devices) */ 504 #define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ 505 /** 506 * @} 507 */ 508 509 /** @defgroup ADC_CFGR1_fields ADCx CFGR fields 510 * @{ 511 */ 512 #define ADC_CFGR1_FIELDS (ADC_CFGR1_AWD1CH | ADC_CFGR1_JAUTO | ADC_CFGR1_JAWD1EN |\ 513 ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | \ 514 ADC_CFGR1_JDISCEN | ADC_CFGR1_DISCNUM | ADC_CFGR1_DISCEN |\ 515 ADC_CFGR1_AUTDLY | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD |\ 516 ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN |\ 517 ADC_CFGR1_RES | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN ) 518 /** 519 * @} 520 */ 521 522 /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields 523 * @{ 524 */ 525 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 526 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 527 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 528 ADC_SMPR1_SMP0) 529 /** 530 * @} 531 */ 532 533 /** @defgroup ADC_CFGR1_fields_2 ADCx CFGR sub fields 534 * @{ 535 */ 536 /* ADC_CFGR1 fields of parameters that can be updated when no conversion 537 (neither regular nor injected) is on-going */ 538 #define ADC_CFGR1_FIELDS_2 ((uint32_t)(ADC_CFGR1_DMNGT | ADC_CFGR1_AUTDLY)) 539 540 /** 541 * @} 542 */ 543 544 /* Exported macros -----------------------------------------------------------*/ 545 546 /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros 547 * @{ 548 */ 549 #if defined(ADC_MULTIMODE_SUPPORT) 550 551 /** @brief Force ADC instance in multimode mode independent (multimode disable). 552 * @note This macro must be used only in case of transition from multimode 553 * to mode independent and in case of unknown previous state, 554 * to ensure ADC configuration is in mode independent. 555 * @note Standard way of multimode configuration change is done from 556 * HAL ADC handle of ADC master using function 557 * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )". 558 * Usage of this macro is not the Standard way of multimode 559 * configuration and can lead to have HAL ADC handles status 560 * misaligned. Usage of this macro must be limited to cases 561 * mentioned above. 562 * @param __HANDLE__ ADC handle. 563 * @retval None 564 */ 565 #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \ 566 LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT) 567 568 #endif /* ADC_MULTIMODE_SUPPORT */ 569 570 /** 571 * @brief Helper macro to determine the selected channel corresponding 572 * negative input on the ADC instance selected. 573 * @param __HANDLE__ ADC handle. 574 * @param __CHANNEL__ This parameter can be one of the following values: 575 * @arg @ref ADC_CHANNEL_0 576 * @arg @ref ADC_CHANNEL_1 577 * @arg @ref ADC_CHANNEL_2 578 * @arg @ref ADC_CHANNEL_3 579 * @arg @ref ADC_CHANNEL_4 580 * @arg @ref ADC_CHANNEL_5 581 * @arg @ref ADC_CHANNEL_6 582 * @arg @ref ADC_CHANNEL_7 583 * @arg @ref ADC_CHANNEL_8 584 * @arg @ref ADC_CHANNEL_9 585 * @arg @ref ADC_CHANNEL_10 586 * @arg @ref ADC_CHANNEL_11 587 * @arg @ref ADC_CHANNEL_12 588 * @arg @ref ADC_CHANNEL_13 589 * @arg @ref ADC_CHANNEL_14 590 * @arg @ref ADC_CHANNEL_15 591 * @arg @ref ADC_CHANNEL_16 592 * @arg @ref ADC_CHANNEL_17 593 * @arg @ref ADC_CHANNEL_18 594 * @arg @ref ADC_CHANNEL_19 595 * @arg @ref ADC_CHANNEL_VREFINT (1)(4) 596 * @arg @ref ADC_CHANNEL_VBAT (2)(4) 597 * @arg @ref ADC_CHANNEL_VDDCORE (2)(4) 598 * 599 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n 600 * (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n 601 * @retval Returned value can be one of the following values: 602 * @arg @ref ADC_CHANNEL_0 603 * @arg @ref ADC_CHANNEL_1 604 * @arg @ref ADC_CHANNEL_2 605 * @arg @ref ADC_CHANNEL_3 606 * @arg @ref ADC_CHANNEL_4 607 * @arg @ref ADC_CHANNEL_5 608 * @arg @ref ADC_CHANNEL_6 609 * @arg @ref ADC_CHANNEL_7 610 * @arg @ref ADC_CHANNEL_8 611 * @arg @ref ADC_CHANNEL_9 612 * @arg @ref ADC_CHANNEL_10 613 * @arg @ref ADC_CHANNEL_11 614 * @arg @ref ADC_CHANNEL_12 615 * @arg @ref ADC_CHANNEL_13 616 * @arg @ref ADC_CHANNEL_14 617 * @arg @ref ADC_CHANNEL_15 618 * @arg @ref ADC_CHANNEL_16 619 * @arg @ref ADC_CHANNEL_17 620 * @arg @ref ADC_CHANNEL_18 621 * @arg @ref ADC_CHANNEL_19 622 * @arg @ref ADC_CHANNEL_VREFINT (1)(3) 623 * @arg @ref ADC_CHANNEL_VBAT (2)(3) 624 * @arg @ref ADC_CHANNEL_VDDCORE (2)(3) 625 * 626 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n 627 * (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n 628 * (3) For ADC channel read back from ADC register, 629 * comparison with internal channel parameter to be done 630 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 631 */ 632 #define __HAL_ADC_CHANNEL_DIFF_NEG_INPUT(__HANDLE__, __CHANNEL__) \ 633 ((IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) != 0UL) \ 634 ? __LL_ADC_CHANNEL_DIFF_NEG_INPUT((__HANDLE__)->Instance, __CHANNEL__) \ 635 : (ADC_CHANNEL_NONE) \ 636 ) 637 /** 638 * @} 639 */ 640 641 /* Private macros ------------------------------------------------------------*/ 642 643 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros 644 * @{ 645 */ 646 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 647 /* code of final user. */ 648 649 /** 650 * @brief Test if conversion trigger of injected group is software start 651 * or external trigger. 652 * @param __HANDLE__ ADC handle. 653 * @retval SET (software start) or RESET (external trigger). 654 */ 655 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 656 (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL) 657 658 /** 659 * @brief Check if conversion is on going on regular or injected groups. 660 * @param __HANDLE__ ADC handle. 661 * @retval SET (conversion is on going) or RESET (no conversion is on going). 662 */ 663 #define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \ 664 (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == 0UL \ 665 ) ? RESET : SET) 666 667 /** 668 * @brief Check if conversion is on going on injected group. 669 * @param __HANDLE__ ADC handle. 670 * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going) 671 */ 672 #define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \ 673 (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance)) 674 675 /** 676 * @brief Check whether or not ADC is independent. 677 * @param __HANDLE__ ADC handle. 678 * @note When multimode feature is not available, the macro always returns SET. 679 * @retval SET (ADC is independent) or RESET (ADC is not). 680 */ 681 #define ADC_IS_INDEPENDENT(__HANDLE__) \ 682 ( ( ( ((__HANDLE__)->Instance) == ADC3) \ 683 )? \ 684 SET \ 685 : \ 686 RESET \ 687 ) 688 689 /** 690 * @brief Set the selected injected Channel rank. 691 * @param __CHANNELNB__ Channel number. 692 * @param __RANKNB__ Rank number. 693 * @retval None 694 */ 695 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) (((__CHANNELNB__)& ADC_CHANNEL_NUMBER_MASK) \ 696 << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) 697 698 699 /** 700 * @brief Configure ADC discontinuous conversion mode for injected group 701 * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode. 702 * @retval None 703 */ 704 #define ADC_CFGR1_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__)\ 705 ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR1_JDISCEN_Pos) 706 707 /** 708 * @brief Configure ADC discontinuous conversion mode for regular group 709 * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode. 710 * @retval None 711 */ 712 #define ADC_CFGR1_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR1_DISCEN_Pos) 713 714 /** 715 * @brief Configure the number of discontinuous conversions for regular group. 716 * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. 717 * @retval None 718 */ 719 #define ADC_CFGR1_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__)\ 720 (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR1_DISCNUM_Pos) 721 722 /** 723 * @brief Configure the ADC auto delay mode. 724 * @param __AUTDLY__ Auto delay bit enable or disable. 725 * @retval None 726 */ 727 #define ADC_CFGR1_AUTODELAY(__AUTDLY__) ((__AUTDLY__) << ADC_CFGR1_AUTDLY_Pos) 728 729 /** 730 * @brief Configure ADC continuous conversion mode. 731 * @param __CONTINUOUS_MODE__ Continuous mode. 732 * @retval None 733 */ 734 #define ADC_CFGR1_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR1_CONT_Pos) 735 736 /** 737 * @brief Enable the ADC DMA continuous request. 738 * @param __DMACONTREQ_MODE__: DMA continuous request mode. 739 * @retval None 740 */ 741 #define ADC_CFGR1_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__)) 742 743 /** 744 * @brief Configure the channel number into offset OFRx register. 745 * @param __CHANNEL__ ADC Channel. 746 * @retval None 747 */ 748 #define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFCFGR1_OFFSET1_CH_Pos) 749 750 /** 751 * @brief Configure the channel number into differential mode selection register. 752 * @param __CHANNEL__ ADC Channel. 753 * @retval None 754 */ 755 #define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__)) 756 757 /** 758 * @brief Configure calibration factor in differential mode to be set into calibration register. 759 * @param __CALIBRATION_FACTOR__ Calibration factor value. 760 * @retval None 761 */ 762 #define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__)\ 763 (((__CALIBRATION_FACTOR__)& (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) )\ 764 << ADC_CALFACT_CALFACT_D_Pos) 765 766 /** 767 * @brief Calibration factor in differential mode to be retrieved from calibration register. 768 * @param __CALIBRATION_FACTOR__ Calibration factor value. 769 * @retval None 770 */ 771 #define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos) 772 773 /** 774 * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. 775 * @param __THRESHOLD__ Threshold value. 776 * @retval None 777 */ 778 #define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL) 779 780 #if defined(ADC_MULTIMODE_SUPPORT) 781 /** 782 * @brief Configure the ADC DMA continuous request for ADC multimode. 783 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 784 * @retval None 785 */ 786 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos) 787 #endif /* ADC_MULTIMODE_SUPPORT */ 788 789 /** 790 * @brief Shift the offset with respect to the selected ADC resolution. 791 * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0. 792 * If resolution 12 bits, no shift. 793 * If resolution 10 bits, shift of 2 ranks on the left. 794 * If resolution 8 bits, shift of 4 ranks on the left. 795 * If resolution 6 bits, shift of 6 ranks on the left. 796 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 2)*2)). 797 * @param __HANDLE__ ADC handle 798 * @param __OFFSET__ Value to be shifted 799 * @retval None 800 */ 801 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ 802 (((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)>> 2UL)*2UL))) 803 804 /** 805 * @brief Shift the AWD1 threshold with respect to the selected ADC resolution. 806 * @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. 807 * If resolution 12 bits, no shift. 808 * If resolution 10 bits, shift of 2 ranks on the left. 809 * If resolution 8 bits, shift of 4 ranks on the left. 810 * If resolution 6 bits, shift of 6 ranks on the left. 811 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 2)*2)). 812 * @param __HANDLE__ ADC handle 813 * @param __THRESHOLD__ Value to be shifted 814 * @retval None 815 */ 816 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 817 ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 2UL) * 2UL)) 818 819 /** 820 * @brief Clear Common Control Register. 821 * @param __HANDLE__ ADC handle. 822 * @retval None 823 */ 824 /** 825 * @brief Report common register to ADC1 and ADC2 826 * @param __HANDLE__: ADC handle 827 * @retval Common control register 828 */ 829 #define ADC12_COMMON_REGISTER(__HANDLE__) (ADC12_COMMON) 830 /** 831 * @brief Report common register to ADC3 832 * @param __HANDLE__: ADC handle 833 * @retval Common control register 834 */ 835 #define ADC3_COMMON_REGISTER(__HANDLE__) (ADC3_COMMON) 836 837 /** 838 * @brief Report Master Instance 839 * @param __HANDLE__: ADC handle 840 * @note return same instance if ADC of input handle is independent ADC 841 * @retval Master Instance 842 */ 843 #define ADC_MASTER_REGISTER(__HANDLE__) \ 844 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \ 845 )? \ 846 ((__HANDLE__)->Instance) \ 847 : \ 848 (ADC1) \ 849 ) 850 851 /** 852 * @brief Check whether or not dual regular conversions are enabled 853 * @param __HANDLE__: ADC handle 854 * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions 855 * are enabled) 856 */ 857 #define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \ 858 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ 859 )? \ 860 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \ 861 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \ 862 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \ 863 : \ 864 RESET \ 865 ) 866 867 /** 868 * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle 869 * of ADC master 870 * @param __HANDLE__: ADC handle 871 * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode) 872 */ 873 #define ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ 874 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2) \ 875 )? \ 876 SET \ 877 : \ 878 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET) \ 879 ) 880 881 /** 882 * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled 883 * @param __HANDLE__: ADC handle 884 * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with 885 * dual regular conversions enabled) 886 */ 887 888 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \ 889 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ 890 )? \ 891 SET \ 892 : \ 893 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 894 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \ 895 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) )) 896 897 /** 898 * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled 899 * @param __HANDLE__: ADC handle 900 * @retval SET (non-MultiMode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with 901 * dual injected conversions enabled) 902 */ 903 904 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \ 905 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ 906 )? \ 907 SET \ 908 : \ 909 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 910 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \ 911 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) )) 912 913 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) \ 914 CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \ 915 ADC_CCR_VBATEN | \ 916 ADC_CCR_VREFEN ) 917 918 /** 919 * @brief Set handle instance of the ADC slave associated to the ADC master. 920 * @param __HANDLE_MASTER__ ADC master handle. 921 * @param __HANDLE_SLAVE__ ADC slave handle. 922 * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC, 923 * __HANDLE_SLAVE__ instance is set to NULL. 924 * @retval None 925 */ 926 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ 927 ((((__HANDLE_MASTER__)->Instance == ADC1)) \ 928 ? ((__HANDLE_SLAVE__)->Instance = ADC2) \ 929 : ((__HANDLE_SLAVE__)->Instance = NULL)) 930 931 932 /** 933 * @brief Verify the ADC instance connected to the battery voltage VBAT. 934 * @param __HANDLE__ ADC handle. 935 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 936 */ 937 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC2)) 938 939 /** 940 * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. 941 * @param __HANDLE__ ADC handle. 942 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 943 */ 944 #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 945 946 /** 947 * @brief Verify the ADC instance connected to the internal VDDCore. 948 * @param __HANDLE__ ADC handle. 949 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 950 */ 951 #define ADC_VDDCORE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC2) ) 952 953 /** 954 * @brief Verify the length of scheduled injected conversions group. 955 * @param __LENGTH__ number of programmed conversions. 956 * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or 957 * RESET (__LENGTH__ is null or too large) 958 */ 959 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) 960 961 /** 962 * @brief Calibration factor value range verification. 963 * @param __CALIBRATION_FACTOR__ Calibration factor value. 964 * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) 965 */ 966 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x1FFU)) 967 968 969 /** 970 * @brief Verify the ADC channel setting. 971 * @param __HANDLE__ ADC handle. 972 * @param __CHANNEL__ programmed ADC channel. 973 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 974 */ 975 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) || \ 976 ((__CHANNEL__) == ADC_CHANNEL_1) || \ 977 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 978 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 979 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 980 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 981 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 982 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 983 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 984 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 985 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 986 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 987 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 988 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 989 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 990 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 991 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 992 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 993 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 994 ((__CHANNEL__) == ADC_CHANNEL_19) || \ 995 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 996 ((__CHANNEL__) == ADC_CHANNEL_VDDCORE) || \ 997 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) ) 998 999 /** 1000 * @brief Verify the ADC channel differential mode availability. 1001 * @param __HANDLE__ ADC handle. 1002 * @param __CHANNEL__ ADC channel 1003 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 1004 */ 1005 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) \ 1006 (__HAL_ADC_CHANNEL_DIFF_NEG_INPUT(__HANDLE__, __CHANNEL__) != ADC_CHANNEL_NONE) 1007 1008 /** 1009 * @brief Verify the ADC single-ended input or differential mode setting. 1010 * @param __SING_DIFF__ programmed channel setting. 1011 * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) 1012 */ 1013 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ 1014 ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) 1015 1016 /** 1017 * @brief Verify the ADC offset sign setting. 1018 * @param __OFFSET_SIGN__ ADC offset sign. 1019 * @retval SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid) 1020 */ 1021 #define IS_ADC_OFFSET_SIGN(__OFFSET_SIGN__) (((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_NEGATIVE) || \ 1022 ((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_POSITIVE) ) 1023 /** 1024 * @brief Verify the ADC offset management setting. 1025 * @param __OFFSET_NUMBER__ ADC offset management. 1026 * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) 1027 */ 1028 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ 1029 ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ 1030 ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ 1031 ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ 1032 ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) 1033 1034 /** 1035 * @brief Verify the ADC injected channel setting. 1036 * @param __CHANNEL__ programmed ADC injected channel. 1037 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 1038 */ 1039 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ 1040 ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ 1041 ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ 1042 ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) 1043 1044 /** 1045 * @brief Verify the ADC injected conversions external trigger. 1046 * @param __ADC_INSTANCE__ ADC instance 1047 * @param __INJ_TRIG_SOURCE__ programmed ADC injected conversions external trigger. 1048 * @retval SET (__INJ_TRIG_SOURCE__ is a valid value) or RESET (__INJ_TRIG_SOURCE__ is invalid) 1049 */ 1050 #define IS_ADC_EXTTRIGINJEC(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ 1051 (((__INJ_TRIG_SOURCE__) == ADC_INJECTED_SOFTWARE_START) \ 1052 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) \ 1053 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T1_CC4) \ 1054 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) \ 1055 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) \ 1056 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T2_CC1) \ 1057 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) \ 1058 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T3_CC1) \ 1059 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T3_CC3) \ 1060 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T3_CC4) \ 1061 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) \ 1062 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) \ 1063 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T5_TRGO) \ 1064 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) \ 1065 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) \ 1066 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) \ 1067 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) \ 1068 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T9_CC2) \ 1069 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T9_TRGO) \ 1070 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T12_TRGO) \ 1071 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) \ 1072 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T18_TRGO) \ 1073 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_LPTIM1_CH2) \ 1074 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_LPTIM2_CH2) \ 1075 || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_LPTIM3_CH2) \ 1076 ) 1077 1078 /** 1079 * @brief Verify the ADC edge trigger setting for injected group. 1080 * @param __EDGE__ programmed ADC edge trigger setting. 1081 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 1082 */ 1083 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ 1084 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ 1085 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ 1086 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) 1087 1088 #if defined(ADC_MULTIMODE_SUPPORT) 1089 /** 1090 * @brief Verify the ADC multimode setting. 1091 * @param __MODE__ programmed ADC multimode setting. 1092 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1093 */ 1094 #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ 1095 ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ 1096 ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ 1097 ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ 1098 ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ 1099 ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ 1100 ((__MODE__) == ADC_DUALMODE_INTERL) || \ 1101 ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) 1102 1103 /** 1104 * @brief Verify the ADC dual data mode setting. 1105 * @param MODE: programmed ADC dual mode setting. 1106 * @retval SET (MODE is valid) or RESET (MODE is invalid) 1107 */ 1108 #define IS_ADC_DUAL_DATA_MODE(MODE) (((MODE) == ADC_DUALMODEDATAFORMAT_DISABLED) || \ 1109 ((MODE) == ADC_DUALMODEDATAFORMAT_32_BIT) || \ 1110 ((MODE) == ADC_DUALMODEDATAFORMAT_8_BIT) ) 1111 1112 /** 1113 * @brief Verify the ADC multimode delay setting. 1114 * @param __DELAY__ programmed ADC multimode delay setting. 1115 * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid) 1116 */ 1117 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ 1118 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \ 1119 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \ 1120 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ 1121 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ 1122 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ 1123 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ 1124 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ 1125 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ 1126 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ 1127 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ 1128 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \ 1129 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) ) 1130 #endif /* ADC_MULTIMODE_SUPPORT */ 1131 1132 /** 1133 * @brief Verify the ADC analog watchdog setting. 1134 * @param __WATCHDOG__ programmed ADC analog watchdog setting. 1135 * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) 1136 */ 1137 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ 1138 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ 1139 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) 1140 1141 /** 1142 * @brief Verify the ADC analog watchdog mode setting. 1143 * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. 1144 * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) 1145 */ 1146 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ 1147 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 1148 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 1149 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)|| \ 1150 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 1151 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 1152 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 1153 1154 /** 1155 * @brief Verify the ADC analog watchdog filtering setting. 1156 * @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting. 1157 * @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is invalid) 1158 */ 1159 #define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(__FILTERING_MODE__) \ 1160 (((__FILTERING_MODE__) == ADC_AWD_FILTERING_NONE) || \ 1161 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_2SAMPLES) || \ 1162 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_3SAMPLES) || \ 1163 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_4SAMPLES) || \ 1164 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_5SAMPLES) || \ 1165 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_6SAMPLES) || \ 1166 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_7SAMPLES) || \ 1167 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_8SAMPLES) ) 1168 1169 1170 /** 1171 * @brief Verify the ADC conversion (regular or injected or both). 1172 * @param __CONVERSION__ ADC conversion group. 1173 * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) 1174 */ 1175 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ 1176 ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ 1177 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) 1178 1179 /** 1180 * @brief Verify the ADC event type. 1181 * @param __EVENT__ ADC event. 1182 * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) 1183 */ 1184 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ 1185 ((__EVENT__) == ADC_AWD_EVENT) || \ 1186 ((__EVENT__) == ADC_AWD2_EVENT) || \ 1187 ((__EVENT__) == ADC_AWD3_EVENT) || \ 1188 ((__EVENT__) == ADC_OVR_EVENT) ) 1189 1190 /** 1191 * @brief Verify the ADC oversampling ratio. 1192 * @param __RATIO__: programmed ADC oversampling ratio. 1193 * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) 1194 */ 1195 #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) >= 1UL) && ((__RATIO__) <= 1024UL)) 1196 1197 /** 1198 * @brief Verify the ADC oversampling shift. 1199 * @param __SHIFT__ programmed ADC oversampling shift. 1200 * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) 1201 */ 1202 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ 1203 ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ 1204 ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ 1205 ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ 1206 ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ 1207 ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ 1208 ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ 1209 ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ 1210 ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ) || \ 1211 ((__SHIFT__) == ADC_RIGHTBITSHIFT_9 ) || \ 1212 ((__SHIFT__) == ADC_RIGHTBITSHIFT_10 )) 1213 1214 /** 1215 * @brief Verify the ADC oversampling triggered mode. 1216 * @param __MODE__ programmed ADC oversampling triggered mode. 1217 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1218 */ 1219 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ 1220 ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) 1221 1222 /** 1223 * @brief Verify the ADC oversampling regular conversion resumed or continued mode. 1224 * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. 1225 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1226 */ 1227 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ 1228 ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) 1229 1230 /** 1231 * @} 1232 */ 1233 1234 1235 /* Exported functions --------------------------------------------------------*/ 1236 /** @addtogroup ADCEx_Exported_Functions 1237 * @{ 1238 */ 1239 1240 /** @addtogroup ADCEx_Exported_Functions_Group1 1241 * @{ 1242 */ 1243 /* IO operation functions *****************************************************/ 1244 1245 /* ADC calibration */ 1246 1247 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 1248 uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 1249 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, 1250 uint32_t CalibrationFactor); 1251 1252 /* Blocking mode: Polling */ 1253 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); 1254 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); 1255 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1256 1257 /* Non-blocking mode: Interruption */ 1258 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); 1259 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); 1260 1261 #if defined(ADC_MULTIMODE_SUPPORT) 1262 /* ADC multimode */ 1263 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1264 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); 1265 uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc); 1266 #endif /* ADC_MULTIMODE_SUPPORT */ 1267 1268 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1269 uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank); 1270 int32_t HAL_ADCEx_InjectedGetSignedValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank); 1271 1272 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ 1273 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); 1274 void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); 1275 void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); 1276 void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); 1277 1278 /* ADC group regular conversions stop */ 1279 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); 1280 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); 1281 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); 1282 #if defined(ADC_MULTIMODE_SUPPORT) 1283 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); 1284 #endif /* ADC_MULTIMODE_SUPPORT */ 1285 1286 /** 1287 * @} 1288 */ 1289 1290 /** @addtogroup ADCEx_Exported_Functions_Group2 1291 * @{ 1292 */ 1293 /* Peripheral Control functions ***********************************************/ 1294 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, 1295 const ADC_InjectionConfTypeDef *pConfigInjected); 1296 1297 #if defined(ADC_MULTIMODE_SUPPORT) 1298 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, 1299 const ADC_MultiModeTypeDef *pMultimode); 1300 #endif /* ADC_MULTIMODE_SUPPORT */ 1301 1302 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc); 1303 1304 /** 1305 * @} 1306 */ 1307 1308 /** 1309 * @} 1310 */ 1311 1312 /** 1313 * @} 1314 */ 1315 1316 /** 1317 * @} 1318 */ 1319 1320 #ifdef __cplusplus 1321 } 1322 #endif 1323 1324 #endif /* STM32N6xx_HAL_ADC_EX_H */ 1325
