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Searched refs:ADC_CSR_EOC3_Pos (Results 1 – 25 of 29) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f215xx.h1645 #define ADC_CSR_EOC3_Pos (17U) macro
1646 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
Dstm32f205xx.h1595 #define ADC_CSR_EOC3_Pos (17U) macro
1596 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
Dstm32f207xx.h1699 #define ADC_CSR_EOC3_Pos (17U) macro
1700 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
Dstm32f217xx.h1749 #define ADC_CSR_EOC3_Pos (17U) macro
1750 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f405xx.h1593 #define ADC_CSR_EOC3_Pos (17U) macro
1594 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
Dstm32f415xx.h1667 #define ADC_CSR_EOC3_Pos (17U) macro
1668 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
Dstm32f407xx.h1697 #define ADC_CSR_EOC3_Pos (17U) macro
1698 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
Dstm32f427xx.h1791 #define ADC_CSR_EOC3_Pos (17U) macro
1792 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
Dstm32f446xx.h1714 #define ADC_CSR_EOC3_Pos (17U) macro
1715 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
Dstm32f417xx.h1771 #define ADC_CSR_EOC3_Pos (17U) macro
1772 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
Dstm32f429xx.h1847 #define ADC_CSR_EOC3_Pos (17U) macro
1848 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
Dstm32f439xx.h1923 #define ADC_CSR_EOC3_Pos (17U) macro
1924 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
Dstm32f437xx.h1869 #define ADC_CSR_EOC3_Pos (17U) macro
1870 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h1723 #define ADC_CSR_EOC3_Pos (17U) macro
1724 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
Dstm32f722xx.h1707 #define ADC_CSR_EOC3_Pos (17U) macro
1708 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
Dstm32f730xx.h1757 #define ADC_CSR_EOC3_Pos (17U) macro
1758 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
Dstm32f733xx.h1757 #define ADC_CSR_EOC3_Pos (17U) macro
1758 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
Dstm32f732xx.h1741 #define ADC_CSR_EOC3_Pos (17U) macro
1742 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
Dstm32f750xx.h2020 #define ADC_CSR_EOC3_Pos (17U) macro
2021 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
Dstm32f745xx.h1890 #define ADC_CSR_EOC3_Pos (17U) macro
1891 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
Dstm32f756xx.h2020 #define ADC_CSR_EOC3_Pos (17U) macro
2021 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
Dstm32f746xx.h1945 #define ADC_CSR_EOC3_Pos (17U) macro
1946 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
Dstm32f765xx.h2047 #define ADC_CSR_EOC3_Pos (17U) macro
2048 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
Dstm32f777xx.h2216 #define ADC_CSR_EOC3_Pos (17U) macro
2217 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
Dstm32f767xx.h2141 #define ADC_CSR_EOC3_Pos (17U) macro
2142 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */

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