Home
last modified time | relevance | path

Searched refs:ADC_CFGR1_AWDCH_Msk (Results 1 – 19 of 19) sorted by relevance

/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l041xx.h713 #define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ macro
714 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits…
Dstm32l010x8.h671 #define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ macro
672 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits…
Dstm32l010xb.h676 #define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ macro
677 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits…
Dstm32l011xx.h683 #define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ macro
684 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits…
Dstm32l021xx.h704 #define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ macro
705 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits…
Dstm32l031xx.h692 #define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ macro
693 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits…
Dstm32l051xx.h727 #define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ macro
728 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits…
Dstm32l010x4.h663 #define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ macro
664 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits…
Dstm32l010x6.h669 #define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ macro
670 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits…
Dstm32l081xx.h770 #define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ macro
771 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits…
Dstm32l071xx.h749 #define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ macro
750 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits…
Dstm32l052xx.h836 #define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ macro
837 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits…
Dstm32l062xx.h857 #define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ macro
858 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits…
Dstm32l053xx.h852 #define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ macro
853 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits…
Dstm32l072xx.h863 #define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ macro
864 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits…
Dstm32l073xx.h879 #define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ macro
880 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits…
Dstm32l083xx.h900 #define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ macro
901 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits…
Dstm32l063xx.h873 #define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ macro
874 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits…
Dstm32l082xx.h884 #define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ macro
885 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits…