1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32U5xx_HAL_H 22 #define __STM32U5xx_HAL_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32u5xx_hal_conf.h" 30 31 /** @addtogroup STM32U5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup HAL 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup HAL_Exported_Types HAL Exported Types 41 * @{ 42 */ 43 44 /** @defgroup HAL_TICK_FREQ Tick Frequency 45 * @{ 46 */ 47 typedef enum 48 { 49 HAL_TICK_FREQ_10HZ = 100U, 50 HAL_TICK_FREQ_100HZ = 10U, 51 HAL_TICK_FREQ_1KHZ = 1U, 52 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 53 } HAL_TickFreqTypeDef; 54 /** 55 * @} 56 */ 57 58 /** 59 * @} 60 */ 61 62 /* Exported variables --------------------------------------------------------*/ 63 /** @defgroup HAL_Exported_Variables HAL Exported Variables 64 * @{ 65 */ 66 extern __IO uint32_t uwTick; 67 extern uint32_t uwTickPrio; 68 extern HAL_TickFreqTypeDef uwTickFreq; 69 /** 70 * @} 71 */ 72 73 /* Exported constants --------------------------------------------------------*/ 74 /** @defgroup REV_ID device revision ID 75 * @{ 76 */ 77 #define REV_ID_A 0x1000U /*!< STM32U5 rev.A */ 78 #define REV_ID_B 0x2000U /*!< STM32U5 rev.B */ 79 /** 80 * @} 81 */ 82 83 84 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 85 * @{ 86 */ 87 88 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts 89 * @{ 90 */ 91 #define SYSCFG_IT_FPU_IOC SYSCFG_FPUIMR_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ 92 #define SYSCFG_IT_FPU_DZC SYSCFG_FPUIMR_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ 93 #define SYSCFG_IT_FPU_UFC SYSCFG_FPUIMR_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ 94 #define SYSCFG_IT_FPU_OFC SYSCFG_FPUIMR_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ 95 #define SYSCFG_IT_FPU_IDC SYSCFG_FPUIMR_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ 96 #define SYSCFG_IT_FPU_IXC SYSCFG_FPUIMR_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ 97 98 /** 99 * @} 100 */ 101 102 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale 103 * @{ 104 */ 105 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ 106 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */ 107 #define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREF_OUT3) */ 108 #define SYSCFG_VREFBUF_VOLTAGE_SCALE3 (VREFBUF_CSR_VRS_0 | VREFBUF_CSR_VRS_1) /*!< Voltage reference scale 3 (VREF_OUT4) */ 109 110 /** 111 * @} 112 */ 113 114 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance 115 * @{ 116 */ 117 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to 118 Voltage reference buffer output */ 119 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 120 121 /** 122 * @} 123 */ 124 125 /** @defgroup SYSCFG_flags_definition Flags 126 * @{ 127 */ 128 129 #define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */ 130 #define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */ 131 132 /** 133 * @} 134 */ 135 136 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO 137 * @{ 138 */ 139 140 /** @brief Fast-mode Plus driving capability on a specific GPIO 141 */ 142 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ 143 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ 144 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ 145 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ 146 147 /** 148 * @} 149 */ 150 151 /** @defgroup SYSCFG_Lock_items SYSCFG Lock items 152 * @brief SYSCFG items to set lock on 153 * @{ 154 */ 155 #define SYSCFG_MPU_NSEC SYSCFG_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or non-secure only) */ 156 #define SYSCFG_VTOR_NSEC SYSCFG_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or non-secure only) */ 157 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 158 #define SYSCFG_SAU (SYSCFG_CSLCKR_LOCKSAU << 16U) /*!< SAU lock (privileged secure code only) */ 159 #define SYSCFG_MPU_SEC (SYSCFG_CSLCKR_LOCKSMPU << 16U) /*!< Secure MPU lock (privileged secure code only) */ 160 #define SYSCFG_VTOR_AIRCR_SEC (SYSCFG_CSLCKR_LOCKSVTAIRCR << 16U) /*!< VTOR_S and AIRCR lock (privileged secure code only) */ 161 #define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC|SYSCFG_SAU|SYSCFG_MPU_SEC|SYSCFG_VTOR_AIRCR_SEC) /*!< All */ 162 #else 163 #define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */ 164 #endif /* __ARM_FEATURE_CMSE */ 165 /** 166 * @} 167 */ 168 169 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 170 171 /** @defgroup SYSCFG_Attributes_items SYSCFG Attributes items 172 * @brief SYSCFG items to configure secure or non-secure attributes on 173 * @{ 174 */ 175 #define SYSCFG_CLK SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock control */ 176 #define SYSCFG_CLASSB SYSCFG_SECCFGR_CLASSBSEC /*!< Class B */ 177 #define SYSCFG_FPU SYSCFG_SECCFGR_FPUSEC /*!< FPU */ 178 #define SYSCFG_ALL (SYSCFG_CLK | SYSCFG_CLASSB | SYSCFG_FPU) /*!< All */ 179 /** 180 * @} 181 */ 182 183 /** @defgroup SYSCFG_attributes SYSCFG attributes 184 * @brief SYSCFG secure or non-secure attributes 185 * @{ 186 */ 187 #define SYSCFG_SEC 0x00000001U /*!< Secure attribute */ 188 #define SYSCFG_NSEC 0x00000000U /*!< Non-secure attribute */ 189 /** 190 * @} 191 */ 192 193 #endif /* __ARM_FEATURE_CMSE */ 194 195 #ifdef SYSCFG_OTGHSPHYCR_EN 196 /** @defgroup SYSCFG_OTG_PHY_RefenceClockSelection OTG PHY Reference Clock Selection 197 * @{ 198 */ 199 200 /** @brief OTG HS PHY reference clock frequency selection 201 */ 202 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_1 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1) /*!< 16Mhz */ 203 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_2 SYSCFG_OTGHSPHYCR_CLKSEL_3 /*!< 19.2Mhz */ 204 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_3 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 20Mhz */ 205 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_4 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 24Mhz */ 206 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_5 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_2 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 26Mhz */ 207 #define SYSCFG_OTG_HS_PHY_CLK_SELECT_6 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 32Mhz */ 208 /** 209 * @} 210 */ 211 212 /** @defgroup SYSCFG_OTG_PHY_PowerDown OTG PHY Power Down 213 * @{ 214 */ 215 216 /** @brief OTG HS PHY Power Down config 217 */ 218 219 #define SYSCFG_OTG_HS_PHY_POWER_ON 0x00000000U /*!< PHY state machine, bias and OTG PHY PLL are powered down */ 220 #define SYSCFG_OTG_HS_PHY_POWER_DOWN SYSCFG_OTGHSPHYCR_PDCTRL /*!< PHY state machine, bias and OTG PHY PLL remain powered */ 221 222 /** 223 * @} 224 */ 225 226 /** @defgroup SYSCFG_OTG_PHY_Enable OTG PHY Enable 227 * @{ 228 */ 229 230 #define SYSCFG_OTG_HS_PHY_UNDERRESET 0x00000000U /*!< PHY under reset */ 231 #define SYSCFG_OTG_HS_PHY_ENABLE SYSCFG_OTGHSPHYCR_EN /*!< PHY enabled */ 232 233 /** 234 * @} 235 */ 236 237 /** @defgroup SYSCFG_OTG_PHYTUNER_PreemphasisCurrent OTG PHYTUNER Preemphasis Current 238 * @{ 239 */ 240 241 /** @brief High-speed (HS) transmitter preemphasis current control 242 */ 243 #define SYSCFG_OTG_HS_PHY_PREEMP_DISABLED 0x00000000U /*!< HS transmitter preemphasis circuit disabled */ 244 #define SYSCFG_OTG_HS_PHY_PREEMP_1X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 /*!< HS transmitter preemphasis circuit sources 1x preemphasis current */ 245 #define SYSCFG_OTG_HS_PHY_PREEMP_2X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1 /*!< HS transmitter preemphasis circuit sources 2x preemphasis current */ 246 #define SYSCFG_OTG_HS_PHY_PREEMP_3X (SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 | SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1) /*!< HS transmitter preemphasis circuit sources 3x preemphasis current */ 247 248 /** 249 * @} 250 */ 251 252 /** @defgroup SYSCFG_OTG_PHYTUNER_SquelchThreshold OTG PHYTUNER Squelch Threshold 253 * @{ 254 */ 255 256 /** @brief Squelch threshold adjustment 257 */ 258 #define SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT 0x00000000U /*!< +15% (recommended value) */ 259 #define SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT (SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_0 | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_1) /*!< 0% (default value) */ 260 261 /** 262 * @} 263 */ 264 265 /** @defgroup SYSCFG_OTG_PHYTUNER_DisconnectThreshold OTG PHYTUNER Disconnect Threshold 266 * @{ 267 */ 268 269 /** @brief Disconnect threshold adjustment 270 */ 271 #define SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_1 /*!< +5.9% (recommended value) */ 272 #define SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_0 /*!< 0% (default value) */ 273 274 /** 275 * @} 276 */ 277 278 #endif /* SYSCFG_OTGHSPHYCR_EN */ 279 /** 280 * @} 281 */ 282 283 /* Exported macros -----------------------------------------------------------*/ 284 285 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 286 * @{ 287 */ 288 289 /** @brief Freeze/Unfreeze Peripherals in Debug mode 290 */ 291 #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) 292 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 293 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 294 #endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */ 295 296 #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) 297 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 298 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 299 #endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */ 300 301 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) 302 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 303 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 304 #endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */ 305 306 #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) 307 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 308 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 309 #endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */ 310 311 #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) 312 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 313 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 314 #endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */ 315 316 #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) 317 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 318 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 319 #endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */ 320 321 #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) 322 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 323 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 324 #endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */ 325 326 #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) 327 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 328 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 329 #endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */ 330 331 #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) 332 #define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 333 #define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 334 #endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */ 335 336 #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) 337 #define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 338 #define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 339 #endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */ 340 341 #if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP) 342 #define __HAL_DBGMCU_FREEZE_I2C4() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 343 #define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 344 #endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */ 345 346 #if defined(DBGMCU_APB1FZR2_DBG_I2C5_STOP) 347 #define __HAL_DBGMCU_FREEZE_I2C5() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C5_STOP) 348 #define __HAL_DBGMCU_UNFREEZE_I2C5() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C5_STOP) 349 #endif /* DBGMCU_APB1FZR2_DBG_I2C5_STOP */ 350 351 #if defined(DBGMCU_APB1FZR2_DBG_I2C6_STOP) 352 #define __HAL_DBGMCU_FREEZE_I2C6() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C6_STOP) 353 #define __HAL_DBGMCU_UNFREEZE_I2C6() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C6_STOP) 354 #endif /* DBGMCU_APB1FZR2_DBG_I2C6_STOP */ 355 356 #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 357 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 358 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 359 #endif /* DBGMCU_APB1FZR2_DBG_LPTIM2_STOP */ 360 361 #if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP) 362 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) 363 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) 364 #endif /* DBGMCU_APB2FZR_DBG_TIM1_STOP */ 365 366 #if defined(DBGMCU_APB2FZR_DBG_TIM8_STOP) 367 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP) 368 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP) 369 #endif /* DBGMCU_APB2FZR_DBG_TIM8_STOP */ 370 371 #if defined(DBGMCU_APB2FZR_DBG_TIM15_STOP) 372 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP) 373 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP) 374 #endif /* DBGMCU_APB2FZR_DBG_TIM15_STOP */ 375 376 #if defined(DBGMCU_APB2FZR_DBG_TIM16_STOP) 377 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) 378 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) 379 #endif /* DBGMCU_APB2FZR_DBG_TIM16_STOP */ 380 381 #if defined(DBGMCU_APB2FZR_DBG_TIM17_STOP) 382 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) 383 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) 384 #endif /* DBGMCU_APB2FZR_DBG_TIM17_STOP */ 385 386 #if defined(DBGMCU_APB3FZR_DBG_I2C3_STOP) 387 #define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP) 388 #define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP) 389 #endif /* DBGMCU_APB3FZR_DBG_I2C3_STOP */ 390 391 #if defined(DBGMCU_APB3FZR_DBG_LPTIM1_STOP) 392 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP) 393 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP) 394 #endif /* DBGMCU_APB3FZR_DBG_LPTIM1_STOP */ 395 396 #if defined(DBGMCU_APB3FZR_DBG_LPTIM3_STOP) 397 #define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP) 398 #define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP) 399 #endif /* DBGMCU_APB3FZR_DBG_LPTIM3_STOP */ 400 401 #if defined(DBGMCU_APB3FZR_DBG_LPTIM4_STOP) 402 #define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP) 403 #define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP) 404 #endif /* DBGMCU_APB3FZR_DBG_LPTIM4_STOP */ 405 406 #if defined(DBGMCU_APB3FZR_DBG_RTC_STOP) 407 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP) 408 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP) 409 #endif /* DBGMCU_APB3FZR_DBG_RTC_STOP */ 410 411 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA0_STOP) 412 #define __HAL_DBGMCU_FREEZE_GPDMA0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA0_STOP) 413 #define __HAL_DBGMCU_UNFREEZE_GPDMA0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA0_STOP) 414 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA0_STOP */ 415 416 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_STOP) 417 #define __HAL_DBGMCU_FREEZE_GPDMA1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_STOP) 418 #define __HAL_DBGMCU_UNFREEZE_GPDMA1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_STOP) 419 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_STOP */ 420 421 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_STOP) 422 #define __HAL_DBGMCU_FREEZE_GPDMA2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_STOP) 423 #define __HAL_DBGMCU_UNFREEZE_GPDMA2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_STOP) 424 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_STOP */ 425 426 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA3_STOP) 427 #define __HAL_DBGMCU_FREEZE_GPDMA3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA3_STOP) 428 #define __HAL_DBGMCU_UNFREEZE_GPDMA3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA3_STOP) 429 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA3_STOP */ 430 431 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA4_STOP) 432 #define __HAL_DBGMCU_FREEZE_GPDMA4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA4_STOP) 433 #define __HAL_DBGMCU_UNFREEZE_GPDMA4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA4_STOP) 434 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA4_STOP */ 435 436 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA5_STOP) 437 #define __HAL_DBGMCU_FREEZE_GPDMA5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA5_STOP) 438 #define __HAL_DBGMCU_UNFREEZE_GPDMA5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA5_STOP) 439 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA5_STOP */ 440 441 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA6_STOP) 442 #define __HAL_DBGMCU_FREEZE_GPDMA6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA6_STOP) 443 #define __HAL_DBGMCU_UNFREEZE_GPDMA6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA6_STOP) 444 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA6_STOP */ 445 446 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA7_STOP) 447 #define __HAL_DBGMCU_FREEZE_GPDMA7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA7_STOP) 448 #define __HAL_DBGMCU_UNFREEZE_GPDMA7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA7_STOP) 449 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA7_STOP */ 450 451 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA8_STOP) 452 #define __HAL_DBGMCU_FREEZE_GPDMA8() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA8_STOP) 453 #define __HAL_DBGMCU_UNFREEZE_GPDMA8() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA8_STOP) 454 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA8_STOP */ 455 456 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA9_STOP) 457 #define __HAL_DBGMCU_FREEZE_GPDMA9() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA9_STOP) 458 #define __HAL_DBGMCU_UNFREEZE_GPDMA9() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA9_STOP) 459 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA9_STOP */ 460 461 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA10_STOP) 462 #define __HAL_DBGMCU_FREEZE_GPDMA10() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA10_STOP) 463 #define __HAL_DBGMCU_UNFREEZE_GPDMA10() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA10_STOP) 464 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA10_STOP */ 465 466 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA11_STOP) 467 #define __HAL_DBGMCU_FREEZE_GPDMA11() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA11_STOP) 468 #define __HAL_DBGMCU_UNFREEZE_GPDMA11() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA11_STOP) 469 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA11_STOP */ 470 471 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA12_STOP) 472 #define __HAL_DBGMCU_FREEZE_GPDMA12() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA12_STOP) 473 #define __HAL_DBGMCU_UNFREEZE_GPDMA12() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA12_STOP) 474 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA12_STOP */ 475 476 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA13_STOP) 477 #define __HAL_DBGMCU_FREEZE_GPDMA13() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA13_STOP) 478 #define __HAL_DBGMCU_UNFREEZE_GPDMA13() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA13_STOP) 479 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA13_STOP */ 480 481 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA14_STOP) 482 #define __HAL_DBGMCU_FREEZE_GPDMA14() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA14_STOP) 483 #define __HAL_DBGMCU_UNFREEZE_GPDMA14() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA14_STOP) 484 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA14_STOP */ 485 486 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA15_STOP) 487 #define __HAL_DBGMCU_FREEZE_GPDMA15() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA15_STOP) 488 #define __HAL_DBGMCU_UNFREEZE_GPDMA15() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA15_STOP) 489 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA15_STOP */ 490 491 #if defined(DBGMCU_AHB3FZR_DBG_LPDMA0_STOP) 492 #define __HAL_DBGMCU_FREEZE_LPDMA0() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA0_STOP) 493 #define __HAL_DBGMCU_UNFREEZE_LPDMA0() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA0_STOP) 494 #endif /* DBGMCU_AHB3FZR_DBG_LPDMA0_STOP */ 495 496 #if defined(DBGMCU_AHB3FZR_DBG_LPDMA1_STOP) 497 #define __HAL_DBGMCU_FREEZE_LPDMA1() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA1_STOP) 498 #define __HAL_DBGMCU_UNFREEZE_LPDMA1() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA1_STOP) 499 #endif /* DBGMCU_AHB3FZR_DBG_LPDMA1_STOP */ 500 501 #if defined(DBGMCU_AHB3FZR_DBG_LPDMA2_STOP) 502 #define __HAL_DBGMCU_FREEZE_LPDMA2() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA2_STOP) 503 #define __HAL_DBGMCU_UNFREEZE_LPDMA2() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA2_STOP) 504 #endif /* DBGMCU_AHB3FZR_DBG_LPDMA2_STOP */ 505 506 #if defined(DBGMCU_AHB3FZR_DBG_LPDMA3_STOP) 507 #define __HAL_DBGMCU_FREEZE_LPDMA3() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA3_STOP) 508 #define __HAL_DBGMCU_UNFREEZE_LPDMA3() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA3_STOP) 509 #endif /* DBGMCU_AHB3FZR_DBG_LPDMA3_STOP */ 510 511 /** 512 * @} 513 */ 514 515 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 516 * @{ 517 */ 518 519 /** @brief Floating Point Unit interrupt enable/disable macros 520 * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts 521 */ 522 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 523 SET_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\ 524 }while(0) 525 526 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 527 CLEAR_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\ 528 }while(0) 529 530 /** @brief SYSCFG Break ECC lock. 531 * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. 532 * @note The selected configuration is locked and can be unlocked only by system reset. 533 */ 534 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) 535 536 /** @brief SYSCFG Break Cortex-M33 Lockup lock. 537 * Enable and lock the connection of Cortex-M33 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. 538 * @note The selected configuration is locked and can be unlocked only by system reset. 539 */ 540 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) 541 542 /** @brief SYSCFG Break PVD lock. 543 * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in 544 * the PWR_CR2 register. 545 * @note The selected configuration is locked and can be unlocked only by system reset. 546 */ 547 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) 548 549 /** @brief SYSCFG Break SRAM2 parity lock. 550 * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input. 551 * @note The selected configuration is locked and can be unlocked by system reset. 552 */ 553 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) 554 555 /** @brief Check SYSCFG flag is set or not. 556 * @param __FLAG__: specifies the flag to check. 557 * This parameter can be one of the following values: 558 * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag 559 * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing 560 * @retval The new state of __FLAG__ (TRUE or FALSE). 561 */ 562 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\ 563 & (__FLAG__))!= 0) ? 1 : 0) 564 565 /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. 566 */ 567 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) 568 569 /** @brief Fast-mode Plus driving capability enable/disable macros 570 * @param __FASTMODEPLUS__: This parameter can be a value of : 571 * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 572 * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 573 * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 574 * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 575 */ 576 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) \ 577 do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 578 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 579 }while(0) 580 581 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) \ 582 do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 583 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 584 }while(0) 585 586 /** 587 * @} 588 */ 589 590 /* Private macros ------------------------------------------------------------*/ 591 592 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros 593 * @{ 594 */ 595 596 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ 597 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ 598 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ 599 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ 600 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ 601 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) 602 603 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ 604 ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ 605 ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ 606 ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) 607 608 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ 609 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \ 610 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \ 611 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3)) 612 613 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 614 ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) 615 616 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) 617 618 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 619 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 620 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ 621 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 622 623 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 624 625 #define IS_SYSCFG_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SYSCFG_SEC) ||\ 626 ((__ATTRIBUTES__) == SYSCFG_NSEC)) 627 628 #define IS_SYSCFG_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SYSCFG_CLK) == SYSCFG_CLK) || \ 629 (((__ITEM__) & SYSCFG_CLASSB) == SYSCFG_CLASSB) || \ 630 (((__ITEM__) & SYSCFG_FPU) == SYSCFG_FPU) || \ 631 (((__ITEM__) & ~(SYSCFG_ALL)) == 0U)) 632 633 #define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \ 634 (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC) || \ 635 (((__ITEM__) & SYSCFG_SAU) == SYSCFG_SAU) || \ 636 (((__ITEM__) & SYSCFG_MPU_SEC) == SYSCFG_MPU_SEC) || \ 637 (((__ITEM__) & SYSCFG_VTOR_AIRCR_SEC) == SYSCFG_VTOR_AIRCR_SEC) || \ 638 (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U)) 639 640 #else 641 642 #define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \ 643 (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC) || \ 644 (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U)) 645 646 647 #endif /* __ARM_FEATURE_CMSE */ 648 649 #ifdef SYSCFG_OTGHSPHYCR_EN 650 #define IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_1) || \ 651 ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_2) || \ 652 ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_3) || \ 653 ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_4) || \ 654 ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_5) || \ 655 ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_6)) 656 657 #define IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_DOWN) || \ 658 ((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_ON)) 659 660 #define IS_SYSCFG_OTGPHY_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_UNDERRESET) || \ 661 ((__VALUE__) == SYSCFG_OTG_HS_PHY_ENABLE)) 662 663 #define IS_SYSCFG_OTGPHY_DISCONNECT(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT) || \ 664 ((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT)) 665 666 #define IS_SYSCFG_OTGPHY_SQUELCH(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT) || \ 667 ((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT)) 668 669 #define IS_SYSCFG_OTGPHY_PREEMPHASIS(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_DISABLED) || \ 670 ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_1X) || \ 671 ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_2X) || \ 672 ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_3X)) 673 #endif /* SYSCFG_OTGHSPHYCR_EN */ 674 675 /** 676 * @} 677 */ 678 679 /** @defgroup HAL_Private_Macros HAL Private Macros 680 * @{ 681 */ 682 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ 683 ((FREQ) == HAL_TICK_FREQ_100HZ) || \ 684 ((FREQ) == HAL_TICK_FREQ_1KHZ)) 685 /** 686 * @} 687 */ 688 689 /* Exported functions --------------------------------------------------------*/ 690 691 /** @addtogroup HAL_Exported_Functions HAL Exported Functions 692 * @{ 693 */ 694 695 /** @addtogroup HAL_Exported_Functions_Group1 HAL Initialization and de-initialization Functions 696 * @{ 697 */ 698 699 /* Initialization and de-initialization functions ******************************/ 700 HAL_StatusTypeDef HAL_Init(void); 701 HAL_StatusTypeDef HAL_DeInit(void); 702 void HAL_MspInit(void); 703 void HAL_MspDeInit(void); 704 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 705 706 /** 707 * @} 708 */ 709 710 /** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions 711 * @{ 712 */ 713 714 /* Peripheral Control functions ************************************************/ 715 void HAL_IncTick(void); 716 void HAL_Delay(uint32_t Delay); 717 uint32_t HAL_GetTick(void); 718 uint32_t HAL_GetTickPrio(void); 719 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 720 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 721 void HAL_SuspendTick(void); 722 void HAL_ResumeTick(void); 723 uint32_t HAL_GetHalVersion(void); 724 uint32_t HAL_GetREVID(void); 725 uint32_t HAL_GetDEVID(void); 726 uint32_t HAL_GetUIDw0(void); 727 uint32_t HAL_GetUIDw1(void); 728 uint32_t HAL_GetUIDw2(void); 729 730 /** 731 * @} 732 */ 733 734 /** @addtogroup HAL_Exported_Functions_Group3 HAL Debug functions 735 * @{ 736 */ 737 738 /* DBGMCU Peripheral Control functions *****************************************/ 739 void HAL_DBGMCU_EnableDBGStopMode(void); 740 void HAL_DBGMCU_DisableDBGStopMode(void); 741 void HAL_DBGMCU_EnableDBGStandbyMode(void); 742 void HAL_DBGMCU_DisableDBGStandbyMode(void); 743 744 /** 745 * @} 746 */ 747 748 /** @addtogroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions 749 * @{ 750 */ 751 752 /* SYSCFG Control functions ****************************************************/ 753 void HAL_SYSCFG_SRAM2Erase(void); 754 755 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 756 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); 757 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 758 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); 759 void HAL_SYSCFG_DisableVREFBUF(void); 760 #ifdef SYSCFG_OTGHSPHYCR_EN 761 void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClkSelection); 762 void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig); 763 void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig); 764 void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold); 765 void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold); 766 void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent); 767 #endif /* SYSCFG_OTGHSPHYCR_EN */ 768 void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); 769 void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); 770 void HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection(void); 771 void HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection(void); 772 void HAL_SYSCFG_EnableSRAMCached(void); 773 void HAL_SYSCFG_DisableSRAMCached(void); 774 void HAL_SYSCFG_EnableVddCompensationCell(void); 775 void HAL_SYSCFG_EnableVddIO2CompensationCell(void); 776 #if defined(SYSCFG_CCCSR_EN3) 777 void HAL_SYSCFG_EnableVddHSPICompensationCell(void); 778 #endif /* SYSCFG_CCCSR_EN3 */ 779 void HAL_SYSCFG_DisableVddCompensationCell(void); 780 void HAL_SYSCFG_DisableVddIO2CompensationCell(void); 781 #if defined(SYSCFG_CCCSR_EN3) 782 void HAL_SYSCFG_DisableVddHSPICompensationCell(void); 783 #endif /* SYSCFG_CCCSR_EN3 */ 784 /** 785 * @} 786 */ 787 788 /** @addtogroup HAL_Exported_Functions_Group5 HAL SYSCFG lock management functions 789 * @{ 790 */ 791 792 /* SYSCFG Lock functions ********************************************/ 793 void HAL_SYSCFG_Lock(uint32_t Item); 794 HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem); 795 796 /** 797 * @} 798 */ 799 800 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 801 802 /** @addtogroup HAL_Exported_Functions_Group6 HAL SYSCFG attributes management functions 803 * @{ 804 */ 805 806 /* SYSCFG Attributes functions ********************************************/ 807 void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes); 808 HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 809 810 /** 811 * @} 812 */ 813 814 #endif /* __ARM_FEATURE_CMSE */ 815 816 /** 817 * @} 818 */ 819 820 /** 821 * @} 822 */ 823 824 /** 825 * @} 826 */ 827 828 #ifdef __cplusplus 829 } 830 #endif 831 832 #endif /* __STM32U5xx_HAL_H */ 833
