TIM_DCR_DBSS_1 (reference) in projects: hal_stm32-3.7.0

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Searched refs:TIM_DCR_DBSS_1 (Results 1 – 25 of 34) sorted by relevance

/hal_stm32-3.7.0/stm32cube/stm32u5xx/drivers/src/
D	stm32u5xx_hal_tim.c	4857 tmpDBSS = TIM_DCR_DBSS_1; in HAL_TIM_DMABurst_MultiWriteStart() 4877 tmpDBSS = (TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart() 4937 tmpDBSS = (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiWriteStart() 4957 tmpDBSS = (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart() 5311 tmpDBSS = TIM_DCR_DBSS_1; in HAL_TIM_DMABurst_MultiReadStart() 5331 tmpDBSS = (TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart() 5391 tmpDBSS = (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiReadStart() 5411 tmpDBSS = (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart()
/hal_stm32-3.7.0/stm32cube/stm32h7rsxx/drivers/src/
D	stm32h7rsxx_hal_tim.c	4847 tmpDBSS = TIM_DCR_DBSS_1; in HAL_TIM_DMABurst_MultiWriteStart() 4867 tmpDBSS = (TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart() 4927 tmpDBSS = (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiWriteStart() 4947 tmpDBSS = (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart() 5299 tmpDBSS = TIM_DCR_DBSS_1; in HAL_TIM_DMABurst_MultiReadStart() 5319 tmpDBSS = (TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart() 5379 tmpDBSS = (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiReadStart() 5399 tmpDBSS = (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart()
/hal_stm32-3.7.0/stm32cube/stm32h5xx/drivers/src/
D	stm32h5xx_hal_tim.c	4857 tmpDBSS = TIM_DCR_DBSS_1; in HAL_TIM_DMABurst_MultiWriteStart() 4877 tmpDBSS = (TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart() 4937 tmpDBSS = (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiWriteStart() 4957 tmpDBSS = (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart() 5311 tmpDBSS = TIM_DCR_DBSS_1; in HAL_TIM_DMABurst_MultiReadStart() 5331 tmpDBSS = (TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart() 5391 tmpDBSS = (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiReadStart() 5411 tmpDBSS = (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart()
/hal_stm32-3.7.0/stm32cube/stm32wbaxx/drivers/src/
D	stm32wbaxx_hal_tim.c	4857 tmpDBSS = TIM_DCR_DBSS_1; in HAL_TIM_DMABurst_MultiWriteStart() 4877 tmpDBSS = (TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart() 4937 tmpDBSS = (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiWriteStart() 4957 tmpDBSS = (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart() 5311 tmpDBSS = TIM_DCR_DBSS_1; in HAL_TIM_DMABurst_MultiReadStart() 5331 tmpDBSS = (TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart() 5391 tmpDBSS = (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiReadStart() 5411 tmpDBSS = (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart()
/hal_stm32-3.7.0/stm32cube/stm32h5xx/drivers/include/
D	stm32h5xx_ll_tim.h	`1357 #define LL_TIM_DMA_CC1 TIM_DCR_DBSS_1 … 1358 #define LL_TIM_DMA_CC2 (TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0) … 1361 #define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1) … 1362 #define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0) …`
/hal_stm32-3.7.0/stm32cube/stm32h7rsxx/drivers/include/
D	stm32h7rsxx_ll_tim.h	`1318 #define LL_TIM_DMA_CC1 TIM_DCR_DBSS_1 … 1319 #define LL_TIM_DMA_CC2 (TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0) … 1322 #define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1) … 1323 #define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0) …`
/hal_stm32-3.7.0/stm32cube/stm32wbaxx/drivers/include/
D	stm32wbaxx_ll_tim.h	`1279 #define LL_TIM_DMA_CC1 TIM_DCR_DBSS_1 … 1280 #define LL_TIM_DMA_CC2 (TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0) … 1283 #define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1) … 1284 #define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0) …`
/hal_stm32-3.7.0/stm32cube/stm32u5xx/drivers/include/
D	stm32u5xx_ll_tim.h	`1426 #define LL_TIM_DMA_CC1 TIM_DCR_DBSS_1 … 1427 #define LL_TIM_DMA_CC2 (TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0) … 1430 #define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1) … 1431 #define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 \| TIM_DCR_DBSS_1 \| TIM_DCR_DBSS_0) …`
/hal_stm32-3.7.0/stm32cube/stm32wbaxx/soc/
D	stm32wba50xx.h	`8903 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro`
D	stm32wba52xx.h	`13070 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro`
D	stm32wba54xx.h	`13778 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro`
D	stm32wba55xx.h	`13796 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro`
/hal_stm32-3.7.0/stm32cube/stm32h5xx/soc/
D	stm32h503xx.h	`7394 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro`
D	stm32h523xx.h	`9835 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro`
D	stm32h562xx.h	`10541 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro`
D	stm32h533xx.h	`10243 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro`
D	stm32h563xx.h	`12625 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro`
D	stm32h573xx.h	`13033 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro`
/hal_stm32-3.7.0/stm32cube/stm32h7rsxx/soc/
D	stm32h7r3xx.h	`20263 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro`
D	stm32h7s3xx.h	`21146 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro`
D	stm32h7s7xx.h	`21578 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro`
D	stm32h7r7xx.h	`20693 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro`
/hal_stm32-3.7.0/stm32cube/stm32u5xx/soc/
D	stm32u535xx.h	`10535 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro`
D	stm32u545xx.h	`10935 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro`
D	stm32u575xx.h	`11557 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
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babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
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