Searched refs:TIM_AF1_ETRSEL_3 (Results 1 – 14 of 14) sorted by relevance
115 #define TIM_TIM1_ETR_ADC2_AWD3 (TIM_AF1_ETRSEL_3) /*!…124 #define TIM_TIM2_ETR_LTDC_VSYNC (TIM_AF1_ETRSEL_3) /*!…125 #define TIM_TIM2_ETR_TIM3_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1) /*!…126 #define TIM_TIM2_ETR_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!…127 #define TIM_TIM2_ETR_TIM5_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!…128 #define TIM_TIM2_ETR_ETH_PPS (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!…135 #define TIM_TIM3_ETR_LTDC_VSYNC (TIM_AF1_ETRSEL_3) /*!…136 #define TIM_TIM3_ETR_TIM2_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) /*!…137 #define TIM_TIM3_ETR_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!…138 #define TIM_TIM3_ETR_TIM5_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!…[all …]
1038 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD3 TIM_AF1_ETRSEL_3 …1053 #define LL_TIM_TIM2_ETRSOURCE_LTDC_VSYNC TIM_AF1_ETRSEL_3 …1054 #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1) …1055 #define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0…1056 #define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) …1057 #define LL_TIM_TIM2_ETRSOURCE_ETH_PPS (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0…1070 #define LL_TIM_TIM3_ETRSOURCE_LTDC_VSYNC TIM_AF1_ETRSEL_3 …1071 #define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) …1072 #define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0…1073 #define LL_TIM_TIM3_ETRSOURCE_TIM5_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) …[all …]
113 #define TIM_TIM1_ETR_ADC4_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!…114 #define TIM_TIM1_ETR_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!…115 #define TIM_TIM1_ETR_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!…121 #define TIM_TIM2_ETR_TIM3_ETR TIM_AF1_ETRSEL_3 /*!…122 #define TIM_TIM2_ETR_LSE (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!…128 #define TIM_TIM3_ETR_TIM2_ETR TIM_AF1_ETRSEL_3 /*!…129 #define TIM_TIM3_ETR_ADC4_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1| TIM_AF1_ETRSEL_0) /*!…130 #define TIM_TIM3_ETR_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!…131 #define TIM_TIM3_ETR_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!…
1030 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) …1031 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) …1032 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) …1046 #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR TIM_AF1_ETRSEL_3 …1047 #define LL_TIM_TIM2_ETRSOURCE_LSE (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)…1061 #define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR TIM_AF1_ETRSEL_3 …1062 #define LL_TIM_TIM3_ETRSOURCE_ADC4_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)…1063 #define LL_TIM_TIM3_ETRSOURCE_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) …1064 #define LL_TIM_TIM3_ETRSOURCE_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0)…
6067 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
5907 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
8956 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000… macro
13123 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000… macro
13831 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000… macro
13849 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000… macro
20280 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
21163 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
21595 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
20710 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro