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Searched refs:SPI_CR2_ERRIE (Results 1 – 25 of 247) sorted by relevance

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/hal_stm32-3.7.0/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_ll_spi.h139 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable …
1088 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_EnableIT_ERR()
1122 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_DisableIT_ERR()
1155 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); in LL_SPI_IsEnabledIT_ERR()
/hal_stm32-3.7.0/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_spi.h139 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable …
1088 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_EnableIT_ERR()
1122 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_DisableIT_ERR()
1155 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); in LL_SPI_IsEnabledIT_ERR()
/hal_stm32-3.7.0/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_ll_spi.h139 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable …
1088 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_EnableIT_ERR()
1122 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_DisableIT_ERR()
1155 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); in LL_SPI_IsEnabledIT_ERR()
/hal_stm32-3.7.0/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_ll_spi.h139 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable …
884 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_EnableIT_ERR()
918 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_DisableIT_ERR()
951 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); in LL_SPI_IsEnabledIT_ERR()
Dstm32f2xx_hal_i2s.h257 #define I2S_IT_ERR SPI_CR2_ERRIE
/hal_stm32-3.7.0/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_ll_spi.h139 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable …
891 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_EnableIT_ERR()
925 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_DisableIT_ERR()
958 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); in LL_SPI_IsEnabledIT_ERR()
Dstm32l1xx_hal_i2s.h255 #define I2S_IT_ERR SPI_CR2_ERRIE
/hal_stm32-3.7.0/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_ll_spi.h139 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable …
884 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_EnableIT_ERR()
918 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_DisableIT_ERR()
951 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); in LL_SPI_IsEnabledIT_ERR()
/hal_stm32-3.7.0/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_ll_spi.h139 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable …
839 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_EnableIT_ERR()
873 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_DisableIT_ERR()
906 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); in LL_SPI_IsEnabledIT_ERR()
Dstm32f1xx_hal_i2s.h255 #define I2S_IT_ERR SPI_CR2_ERRIE
/hal_stm32-3.7.0/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_ll_spi.h139 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable …
884 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_EnableIT_ERR()
918 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_DisableIT_ERR()
951 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); in LL_SPI_IsEnabledIT_ERR()
Dstm32l0xx_hal_i2s.h255 #define I2S_IT_ERR SPI_CR2_ERRIE
/hal_stm32-3.7.0/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_ll_spi.h139 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable …
1088 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_EnableIT_ERR()
1122 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_DisableIT_ERR()
1155 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); in LL_SPI_IsEnabledIT_ERR()
Dstm32f7xx_hal_i2s.h257 #define I2S_IT_ERR SPI_CR2_ERRIE
/hal_stm32-3.7.0/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_ll_spi.h139 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable …
1088 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_EnableIT_ERR()
1122 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_DisableIT_ERR()
1155 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); in LL_SPI_IsEnabledIT_ERR()
Dstm32c0xx_hal_i2s.h255 #define I2S_IT_ERR SPI_CR2_ERRIE
/hal_stm32-3.7.0/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_ll_spi.h139 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable …
1088 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_EnableIT_ERR()
1122 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_DisableIT_ERR()
1155 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); in LL_SPI_IsEnabledIT_ERR()
Dstm32f0xx_hal_i2s.h255 #define I2S_IT_ERR SPI_CR2_ERRIE
/hal_stm32-3.7.0/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_ll_spi.h139 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable …
1088 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_EnableIT_ERR()
1122 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_DisableIT_ERR()
1155 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); in LL_SPI_IsEnabledIT_ERR()
Dstm32f3xx_hal_i2s.h272 #define I2S_IT_ERR SPI_CR2_ERRIE
/hal_stm32-3.7.0/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_spi.h139 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable …
1088 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_EnableIT_ERR()
1122 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_DisableIT_ERR()
1155 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); in LL_SPI_IsEnabledIT_ERR()
Dstm32g4xx_hal_i2s.h255 #define I2S_IT_ERR SPI_CR2_ERRIE
/hal_stm32-3.7.0/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_spi.h139 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable …
1088 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_EnableIT_ERR()
1122 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_DisableIT_ERR()
1155 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); in LL_SPI_IsEnabledIT_ERR()
Dstm32wlxx_hal_i2s.h254 #define I2S_IT_ERR SPI_CR2_ERRIE
/hal_stm32-3.7.0/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_ll_spi.h139 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable …
1088 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_EnableIT_ERR()
1122 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); in LL_SPI_DisableIT_ERR()
1155 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); in LL_SPI_IsEnabledIT_ERR()

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