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Searched refs:RI_HYSCR4_PG_Pos (Results 1 – 16 of 16) sorted by relevance

/hal_stm32-3.7.0/stm32cube/stm32l1xx/soc/
Dstm32l100xc.h5958 #define RI_HYSCR4_PG_Pos (0U) macro
5959 #define RI_HYSCR4_PG_Msk (0xFFFFUL << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */
5961 #define RI_HYSCR4_PG_0 (0x0001UL << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */
5962 #define RI_HYSCR4_PG_1 (0x0002UL << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */
5963 #define RI_HYSCR4_PG_2 (0x0004UL << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */
5964 #define RI_HYSCR4_PG_3 (0x0008UL << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */
5965 #define RI_HYSCR4_PG_4 (0x0010UL << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */
5966 #define RI_HYSCR4_PG_5 (0x0020UL << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */
5967 #define RI_HYSCR4_PG_6 (0x0040UL << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */
5968 #define RI_HYSCR4_PG_7 (0x0080UL << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */
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Dstm32l151xc.h6147 #define RI_HYSCR4_PG_Pos (0U) macro
6148 #define RI_HYSCR4_PG_Msk (0xFFFFUL << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */
6150 #define RI_HYSCR4_PG_0 (0x0001UL << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */
6151 #define RI_HYSCR4_PG_1 (0x0002UL << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */
6152 #define RI_HYSCR4_PG_2 (0x0004UL << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */
6153 #define RI_HYSCR4_PG_3 (0x0008UL << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */
6154 #define RI_HYSCR4_PG_4 (0x0010UL << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */
6155 #define RI_HYSCR4_PG_5 (0x0020UL << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */
6156 #define RI_HYSCR4_PG_6 (0x0040UL << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */
6157 #define RI_HYSCR4_PG_7 (0x0080UL << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */
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Dstm32l151xca.h6211 #define RI_HYSCR4_PG_Pos (0U) macro
6212 #define RI_HYSCR4_PG_Msk (0xFFFFUL << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */
6214 #define RI_HYSCR4_PG_0 (0x0001UL << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */
6215 #define RI_HYSCR4_PG_1 (0x0002UL << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */
6216 #define RI_HYSCR4_PG_2 (0x0004UL << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */
6217 #define RI_HYSCR4_PG_3 (0x0008UL << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */
6218 #define RI_HYSCR4_PG_4 (0x0010UL << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */
6219 #define RI_HYSCR4_PG_5 (0x0020UL << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */
6220 #define RI_HYSCR4_PG_6 (0x0040UL << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */
6221 #define RI_HYSCR4_PG_7 (0x0080UL << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */
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Dstm32l151xdx.h6276 #define RI_HYSCR4_PG_Pos (0U) macro
6277 #define RI_HYSCR4_PG_Msk (0xFFFFUL << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */
6279 #define RI_HYSCR4_PG_0 (0x0001UL << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */
6280 #define RI_HYSCR4_PG_1 (0x0002UL << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */
6281 #define RI_HYSCR4_PG_2 (0x0004UL << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */
6282 #define RI_HYSCR4_PG_3 (0x0008UL << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */
6283 #define RI_HYSCR4_PG_4 (0x0010UL << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */
6284 #define RI_HYSCR4_PG_5 (0x0020UL << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */
6285 #define RI_HYSCR4_PG_6 (0x0040UL << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */
6286 #define RI_HYSCR4_PG_7 (0x0080UL << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */
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Dstm32l151xe.h6276 #define RI_HYSCR4_PG_Pos (0U) macro
6277 #define RI_HYSCR4_PG_Msk (0xFFFFUL << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */
6279 #define RI_HYSCR4_PG_0 (0x0001UL << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */
6280 #define RI_HYSCR4_PG_1 (0x0002UL << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */
6281 #define RI_HYSCR4_PG_2 (0x0004UL << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */
6282 #define RI_HYSCR4_PG_3 (0x0008UL << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */
6283 #define RI_HYSCR4_PG_4 (0x0010UL << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */
6284 #define RI_HYSCR4_PG_5 (0x0020UL << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */
6285 #define RI_HYSCR4_PG_6 (0x0040UL << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */
6286 #define RI_HYSCR4_PG_7 (0x0080UL << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */
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Dstm32l152xc.h6276 #define RI_HYSCR4_PG_Pos (0U) macro
6277 #define RI_HYSCR4_PG_Msk (0xFFFFUL << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */
6279 #define RI_HYSCR4_PG_0 (0x0001UL << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */
6280 #define RI_HYSCR4_PG_1 (0x0002UL << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */
6281 #define RI_HYSCR4_PG_2 (0x0004UL << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */
6282 #define RI_HYSCR4_PG_3 (0x0008UL << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */
6283 #define RI_HYSCR4_PG_4 (0x0010UL << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */
6284 #define RI_HYSCR4_PG_5 (0x0020UL << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */
6285 #define RI_HYSCR4_PG_6 (0x0040UL << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */
6286 #define RI_HYSCR4_PG_7 (0x0080UL << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */
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Dstm32l152xca.h6361 #define RI_HYSCR4_PG_Pos (0U) macro
6362 #define RI_HYSCR4_PG_Msk (0xFFFFUL << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */
6364 #define RI_HYSCR4_PG_0 (0x0001UL << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */
6365 #define RI_HYSCR4_PG_1 (0x0002UL << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */
6366 #define RI_HYSCR4_PG_2 (0x0004UL << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */
6367 #define RI_HYSCR4_PG_3 (0x0008UL << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */
6368 #define RI_HYSCR4_PG_4 (0x0010UL << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */
6369 #define RI_HYSCR4_PG_5 (0x0020UL << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */
6370 #define RI_HYSCR4_PG_6 (0x0040UL << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */
6371 #define RI_HYSCR4_PG_7 (0x0080UL << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */
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Dstm32l152xdx.h6426 #define RI_HYSCR4_PG_Pos (0U) macro
6427 #define RI_HYSCR4_PG_Msk (0xFFFFUL << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */
6429 #define RI_HYSCR4_PG_0 (0x0001UL << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */
6430 #define RI_HYSCR4_PG_1 (0x0002UL << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */
6431 #define RI_HYSCR4_PG_2 (0x0004UL << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */
6432 #define RI_HYSCR4_PG_3 (0x0008UL << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */
6433 #define RI_HYSCR4_PG_4 (0x0010UL << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */
6434 #define RI_HYSCR4_PG_5 (0x0020UL << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */
6435 #define RI_HYSCR4_PG_6 (0x0040UL << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */
6436 #define RI_HYSCR4_PG_7 (0x0080UL << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */
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Dstm32l152xe.h6426 #define RI_HYSCR4_PG_Pos (0U) macro
6427 #define RI_HYSCR4_PG_Msk (0xFFFFUL << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */
6429 #define RI_HYSCR4_PG_0 (0x0001UL << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */
6430 #define RI_HYSCR4_PG_1 (0x0002UL << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */
6431 #define RI_HYSCR4_PG_2 (0x0004UL << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */
6432 #define RI_HYSCR4_PG_3 (0x0008UL << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */
6433 #define RI_HYSCR4_PG_4 (0x0010UL << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */
6434 #define RI_HYSCR4_PG_5 (0x0020UL << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */
6435 #define RI_HYSCR4_PG_6 (0x0040UL << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */
6436 #define RI_HYSCR4_PG_7 (0x0080UL << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */
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Dstm32l162xca.h6500 #define RI_HYSCR4_PG_Pos (0U) macro
6501 #define RI_HYSCR4_PG_Msk (0xFFFFUL << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */
6503 #define RI_HYSCR4_PG_0 (0x0001UL << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */
6504 #define RI_HYSCR4_PG_1 (0x0002UL << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */
6505 #define RI_HYSCR4_PG_2 (0x0004UL << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */
6506 #define RI_HYSCR4_PG_3 (0x0008UL << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */
6507 #define RI_HYSCR4_PG_4 (0x0010UL << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */
6508 #define RI_HYSCR4_PG_5 (0x0020UL << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */
6509 #define RI_HYSCR4_PG_6 (0x0040UL << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */
6510 #define RI_HYSCR4_PG_7 (0x0080UL << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */
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Dstm32l162xc.h6415 #define RI_HYSCR4_PG_Pos (0U) macro
6416 #define RI_HYSCR4_PG_Msk (0xFFFFUL << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */
6418 #define RI_HYSCR4_PG_0 (0x0001UL << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */
6419 #define RI_HYSCR4_PG_1 (0x0002UL << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */
6420 #define RI_HYSCR4_PG_2 (0x0004UL << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */
6421 #define RI_HYSCR4_PG_3 (0x0008UL << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */
6422 #define RI_HYSCR4_PG_4 (0x0010UL << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */
6423 #define RI_HYSCR4_PG_5 (0x0020UL << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */
6424 #define RI_HYSCR4_PG_6 (0x0040UL << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */
6425 #define RI_HYSCR4_PG_7 (0x0080UL << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */
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Dstm32l162xdx.h6565 #define RI_HYSCR4_PG_Pos (0U) macro
6566 #define RI_HYSCR4_PG_Msk (0xFFFFUL << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */
6568 #define RI_HYSCR4_PG_0 (0x0001UL << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */
6569 #define RI_HYSCR4_PG_1 (0x0002UL << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */
6570 #define RI_HYSCR4_PG_2 (0x0004UL << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */
6571 #define RI_HYSCR4_PG_3 (0x0008UL << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */
6572 #define RI_HYSCR4_PG_4 (0x0010UL << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */
6573 #define RI_HYSCR4_PG_5 (0x0020UL << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */
6574 #define RI_HYSCR4_PG_6 (0x0040UL << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */
6575 #define RI_HYSCR4_PG_7 (0x0080UL << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */
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Dstm32l162xe.h6565 #define RI_HYSCR4_PG_Pos (0U) macro
6566 #define RI_HYSCR4_PG_Msk (0xFFFFUL << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */
6568 #define RI_HYSCR4_PG_0 (0x0001UL << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */
6569 #define RI_HYSCR4_PG_1 (0x0002UL << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */
6570 #define RI_HYSCR4_PG_2 (0x0004UL << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */
6571 #define RI_HYSCR4_PG_3 (0x0008UL << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */
6572 #define RI_HYSCR4_PG_4 (0x0010UL << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */
6573 #define RI_HYSCR4_PG_5 (0x0020UL << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */
6574 #define RI_HYSCR4_PG_6 (0x0040UL << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */
6575 #define RI_HYSCR4_PG_7 (0x0080UL << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */
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Dstm32l151xd.h6911 #define RI_HYSCR4_PG_Pos (0U) macro
6912 #define RI_HYSCR4_PG_Msk (0xFFFFUL << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */
6914 #define RI_HYSCR4_PG_0 (0x0001UL << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */
6915 #define RI_HYSCR4_PG_1 (0x0002UL << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */
6916 #define RI_HYSCR4_PG_2 (0x0004UL << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */
6917 #define RI_HYSCR4_PG_3 (0x0008UL << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */
6918 #define RI_HYSCR4_PG_4 (0x0010UL << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */
6919 #define RI_HYSCR4_PG_5 (0x0020UL << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */
6920 #define RI_HYSCR4_PG_6 (0x0040UL << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */
6921 #define RI_HYSCR4_PG_7 (0x0080UL << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */
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Dstm32l152xd.h7061 #define RI_HYSCR4_PG_Pos (0U) macro
7062 #define RI_HYSCR4_PG_Msk (0xFFFFUL << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */
7064 #define RI_HYSCR4_PG_0 (0x0001UL << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */
7065 #define RI_HYSCR4_PG_1 (0x0002UL << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */
7066 #define RI_HYSCR4_PG_2 (0x0004UL << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */
7067 #define RI_HYSCR4_PG_3 (0x0008UL << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */
7068 #define RI_HYSCR4_PG_4 (0x0010UL << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */
7069 #define RI_HYSCR4_PG_5 (0x0020UL << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */
7070 #define RI_HYSCR4_PG_6 (0x0040UL << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */
7071 #define RI_HYSCR4_PG_7 (0x0080UL << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */
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Dstm32l162xd.h7200 #define RI_HYSCR4_PG_Pos (0U) macro
7201 #define RI_HYSCR4_PG_Msk (0xFFFFUL << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */
7203 #define RI_HYSCR4_PG_0 (0x0001UL << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */
7204 #define RI_HYSCR4_PG_1 (0x0002UL << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */
7205 #define RI_HYSCR4_PG_2 (0x0004UL << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */
7206 #define RI_HYSCR4_PG_3 (0x0008UL << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */
7207 #define RI_HYSCR4_PG_4 (0x0010UL << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */
7208 #define RI_HYSCR4_PG_5 (0x0020UL << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */
7209 #define RI_HYSCR4_PG_6 (0x0040UL << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */
7210 #define RI_HYSCR4_PG_7 (0x0080UL << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */
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