RCC_PLL1DIVR_PLL1R_Pos (reference) in projects: hal_stm32-3.7.0

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Searched refs:RCC_PLL1DIVR_PLL1R_Pos (Results 1 – 25 of 37) sorted by relevance

/hal_stm32-3.7.0/stm32cube/stm32wbaxx/drivers/src/
D	stm32wbaxx_hal_rcc.c	`819 ((RCC_OscInitStruct->PLL1.PLLR - 1u) << RCC_PLL1DIVR_PLL1R_Pos)); in HAL_RCC_OscConfig() 888 …(((tmpreg2 & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) != (RCC_OscInitStruct->PLL1.PLLR - 1u)… in HAL_RCC_OscConfig() 1425 pllr = ((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U; in HAL_RCC_GetPLL1RFreq() 1506 RCC_OscInitStruct->PLL1.PLLR = (((regvalue & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U); in HAL_RCC_GetOscConfig()`
/hal_stm32-3.7.0/stm32cube/stm32u5xx/drivers/src/
D	stm32u5xx_hal_rcc.c	`1283 RCC_PLL1DIVR_PLL1R_Pos) != (pRCC_OscInitStruct->PLL.PLLR - 1U))) in HAL_RCC_OscConfig() 1793 pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U); in HAL_RCC_GetSysClockFreq() 1940 …InitStruct->PLL.PLLR = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U); in HAL_RCC_GetOscConfig()`
/hal_stm32-3.7.0/stm32cube/stm32wbaxx/drivers/include/
D	stm32wbaxx_ll_rcc.h	`2309 …L1DIVR_PLL1R, ((PLLN - 1UL) << RCC_PLL1DIVR_PLL1N_Pos) \| ((PLLR - 1UL) << RCC_PLL1DIVR_PLL1R_Pos)); in LL_RCC_PLL1_ConfigDomain_PLL1R() 2459 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R, (PLL1R - 1UL) << RCC_PLL1DIVR_PLL1R_Pos); in LL_RCC_PLL1_SetR() 2470 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1UL); in LL_RCC_PLL1_GetR()`
D	stm32wbaxx_hal_rcc.h	`1981 …(((__PLL1R__) - 1U) << RCC_PLL1DIVR_PLL1R_Pos))); …`
/hal_stm32-3.7.0/stm32cube/stm32u5xx/soc/
D	system_stm32u5xx.c	`335 pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U ); in SystemCoreClockUpdate()`
D	system_stm32u5xx_s.c	`358 pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U ); in SystemCoreClockUpdate()`
D	stm32u535xx.h	14089 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro 14090 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x7F000000… 14092 #define RCC_PLL1DIVR_PLL1R_0 (0x001UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x01000000… 14093 #define RCC_PLL1DIVR_PLL1R_1 (0x002UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x02000000… 14094 #define RCC_PLL1DIVR_PLL1R_2 (0x004UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x04000000… 14095 #define RCC_PLL1DIVR_PLL1R_3 (0x008UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x08000000… 14096 #define RCC_PLL1DIVR_PLL1R_4 (0x010UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x10000000… 14097 #define RCC_PLL1DIVR_PLL1R_5 (0x020UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x20000000… 14098 #define RCC_PLL1DIVR_PLL1R_6 (0x040UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x40000000…
D	stm32u545xx.h	14602 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro 14603 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x7F000000… 14605 #define RCC_PLL1DIVR_PLL1R_0 (0x001UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x01000000… 14606 #define RCC_PLL1DIVR_PLL1R_1 (0x002UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x02000000… 14607 #define RCC_PLL1DIVR_PLL1R_2 (0x004UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x04000000… 14608 #define RCC_PLL1DIVR_PLL1R_3 (0x008UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x08000000… 14609 #define RCC_PLL1DIVR_PLL1R_4 (0x010UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x10000000… 14610 #define RCC_PLL1DIVR_PLL1R_5 (0x020UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x20000000… 14611 #define RCC_PLL1DIVR_PLL1R_6 (0x040UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x40000000…
D	stm32u575xx.h	15496 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro 15497 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x7F000000… 15499 #define RCC_PLL1DIVR_PLL1R_0 (0x001UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x01000000… 15500 #define RCC_PLL1DIVR_PLL1R_1 (0x002UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x02000000… 15501 #define RCC_PLL1DIVR_PLL1R_2 (0x004UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x04000000… 15502 #define RCC_PLL1DIVR_PLL1R_3 (0x008UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x08000000… 15503 #define RCC_PLL1DIVR_PLL1R_4 (0x010UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x10000000… 15504 #define RCC_PLL1DIVR_PLL1R_5 (0x020UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x20000000… 15505 #define RCC_PLL1DIVR_PLL1R_6 (0x040UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x40000000…
D	stm32u585xx.h	16058 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro 16059 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x7F000000… 16061 #define RCC_PLL1DIVR_PLL1R_0 (0x001UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x01000000… 16062 #define RCC_PLL1DIVR_PLL1R_1 (0x002UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x02000000… 16063 #define RCC_PLL1DIVR_PLL1R_2 (0x004UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x04000000… 16064 #define RCC_PLL1DIVR_PLL1R_3 (0x008UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x08000000… 16065 #define RCC_PLL1DIVR_PLL1R_4 (0x010UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x10000000… 16066 #define RCC_PLL1DIVR_PLL1R_5 (0x020UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x20000000… 16067 #define RCC_PLL1DIVR_PLL1R_6 (0x040UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x40000000…
/hal_stm32-3.7.0/stm32cube/stm32wbaxx/soc/
D	system_stm32wbaxx.c	`320 pllr = ((tmp2 & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U; in SystemCoreClockUpdate()`
D	system_stm32wbaxx_s.c	`342 pllr = ((tmp2 & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U; in SystemCoreClockUpdate()`
D	stm32wba50xx.h	6062 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro 6063 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x7F000000… 6065 #define RCC_PLL1DIVR_PLL1R_0 (0x01UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x01000000… 6066 #define RCC_PLL1DIVR_PLL1R_1 (0x02UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x02000000… 6067 #define RCC_PLL1DIVR_PLL1R_2 (0x04UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x04000000… 6068 #define RCC_PLL1DIVR_PLL1R_3 (0x08UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x08000000… 6069 #define RCC_PLL1DIVR_PLL1R_4 (0x10UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x10000000… 6070 #define RCC_PLL1DIVR_PLL1R_5 (0x20UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x20000000… 6071 #define RCC_PLL1DIVR_PLL1R_6 (0x40UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x40000000…
D	stm32wba52xx.h	9835 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro 9836 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x7F000000… 9838 #define RCC_PLL1DIVR_PLL1R_0 (0x01UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x01000000… 9839 #define RCC_PLL1DIVR_PLL1R_1 (0x02UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x02000000… 9840 #define RCC_PLL1DIVR_PLL1R_2 (0x04UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x04000000… 9841 #define RCC_PLL1DIVR_PLL1R_3 (0x08UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x08000000… 9842 #define RCC_PLL1DIVR_PLL1R_4 (0x10UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x10000000… 9843 #define RCC_PLL1DIVR_PLL1R_5 (0x20UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x20000000… 9844 #define RCC_PLL1DIVR_PLL1R_6 (0x40UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x40000000…
D	stm32wba54xx.h	10107 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro 10108 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x7F000000… 10110 #define RCC_PLL1DIVR_PLL1R_0 (0x01UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x01000000… 10111 #define RCC_PLL1DIVR_PLL1R_1 (0x02UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x02000000… 10112 #define RCC_PLL1DIVR_PLL1R_2 (0x04UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x04000000… 10113 #define RCC_PLL1DIVR_PLL1R_3 (0x08UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x08000000… 10114 #define RCC_PLL1DIVR_PLL1R_4 (0x10UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x10000000… 10115 #define RCC_PLL1DIVR_PLL1R_5 (0x20UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x20000000… 10116 #define RCC_PLL1DIVR_PLL1R_6 (0x40UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x40000000…
D	stm32wba55xx.h	10125 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro 10126 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x7F000000… 10128 #define RCC_PLL1DIVR_PLL1R_0 (0x01UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x01000000… 10129 #define RCC_PLL1DIVR_PLL1R_1 (0x02UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x02000000… 10130 #define RCC_PLL1DIVR_PLL1R_2 (0x04UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x04000000… 10131 #define RCC_PLL1DIVR_PLL1R_3 (0x08UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x08000000… 10132 #define RCC_PLL1DIVR_PLL1R_4 (0x10UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x10000000… 10133 #define RCC_PLL1DIVR_PLL1R_5 (0x20UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x20000000… 10134 #define RCC_PLL1DIVR_PLL1R_6 (0x40UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x40000000…
/hal_stm32-3.7.0/stm32cube/stm32h5xx/drivers/src/
D	stm32h5xx_hal_rcc.c	`962 RCC_PLL1DIVR_PLL1R_Pos) != (pOscInitStruct->PLL.PLLR - 1U))) in HAL_RCC_OscConfig() 1608 …pOscInitStruct->PLL.PLLR = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) +… in HAL_RCC_GetOscConfig()`
/hal_stm32-3.7.0/stm32cube/stm32u5xx/drivers/include/
D	stm32u5xx_ll_rcc.h	`3896 RCC_PLL1DIVR_PLL1R_Pos)); in LL_RCC_PLL1_ConfigDomain_SYS() 4065 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R, (PLL1R - 1UL) << RCC_PLL1DIVR_PLL1R_Pos); in LL_RCC_PLL1_SetR() 4077 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1UL); in LL_RCC_PLL1_GetR()`
/hal_stm32-3.7.0/stm32cube/stm32h5xx/soc/
D	stm32h503xx.h	8591 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro 8592 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x7F000000… 8594 #define RCC_PLL1DIVR_PLL1R_0 (0x001UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x01000000… 8595 #define RCC_PLL1DIVR_PLL1R_1 (0x002UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x02000000… 8596 #define RCC_PLL1DIVR_PLL1R_2 (0x004UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x04000000… 8597 #define RCC_PLL1DIVR_PLL1R_3 (0x008UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x08000000… 8598 #define RCC_PLL1DIVR_PLL1R_4 (0x010UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x10000000… 8599 #define RCC_PLL1DIVR_PLL1R_5 (0x020UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x20000000… 8600 #define RCC_PLL1DIVR_PLL1R_6 (0x040UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x40000000…
D	stm32h523xx.h	12769 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro 12770 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x7F000000… 12772 #define RCC_PLL1DIVR_PLL1R_0 (0x001UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x01000000… 12773 #define RCC_PLL1DIVR_PLL1R_1 (0x002UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x02000000… 12774 #define RCC_PLL1DIVR_PLL1R_2 (0x004UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x04000000… 12775 #define RCC_PLL1DIVR_PLL1R_3 (0x008UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x08000000… 12776 #define RCC_PLL1DIVR_PLL1R_4 (0x010UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x10000000… 12777 #define RCC_PLL1DIVR_PLL1R_5 (0x020UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x20000000… 12778 #define RCC_PLL1DIVR_PLL1R_6 (0x040UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x40000000…
D	stm32h562xx.h	13429 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro 13430 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x7F000000… 13432 #define RCC_PLL1DIVR_PLL1R_0 (0x001UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x01000000… 13433 #define RCC_PLL1DIVR_PLL1R_1 (0x002UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x02000000… 13434 #define RCC_PLL1DIVR_PLL1R_2 (0x004UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x04000000… 13435 #define RCC_PLL1DIVR_PLL1R_3 (0x008UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x08000000… 13436 #define RCC_PLL1DIVR_PLL1R_4 (0x010UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x10000000… 13437 #define RCC_PLL1DIVR_PLL1R_5 (0x020UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x20000000… 13438 #define RCC_PLL1DIVR_PLL1R_6 (0x040UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x40000000…
D	stm32h533xx.h	13287 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro 13288 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x7F000000… 13290 #define RCC_PLL1DIVR_PLL1R_0 (0x001UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x01000000… 13291 #define RCC_PLL1DIVR_PLL1R_1 (0x002UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x02000000… 13292 #define RCC_PLL1DIVR_PLL1R_2 (0x004UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x04000000… 13293 #define RCC_PLL1DIVR_PLL1R_3 (0x008UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x08000000… 13294 #define RCC_PLL1DIVR_PLL1R_4 (0x010UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x10000000… 13295 #define RCC_PLL1DIVR_PLL1R_5 (0x020UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x20000000… 13296 #define RCC_PLL1DIVR_PLL1R_6 (0x040UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x40000000…
D	stm32h563xx.h	15513 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro 15514 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x7F000000… 15516 #define RCC_PLL1DIVR_PLL1R_0 (0x001UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x01000000… 15517 #define RCC_PLL1DIVR_PLL1R_1 (0x002UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x02000000… 15518 #define RCC_PLL1DIVR_PLL1R_2 (0x004UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x04000000… 15519 #define RCC_PLL1DIVR_PLL1R_3 (0x008UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x08000000… 15520 #define RCC_PLL1DIVR_PLL1R_4 (0x010UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x10000000… 15521 #define RCC_PLL1DIVR_PLL1R_5 (0x020UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x20000000… 15522 #define RCC_PLL1DIVR_PLL1R_6 (0x040UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x40000000…
D	stm32h573xx.h	16031 #define RCC_PLL1DIVR_PLL1R_Pos (24U) macro 16032 #define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x7F000000… 16034 #define RCC_PLL1DIVR_PLL1R_0 (0x001UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x01000000… 16035 #define RCC_PLL1DIVR_PLL1R_1 (0x002UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x02000000… 16036 #define RCC_PLL1DIVR_PLL1R_2 (0x004UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x04000000… 16037 #define RCC_PLL1DIVR_PLL1R_3 (0x008UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x08000000… 16038 #define RCC_PLL1DIVR_PLL1R_4 (0x010UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x10000000… 16039 #define RCC_PLL1DIVR_PLL1R_5 (0x020UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x20000000… 16040 #define RCC_PLL1DIVR_PLL1R_6 (0x040UL << RCC_PLL1DIVR_PLL1R_Pos) /!< 0x40000000…
/hal_stm32-3.7.0/stm32cube/stm32h5xx/drivers/include/
D	stm32h5xx_ll_rcc.h	`4424 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R, (PLL1R - 1UL) << RCC_PLL1DIVR_PLL1R_Pos); in LL_RCC_PLL1_SetR() 4435 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1UL); in LL_RCC_PLL1_GetR()`

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hal_atmel-3.5.0-3.4.0
hal_atmel-3.6.0
hal_atmel-3.7.0
hal_cypress-2.7.6
hal_espressif-2.7.6
hal_espressif-3.4.0
hal_espressif-3.5.0
hal_espressif-3.6.0
hal_espressif-3.7.0
hal_ethos_u-3.6.0-3.5.0-3.4.0
hal_ethos_u-3.7.0
hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0
hal_infineon-2.7.6
hal_infineon-3.4.0
hal_infineon-3.5.0
hal_infineon-3.6.0
hal_infineon-3.7.0
hal_intel-3.5.0
hal_intel-3.6.0
hal_intel-3.7.0
hal_microchip-2.7.6
hal_microchip-3.6.0-3.5.0-3.4.0
hal_microchip-3.7.0
hal_nordic-2.7.6
hal_nordic-3.4.0
hal_nordic-3.5.0
hal_nordic-3.6.0
hal_nordic-3.7.0
hal_nuvoton-2.7.6
hal_nuvoton-3.4.0
hal_nuvoton-3.5.0
hal_nuvoton-3.6.0
hal_nuvoton-3.7.0
hal_nxp-2.7.6
hal_nxp-3.4.0
hal_nxp-3.5.0
hal_nxp-3.6.0
hal_nxp-3.7.0
hal_openisa-2.7.6
hal_openisa-3.5.0-3.4.0
hal_openisa-3.7.0-3.6.0
hal_quicklogic-3.6.0-3.5.0-3.4.0-2.7.6
hal_quicklogic-3.7.0
hal_renesas-3.4.0
hal_renesas-3.5.0
hal_renesas-3.6.0
hal_renesas-3.7.0
hal_rpi_pico-3.4.0
hal_rpi_pico-3.7.0-3.6.0-3.5.0
hal_silabs-2.7.6
hal_silabs-3.4.0
hal_silabs-3.5.0
hal_silabs-3.6.0
hal_silabs-3.7.0
hal_st-2.7.6
hal_st-3.4.0
hal_st-3.5.0
hal_st-3.6.0
hal_st-3.7.0
hal_stm32-2.7.6
hal_stm32-3.4.0
hal_stm32-3.5.0
hal_stm32-3.6.0
hal_stm32-3.7.0
hal_telink-2.7.6
hal_telink-3.6.0-3.5.0-3.4.0
hal_telink-3.7.0
hal_ti-2.7.6
hal_ti-3.4.0
hal_ti-3.7.0-3.6.0-3.5.0
hal_wurthelektronik-3.5.0-3.4.0
hal_wurthelektronik-3.7.0-3.6.0
hal_xtensa-2.7.6
hal_xtensa-3.4.0
hal_xtensa-3.5.0
hal_xtensa-3.6.0
hal_xtensa-3.7.0
hostap-3.6.0
hostap-3.7.0
liblc3-3.5.0-3.4.0
liblc3-3.7.0-3.6.0
libmetal-2.7.6
libmetal-3.5.0-3.4.0
libmetal-3.6.0
libmetal-3.7.0
littlefs-2.7.6
littlefs-3.5.0-3.4.0
littlefs-3.7.0-3.6.0
loramac-node-2.7.6
loramac-node-3.4.0
loramac-node-3.6.0-3.5.0
loramac-node-3.7.0
lvgl-2.7.6
lvgl-3.4.0
lvgl-3.5.0
lvgl-3.6.0
lvgl-3.7.0
lz4-3.4.0-2.7.6
mbedtls-2.7.6
mbedtls-3.4.0
mbedtls-3.5.0
mbedtls-3.6.0
mbedtls-3.7.0
mcuboot-2.7.6
mcuboot-3.4.0
mcuboot-3.5.0
mcuboot-3.6.0
mcuboot-3.7.0
mcumgr-2.7.6
mipi-sys-t-2.7.6
mipi-sys-t-3.4.0
mipi-sys-t-3.6.0-3.5.0
mipi-sys-t-3.7.0
nanopb-2.7.6
nanopb-3.4.0
net-tools-2.7.6
net-tools-3.4.0
net-tools-3.5.0
net-tools-3.6.0
net-tools-3.7.0
nrf_hw_models-2.7.6
nrf_hw_models-3.4.0
nrf_hw_models-3.5.0
nrf_hw_models-3.6.0
nrf_hw_models-3.7.0
open-amp-2.7.6
open-amp-3.4.0
open-amp-3.5.0
open-amp-3.6.0
open-amp-3.7.0
openthread-2.7.6
openthread-3.4.0
openthread-3.5.0
openthread-3.6.0
openthread-3.7.0
percepio-3.5.0
percepio-3.6.0
percepio-3.7.0
picolibc-3.5.0-3.4.0
picolibc-3.7.0-3.6.0
psa-arch-tests-3.4.0
segger-2.7.6
segger-3.4.0
segger-3.6.0-3.5.0
segger-3.7.0
sof-2.7.6
sof-3.4.0
tf-m-tests-3.4.0
tflite-micro-3.4.0-2.7.6
thrift-3.4.0
tinycbor-2.7.6
tinycrypt-3.6.0-3.5.0-3.4.0-2.7.6
tinycrypt-3.7.0
trusted-firmware-a-3.4.0
trusted-firmware-a-3.6.0-3.5.0
trusted-firmware-a-3.7.0
trusted-firmware-m-3.4.0
trusted-firmware-m-3.5.0
trusted-firmware-m-3.6.0
trusted-firmware-m-3.7.0
uoscore-uedhoc-3.4.0
uoscore-uedhoc-3.5.0
uoscore-uedhoc-3.6.0
uoscore-uedhoc-3.7.0
zcbor-3.5.0-3.4.0
zcbor-3.6.0
zcbor-3.7.0
zscilib-3.4.0