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Searched refs:RCC_PLL1CFGR_PLL1M (Results 1 – 25 of 39) sorted by relevance

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/hal_stm32-3.7.0/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_rcc.c810 …2 &= ~(RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1RGE | RCC_PLL1CFGR_PLL1FRACEN | RCC_PLL1CFGR_PLL1M); in HAL_RCC_OscConfig()
884 …(((tmpreg1 & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) != (RCC_OscInitStruct->PLL1.PLLM - 1u)… in HAL_RCC_OscConfig()
1489 RCC_OscInitStruct->PLL1.PLLM = (((regvalue & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U); in HAL_RCC_GetOscConfig()
1768 tmp = ((tmpreg1 & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U; in RCC_PLL1_GetVCOOutputFreq()
/hal_stm32-3.7.0/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_rcc.h2308 …MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | ((PLLM - 1UL) << RCC… in LL_RCC_PLL1_ConfigDomain_PLL1R()
2331 …MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | ((PLLM - 1UL) << RCC… in LL_RCC_PLL1_ConfigDomain_PLL1P()
2354 …MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | ((PLLM - 1UL) << RCC… in LL_RCC_PLL1_ConfigDomain_PLL1Q()
2480 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, (PLL1M - 1UL) << RCC_PLL1CFGR_PLL1M_Pos); in LL_RCC_PLL1_SetDivider()
2490 return (uint32_t)((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1UL); in LL_RCC_PLL1_GetDivider()
Dstm32wbaxx_hal_rcc.h1979 …MODIFY_REG(RCC->PLL1CFGR, (RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M), ((__PLL1SOURCE__) | (((__PL…
/hal_stm32-3.7.0/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_rcc.c954 ((READ_BIT(temp1_pllckcfg, RCC_PLL1CFGR_PLL1M) >> \ in HAL_RCC_OscConfig()
1432 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos); in HAL_RCC_GetSysClockFreq()
1605 pOscInitStruct->PLL.PLLM = (uint32_t)((reg1val & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos); in HAL_RCC_GetOscConfig()
Dstm32h5xx_hal_rcc_ex.c2790 pll1m = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos); in HAL_RCCEx_GetPLL1ClockFreq()
/hal_stm32-3.7.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_rcc.h3892 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | \ in LL_RCC_PLL1_ConfigDomain_SYS()
3920 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | \ in LL_RCC_PLL1_ConfigDomain_SAI()
3948 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | \ in LL_RCC_PLL1_ConfigDomain_48M()
4088 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, (PLL1M - 1UL) << RCC_PLL1CFGR_PLL1M_Pos); in LL_RCC_PLL1_SetDivider()
4099 return (uint32_t)((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1UL); in LL_RCC_PLL1_GetDivider()
Dstm32u5xx_hal_rcc.h4453 do{ MODIFY_REG(RCC->PLL1CFGR,(RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M|\
/hal_stm32-3.7.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_rcc.c1274 ((READ_BIT(temp1_pllckcfg, RCC_PLL1CFGR_PLL1M) >> \ in HAL_RCC_OscConfig()
1769 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U; in HAL_RCC_GetSysClockFreq()
1937 …pRCC_OscInitStruct->PLL.PLLM = (uint32_t)(((reg1val & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Po… in HAL_RCC_GetOscConfig()
Dstm32u5xx_hal_rcc_ex.c1509 pll1m = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U; in HAL_RCCEx_GetPLL1ClockFreq()
/hal_stm32-3.7.0/stm32cube/stm32u5xx/soc/
Dsystem_stm32u5xx.c311 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos) + 1U; in SystemCoreClockUpdate()
Dsystem_stm32u5xx_s.c334 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos) + 1U; in SystemCoreClockUpdate()
/hal_stm32-3.7.0/stm32cube/stm32wbaxx/soc/
Dsystem_stm32wbaxx.c318 pllm = ((tmp1 & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U; in SystemCoreClockUpdate()
Dsystem_stm32wbaxx_s.c340 pllm = ((tmp1 & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U; in SystemCoreClockUpdate()
Dstm32wba50xx.h6006 #define RCC_PLL1CFGR_PLL1M RCC_PLL1CFGR_PLL1M_Msk macro
Dstm32wba52xx.h9779 #define RCC_PLL1CFGR_PLL1M RCC_PLL1CFGR_PLL1M_Msk macro
Dstm32wba54xx.h10051 #define RCC_PLL1CFGR_PLL1M RCC_PLL1CFGR_PLL1M_Msk macro
Dstm32wba55xx.h10069 #define RCC_PLL1CFGR_PLL1M RCC_PLL1CFGR_PLL1M_Msk macro
/hal_stm32-3.7.0/stm32cube/stm32h5xx/soc/
Dsystem_stm32h5xx.c346 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos); in SystemCoreClockUpdate()
Dsystem_stm32h5xx_s.c360 pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos); in SystemCoreClockUpdate()
Dstm32h503xx.h8505 #define RCC_PLL1CFGR_PLL1M RCC_PLL1CFGR_PLL1M_Msk macro
Dstm32h523xx.h12647 #define RCC_PLL1CFGR_PLL1M RCC_PLL1CFGR_PLL1M_Msk macro
Dstm32h562xx.h13307 #define RCC_PLL1CFGR_PLL1M RCC_PLL1CFGR_PLL1M_Msk macro
Dstm32h533xx.h13165 #define RCC_PLL1CFGR_PLL1M RCC_PLL1CFGR_PLL1M_Msk macro
/hal_stm32-3.7.0/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_rcc.h4317 …MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | (PLL1M << RCC_PLL1CF… in LL_RCC_PLL1_ConfigDomain_SYS()
4445 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, PLL1M << RCC_PLL1CFGR_PLL1M_Pos); in LL_RCC_PLL1_SetM()
4455 return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos); in LL_RCC_PLL1_GetM()
Dstm32h5xx_hal_rcc.h4568 do{ MODIFY_REG(RCC->PLL1CFGR, (RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M), \
4601 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, (__PLL1M__) << RCC_PLL1CFGR_PLL1M_Pos)

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