RCC_CCIPR1_I2C1SEL (reference) in projects: hal_stm32-3.7.0

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Searched refs:RCC_CCIPR1_I2C1SEL (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-3.7.0/stm32cube/stm32wbaxx/drivers/include/
D	stm32wbaxx_hal_rcc_ex.h	`496 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL, (__I2C1_CLKSOURCE__)) 504 #define __HAL_RCC_GET_I2C1_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL)`
D	stm32wbaxx_ll_rcc.h	`563 … ((RCC_OFFSET_CCIPR1 << 24U) \| (RCC_CCIPR1_I2C1SEL_Pos << 16U) \| (RCC_CCIPR1_I2C1SEL >> RCC_CCIPR…`
/hal_stm32-3.7.0/stm32cube/stm32u5xx/drivers/include/
D	stm32u5xx_hal_rcc_ex.h	`1614 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) 1623 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL)))`
D	stm32u5xx_ll_rcc.h	`524 … (RCC_CCIPR1_I2C1SEL >> RCC_CCIPR1_I2C1SEL_Pos)) /!< MSIK clock used as I2C1 clock source / 880 … (RCC_CCIPR1_I2C1SEL >> RCC_CCIPR1_I2C1SEL_Pos)) /!< I2C1 Clock source selection /`
/hal_stm32-3.7.0/stm32cube/stm32l5xx/drivers/include/
D	stm32l5xx_hal_rcc_ex.h	`1041 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) 1049 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL)))`
D	stm32l5xx_ll_rcc.h	`590 …FSET_CCIPR1 << 24U) \| ((uint32_t)RCC_CCIPR1_I2C1SEL_Pos << 16U) \| (RCC_CCIPR1_I2C1SEL >> RCC_CCIPR…`
/hal_stm32-3.7.0/stm32cube/stm32wbaxx/drivers/src/
D	stm32wbaxx_hal_rcc_ex.c	`442 PeriphClkInit->I2c1ClockSelection = (tmpreg & RCC_CCIPR1_I2C1SEL); in HAL_RCCEx_GetPeriphCLKConfig()`
/hal_stm32-3.7.0/stm32cube/stm32wbaxx/soc/
D	stm32wba52xx.h	`10287 #define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk macro`
D	stm32wba54xx.h	`10595 #define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk macro`
D	stm32wba55xx.h	`10613 #define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk macro`
/hal_stm32-3.7.0/stm32cube/stm32l5xx/soc/
D	stm32l552xx.h	`12094 #define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk macro`
D	stm32l562xx.h	`12824 #define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk macro`
/hal_stm32-3.7.0/stm32cube/stm32u5xx/soc/
D	stm32u535xx.h	`15083 #define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk /*!< I2C1SEL[1… macro`
D	stm32u545xx.h	`15632 #define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk /*!< I2C1SEL[1… macro`
D	stm32u575xx.h	`16591 #define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk /*!< I2C1SEL[1… macro`
D	stm32u585xx.h	`17198 #define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk /*!< I2C1SEL[1… macro`
D	stm32u5f7xx.h	`19266 #define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk /*!< I2C1SEL[1… macro`
D	stm32u595xx.h	`17676 #define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk /*!< I2C1SEL[1… macro`
D	stm32u5a5xx.h	`18283 #define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk /*!< I2C1SEL[1… macro`
D	stm32u599xx.h	`21444 #define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk /*!< I2C1SEL[1… macro`
D	stm32u5g7xx.h	`19873 #define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk /*!< I2C1SEL[1… macro`
D	stm32u5g9xx.h	`23011 #define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk /*!< I2C1SEL[1… macro`
D	stm32u5f9xx.h	`22404 #define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk /*!< I2C1SEL[1… macro`
D	stm32u5a9xx.h	`22051 #define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk /*!< I2C1SEL[1… macro`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
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Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
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hal_nxp-2.7.6
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