1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WBAxx_LL_RCC_H
21 #define STM32WBAxx_LL_RCC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbaxx.h"
29
30 /** @addtogroup STM32WBAxx_LL_Driver
31 * @{
32 */
33
34 #if defined(RCC)
35
36 /** @defgroup RCC_LL RCC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
44 * @{
45 */
46 /* Defines used to perform offsets*/
47 /* Offset used to access to RCC_CCIPR1, RCC_CCIPR2 and RCC_CCIPR3 registers */
48 #define RCC_OFFSET_CCIPR1 0U
49 #define RCC_OFFSET_CCIPR2 0x04U
50 #define RCC_OFFSET_CCIPR3 0x08U
51
52 /* Defines used for security configuration extension */
53 #define RCC_SECURE_MASK 0x10FBU
54 /**
55 * @}
56 */
57
58 /* Private macros ------------------------------------------------------------*/
59 /* Exported types ------------------------------------------------------------*/
60 #if defined(USE_FULL_LL_DRIVER)
61 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
62 * @{
63 */
64
65 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
66 * @{
67 */
68
69 /**
70 * @brief RCC Clocks Frequency Structure
71 */
72 typedef struct
73 {
74 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
75 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
76 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
77 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
78 uint32_t PCLK7_Frequency; /*!< PCLK7 clock frequency */
79 } LL_RCC_ClocksTypeDef;
80
81 /**
82 * @}
83 */
84
85 /**
86 * @}
87 */
88 #endif /* USE_FULL_LL_DRIVER */
89
90 /* Exported constants --------------------------------------------------------*/
91 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
92 * @{
93 */
94
95 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
96 * @brief Defines used to adapt values of different oscillators
97 * @note These values could be modified in the user environment according to
98 * HW set-up.
99 * @{
100 */
101 #if !defined (HSE_VALUE)
102 #define HSE_VALUE 32000000U /*!< Value of the HSE oscillator in Hz */
103 #endif /* HSE_VALUE */
104
105 #if !defined (HSI_VALUE)
106 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
107 #endif /* HSI_VALUE */
108
109 #if !defined (LSE_VALUE)
110 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
111 #endif /* LSE_VALUE */
112
113 #if !defined (LSI_VALUE)
114 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
115 #endif /* LSI_VALUE */
116
117 #if defined (RCC_LSI2_SUPPORT)
118 #if !defined (LSI2_VALUE)
119 #define LSI2_VALUE 32000U /*!< Value of the LSI2 oscillator in Hz */
120 #endif /* LSI_VALUE */
121 #endif
122
123 #if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
124 #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */
125 #endif /* EXTERNAL_SAI1_CLOCK_VALUE */
126
127 /**
128 * @}
129 */
130
131 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
132 * @brief Flags defines which can be used with LL_RCC_WriteReg function
133 * @{
134 */
135 #define LL_RCC_CICR_LSI1RDYC RCC_CICR_LSI1RDYC /*!< LSI1 Ready Interrupt Clear */
136 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
137 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
138 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
139 #define LL_RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC /*!< PLL1 Ready Interrupt Clear */
140 #define LL_RCC_CICR_HSECSSC RCC_CICR_HSECSSC /*!< HSE Clock Security System Interrupt Clear */
141 #define LL_RCC_CICR_LSI2RDYC RCC_CICR_LSI2RDYC /*!< LSI2 Ready Interrupt Clear */
142 /**
143 * @}
144 */
145
146 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
147 * @brief Flags defines which can be used with LL_RCC_ReadReg function
148 * @{
149 */
150 #define LL_RCC_CIFR_LSI1RDYF RCC_CIFR_LSI1RDYF /*!< LSI1 Ready Interrupt flag */
151 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
152 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
153 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
154 #define LL_RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF /*!< PLL1 Ready Interrupt flag */
155 #define LL_RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF /*!< HSE Clock Security System Interrupt flag */
156 #define LL_RCC_CIFR_LSI2RDYF RCC_CIFR_LSI2RDYF /*!< LSI2 Ready Interrupt flag */
157 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< Option byte loader reset flag */
158 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< NRST pin reset flag */
159 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
160 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software reset flag */
161 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent watchdog reset flag */
162 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
163 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-power reset flag */
164 /**
165 * @}
166 */
167
168 /** @defgroup RCC_LL_EC_IT IT Defines
169 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
170 * @{
171 */
172 #define LL_RCC_CIER_LSI1RDYIE RCC_CIER_LSI1RDYIE /*!< LSI1 Ready Interrupt Enable */
173 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
174 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
175 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
176 #define LL_RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE /*!< PLL1 Ready Interrupt Enable */
177 #define LL_RCC_CIER_LSI2RDYIE RCC_CIER_LSI2RDYIE /*!< LSI2 Ready Interrupt Enable */
178 /**
179 * @}
180 */
181
182 /** @defgroup RCC_LL_EC_LSIPRE LSI prescaler
183 * @{
184 */
185 #define LL_RCC_LSI_DIV_1 0U /*!< LSI1 divided by 1 */
186 #define LL_RCC_LSI_DIV_128 RCC_BDCR1_LSI1PREDIV /*!< LSI1 divided by 128 */
187 /**
188 * @}
189 */
190
191 #if defined(RCC_BDCR2_LSI2CFG)
192 /** @defgroup RCC_LL_EC_LSI2CFG LSI2 oscillator temperature sensitivity configuration
193 * @{
194 */
195 #define LL_RCC_LSI2_TEMP_SENSITIVITY_80 0U /*!< LSI2 frequency temperature sensitivity is close to zero at +80 degrees C */
196 #define LL_RCC_LSI2_TEMP_SENSITIVITY_50 RCC_BDCR2_LSI2CFG_0 /*!< LSI2 frequency temperature sensitivity is close to zero at +50 degrees C */
197 #define LL_RCC_LSI2_TEMP_SENSITIVITY_20 RCC_BDCR2_LSI2CFG_1 /*!< LSI2 frequency temperature sensitivity is close to zero at +20 degrees C */
198 /**
199 * @}
200 */
201 #endif /* RCC_BDCR2_LSI2CFG */
202
203 #if defined(RCC_BDCR2_LSI2MODE)
204 /** @defgroup RCC_LL_EC_LSI2MODE LSI2 oscillator operating mode configuration
205 * @{
206 */
207 #define LL_RCC_LSI2_NOMINAL_MODE 0U /*!< LSI2 nominal power, high accuracy */
208 #define LL_RCC_LSI2_LOWPOWER_MODE RCC_BDCR2_LSI2MODE_0 /*!< LSI2 low power, medium accuracy */
209 #define LL_RCC_LSI2_ULTRALOWPOWER_MODE RCC_BDCR2_LSI2MODE_1 /*!< LSI2 ultra low power, low accuracy */
210 /**
211 * @}
212 */
213 #endif /* RCC_BDCR2_LSI2MODE */
214
215 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
216 * @{
217 */
218 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR1_LSEDRV_0 /*!< Xtal mode medium low driving capability */
219 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR1_LSEDRV_1 /*!< Xtal mode medium high driving capability */
220 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR1_LSEDRV /*!< Xtal mode higher driving capability */
221 /**
222 * @}
223 */
224
225 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
226 * @{
227 */
228 #define LL_RCC_LSCO_CLKSOURCE_LSI 0U /*!< LSI selection for low speed clock */
229 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR1_LSCOSEL /*!< LSE selection for low speed clock */
230 /**
231 * @}
232 */
233
234
235 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
236 * @{
237 */
238 #define LL_RCC_SYS_CLKSOURCE_HSI 0U /*!< HSI selection as system clock */
239 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE selection as system clock */
240 #define LL_RCC_SYS_CLKSOURCE_PLL1R (RCC_CFGR1_SW_1 | RCC_CFGR1_SW_0) /*!< PLL1R selection as system clock */
241 /**
242 * @}
243 */
244
245
246 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
247 * @{
248 */
249 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI 0U /*!< HSI used as system clock */
250 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE used as system clock */
251 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1R (RCC_CFGR1_SWS_1 | RCC_CFGR1_SWS_0) /*!< PLL1R used as system clock */
252 /**
253 * @}
254 */
255
256
257 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
258 * @{
259 */
260 #define LL_RCC_SYSCLK_DIV_1 0U /*!< SYSCLK not divided */
261 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR2_HPRE_2 /*!< SYSCLK divided by 2 */
262 #define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 4 */
263 #define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1) /*!< SYSCLK divided by 8 */
264 #define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 16 */
265 /**
266 * @}
267 */
268
269
270 /** @defgroup RCC_LL_EC_SYSTICK_CLKSOURCE SYSTICK clock source selection
271 * @{
272 */
273 #define LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 0U /*!< HCLKDIV8 clock used as SYSTICK clock source */
274 #define LL_RCC_SYSTICK_CLKSOURCE_LSI RCC_CCIPR1_SYSTICKSEL_0 /*!< LSI clock used as SYSTICK clock source */
275 #define LL_RCC_SYSTICK_CLKSOURCE_LSE RCC_CCIPR1_SYSTICKSEL_1 /*!< LSE clock used as SYSTICK clock source */
276 /**
277 * @}
278 */
279
280 /** @defgroup RCC_LL_EC_APB1_DIV APB1 prescaler
281 * @{
282 */
283 #define LL_RCC_APB1_DIV_1 0U /*!< HCLK not divided */
284 #define LL_RCC_APB1_DIV_2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */
285 #define LL_RCC_APB1_DIV_4 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 4 */
286 #define LL_RCC_APB1_DIV_8 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1) /*!< HCLK divided by 8 */
287 #define LL_RCC_APB1_DIV_16 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 16 */
288 /**
289 * @}
290 */
291
292
293 /** @defgroup RCC_LL_EC_APB2_DIV APB2 prescaler
294 * @{
295 */
296 #define LL_RCC_APB2_DIV_1 0U /*!< HCLK not divided */
297 #define LL_RCC_APB2_DIV_2 RCC_CFGR2_PPRE2_2 /*!< HCLK divided by 2 */
298 #define LL_RCC_APB2_DIV_4 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 4 */
299 #define LL_RCC_APB2_DIV_8 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1) /*!< HCLK divided by 8 */
300 #define LL_RCC_APB2_DIV_16 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 16 */
301 /**
302 * @}
303 */
304
305 /** @defgroup RCC_LL_EC_APB7_DIV APB7 prescaler
306 * @{
307 */
308 #define LL_RCC_APB7_DIV_1 0U /*!< HCLK not divided */
309 #define LL_RCC_APB7_DIV_2 RCC_CFGR3_PPRE7_2 /*!< HCLK divided by 2 */
310 #define LL_RCC_APB7_DIV_4 (RCC_CFGR3_PPRE7_2 | RCC_CFGR3_PPRE7_0) /*!< HCLK divided by 4 */
311 #define LL_RCC_APB7_DIV_8 (RCC_CFGR3_PPRE7_2 | RCC_CFGR3_PPRE7_1) /*!< HCLK divided by 8 */
312 #define LL_RCC_APB7_DIV_16 (RCC_CFGR3_PPRE7_2 | RCC_CFGR3_PPRE7_1 | RCC_CFGR3_PPRE7_0) /*!< HCLK divided by 16 */
313 /**
314 * @}
315 */
316
317 /** @defgroup RCC_LL_EC_AHB5_DIV AHB5 prescaler when SYSCLK is PLL1R
318 * @{
319 */
320 #define LL_RCC_AHB5_DIV_1 0U /*!< SYSCLK not divided */
321 #define LL_RCC_AHB5_DIV_2 RCC_CFGR4_HPRE5_2 /*!< SYSCLK divided by 2 */
322 #define LL_RCC_AHB5_DIV_3 (RCC_CFGR4_HPRE5_2 | RCC_CFGR4_HPRE5_0) /*!< SYSCLK divided by 3 */
323 #define LL_RCC_AHB5_DIV_4 (RCC_CFGR4_HPRE5_2 | RCC_CFGR4_HPRE5_1) /*!< SYSCLK divided by 4 */
324 #define LL_RCC_AHB5_DIV_6 (RCC_CFGR4_HPRE5_2 | RCC_CFGR4_HPRE5_1 | RCC_CFGR4_HPRE5_0) /*!< SYSCLK divided by 6 */
325 /**
326 * @}
327 */
328
329 /** @defgroup RCC_LL_EC_AHB5_DIVIDER AHB5 divider when SYSCLK is HSI or HSE
330 * @{
331 */
332 #define LL_RCC_AHB5_DIVIDER_1 0U /*!< SYSCLK not divided */
333 #define LL_RCC_AHB5_DIVIDER_2 RCC_CFGR4_HDIV5 /*!< SYSCLK divided by 2 */
334 /**
335 * @}
336 */
337
338 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
339 * @{
340 */
341 #define LL_RCC_MCO1SOURCE_NOCLOCK 0U /*!< MCO output disabled, no clock on MCO */
342 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR1_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
343 #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_1) /*!< HSI selection as MCO1 source */
344 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR1_MCOSEL_2 /*!< HSE selection as MCO1 source */
345 #define LL_RCC_MCO1SOURCE_PLL1R (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_2) /*!< PLL1RCLK selection as MCO1 source */
346 #define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR1_MCOSEL_1 | RCC_CFGR1_MCOSEL_2) /*!< LSI selection as MCO1 source */
347 #define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_1| RCC_CFGR1_MCOSEL_2)/*!< LSE selection as MCO1 source */
348 #define LL_RCC_MCO1SOURCE_PLL1P RCC_CFGR1_MCOSEL_3 /*!< PLL1PCLK selection as MCO1 source */
349 #define LL_RCC_MCO1SOURCE_PLL1Q (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_3) /*!< PLL1QCLK selection as MCO1 source */
350 #define LL_RCC_MCO1SOURCE_HCLK5 (RCC_CFGR1_MCOSEL_1 | RCC_CFGR1_MCOSEL_3) /*!< HCLK5 selection as MCO1 source */
351 /**
352 * @}
353 */
354
355 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
356 * @{
357 */
358 #define LL_RCC_MCO1_DIV_1 0U /*!< MCO not divided */
359 #define LL_RCC_MCO1_DIV_2 RCC_CFGR1_MCOPRE_0 /*!< MCO divided by 2 */
360 #define LL_RCC_MCO1_DIV_4 RCC_CFGR1_MCOPRE_1 /*!< MCO divided by 4 */
361 #define LL_RCC_MCO1_DIV_8 (RCC_CFGR1_MCOPRE_1 | RCC_CFGR1_MCOPRE_0) /*!< MCO divided by 8 */
362 #define LL_RCC_MCO1_DIV_16 RCC_CFGR1_MCOPRE_2 /*!< MCO divided by 16 */
363 /**
364 * @}
365 */
366
367 #if defined(USE_FULL_LL_DRIVER)
368 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
369 * @{
370 */
371 #define LL_RCC_PERIPH_FREQUENCY_NO 0U /*!< No clock enabled for the peripheral */
372 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
373 /**
374 * @}
375 */
376 #endif /* USE_FULL_LL_DRIVER */
377
378 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
379 * @{
380 */
381 #define LL_RCC_RTC_CLKSOURCE_NONE 0U /*!< No clock used as RTC clock */
382 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR1_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
383 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR1_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
384 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR1_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
385 /**
386 * @}
387 */
388
389 /** @defgroup RCC_LL_EC_RADIO_SLEEPTIMER_CLKSOURCE RADIO Sleep Timer Clock source
390 * @{
391 */
392 #define LL_RCC_RADIOSLEEPSOURCE_NONE 0U /*!< No clock selected, 2.4 GHz RADIO sleep timer kernel clock disabled */
393 #define LL_RCC_RADIOSLEEPSOURCE_LSE RCC_BDCR1_RADIOSTSEL_0 /*!< LSE oscillator clock selected */
394 #define LL_RCC_RADIOSLEEPSOURCE_LSI RCC_BDCR1_RADIOSTSEL_1 /*!< LSI oscillator clock selected */
395 #define LL_RCC_RADIOSLEEPSOURCE_HSE_DIV1000 RCC_BDCR1_RADIOSTSEL /*!< HSE oscillator clock divided by 1000 selected */
396 /**
397 * @}
398 */
399
400 /** @defgroup RCC_LL_EC_USART_CLKSOURCE Peripheral USARTx clock source selection
401 * @{
402 */
403 #define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR1_USART1SEL << 16U) /*!< PCLK2 clock used as USART1 clock source */
404 #define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR1_USART1SEL << 16U) | RCC_CCIPR1_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
405 #define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR1_USART1SEL << 16U) | RCC_CCIPR1_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
406 #define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR1_USART1SEL << 16U) | RCC_CCIPR1_USART1SEL) /*!< LSE clock used as USART1 clock source */
407 #if defined(USART2)
408 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR1_USART2SEL << 16U) /*!< PCLK1 clock used as USART2 clock source */
409 #define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR1_USART2SEL << 16U) | RCC_CCIPR1_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
410 #define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR1_USART2SEL << 16U) | RCC_CCIPR1_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
411 #define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR1_USART2SEL << 16U) | RCC_CCIPR1_USART2SEL) /*!< LSE clock used as USART2 clock source */
412 #endif /* USART2 */
413 /**
414 * @}
415 */
416
417 /** @defgroup RCC_LL_EC_LPUART_CLKSOURCE Peripheral LPUARTx clock source selection
418 * @{
419 */
420 #define LL_RCC_LPUART1_CLKSOURCE_PCLK7 0U /*!< PCLK3 clock used as LPUART1 clock source */
421 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR3_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */
422 #define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR3_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */
423 #define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_1) /*!< LSE clock used as LPUART1 clock source */
424 /**
425 * @}
426 */
427
428 /** @defgroup RCC_LL_EC_I2C_CLKSOURCE Peripheral I2Cx clock source selection
429 * @{
430 */
431 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */
432 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL_0 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */
433 #define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL_1 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */
434 #define LL_RCC_I2C3_CLKSOURCE_PCLK7 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U)) /*!< PCLK7 clock used as I2C3 clock source */
435 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | (RCC_CCIPR3_I2C3SEL_0 >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */
436 #define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | (RCC_CCIPR3_I2C3SEL_1 >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */
437 /**
438 * @}
439 */
440
441 /** @defgroup RCC_LL_EC_SPI_CLKSOURCE Peripheral SPIx clock source selection
442 * @{
443 */
444 #if defined(SPI1)
445 #define LL_RCC_SPI1_CLKSOURCE_PCLK2 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U)) /*!< PCLK2 clock used as SPI1 clock source */
446 #define LL_RCC_SPI1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | (RCC_CCIPR1_SPI1SEL_0 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< SYSCLK clock used as SPI1 clock source */
447 #define LL_RCC_SPI1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | (RCC_CCIPR1_SPI1SEL_1 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< HSI clock used as SPI1 clock source */
448 #endif /* SPI1 */
449 #define LL_RCC_SPI3_CLKSOURCE_PCLK7 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U)) /*!< PCLK7 clock used as SPI3 clock source */
450 #define LL_RCC_SPI3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | (RCC_CCIPR3_SPI3SEL_0 >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< SYSCLK clock used as SPI3 clock source */
451 #define LL_RCC_SPI3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | (RCC_CCIPR3_SPI3SEL_1 >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< HSI clock used as SPI3 clock source */
452 /**
453 * @}
454 */
455
456 /** @defgroup RCC_LL_EC_LPTIM_CLKSOURCE Peripheral LPTIMx clock source selection
457 * @{
458 */
459 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK7 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U)) /*!< PCLK7 clock used as LPTIM1 clock source */
460 #define LL_RCC_LPTIM1_CLKSOURCE_LSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | (RCC_CCIPR3_LPTIM1SEL_0 >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LSI clock used as LPTIM1 clock source */
461 #define LL_RCC_LPTIM1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | (RCC_CCIPR3_LPTIM1SEL_1 >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< HSI clock used as LPTIM1 clock source */
462 #define LL_RCC_LPTIM1_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | (RCC_CCIPR3_LPTIM1SEL >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LSE clock used as LPTIM1 clock source */
463 #if defined(LPTIM2)
464 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U)) /*!< PCLK1 clock used as LPTIM2 clock source */
465 #define LL_RCC_LPTIM2_CLKSOURCE_LSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | (RCC_CCIPR1_LPTIM2SEL_0 >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LSI clock used as LPTIM2 clock source */
466 #define LL_RCC_LPTIM2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | (RCC_CCIPR1_LPTIM2SEL_1 >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< HSI clock used as LPTIM2 clock source */
467 #define LL_RCC_LPTIM2_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | (RCC_CCIPR1_LPTIM2SEL >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LSE clock used as LPTIM2 clock source */
468 #endif /* LPTIM2 */
469 /**
470 * @}
471 */
472
473 #if defined(SAI1)
474 /** @defgroup RCC_LL_EC_SAI_CLKSOURCE Peripheral SAIx clock source selection
475 * @{
476 */
477 #define LL_RCC_SAI1_CLKSOURCE_PLL1P (RCC_CCIPR2_SAI1SEL << 16U) /*!< PLL1P clock used as SAI1 clock source */
478 #define LL_RCC_SAI1_CLKSOURCE_PLL1Q ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0) /*!< PLL1Q clock used as SAI1 clock source */
479 #define LL_RCC_SAI1_CLKSOURCE_SYSCLK ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< System clock used as SAI1 clock source */
480 #define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0)) /*!< External input clock used as SAI1 clock source */
481 #define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */
482 /**
483 * @}
484 */
485 #endif /* SAI1 */
486
487
488 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
489 * @{
490 */
491 #define LL_RCC_RNG_CLKSOURCE_LSE 0U /*!< LSE clock used as RNG clock source */
492 #define LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR2_RNGSEL_0 /*!< LSI clock used as RNG clock source */
493 #define LL_RCC_RNG_CLKSOURCE_HSI RCC_CCIPR2_RNGSEL_1 /*!< HSI clock used as RNG clock source */
494 #define LL_RCC_RNG_CLKSOURCE_PLL1Q_DIV2 (RCC_CCIPR2_RNGSEL_1 | RCC_CCIPR2_RNGSEL_0) /*!< PLL1Q/2 clock used as RNG clock source */
495 /**
496 * @}
497 */
498 /** Legacy definitions for compatibility purpose
499 @cond 0
500 */
501 #define LL_RCC_RNG_CLKSOURCE_PLL1Q LL_RCC_RNG_CLKSOURCE_PLL1Q_DIV2
502 /**
503 @endcond
504 */
505
506 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC4 clock source selection
507 * @{
508 */
509 #define LL_RCC_ADC_CLKSOURCE_HCLK 0U /*!< HCLK1 clock used as ADC4 clock source */
510 #define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR3_ADCSEL_0 /*!< SYSCLK clock used as ADC4 clock source */
511 #define LL_RCC_ADC_CLKSOURCE_PLL1P RCC_CCIPR3_ADCSEL_1 /*!< PLL1P clock used as ADC4 clock source */
512 #define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR3_ADCSEL_2 /*!< HSI clock used as ADC4 clock source */
513 #define LL_RCC_ADC_CLKSOURCE_HSE (RCC_CCIPR3_ADCSEL_1 | RCC_CCIPR3_ADCSEL_0) /*!< HSE clock used as ADC4 clock source */
514 /**
515 * @}
516 */
517
518
519
520 /** @defgroup RCC_LL_EC_TIM_INPUT_CAPTURE_CLOCKSource TIM Input capture clock source selection
521 * @{
522 */
523 #define LL_RCC_TIMIC_CLKSOURCE_NONE 0U /*!< No clock available for TIM16/TIM17 and LPTIM2 input capture */
524 #define LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256 RCC_CCIPR1_TIMICSEL /*!< HSI/256 selected for TIM16/TIM17 and LPTIM2 input capture */
525 /**
526 * @}
527 */
528
529 /** @defgroup RCC_LL_EC_USART Peripheral USARTx get clock source
530 * @{
531 */
532 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR1_USART1SEL /*!< USART1 Clock source selection */
533 #if defined(USART2)
534 #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR1_USART2SEL /*!< USART2 Clock source selection */
535 #endif /* USART2 */
536 /**
537 * @}
538 */
539
540 /** @defgroup RCC_LL_EC_SPI Peripheral SPIx get clock source
541 * @{
542 */
543 #if defined(SPI1)
544 #define LL_RCC_SPI1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | (RCC_CCIPR1_SPI1SEL >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< SPI1 Clock source selection */
545 #endif /* SPI1 */
546 #define LL_RCC_SPI3_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | (RCC_CCIPR3_SPI3SEL >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< SPI3 Clock source selection */
547 /**
548 * @}
549 */
550
551 /** @defgroup RCC_LL_EC_LPUART Peripheral LPUARTx get clock source
552 * @{
553 */
554 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR3_LPUART1SEL /*!< LPUART1 Clock source selection */
555 /**
556 * @}
557 */
558
559 /** @defgroup RCC_LL_EC_I2C Peripheral I2Cx get clock source
560 * @{
561 */
562 #if defined(I2C1)
563 #define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
564 #endif /* I2C1 */
565 #define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | (RCC_CCIPR3_I2C3SEL >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
566
567 /**
568 * @}
569 */
570
571 /** @defgroup RCC_LL_EC_LPTIM Peripheral LPTIMx get clock source
572 * @{
573 */
574 #define LL_RCC_LPTIM1_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | (RCC_CCIPR3_LPTIM1SEL >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LPTIM1 Clock source selection */
575 #if defined(LPTIM2)
576 #define LL_RCC_LPTIM2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | (RCC_CCIPR1_LPTIM2SEL >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LPTIM2 Clock source selection */
577 #endif /* LPTIM2 */
578 /**
579 * @}
580 */
581
582 #if defined(SAI1)
583 /** @defgroup RCC_LL_EC_SAI Peripheral SAIx get clock source
584 * @{
585 */
586 #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL /*!< SAI1 Clock source selection */
587 /**
588 * @}
589 */
590 #endif /* SAI1 */
591
592 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
593 * @{
594 */
595 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR2_RNGSEL /*!< RNG Clock source selection */
596 /**
597 * @}
598 */
599
600 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
601 * @{
602 */
603 #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR3_ADCSEL /*!< ADCs Clock source selection */
604 /**
605 * @}
606 */
607
608
609 /** @defgroup RCC_LL_EC_PLL1SOURCE PLL1 entry clock source
610 * @{
611 */
612 #define LL_RCC_PLL1SOURCE_NONE 0U /*!< No clock selected as PLL1 entry clock source */
613 #define LL_RCC_PLL1SOURCE_HSI RCC_PLL1CFGR_PLL1SRC_1 /*!< HSI clock selected as PLL1 entry clock source */
614 #define LL_RCC_PLL1SOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) /*!< HSE clock selected as PLL1 entry clock source */
615 /**
616 * @}
617 */
618
619 /** @defgroup RCC_LL_EC_PLLINPUTRANGE All PLLs input ranges
620 * @{
621 */
622 #define LL_RCC_PLLINPUTRANGE_4_8 2U /*!< VCO input range: 4 to 8 MHz */
623 #define LL_RCC_PLLINPUTRANGE_8_16 3U /*!< VCO input range: 8 to 16 MHz */
624 /**
625 * @}
626 */
627
628 /** @defgroup RCC_LL_EC_PLL1RCLKPRESTEP PLL1RCLK prescaler steps division
629 * @{
630 */
631 #define LL_RCC_PLL1RCLK_2_STEP_DIV 0U /*!< PLL1RCLK 2-step division */
632 #define LL_RCC_PLL1RCLK_3_STEP_DIV RCC_PLL1CFGR_PLL1RCLKPRESTEP /*!< PLL1RCLK 3-step division */
633 /**
634 * @}
635 */
636
637 /** @defgroup RCC_LSE_Trimming LSE Trimming
638 * @{
639 */
640 #define LL_RCC_LSETRIMMING_R 0U /*!< Current source resistance R */
641 #define LL_RCC_LSETRIMMING_3_4_R RCC_BDCR1_LSETRIM_0 /*!< Current source resistance 3/4 * R */
642 #define LL_RCC_LSETRIMMING_2_3_R RCC_BDCR1_LSETRIM_1 /*!< Current source resistance 2/3 * R */
643 #define LL_RCC_LSETRIMMING_1_2_R RCC_BDCR1_LSETRIM /*!< Current source resistance 1/2 * R */
644 /**
645 * @}
646 */
647
648 /** @defgroup RCC_LL_EF_Security_Services Security Services
649 * @note Only available when system implements security (TZEN=1)
650 * @{
651 */
652 #define LL_RCC_ALL_NSEC 0U /*!< No security on RCC resources (default) */
653 #define LL_RCC_ALL_SEC RCC_SECURE_MASK /*!< Security on all RCC resources */
654
655 #define LL_RCC_HSI_SEC RCC_SECCFGR_HSISEC /*!< HSI clock configuration secure-only access */
656 #define LL_RCC_HSI_NSEC 0U /*!< HSI clock configuration secure/non-secure access */
657 #define LL_RCC_HSE_SEC RCC_SECCFGR_HSESEC /*!< HSE clock configuration secure-only access */
658 #define LL_RCC_HSE_NSEC 0U /*!< HSE clock configuration secure/non-secure access */
659 #define LL_RCC_LSE_SEC RCC_SECCFGR_LSESEC /*!< LSE clock configuration secure-only access */
660 #define LL_RCC_LSE_NSEC 0U /*!< LSE clock configuration secure/non-secure access */
661 #define LL_RCC_LSI_SEC RCC_SECCFGR_LSISEC /*!< LSI clock configuration secure-only access */
662 #define LL_RCC_LSI_NSEC 0U /*!< LSI clock configuration secure/non-secure access */
663 #define LL_RCC_SYSCLK_SEC RCC_SECCFGR_SYSCLKSEC /*!< SYSCLK clock; STOPWUCK and MCO output configuration secure-only access */
664 #define LL_RCC_SYSCLK_NSEC 0U /*!< SYSCLK clock; STOPWUCK and MCO output configuration secure/non-secure access */
665 #define LL_RCC_PRESCALERS_SEC RCC_SECCFGR_PRESCSEC /*!< AHBx/APBx prescaler configuration secure-only access */
666 #define LL_RCC_PRESCALERS_NSEC 0U /*!< AHBx/APBx prescaler configuration secure/non-secure access */
667 #define LL_RCC_PLL1_SEC RCC_SECCFGR_PLL1SEC /*!< PLL1 clock configuration secure-only access */
668 #define LL_RCC_PLL1_NSEC 0U /*!< PLL1 clock configuration secure/non-secure access */
669 #define LL_RCC_RESET_FLAGS_SEC RCC_SECCFGR_RMVFSEC /*!< Remove reset flag secure-only access */
670 #define LL_RCC_RESET_FLAGS_NSEC 0U /*!< Remove reset flag secure/non-secure access */
671 /**
672 * @}
673 */
674
675 /**
676 * @}
677 */
678
679 /* Exported macro ------------------------------------------------------------*/
680 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
681 * @{
682 */
683
684 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
685 * @{
686 */
687
688 /**
689 * @brief Write a value in RCC register
690 * @param __REG__ Register to be written
691 * @param __VALUE__ Value to be written in the register
692 * @retval None
693 */
694 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
695
696 /**
697 * @brief Read a value in RCC register
698 * @param __REG__ Register to be read
699 * @retval Register value
700 */
701 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
702 /**
703 * @}
704 */
705
706 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
707 * @{
708 */
709
710 /**
711 * @brief Helper macro to calculate the PLL1RCLK frequency on system domain
712 * @note ex: @ref __LL_RCC_CALC_PLL1RCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (),
713 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetR ());
714 * @param __INPUTFREQ__ PLL1 Input frequency (based on HSE/HSI)
715 * @param __PLL1M__ parameter can be a value between 1 and 16
716 * @param __PLL1N__ parameter can be a value between 4 and 512
717 * @param __PLL1R__ parameter can be a value between 1 and 128
718 * @retval PLL1R clock frequency (in Hz)
719 */
720
721 #define __LL_RCC_CALC_PLL1RCLK_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1R__) ((((__INPUTFREQ__) /(__PLL1M__)) * (__PLL1N__)) / (__PLL1R__))
722
723 /**
724 * @brief Helper macro to calculate the PLL1PCLK frequency
725 * @note ex: @ref __LL_RCC_CALC_PLL1PCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (),
726 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetP ());
727 * @param __INPUTFREQ__ PLL1 Input frequency (based on HSE/HSI)
728 * @param __PLL1M__ parameter can be a value between 1 and 16
729 * @param __PLL1N__ parameter can be a value between 4 and 512
730 * @param __PLL1P__ parameter can be a value between 2 and 128
731 * @retval PLL1P clock frequency (in Hz)
732 */
733 #define __LL_RCC_CALC_PLL1PCLK_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1P__) ((((__INPUTFREQ__) /(__PLL1M__)) * (__PLL1N__)) / (__PLL1P__))
734
735 /**
736 * @brief Helper macro to calculate the PLL1QCLK frequency
737 * @note ex: @ref __LL_RCC_CALC_PLL1QCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (),
738 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetQ ());
739 * @param __INPUTFREQ__ PLL1 Input frequency (based on HSE/HSI)
740 * @param __PLL1M__ parameter can be a value between 1 and 16
741 * @param __PLL1N__ parameter can be a value between 4 and 512
742 * @param __PLL1Q__ parameter can be a value between 1 and 128
743 * @retval PLL1 clock frequency (in Hz)
744 */
745 #define __LL_RCC_CALC_PLL1QCLK_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1Q__) ((((__INPUTFREQ__) /(__PLL1M__)) * (__PLL1N__)) / (__PLL1Q__))
746
747 /**
748 * @brief Helper macro to calculate the HCLK frequency
749 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
750 * @param __AHBPRESCALER__ This parameter can be one of the following values:
751 * @arg @ref LL_RCC_SYSCLK_DIV_1
752 * @arg @ref LL_RCC_SYSCLK_DIV_2
753 * @arg @ref LL_RCC_SYSCLK_DIV_4
754 * @arg @ref LL_RCC_SYSCLK_DIV_8
755 * @arg @ref LL_RCC_SYSCLK_DIV_16
756 * @retval HCLK clock frequency (in Hz)
757 */
758 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos])
759
760 /**
761 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
762 * @param __HCLKFREQ__ HCLK frequency
763 * @param __APB1PRESCALER__ This parameter can be one of the following values:
764 * @arg @ref LL_RCC_APB1_DIV_1
765 * @arg @ref LL_RCC_APB1_DIV_2
766 * @arg @ref LL_RCC_APB1_DIV_4
767 * @arg @ref LL_RCC_APB1_DIV_8
768 * @arg @ref LL_RCC_APB1_DIV_16
769 * @retval PCLK1 clock frequency (in Hz)
770 */
771 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[((__APB1PRESCALER__) & RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_Pos]))
772
773 /**
774 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
775 * @param __HCLKFREQ__ HCLK frequency
776 * @param __APB2PRESCALER__ This parameter can be one of the following values:
777 * @arg @ref LL_RCC_APB2_DIV_1
778 * @arg @ref LL_RCC_APB2_DIV_2
779 * @arg @ref LL_RCC_APB2_DIV_4
780 * @arg @ref LL_RCC_APB2_DIV_8
781 * @arg @ref LL_RCC_APB2_DIV_16
782 * @retval PCLK2 clock frequency (in Hz)
783 */
784 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR2_PPRE2_Pos])
785
786
787 /**
788 * @brief Helper macro to calculate the PCLK7 frequency (ABP7)
789 * @param __HCLKFREQ__ HCLK frequency
790 * @param __APB7PRESCALER__ This parameter can be one of the following values:
791 * @arg @ref LL_RCC_APB7_DIV_1
792 * @arg @ref LL_RCC_APB7_DIV_2
793 * @arg @ref LL_RCC_APB7_DIV_4
794 * @arg @ref LL_RCC_APB7_DIV_8
795 * @arg @ref LL_RCC_APB7_DIV_16
796 * @retval PCLK3 clock frequency (in Hz)
797 */
798 #define __LL_RCC_CALC_PCLK7_FREQ(__HCLKFREQ__, __APB7PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB7PRESCALER__) >> RCC_CFGR3_PPRE7_Pos])
799
800 /**
801 * @}
802 */
803
804 /**
805 * @}
806 */
807
808 /* Exported functions --------------------------------------------------------*/
809 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
810 * @{
811 */
812
813 /** @defgroup RCC_LL_EF_HSE HSE
814 * @{
815 */
816
817 /**
818 * @brief Enable HSE crystal oscillator (HSE ON)
819 * @rmtoll CR HSEON LL_RCC_HSE_Enable
820 * @retval None
821 */
LL_RCC_HSE_Enable(void)822 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
823 {
824 SET_BIT(RCC->CR, RCC_CR_HSEON);
825 }
826
827 /**
828 * @brief Disable HSE crystal oscillator (HSE ON)
829 * @rmtoll CR HSEON LL_RCC_HSE_Disable
830 * @retval None
831 */
LL_RCC_HSE_Disable(void)832 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
833 {
834 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
835 }
836
837 /**
838 * @brief Check if HSE oscillator Ready
839 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
840 * @retval State of bit (1 or 0).
841 */
LL_RCC_HSE_IsReady(void)842 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
843 {
844 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL);
845 }
846
847 /**
848 * @brief Enable HSE clock prescaler for sysclk
849 * @rmtoll CR HSEPRE LL_RCC_HSE_EnablePrescaler
850 * @note Control the division factor of the HSE32 clock for sysclk
851 * @retval None
852 */
LL_RCC_HSE_EnablePrescaler(void)853 __STATIC_INLINE void LL_RCC_HSE_EnablePrescaler(void)
854 {
855 SET_BIT(RCC->CR, RCC_CR_HSEPRE);
856 }
857
858 /**
859 * @brief Check if HSE clock prescaler for sysclk is enabled
860 * @rmtoll CR HSEPRE LL_RCC_HSE_IsEnabledPrescaler
861 * @note Check if the HSE32 clock for sysclk is divided by 2 or not
862 * @retval State of bit (1 or 0).
863 */
LL_RCC_HSE_IsEnabledPrescaler(void)864 __STATIC_INLINE uint32_t LL_RCC_HSE_IsEnabledPrescaler(void)
865 {
866 return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == RCC_CR_HSEPRE) ? 1UL : 0UL);
867 }
868
869 /**
870 * @brief Disable HSE clock prescaler for sysclk
871 * @rmtoll CR HSEPRE LL_RCC_HSE_DisablePrescaler
872 * @note Control the division factor of the HSE32 clock for sysclk
873 * @retval None
874 */
LL_RCC_HSE_DisablePrescaler(void)875 __STATIC_INLINE void LL_RCC_HSE_DisablePrescaler(void)
876 {
877 CLEAR_BIT(RCC->CR, RCC_CR_HSEPRE);
878 }
879
880 /**
881 * @brief Enable the Clock Security System.
882 * @rmtoll CR HSECSSON LL_RCC_HSE_EnableCSS
883 * @retval None
884 */
LL_RCC_HSE_EnableCSS(void)885 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
886 {
887 SET_BIT(RCC->CR, RCC_CR_HSECSSON);
888 }
889
890 /**
891 * @brief Set HSE clock trimming
892 * @note user-programmable capacitor trimming value.
893 * @rmtoll ECSCR1 HSETRIM LL_RCC_HSE_SetClockTrimming
894 * @param Value Between Min_Data = 0 and Max_Data = 63
895 * @retval None
896 */
LL_RCC_HSE_SetClockTrimming(uint32_t Value)897 __STATIC_INLINE void LL_RCC_HSE_SetClockTrimming(uint32_t Value)
898 {
899 MODIFY_REG(RCC->ECSCR1, RCC_ECSCR1_HSETRIM, Value << RCC_ECSCR1_HSETRIM_Pos);
900 }
901
902 /**
903 * @brief Get HSE clock trimming
904 * @rmtoll ECSCR1 HSETRIM LL_RCC_HSE_GetClockTrimming
905 * @retval Between Min_Data = 0 and Max_Data = 63
906 */
LL_RCC_HSE_GetClockTrimming(void)907 __STATIC_INLINE uint32_t LL_RCC_HSE_GetClockTrimming(void)
908 {
909 return (uint32_t)(READ_BIT(RCC->ECSCR1, RCC_ECSCR1_HSETRIM) >> RCC_ECSCR1_HSETRIM_Pos);
910 }
911 /**
912 * @}
913 */
914
915 /** @defgroup RCC_LL_EF_HSI HSI
916 * @{
917 */
918
919 /**
920 * @brief Enable HSI even in stop mode
921 * @note HSI oscillator is forced ON even in Stop mode
922 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
923 * @retval None
924 */
LL_RCC_HSI_EnableInStopMode(void)925 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
926 {
927 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
928 }
929
930 /**
931 * @brief Disable HSI in stop mode
932 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
933 * @retval None
934 */
LL_RCC_HSI_DisableInStopMode(void)935 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
936 {
937 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
938 }
939
940 /**
941 * @brief Check if HSI is enabled in stop mode
942 * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
943 * @retval State of bit (1 or 0).
944 */
LL_RCC_HSI_IsEnabledInStopMode(void)945 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
946 {
947 return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == RCC_CR_HSIKERON) ? 1UL : 0UL);
948 }
949
950 /**
951 * @brief Enable HSI oscillator
952 * @rmtoll CR HSION LL_RCC_HSI_Enable
953 * @retval None
954 */
LL_RCC_HSI_Enable(void)955 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
956 {
957 SET_BIT(RCC->CR, RCC_CR_HSION);
958 }
959
960 /**
961 * @brief Disable HSI oscillator
962 * @rmtoll CR HSION LL_RCC_HSI_Disable
963 * @retval None
964 */
LL_RCC_HSI_Disable(void)965 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
966 {
967 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
968 }
969
970 /**
971 * @brief Check if HSI clock is ready
972 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
973 * @retval State of bit (1 or 0).
974 */
LL_RCC_HSI_IsReady(void)975 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
976 {
977 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL);
978 }
979
980 /**
981 * @brief Get HSI Calibration value
982 * @note When HSITRIM is written, HSICAL is updated with the sum of
983 * HSITRIM and the factory trim value
984 * @rmtoll ICSCR3 HSICAL LL_RCC_HSI_GetCalibration
985 * @retval Between Min_Data = 0 and Max_Data = 4095
986 */
LL_RCC_HSI_GetCalibration(void)987 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
988 {
989 return (uint32_t)(READ_BIT(RCC->ICSCR3, RCC_ICSCR3_HSICAL) >> RCC_ICSCR3_HSICAL_Pos);
990 }
991
992 /**
993 * @brief Set HSI Calibration trimming
994 * @note user-programmable trimming value that is added to the HSICAL
995 * @note Default value is 16, which, when added to the HSICAL value,
996 * should trim the HSI to 16 MHz +/- 1 %
997 * @rmtoll ICSCR3 HSITRIM LL_RCC_HSI_SetCalibTrimming
998 * @param Value Between Min_Data = 0 and Max_Data = 31
999 * @retval None
1000 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)1001 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1002 {
1003 MODIFY_REG(RCC->ICSCR3, RCC_ICSCR3_HSITRIM, Value << RCC_ICSCR3_HSITRIM_Pos);
1004 }
1005
1006 /**
1007 * @brief Get HSI Calibration trimming
1008 * @rmtoll ICSCR3 HSITRIM LL_RCC_HSI_GetCalibTrimming
1009 * @retval Between Min_Data = 0 and Max_Data = 31
1010 */
LL_RCC_HSI_GetCalibTrimming(void)1011 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1012 {
1013 return (uint32_t)(READ_BIT(RCC->ICSCR3, RCC_ICSCR3_HSITRIM) >> RCC_ICSCR3_HSITRIM_Pos);
1014 }
1015
1016 /**
1017 * @}
1018 */
1019
1020 /** @defgroup RCC_LL_EF_LSE LSE
1021 * @{
1022 */
1023
1024 /**
1025 * @brief Enable Low Speed External (LSE) crystal.
1026 * @rmtoll BDCR1 LSEON LL_RCC_LSE_Enable
1027 * @retval None
1028 */
LL_RCC_LSE_Enable(void)1029 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
1030 {
1031 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEON);
1032 }
1033
1034 /**
1035 * @brief Disable Low Speed External (LSE) crystal.
1036 * @rmtoll BDCR1 LSEON LL_RCC_LSE_Disable
1037 * @retval None
1038 */
LL_RCC_LSE_Disable(void)1039 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
1040 {
1041 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSEON);
1042 }
1043
1044 /**
1045 * @brief Enable external clock source (LSE bypass).
1046 * @rmtoll BDCR1 LSEBYP LL_RCC_LSE_EnableBypass
1047 * @retval None
1048 */
LL_RCC_LSE_EnableBypass(void)1049 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
1050 {
1051 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEBYP);
1052 }
1053
1054 /**
1055 * @brief Disable external clock source (LSE bypass).
1056 * @rmtoll BDCR1 LSEBYP LL_RCC_LSE_DisableBypass
1057 * @retval None
1058 */
LL_RCC_LSE_DisableBypass(void)1059 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
1060 {
1061 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSEBYP);
1062 }
1063
1064 /**
1065 * @brief Enable LSE clock glitch filter.
1066 * @rmtoll BDCR1 LSEGFON LL_RCC_LSE_EnableGlitchFilter
1067 * @retval None
1068 */
LL_RCC_LSE_EnableGlitchFilter(void)1069 __STATIC_INLINE void LL_RCC_LSE_EnableGlitchFilter(void)
1070 {
1071 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEGFON);
1072 }
1073
1074 /**
1075 * @brief Disable LSE clock glitch filter.
1076 * @rmtoll BDCR1 LSEGFON LL_RCC_LSE_DisableGlitchFilter
1077 * @retval None
1078 */
LL_RCC_LSE_DisableGlitchFilter(void)1079 __STATIC_INLINE void LL_RCC_LSE_DisableGlitchFilter(void)
1080 {
1081 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSEGFON);
1082 }
1083
1084 /**
1085 * @brief Set LSE trimming
1086 * @rmtoll BDCR1 LSETRIM LL_RCC_LSE_SetClockTrimming
1087 * @param LSETrim This parameter can be one of the following values:
1088 * @arg @ref LL_RCC_LSETRIMMING_R
1089 * @arg @ref LL_RCC_LSETRIMMING_3_4_R
1090 * @arg @ref LL_RCC_LSETRIMMING_2_3_R
1091 * @arg @ref LL_RCC_LSETRIMMING_1_2_R
1092 * @retval None
1093 */
LL_RCC_LSE_SetClockTrimming(uint32_t LSETrim)1094 __STATIC_INLINE void LL_RCC_LSE_SetClockTrimming(uint32_t LSETrim)
1095 {
1096 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSETRIM, LSETrim);
1097 }
1098
1099 /**
1100 * @brief Get LSE trimming
1101 * @rmtoll BDCR1 LSETRIM LL_RCC_LSE_GetClockTrimming
1102 * @retval Returned value can be one of the following values:
1103 * @arg @ref LL_RCC_LSETRIMMING_R
1104 * @arg @ref LL_RCC_LSETRIMMING_3_4_R
1105 * @arg @ref LL_RCC_LSETRIMMING_2_3_R
1106 * @arg @ref LL_RCC_LSETRIMMING_1_2_R
1107 * @retval None
1108 */
LL_RCC_LSE_GetClockTrimming(void)1109 __STATIC_INLINE uint32_t LL_RCC_LSE_GetClockTrimming(void)
1110 {
1111 return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_LSETRIM));
1112 }
1113
1114 /**
1115 * @brief Set LSE oscillator drive capability
1116 * @note The oscillator is in Xtal mode when it is not in bypass mode.
1117 * @rmtoll BDCR1 LSEDRV LL_RCC_LSE_SetDriveCapability
1118 * @param LSEDrive This parameter can be one of the following values:
1119 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1120 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1121 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1122 * @retval None
1123 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)1124 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
1125 {
1126 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSEDRV, LSEDrive);
1127 }
1128
1129 /**
1130 * @brief Get LSE oscillator drive capability
1131 * @rmtoll BDCR1 LSEDRV LL_RCC_LSE_GetDriveCapability
1132 * @retval Returned value can be one of the following values:
1133 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1134 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1135 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1136 */
LL_RCC_LSE_GetDriveCapability(void)1137 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
1138 {
1139 return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_LSEDRV));
1140 }
1141
1142 /**
1143 * @brief Enable Clock security system on LSE.
1144 * @rmtoll BDCR1 LSECSSON LL_RCC_LSE_EnableCSS
1145 * @retval None
1146 */
LL_RCC_LSE_EnableCSS(void)1147 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
1148 {
1149 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSECSSON);
1150 }
1151
1152 /**
1153 * @brief Disable Clock security system on LSE.
1154 * @note Clock security system can be disabled only after a LSE
1155 * failure detection. In that case it MUST be disabled by software.
1156 * @rmtoll BDCR1 LSECSSON LL_RCC_LSE_DisableCSS
1157 * @retval None
1158 */
LL_RCC_LSE_DisableCSS(void)1159 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
1160 {
1161 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSECSSON);
1162 }
1163
1164 /**
1165 * @brief Check if LSE oscillator Ready
1166 * @rmtoll BDCR1 LSERDY LL_RCC_LSE_IsReady
1167 * @retval State of bit (1 or 0).
1168 */
LL_RCC_LSE_IsReady(void)1169 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
1170 {
1171 return ((READ_BIT(RCC->BDCR1, RCC_BDCR1_LSERDY) == RCC_BDCR1_LSERDY) ? 1UL : 0UL);
1172 }
1173
1174 /**
1175 * @brief Enable LSE oscillator propagation for system clock
1176 * @rmtoll BDCR1 LSESYSEN LL_RCC_LSE_EnablePropagation
1177 * @retval None
1178 */
LL_RCC_LSE_EnablePropagation(void)1179 __STATIC_INLINE void LL_RCC_LSE_EnablePropagation(void)
1180 {
1181 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSESYSEN);
1182 }
1183
1184 /**
1185 * @brief Disable LSE oscillator propagation for system clock
1186 * @rmtoll BDCR1 LSESYSEN LL_RCC_LSE_DisablePropagation
1187 * @retval None
1188 */
LL_RCC_LSE_DisablePropagation(void)1189 __STATIC_INLINE void LL_RCC_LSE_DisablePropagation(void)
1190 {
1191 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSESYSEN);
1192 }
1193
1194 /**
1195 * @brief Check if LSE oscillator propagation for system clock Ready
1196 * @rmtoll BDCR1 LSESYSRDY LL_RCC_LSE_IsPropagationReady
1197 * @retval State of bit (1 or 0).
1198 */
LL_RCC_LSE_IsPropagationReady(void)1199 __STATIC_INLINE uint32_t LL_RCC_LSE_IsPropagationReady(void)
1200 {
1201 return ((READ_BIT(RCC->BDCR1, RCC_BDCR1_LSESYSRDY) == RCC_BDCR1_LSESYSRDY) ? 1UL : 0UL);
1202 }
1203
1204 /**
1205 * @brief Check if CSS on LSE failure Detection
1206 * @rmtoll BDCR1 LSECSSD LL_RCC_LSE_IsCSSDetected
1207 * @retval State of bit (1 or 0).
1208 */
LL_RCC_LSE_IsCSSDetected(void)1209 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
1210 {
1211 return ((READ_BIT(RCC->BDCR1, RCC_BDCR1_LSECSSD) == RCC_BDCR1_LSECSSD) ? 1UL : 0UL);
1212 }
1213
1214 /**
1215 * @}
1216 */
1217
1218 /** @defgroup RCC_LL_EF_LSI1 LSI1
1219 * @{
1220 */
1221
1222 /**
1223 * @brief Enable LSI1 Oscillator
1224 * @rmtoll BDCR1 LSI1ON LL_RCC_LSI1_Enable
1225 * @retval None
1226 */
LL_RCC_LSI1_Enable(void)1227 __STATIC_INLINE void LL_RCC_LSI1_Enable(void)
1228 {
1229 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSI1ON);
1230 }
1231
1232 /**
1233 * @brief Disable LSI1 Oscillator
1234 * @rmtoll BDCR1 LSI1ON LL_RCC_LSI1_Disable
1235 * @retval None
1236 */
LL_RCC_LSI1_Disable(void)1237 __STATIC_INLINE void LL_RCC_LSI1_Disable(void)
1238 {
1239 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSI1ON);
1240 }
1241
1242 /**
1243 * @brief Check if LSI1 is Ready
1244 * @rmtoll BDCR1 LSI1RDY LL_RCC_LSI1_IsReady
1245 * @retval State of bit (1 or 0).
1246 */
LL_RCC_LSI1_IsReady(void)1247 __STATIC_INLINE uint32_t LL_RCC_LSI1_IsReady(void)
1248 {
1249 return ((READ_BIT(RCC->BDCR1, RCC_BDCR1_LSI1RDY) == RCC_BDCR1_LSI1RDY) ? 1UL : 0UL);
1250 }
1251
1252 /**
1253 * @brief Set LSI1 prescaler
1254 * @rmtoll BDCR1 LSI1PREDIV LL_RCC_LSI1_SetPrescaler
1255 * @param LSI1Prescaler This parameter can be one of the following values:
1256 * @arg @ref LL_RCC_LSI_DIV_1
1257 * @arg @ref LL_RCC_LSI_DIV_128
1258 * @retval None
1259 */
LL_RCC_LSI1_SetPrescaler(uint32_t LSI1Prescaler)1260 __STATIC_INLINE void LL_RCC_LSI1_SetPrescaler(uint32_t LSI1Prescaler)
1261 {
1262 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV, LSI1Prescaler);
1263 }
1264
1265 /**
1266 * @brief Get LSI1 prescaler
1267 * @rmtoll BDCR1 LSI1PREDIV LL_RCC_LSI1_GetPrescaler
1268 * @retval Returned value can be one of the following values:
1269 * @arg @ref LL_RCC_LSI_DIV_1
1270 * @arg @ref LL_RCC_LSI_DIV_128
1271 */
LL_RCC_LSI1_GetPrescaler(void)1272 __STATIC_INLINE uint32_t LL_RCC_LSI1_GetPrescaler(void)
1273 {
1274 return (READ_BIT(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV));
1275 }
1276
1277 /**
1278 * @}
1279 */
1280
1281 #if defined(RCC_LSI2_SUPPORT)
1282 /** @defgroup RCC_LL_EF_LSI2 LSI2
1283 * @{
1284 */
1285
1286 /**
1287 * @brief Enable LSI2 Oscillator
1288 * @rmtoll BDCR1 LSI2ON LL_RCC_LSI2_Enable
1289 * @retval None
1290 */
LL_RCC_LSI2_Enable(void)1291 __STATIC_INLINE void LL_RCC_LSI2_Enable(void)
1292 {
1293 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSI2ON);
1294 }
1295
1296 /**
1297 * @brief Disable LSI2 Oscillator
1298 * @rmtoll BDCR1 LSI2ON LL_RCC_LSI2_Disable
1299 * @retval None
1300 */
LL_RCC_LSI2_Disable(void)1301 __STATIC_INLINE void LL_RCC_LSI2_Disable(void)
1302 {
1303 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSI2ON);
1304 }
1305
1306 /**
1307 * @brief Check if LSI2 is Ready
1308 * @rmtoll BDCR1 LSI2RDY LL_RCC_LSI2_IsReady
1309 * @retval State of bit (1 or 0).
1310 */
LL_RCC_LSI2_IsReady(void)1311 __STATIC_INLINE uint32_t LL_RCC_LSI2_IsReady(void)
1312 {
1313 return ((READ_BIT(RCC->BDCR1, RCC_BDCR1_LSI2RDY) == RCC_BDCR1_LSI2RDY) ? 1UL : 0UL);
1314 }
1315
1316 /**
1317 * @brief Configure LSI2 oscillator temperature sensitivity
1318 * @rmtoll BDCR2 LSI2CFG LL_RCC_LSI2_SetTempSensitivity
1319 * @param Sensitivity This parameter can be one of the following values:
1320 * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_80
1321 * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_50
1322 * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_20
1323 * @retval None
1324 */
LL_RCC_LSI2_SetTempSensitivity(uint32_t Sensitivity)1325 __STATIC_INLINE void LL_RCC_LSI2_SetTempSensitivity(uint32_t Sensitivity)
1326 {
1327 MODIFY_REG(RCC->BDCR2, RCC_BDCR2_LSI2CFG, Sensitivity);
1328 }
1329
1330 /**
1331 * @brief Get LSI2 oscillator temperature sensitivity
1332 * @rmtoll BDCR2 LSI2CFG LL_RCC_LSI2_GetTempSensitivity
1333 * @retval Returned value can be one of the following values:
1334 * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_80
1335 * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_50
1336 * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_20
1337 */
LL_RCC_LSI2_GetTempSensitivity(void)1338 __STATIC_INLINE uint32_t LL_RCC_LSI2_GetTempSensitivity(void)
1339 {
1340 return (uint32_t)(READ_BIT(RCC->BDCR2, RCC_BDCR2_LSI2CFG));
1341 }
1342
1343 /**
1344 * @brief Configure LSI2 operating mode configuration
1345 * @rmtoll BDCR2 LSI2MODE LL_RCC_LSI2_SetOperatingMode
1346 * @param Mode This parameter can be one of the following values:
1347 * @arg @ref LL_RCC_LSI2_NOMINAL_MODE
1348 * @arg @ref LL_RCC_LSI2_LOWPOWER_MODE
1349 * @arg @ref LL_RCC_LSI2_ULTRALOWPOWER_MODE
1350 * @retval None
1351 */
LL_RCC_LSI2_SetOperatingMode(uint32_t Mode)1352 __STATIC_INLINE void LL_RCC_LSI2_SetOperatingMode(uint32_t Mode)
1353 {
1354 MODIFY_REG(RCC->BDCR2, RCC_BDCR2_LSI2MODE, Mode);
1355 }
1356
1357 /**
1358 * @brief Get LSI2 oscillator operating mode
1359 * @rmtoll BDCR2 LSI2MODE LL_RCC_LSI2_GetOperatingMode
1360 * @retval Returned value can be one of the following values:
1361 * @arg @ref LL_RCC_LSI2_NOMINAL_MODE
1362 * @arg @ref LL_RCC_LSI2_LOWPOWER_MODE
1363 * @arg @ref LL_RCC_LSI2_ULTRALOWPOWER_MODE
1364 */
LL_RCC_LSI2_GetOperatingMode(void)1365 __STATIC_INLINE uint32_t LL_RCC_LSI2_GetOperatingMode(void)
1366 {
1367 return (uint32_t)(READ_BIT(RCC->BDCR2, RCC_BDCR2_LSI2MODE));
1368 }
1369
1370 /**
1371 * @}
1372 */
1373 #endif /* LSI2 */
1374
1375 /** @defgroup RCC_LL_EF_LSCO LSCO
1376 * @{
1377 */
1378
1379 /**
1380 * @brief Enable Low speed clock
1381 * @rmtoll BDCR1 LSCOEN LL_RCC_LSCO_Enable
1382 * @retval None
1383 */
LL_RCC_LSCO_Enable(void)1384 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
1385 {
1386 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSCOEN);
1387 }
1388
1389 /**
1390 * @brief Disable Low speed clock
1391 * @rmtoll BDCR1 LSCOEN LL_RCC_LSCO_Disable
1392 * @retval None
1393 */
LL_RCC_LSCO_Disable(void)1394 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
1395 {
1396 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSCOEN);
1397 }
1398
1399 /**
1400 * @brief Configure Low speed clock selection
1401 * @rmtoll BDCR1 LSCOSEL LL_RCC_LSCO_SetSource
1402 * @param Source This parameter can be one of the following values:
1403 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
1404 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
1405 * @retval None
1406 */
LL_RCC_LSCO_SetSource(uint32_t Source)1407 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
1408 {
1409 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSCOSEL, Source);
1410 }
1411
1412 /**
1413 * @brief Get Low speed clock selection
1414 * @rmtoll BDCR1 LSCOSEL LL_RCC_LSCO_GetSource
1415 * @retval Returned value can be one of the following values:
1416 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
1417 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
1418 */
LL_RCC_LSCO_GetSource(void)1419 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
1420 {
1421 return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_LSCOSEL));
1422 }
1423
1424 /**
1425 * @}
1426 */
1427
1428 /** @defgroup RCC_LL_EF_System System
1429 * @{
1430 */
1431
1432 /**
1433 * @brief Configure the system clock source
1434 * @rmtoll CFGR1 SW LL_RCC_SetSysClkSource
1435 * @param Source This parameter can be one of the following values:
1436 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
1437 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
1438 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1R
1439 * @retval None
1440 */
LL_RCC_SetSysClkSource(uint32_t Source)1441 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
1442 {
1443 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, Source);
1444 }
1445
1446 /**
1447 * @brief Get the system clock source
1448 * @rmtoll CFGR1 SWS LL_RCC_GetSysClkSource
1449 * @retval Returned value can be one of the following values:
1450 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
1451 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
1452 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1R
1453 */
LL_RCC_GetSysClkSource(void)1454 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
1455 {
1456 return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_SWS));
1457 }
1458
1459 /**
1460 * @brief Set AHB prescaler
1461 * @rmtoll CFGR2 HPRE LL_RCC_SetAHBPrescaler
1462 * @param Prescaler This parameter can be one of the following values:
1463 * @arg @ref LL_RCC_SYSCLK_DIV_1
1464 * @arg @ref LL_RCC_SYSCLK_DIV_2
1465 * @arg @ref LL_RCC_SYSCLK_DIV_4
1466 * @arg @ref LL_RCC_SYSCLK_DIV_8
1467 * @arg @ref LL_RCC_SYSCLK_DIV_16
1468 * @retval None
1469 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)1470 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
1471 {
1472 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, Prescaler);
1473 }
1474
1475 /**
1476 * @brief Set Systick clock source
1477 * @rmtoll CCIPR1 SYSTICKSEL LL_RCC_SetSystickClockSource
1478 * @param SystickSource This parameter can be one of the following values:
1479 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI
1480 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE
1481 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8
1482 * @retval None
1483 */
LL_RCC_SetSystickClockSource(uint32_t SystickSource)1484 __STATIC_INLINE void LL_RCC_SetSystickClockSource(uint32_t SystickSource)
1485 {
1486 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, SystickSource);
1487 }
1488
1489 /**
1490 * @brief Set APB1 prescaler
1491 * @rmtoll CFGR2 PPRE1 LL_RCC_SetAPB1Prescaler
1492 * @param Prescaler This parameter can be one of the following values:
1493 * @arg @ref LL_RCC_APB1_DIV_1
1494 * @arg @ref LL_RCC_APB1_DIV_2
1495 * @arg @ref LL_RCC_APB1_DIV_4
1496 * @arg @ref LL_RCC_APB1_DIV_8
1497 * @arg @ref LL_RCC_APB1_DIV_16
1498 * @retval None
1499 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)1500 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
1501 {
1502 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, Prescaler);
1503 }
1504
1505 /**
1506 * @brief Set APB2 prescaler
1507 * @rmtoll CFGR2 PPRE2 LL_RCC_SetAPB2Prescaler
1508 * @param Prescaler This parameter can be one of the following values:
1509 * @arg @ref LL_RCC_APB2_DIV_1
1510 * @arg @ref LL_RCC_APB2_DIV_2
1511 * @arg @ref LL_RCC_APB2_DIV_4
1512 * @arg @ref LL_RCC_APB2_DIV_8
1513 * @arg @ref LL_RCC_APB2_DIV_16
1514 * @retval None
1515 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)1516 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
1517 {
1518 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, Prescaler);
1519 }
1520
1521 /**
1522 * @brief Set APB7 prescaler
1523 * @rmtoll CFGR3 PPRE7 LL_RCC_SetAPB7Prescaler
1524 * @param Prescaler This parameter can be one of the following values:
1525 * @arg @ref LL_RCC_APB7_DIV_1
1526 * @arg @ref LL_RCC_APB7_DIV_2
1527 * @arg @ref LL_RCC_APB7_DIV_4
1528 * @arg @ref LL_RCC_APB7_DIV_8
1529 * @arg @ref LL_RCC_APB7_DIV_16
1530 * @retval None
1531 */
LL_RCC_SetAPB7Prescaler(uint32_t Prescaler)1532 __STATIC_INLINE void LL_RCC_SetAPB7Prescaler(uint32_t Prescaler)
1533 {
1534 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE7, Prescaler);
1535 }
1536
1537 /**
1538 * @brief Set AHB5 prescaler when SYSCLK is PLL1R
1539 * @rmtoll CFGR4 HPRE5 LL_RCC_SetAHB5Prescaler
1540 * @param Prescaler This parameter can be one of the following values:
1541 * @arg @ref LL_RCC_AHB5_DIV_1
1542 * @arg @ref LL_RCC_AHB5_DIV_2
1543 * @arg @ref LL_RCC_AHB5_DIV_3
1544 * @arg @ref LL_RCC_AHB5_DIV_4
1545 * @arg @ref LL_RCC_AHB5_DIV_6
1546 * @retval None
1547 */
LL_RCC_SetAHB5Prescaler(uint32_t Prescaler)1548 __STATIC_INLINE void LL_RCC_SetAHB5Prescaler(uint32_t Prescaler)
1549 {
1550 MODIFY_REG(RCC->CFGR4, RCC_CFGR4_HPRE5, Prescaler);
1551 }
1552
1553 /**
1554 * @brief Set AHB5 divider when SYSCLK is HSI or HSE
1555 * @rmtoll CFGR4 HDIV5 LL_RCC_SetAHB5Divider
1556 * @param Divider This parameter can be one of the following values:
1557 * @arg @ref LL_RCC_AHB5_DIVIDER_1
1558 * @arg @ref LL_RCC_AHB5_DIVIDER_2
1559 * @retval None
1560 */
LL_RCC_SetAHB5Divider(uint32_t Divider)1561 __STATIC_INLINE void LL_RCC_SetAHB5Divider(uint32_t Divider)
1562 {
1563 MODIFY_REG(RCC->CFGR4, RCC_CFGR4_HDIV5, Divider);
1564 }
1565
1566 /**
1567 * @brief Get AHB prescaler
1568 * @rmtoll CFGR2 HPRE LL_RCC_GetAHBPrescaler
1569 * @retval Returned value can be one of the following values:
1570 * @arg @ref LL_RCC_SYSCLK_DIV_1
1571 * @arg @ref LL_RCC_SYSCLK_DIV_2
1572 * @arg @ref LL_RCC_SYSCLK_DIV_4
1573 * @arg @ref LL_RCC_SYSCLK_DIV_8
1574 * @arg @ref LL_RCC_SYSCLK_DIV_16
1575 */
LL_RCC_GetAHBPrescaler(void)1576 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
1577 {
1578 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_HPRE));
1579 }
1580
1581 /**
1582 * @brief Get Sysctick clock source
1583 * @rmtoll CCIPR1 SYSTICKSEL LL_RCC_SetSystickClockSource
1584 * @retval Returned value can be one of the following values:
1585 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI
1586 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE
1587 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8
1588 */
LL_RCC_GetSystickClockSource(void)1589 __STATIC_INLINE uint32_t LL_RCC_GetSystickClockSource(void)
1590 {
1591 return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL));
1592 }
1593
1594 /**
1595 * @brief Get APB1 prescaler
1596 * @rmtoll CFGR2 PPRE1 LL_RCC_GetAPB1Prescaler
1597 * @retval Returned value can be one of the following values:
1598 * @arg @ref LL_RCC_APB1_DIV_1
1599 * @arg @ref LL_RCC_APB1_DIV_2
1600 * @arg @ref LL_RCC_APB1_DIV_4
1601 * @arg @ref LL_RCC_APB1_DIV_8
1602 * @arg @ref LL_RCC_APB1_DIV_16
1603 */
LL_RCC_GetAPB1Prescaler(void)1604 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
1605 {
1606 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE1));
1607 }
1608
1609 /**
1610 * @brief Get APB2 prescaler
1611 * @rmtoll CFGR2 PPRE2 LL_RCC_GetAPB2Prescaler
1612 * @retval Returned value can be one of the following values:
1613 * @arg @ref LL_RCC_APB2_DIV_1
1614 * @arg @ref LL_RCC_APB2_DIV_2
1615 * @arg @ref LL_RCC_APB2_DIV_4
1616 * @arg @ref LL_RCC_APB2_DIV_8
1617 * @arg @ref LL_RCC_APB2_DIV_16
1618 */
LL_RCC_GetAPB2Prescaler(void)1619 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
1620 {
1621 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE2));
1622 }
1623
1624 /**
1625 * @brief Get APB7 prescaler
1626 * @rmtoll CFGR3 PPRE7 LL_RCC_GetAPB7Prescaler
1627 * @retval Returned value can be one of the following values:
1628 * @arg @ref LL_RCC_APB7_DIV_1
1629 * @arg @ref LL_RCC_APB7_DIV_2
1630 * @arg @ref LL_RCC_APB7_DIV_4
1631 * @arg @ref LL_RCC_APB7_DIV_8
1632 * @arg @ref LL_RCC_APB7_DIV_16
1633 */
LL_RCC_GetAPB7Prescaler(void)1634 __STATIC_INLINE uint32_t LL_RCC_GetAPB7Prescaler(void)
1635 {
1636 return (uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_PPRE7));
1637 }
1638
1639 /**
1640 * @brief Get AHB5 prescaler when SYSCLK is PLL1R
1641 * @rmtoll CFGR4 HPRE5 LL_RCC_GetAHB5Prescaler
1642 * @retval Returned value can be one of the following values:
1643 * @arg @ref LL_RCC_AHB5_DIV_1
1644 * @arg @ref LL_RCC_AHB5_DIV_2
1645 * @arg @ref LL_RCC_AHB5_DIV_3
1646 * @arg @ref LL_RCC_AHB5_DIV_4
1647 * @arg @ref LL_RCC_AHB5_DIV_6
1648 */
LL_RCC_GetAHB5Prescaler(void)1649 __STATIC_INLINE uint32_t LL_RCC_GetAHB5Prescaler(void)
1650 {
1651 return (uint32_t)(READ_BIT(RCC->CFGR4, RCC_CFGR4_HPRE5));
1652 }
1653
1654 /**
1655 * @brief Get AHB5 divider when SYSCLK is HSI or HSE
1656 * @rmtoll CFGR4 HDIV5 LL_RCC_GetAHB5Divider
1657 * @retval Returned value can be one of the following values:
1658 * @arg @ref LL_RCC_AHB5_DIVIDER_1
1659 * @arg @ref LL_RCC_AHB5_DIVIDER_2
1660 */
LL_RCC_GetAHB5Divider(void)1661 __STATIC_INLINE uint32_t LL_RCC_GetAHB5Divider(void)
1662 {
1663 return (uint32_t)(READ_BIT(RCC->CFGR4, RCC_CFGR4_HDIV5));
1664 }
1665 /**
1666 * @}
1667 */
1668
1669 /** @defgroup RCC_LL_EF_RADIO RADIO
1670 * @{
1671 */
1672
1673 /**
1674 * @brief Enable the 2.4 GHz RADIO baseband clock
1675 * @rmtoll RADIOENR BBCLKEN LL_RCC_RADIO_EnableBasebandClock
1676 * @retval None
1677 */
LL_RCC_RADIO_EnableBasebandClock(void)1678 __STATIC_INLINE void LL_RCC_RADIO_EnableBasebandClock(void)
1679 {
1680 SET_BIT(RCC->RADIOENR, RCC_RADIOENR_BBCLKEN);
1681 }
1682
1683 /**
1684 * @brief Disable the 2.4 GHz RADIO baseband clock
1685 * @rmtoll RADIOENR BBCLKEN LL_RCC_RADIO_DisableBasebandClock
1686 * @retval None
1687 */
LL_RCC_RADIO_DisableBasebandClock(void)1688 __STATIC_INLINE void LL_RCC_RADIO_DisableBasebandClock(void)
1689 {
1690 CLEAR_BIT(RCC->RADIOENR, RCC_RADIOENR_BBCLKEN);
1691 }
1692
1693 /**
1694 * @brief Check if 2.4 GHz RADIO baseband clock is enabled
1695 * @rmtoll RADIOENR BBCLKEN LL_RCC_RADIO_IsEnabledBasebandClock
1696 * @retval State of bit (1 or 0).
1697 */
LL_RCC_RADIO_IsEnabledBasebandClock(void)1698 __STATIC_INLINE uint32_t LL_RCC_RADIO_IsEnabledBasebandClock(void)
1699 {
1700 return ((READ_BIT(RCC->RADIOENR, RCC_RADIOENR_BBCLKEN) == RCC_RADIOENR_BBCLKEN) ? 1UL : 0UL);
1701 }
1702
1703 /**
1704 * @brief Disable the 2.4 GHz RADIO bus clock and HSE32 oscillator by 2.4 GHz RADIO sleep timer wakeup event
1705 * @rmtoll RADIOENR STRADIOCLKON LL_RCC_RADIO_DisableSleepTimerClock
1706 * @retval None
1707 */
LL_RCC_RADIO_DisableSleepTimerClock(void)1708 __STATIC_INLINE void LL_RCC_RADIO_DisableSleepTimerClock(void)
1709 {
1710 CLEAR_BIT(RCC->RADIOENR, RCC_RADIOENR_STRADIOCLKON);
1711 }
1712
1713 /**
1714 * @brief Check if 2.4 GHz RADIO bus clock and HSE32 oscillator are enabled by 2.4 GHz RADIO sleep timer wakeup event
1715 * @rmtoll RADIOENR STRADIOCLKON LL_RCC_RADIO_IsEnabledSleepTimerClock
1716 * @retval State of bit (1 or 0).
1717 */
LL_RCC_RADIO_IsEnabledSleepTimerClock(void)1718 __STATIC_INLINE uint32_t LL_RCC_RADIO_IsEnabledSleepTimerClock(void)
1719 {
1720 return ((READ_BIT(RCC->RADIOENR, RCC_RADIOENR_STRADIOCLKON) == RCC_RADIOENR_STRADIOCLKON) ? 1UL : 0UL);
1721 }
1722
1723 /**
1724 * @brief Check if 2.4 GHz RADIO bus clock is ready
1725 * @rmtoll RADIOENR RADIOCLKRDY LL_RCC_RADIO_IsBusClockReady
1726 * @retval State of bit (1 or 0).
1727 */
LL_RCC_RADIO_IsBusClockReady(void)1728 __STATIC_INLINE uint32_t LL_RCC_RADIO_IsBusClockReady(void)
1729 {
1730 return ((READ_BIT(RCC->RADIOENR, RCC_RADIOENR_RADIOCLKRDY) == RCC_RADIOENR_RADIOCLKRDY) ? 1UL : 0UL);
1731 }
1732
1733 /**
1734 * @brief Set the 2.4 GHz RADIO sleep timer kernel clock
1735 * @rmtoll BDCR1 RADIOSTSEL LL_RCC_RADIO_SetSleepTimerClockSource
1736 * @param Source This parameter can be one of the following values:
1737 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_NONE
1738 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_LSE
1739 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_LSI (*)
1740 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_HSE_DIV1000
1741 *
1742 * (*) value not defined in all devices.
1743 * @retval None
1744 */
LL_RCC_RADIO_SetSleepTimerClockSource(uint32_t Source)1745 __STATIC_INLINE void LL_RCC_RADIO_SetSleepTimerClockSource(uint32_t Source)
1746 {
1747 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_RADIOSTSEL, Source);
1748 }
1749
1750 /**
1751 * @brief Get the 2.4 GHz RADIO sleep timer kernel clock
1752 * @rmtoll BDCR1 RADIOSTSEL LL_RCC_RADIO_GetSleepTimerClockSource
1753 * @retval Returned value can be one of the following values:
1754 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_NONE
1755 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_LSE
1756 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_LSI (*)
1757 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_HSE_DIV1000
1758 *
1759 * (*) value not defined in all devices.
1760 */
LL_RCC_RADIO_GetSleepTimerClockSource(void)1761 __STATIC_INLINE uint32_t LL_RCC_RADIO_GetSleepTimerClockSource(void)
1762 {
1763 return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_RADIOSTSEL));
1764 }
1765
1766 /**
1767 * @}
1768 */
1769
1770 /** @defgroup RCC_LL_EF_MCO MCO
1771 * @{
1772 */
1773
1774 /**
1775 * @brief Configure MCOx
1776 * @rmtoll CFGR1 MCOSEL LL_RCC_ConfigMCO\n
1777 * CFGR1 MCOPRE LL_RCC_ConfigMCO
1778 * @param MCOxSource This parameter can be one of the following values:
1779 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
1780 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
1781 * @arg @ref LL_RCC_MCO1SOURCE_HSI
1782 * @arg @ref LL_RCC_MCO1SOURCE_HSE
1783 * @arg @ref LL_RCC_MCO1SOURCE_PLL1R
1784 * @arg @ref LL_RCC_MCO1SOURCE_PLL1Q
1785 * @arg @ref LL_RCC_MCO1SOURCE_PLL1P
1786 * @arg @ref LL_RCC_MCO1SOURCE_LSI
1787 * @arg @ref LL_RCC_MCO1SOURCE_LSE
1788 * @arg @ref LL_RCC_MCO1SOURCE_HCLK5
1789 * @param MCOxPrescaler This parameter can be one of the following values:
1790 * @arg @ref LL_RCC_MCO1_DIV_1
1791 * @arg @ref LL_RCC_MCO1_DIV_2
1792 * @arg @ref LL_RCC_MCO1_DIV_4
1793 * @arg @ref LL_RCC_MCO1_DIV_8
1794 * @arg @ref LL_RCC_MCO1_DIV_16
1795 * @retval None
1796 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)1797 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
1798 {
1799 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE, MCOxSource | MCOxPrescaler);
1800 }
1801
1802 /**
1803 * @}
1804 */
1805
1806 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
1807 * @{
1808 */
1809
1810 /**
1811 * @brief Configure USARTx clock source
1812 * @rmtoll CCIPR1 USART1SEL LL_RCC_SetUSARTClockSource\n
1813 * CCIPR1 USART2SEL LL_RCC_SetUSARTClockSource\n
1814 * @param USARTxSource This parameter can be one of the following values:
1815 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
1816 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1817 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
1818 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1819 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
1820 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
1821 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
1822 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
1823 * @retval None
1824 */
LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)1825 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
1826 {
1827 MODIFY_REG(RCC->CCIPR1, USARTxSource >> 16U, (USARTxSource & 0x0000FFFFU));
1828 }
1829
1830 /**
1831 * @brief Configure LPUARTx clock source
1832 * @rmtoll CCIPR3 LPUART1SEL LL_RCC_SetLPUARTClockSource
1833 * @param LPUARTxSource This parameter can be one of the following values:
1834 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK7
1835 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
1836 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
1837 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
1838 * @retval None
1839 */
LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)1840 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
1841 {
1842 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL, LPUARTxSource);
1843 }
1844
1845 /**
1846 * @brief Configure I2Cx clock source
1847 * @rmtoll CCIPR1 I2C1SEL LL_RCC_SetI2CClockSource\n
1848 * CCIPR3 I2C3SEL LL_RCC_SetI2CClockSource\n
1849 * @param I2CxSource This parameter can be one of the following values:
1850 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
1851 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1852 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
1853 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK7
1854 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
1855 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
1856 * @retval None
1857 */
LL_RCC_SetI2CClockSource(uint32_t I2CxSource)1858 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
1859 {
1860 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2CxSource >> 24U));
1861 MODIFY_REG(*reg, 3U << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((I2CxSource & 0x000000FFU) << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU)));
1862 }
1863
1864 /**
1865 * @brief Configure SPIx clock source
1866 * @rmtoll CCIPR1 SPI1SEL LL_RCC_SetSPIClockSource\n
1867 * CCIPR3 SPI3SEL LL_RCC_SetSPIClockSource\n
1868 * @param SPIxSource This parameter can be one of the following values:
1869 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2
1870 * @arg @ref LL_RCC_SPI1_CLKSOURCE_SYSCLK
1871 * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI
1872 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK7
1873 * @arg @ref LL_RCC_SPI3_CLKSOURCE_SYSCLK
1874 * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI
1875 * @retval None
1876 */
LL_RCC_SetSPIClockSource(uint32_t SPIxSource)1877 __STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t SPIxSource)
1878 {
1879 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIxSource >> 24U));
1880 MODIFY_REG(*reg, 3U << (((SPIxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((SPIxSource & 0x000000FFU) << (((SPIxSource & 0x00FF0000U) >> 16U) & 0x1FU)));
1881 }
1882
1883 /**
1884 * @brief Configure LPTIMx clock source
1885 * @rmtoll CCIPR3 LPTIM1SEL LL_RCC_SetLPTIMClockSource\n
1886 * CCIPR1 LPTIM2SEL LL_RCC_SetLPTIMClockSource\n
1887 * @param LPTIMxSource This parameter can be one of the following values:
1888 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK7
1889 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
1890 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
1891 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
1892 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
1893 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
1894 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
1895 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
1896 * @retval None
1897 */
LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)1898 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
1899 {
1900 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMxSource >> 24U));
1901 MODIFY_REG(*reg, 3U << (((LPTIMxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((LPTIMxSource & 0x000000FFU) << (((LPTIMxSource & 0x00FF0000U) >> 16U) & 0x1FU)));
1902 }
1903
1904
1905 /**
1906 * @brief Configure SAIx clock source
1907 * @rmtoll CCIPR2 SAI1SEL LL_RCC_SetSAIClockSource\n
1908 * @param SAIxSource This parameter can be one of the following values:
1909 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1P(*)
1910 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q(*)
1911 * @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK(*)
1912 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN(*)
1913 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI(*)
1914 * (*) Feature not available on all devices of the family
1915 * @retval None
1916 */
LL_RCC_SetSAIClockSource(uint32_t SAIxSource)1917 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
1918 {
1919 MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU));
1920 }
1921
1922 /**
1923 * @brief Configure RNG clock source
1924 * @rmtoll CCIPR2 RNGSEL LL_RCC_SetRNGClockSource
1925 * @param RNGxSource This parameter can be one of the following values:
1926 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
1927 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
1928 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI
1929 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q_DIV2
1930 * @retval None
1931 */
LL_RCC_SetRNGClockSource(uint32_t RNGxSource)1932 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
1933 {
1934 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_RNGSEL, RNGxSource);
1935 }
1936
1937 /**
1938 * @brief Configure ADC clock source
1939 * @rmtoll CCIPR3 ADCSEL LL_RCC_SetADCClockSource
1940 * @param ADC4Source This parameter can be one of the following values:
1941 * @arg @ref LL_RCC_ADC_CLKSOURCE_HCLK
1942 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
1943 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL1P
1944 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSE
1945 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI
1946 * @retval None
1947 */
LL_RCC_SetADCClockSource(uint32_t ADC4Source)1948 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADC4Source)
1949 {
1950 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADCSEL, ADC4Source);
1951 }
1952
1953
1954 /**
1955 * @brief Get USARTx clock source
1956 * @rmtoll CCIPR1 USART1SEL LL_RCC_GetUSARTClockSource\n
1957 * CCIPR1 USART2SEL LL_RCC_GetUSARTClockSource\n
1958 * @param USARTx This parameter can be one of the following values:
1959 * @arg @ref LL_RCC_USART1_CLKSOURCE
1960 * @arg @ref LL_RCC_USART2_CLKSOURCE
1961 * @retval Returned value can be one of the following values:
1962 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
1963 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1964 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
1965 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1966 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
1967 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
1968 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
1969 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
1970 */
LL_RCC_GetUSARTClockSource(uint32_t USARTx)1971 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
1972 {
1973 return (uint32_t)(READ_BIT(RCC->CCIPR1, USARTx) | (USARTx << 16U));
1974 }
1975
1976 /**
1977 * @brief Get LPUARTx clock source
1978 * @rmtoll CCIPR3 LPUART1SEL LL_RCC_GetLPUARTClockSource
1979 * @param LPUARTx This parameter can be one of the following values:
1980 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
1981 * @retval Returned value can be one of the following values:
1982 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK7
1983 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
1984 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
1985 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
1986 */
LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)1987 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
1988 {
1989 return (uint32_t)(READ_BIT(RCC->CCIPR3, LPUARTx));
1990 }
1991
1992 /**
1993 * @brief Get I2Cx clock source
1994 * @rmtoll CCIPR1 I2C1SEL LL_RCC_GetI2CClockSource\n
1995 * CCIPR3 I2C3SEL LL_RCC_GetI2CClockSource\n
1996 * @param I2Cx This parameter can be one of the following values:
1997 * @arg @ref LL_RCC_I2C1_CLKSOURCE
1998 * @arg @ref LL_RCC_I2C3_CLKSOURCE
1999 * @retval Returned value can be one of the following values:
2000 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2001 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
2002 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2003 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK7
2004 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
2005 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
2006 */
LL_RCC_GetI2CClockSource(uint32_t I2Cx)2007 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
2008 {
2009 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2Cx >> 24U));
2010 return (uint32_t)((READ_BIT(*reg, (3UL << (((I2Cx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> (((I2Cx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (I2Cx & 0xFFFF0000UL));
2011 }
2012
2013 /**
2014 * @brief Get SPIx clock source
2015 * @rmtoll CCIPR1 SPI1SEL LL_RCC_GetSPIClockSource\n
2016 * CCIPR3 SPI3SEL LL_RCC_GetSPIClockSource
2017 * @param SPIx This parameter can be one of the following values:
2018 * @arg @ref LL_RCC_SPI1_CLKSOURCE
2019 * @arg @ref LL_RCC_SPI3_CLKSOURCE
2020 * @retval Returned value can be one of the following values:
2021 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2
2022 * @arg @ref LL_RCC_SPI1_CLKSOURCE_SYSCLK
2023 * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI
2024 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK7
2025 * @arg @ref LL_RCC_SPI3_CLKSOURCE_SYSCLK
2026 * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI
2027 */
LL_RCC_GetSPIClockSource(uint32_t SPIx)2028 __STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t SPIx)
2029 {
2030 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIx >> 24U));
2031 return (uint32_t)((READ_BIT(*reg, (3UL << (((SPIx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> (((SPIx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (SPIx & 0xFFFF0000UL));
2032 }
2033
2034 /**
2035 * @brief Get LPTIMx clock source
2036 * @rmtoll CCIPR3 LPTIM1SEL LL_RCC_GetLPTIMClockSource\n
2037 * CCIPR1 LPTIM2SEL LL_RCC_GetLPTIMClockSource\n
2038 * @param LPTIMx This parameter can be one of the following values:
2039 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
2040 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
2041 * @retval Returned value can be one of the following values:
2042 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK7
2043 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2044 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2045 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2046 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
2047 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2048 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
2049 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2050 */
LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)2051 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
2052 {
2053 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMx >> 24U));
2054 return (uint32_t)((READ_BIT(*reg, (3UL << (((LPTIMx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> (((LPTIMx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (LPTIMx & 0xFFFF0000UL));
2055 }
2056
2057 /**
2058 * @brief Set Tim Input capture clock source
2059 * @rmtoll CCIPR1 TIMICSEL LL_RCC_SetTIMICClockSource
2060 * @param TIMICSource This parameter can be one of the following combined values:
2061 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_NONE
2062 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256
2063 * @note HSI clock without division is also available when TIMICSEL[2] is 1.
2064 * @retval None
2065 */
LL_RCC_SetTIMICClockSource(uint32_t TIMICSource)2066 __STATIC_INLINE void LL_RCC_SetTIMICClockSource(uint32_t TIMICSource)
2067 {
2068 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL, TIMICSource);
2069 }
2070
2071 /**
2072 * @brief Get Tim Input capture clock source
2073 * @rmtoll CCIPR1 TIMICSEL LL_RCC_GetTIMICClockSource
2074 * @retval Returned value can be one of the following combined values:
2075 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_NONE
2076 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256
2077 */
LL_RCC_GetTIMICClockSource(void)2078 __STATIC_INLINE uint32_t LL_RCC_GetTIMICClockSource(void)
2079 {
2080 return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL));
2081 }
2082
2083 /**
2084 * @brief Get SAIx clock source
2085 * @rmtoll CCIPR2 SAI1SEL LL_RCC_GetSAIClockSource\n
2086 * @param SAIx This parameter can be one of the following values:
2087 * @arg @ref LL_RCC_SAI1_CLKSOURCE(*)
2088 * @retval Returned value can be one of the following values:
2089 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1P(*)
2090 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q(*)
2091 * @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK(*)
2092 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN(*)
2093 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI(*)
2094 * (*) Feature not available on all devices of the family
2095 */
LL_RCC_GetSAIClockSource(uint32_t SAIx)2096 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
2097 {
2098 return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) | (SAIx << 16U));
2099 }
2100
2101 /**
2102 * @brief Get RNGx clock source
2103 * @rmtoll CCIPR2 RNGSEL LL_RCC_GetRNGClockSource
2104 * @param RNGx This parameter can be one of the following values:
2105 * @arg @ref LL_RCC_RNG_CLKSOURCE
2106 * @retval Returned value can be one of the following values:
2107 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
2108 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
2109 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI
2110 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q_DIV2
2111 */
LL_RCC_GetRNGClockSource(uint32_t RNGx)2112 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
2113 {
2114 return (uint32_t)(READ_BIT(RCC->CCIPR2, RNGx));
2115 }
2116
2117 /**
2118 * @brief Get ADCx clock source
2119 * @rmtoll CCIPR3 ADCSEL LL_RCC_GetADCClockSource
2120 * @param ADCx This parameter can be one of the following values:
2121 * @arg @ref LL_RCC_ADC_CLKSOURCE
2122 * @retval Returned value can be one of the following values:
2123 * @arg @ref LL_RCC_ADC_CLKSOURCE_HCLK
2124 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
2125 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL1P
2126 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSE
2127 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI
2128 */
LL_RCC_GetADCClockSource(uint32_t ADCx)2129 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
2130 {
2131 return (uint32_t)(READ_BIT(RCC->CCIPR3, ADCx));
2132 }
2133
2134
2135 /**
2136 * @}
2137 */
2138
2139 /** @defgroup RCC_LL_EF_RTC RTC
2140 * @{
2141 */
2142
2143 /**
2144 * @brief Set RTC Clock Source
2145 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
2146 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
2147 * set). The BDRST bit can be used to reset them.
2148 * @rmtoll BDCR1 RTCSEL LL_RCC_SetRTCClockSource
2149 * @param Source This parameter can be one of the following values:
2150 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2151 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2152 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2153 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2154 * @retval None
2155 */
LL_RCC_SetRTCClockSource(uint32_t Source)2156 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
2157 {
2158 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_RTCSEL, Source);
2159 }
2160
2161 /**
2162 * @brief Get RTC Clock Source
2163 * @rmtoll BDCR1 RTCSEL LL_RCC_GetRTCClockSource
2164 * @retval Returned value can be one of the following values:
2165 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2166 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2167 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2168 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2169 */
LL_RCC_GetRTCClockSource(void)2170 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
2171 {
2172 return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_RTCSEL));
2173 }
2174
2175 /**
2176 * @brief Force the Backup domain reset
2177 * @rmtoll BDCR1 BDRST LL_RCC_ForceBackupDomainReset
2178 * @retval None
2179 */
LL_RCC_ForceBackupDomainReset(void)2180 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
2181 {
2182 SET_BIT(RCC->BDCR1, RCC_BDCR1_BDRST);
2183 }
2184
2185 /**
2186 * @brief Release the Backup domain reset
2187 * @rmtoll BDCR1 BDRST LL_RCC_ReleaseBackupDomainReset
2188 * @retval None
2189 */
LL_RCC_ReleaseBackupDomainReset(void)2190 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
2191 {
2192 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_BDRST);
2193 }
2194
2195 /**
2196 * @}
2197 */
2198
2199 /** @defgroup RCC_LL_EF_PLL1 PLL1
2200 * @{
2201 */
2202
2203 /**
2204 * @brief Enable PLL1
2205 * @rmtoll CR PLL1ON LL_RCC_PLL1_Enable
2206 * @retval None
2207 */
LL_RCC_PLL1_Enable(void)2208 __STATIC_INLINE void LL_RCC_PLL1_Enable(void)
2209 {
2210 SET_BIT(RCC->CR, RCC_CR_PLL1ON);
2211 }
2212
2213 /**
2214 * @brief Disable PLL1
2215 * @note Cannot be disabled if the PLL1 clock is used as the system clock
2216 * @rmtoll CR PLL1ON LL_RCC_PLL1_Disable
2217 * @retval None
2218 */
LL_RCC_PLL1_Disable(void)2219 __STATIC_INLINE void LL_RCC_PLL1_Disable(void)
2220 {
2221 CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
2222 }
2223
2224 /**
2225 * @brief Check if PLL1 Ready
2226 * @rmtoll CR PLL1RDY LL_RCC_PLL1_IsReady
2227 * @retval State of bit (1 or 0).
2228 */
LL_RCC_PLL1_IsReady(void)2229 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)
2230 {
2231 return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == RCC_CR_PLL1RDY) ? 1UL : 0UL);
2232 }
2233
2234 /**
2235 * @brief Enable prescaler division on PLL1RCLK for SYSCLK
2236 * @rmtoll PLL1CFGR PLL1RCLKPRE LL_RCC_PLL1_EnablePLL1RCLKDivision
2237 * @retval None
2238 */
LL_RCC_PLL1_EnablePLL1RCLKDivision(void)2239 __STATIC_INLINE void LL_RCC_PLL1_EnablePLL1RCLKDivision(void)
2240 {
2241 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRE);
2242 }
2243
2244 /**
2245 * @brief Disable PLL1RCLK for SYSCLK prescaler division
2246 * @rmtoll PLL1CFGR PLL1RCLKPRE LL_RCC_PLL1_DisablePLL1RCLKDivision
2247 * @retval None
2248 */
LL_RCC_PLL1_DisablePLL1RCLKDivision(void)2249 __STATIC_INLINE void LL_RCC_PLL1_DisablePLL1RCLKDivision(void)
2250 {
2251 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRE);
2252 }
2253
2254 /**
2255 * @brief Set the division step of PLL1RCLK clock for SYSCLK
2256 * @rmtoll PLL1CFGR PLL1RCLKPRESTEP LL_RCC_PLL1_SetPLL1RCLKDivisionStep
2257 * @param Step This parameter can be one of the following values:
2258 * @arg @ref LL_RCC_PLL1RCLK_2_STEP_DIV
2259 * @arg @ref LL_RCC_PLL1RCLK_3_STEP_DIV
2260 * @retval None
2261 */
LL_RCC_PLL1_SetPLL1RCLKDivisionStep(uint32_t Step)2262 __STATIC_INLINE void LL_RCC_PLL1_SetPLL1RCLKDivisionStep(uint32_t Step)
2263 {
2264 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRESTEP, Step);
2265 }
2266
2267 /**
2268 * @brief Get the division step of PLL1RCLK clock for SYSCLK
2269 * @rmtoll PLL1CFGR PLL1RCLKPRESTEP LL_RCC_PLL1_GetPLL1RCLKDivisionStep
2270 * @retval Returned value can be one of the following values:
2271 * @arg @ref LL_RCC_PLL1RCLK_2_STEP_DIV
2272 * @arg @ref LL_RCC_PLL1RCLK_3_STEP_DIV
2273 */
LL_RCC_PLL1_GetPLL1RCLKDivisionStep(void)2274 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetPLL1RCLKDivisionStep(void)
2275 {
2276 return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRESTEP));
2277 }
2278
2279 /**
2280 * @brief Check if prescaler division on PLL1RCLK for SYSCLK is ready
2281 * @rmtoll PLL1CFGR PLL1RCLKPRERDY LL_RCC_PLL1_IsPLL1RCLKDivisionReady
2282 * @retval State of bit (1 or 0).
2283 */
LL_RCC_PLL1_IsPLL1RCLKDivisionReady(void)2284 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsPLL1RCLKDivisionReady(void)
2285 {
2286 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRERDY) == RCC_PLL1CFGR_PLL1RCLKPRERDY) ? 1UL : 0UL);
2287 }
2288
2289 /**
2290 * @brief Configure PLL1R used for SYSCLK Domain
2291 * @note PLL1 Source, PLLM, PLLN and PLLR can be written only when PLL1 is disabled.
2292 * @note PLLN/PLLR can be written only when PLL1 is disabled.
2293 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_PLL1R\n
2294 * PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_PLL1R\n
2295 * PLL1DIVR PLL1N LL_RCC_PLL1_ConfigDomain_PLL1R\n
2296 * PLL1DIVR PLL1R LL_RCC_PLL1_ConfigDomain_PLL1R
2297 * @param Source This parameter can be one of the following values:
2298 * @arg @ref LL_RCC_PLL1SOURCE_NONE
2299 * @arg @ref LL_RCC_PLL1SOURCE_HSI
2300 * @arg @ref LL_RCC_PLL1SOURCE_HSE
2301 * @param PLLM parameter can be a value between 1 and 16
2302 * @param PLLR parameter can be a value between 1 and 128
2303 * @param PLLN parameter can be a value between 4 and 512
2304 * @retval None
2305 */
LL_RCC_PLL1_ConfigDomain_PLL1R(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)2306 __STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_PLL1R(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
2307 {
2308 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos));
2309 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1R, ((PLLN - 1UL) << RCC_PLL1DIVR_PLL1N_Pos) | ((PLLR - 1UL) << RCC_PLL1DIVR_PLL1R_Pos));
2310 }
2311
2312 /**
2313 * @brief Configure PLL1P
2314 * @note PLL1 Source, PLLM, PLLN and PLLPDIV can be written only when PLL1 is disabled.
2315 * @note This can be selected for ADC and SAI
2316 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_PLL1P\n
2317 * PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_PLL1P\n
2318 * PLL1DIVR PLL1N LL_RCC_PLL1_ConfigDomain_PLL1P\n
2319 * PLL1DIVR PLL1P LL_RCC_PLL1_ConfigDomain_PLL1P
2320 * @param Source This parameter can be one of the following values:
2321 * @arg @ref LL_RCC_PLL1SOURCE_NONE
2322 * @arg @ref LL_RCC_PLL1SOURCE_HSI
2323 * @arg @ref LL_RCC_PLL1SOURCE_HSE
2324 * @param PLLM parameter can be a value between 1 and 16
2325 * @param PLLN parameter can be a value between 4 and 512
2326 * @param PLLP parameter can be a value between 2 and 128
2327 * @retval None
2328 */
LL_RCC_PLL1_ConfigDomain_PLL1P(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)2329 __STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_PLL1P(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
2330 {
2331 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos));
2332 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1P, ((PLLN - 1UL) << RCC_PLL1DIVR_PLL1N_Pos) | ((PLLP - 1UL) << RCC_PLL1DIVR_PLL1P_Pos));
2333 }
2334
2335 /**
2336 * @brief Configure PLL1Q
2337 * @note PLL1 Source, PLLM, PLLN and PLLQ can be written only when PLL1 is disabled.
2338 * @note This can be selected for RNG and SAI
2339 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_PLL1Q\n
2340 * PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_PLL1Q\n
2341 * PLL1DIVR PLL1N LL_RCC_PLL1_ConfigDomain_PLL1Q\n
2342 * PLL1DIVR PLL1Q LL_RCC_PLL1_ConfigDomain_PLL1Q
2343 * @param Source This parameter can be one of the following values:
2344 * @arg @ref LL_RCC_PLL1SOURCE_NONE
2345 * @arg @ref LL_RCC_PLL1SOURCE_HSI
2346 * @arg @ref LL_RCC_PLL1SOURCE_HSE
2347 * @param PLLM parameter can be a value between 1 and 16
2348 * @param PLLN parameter can be a value between 4 and 512
2349 * @param PLLQ parameter can be a value between 1 and 128
2350 * @retval None
2351 */
LL_RCC_PLL1_ConfigDomain_PLL1Q(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)2352 __STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_PLL1Q(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
2353 {
2354 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos));
2355 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1Q, ((PLLN - 1UL) << RCC_PLL1DIVR_PLL1N_Pos) | ((PLLQ - 1UL) << RCC_PLL1DIVR_PLL1Q_Pos));
2356 }
2357
2358 /**
2359 * @brief Configure PLL1 clock source
2360 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_SetMainSource
2361 * @param PLL1Source This parameter can be one of the following values:
2362 * @arg @ref LL_RCC_PLL1SOURCE_NONE
2363 * @arg @ref LL_RCC_PLL1SOURCE_HSI
2364 * @arg @ref LL_RCC_PLL1SOURCE_HSE
2365 * @retval None
2366 */
LL_RCC_PLL1_SetMainSource(uint32_t PLL1Source)2367 __STATIC_INLINE void LL_RCC_PLL1_SetMainSource(uint32_t PLL1Source)
2368 {
2369 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, PLL1Source);
2370 }
2371
2372 /**
2373 * @brief Get the oscillator used as PLL1 clock source.
2374 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_GetMainSource
2375 * @retval Returned value can be one of the following values:
2376 * @arg @ref LL_RCC_PLL1SOURCE_NONE
2377 * @arg @ref LL_RCC_PLL1SOURCE_HSI
2378 * @arg @ref LL_RCC_PLL1SOURCE_HSE
2379 */
LL_RCC_PLL1_GetMainSource(void)2380 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetMainSource(void)
2381 {
2382 return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC));
2383 }
2384
2385 /**
2386 * @brief Set PLL1 multiplication factor for VCO
2387 * @rmtoll PLL1DIVR PLL1N LL_RCC_PLL1_SetN
2388 * @param PLL1N parameter can be a value between 4 and 512
2389 */
LL_RCC_PLL1_SetN(uint32_t PLL1N)2390 __STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t PLL1N)
2391 {
2392 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N, (PLL1N - 1UL) << RCC_PLL1DIVR_PLL1N_Pos);
2393 }
2394
2395 /**
2396 * @brief Get PLL1 multiplication factor for VCO
2397 * @rmtoll PLL1DIVR PLL1N LL_RCC_PLL1_GetN
2398 * @retval Between 4 and 512
2399 */
LL_RCC_PLL1_GetN(void)2400 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void)
2401 {
2402 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1UL);
2403 }
2404
2405
2406 /**
2407 * @brief Set PLL1 division factor for PLL1P
2408 * @note Used for PLL1PCLK selected ADC and SAI
2409 * @rmtoll PLL1DIVR PLL1P LL_RCC_PLL1_SetP
2410 * @param PLL1P parameter can be a value between 2 and 128
2411 */
LL_RCC_PLL1_SetP(uint32_t PLL1P)2412 __STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t PLL1P)
2413 {
2414 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P, (PLL1P - 1UL) << RCC_PLL1DIVR_PLL1P_Pos);
2415 }
2416
2417 /**
2418 * @brief Get PLL1 division factor for PLL1P
2419 * @note Used for PLL1PCLK selected ADC and SAI
2420 * @rmtoll PLL1DIVR PLL1P LL_RCC_PLL1_GetP
2421 * @retval Between 2 and 128
2422 */
LL_RCC_PLL1_GetP(void)2423 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void)
2424 {
2425 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1UL);
2426 }
2427
2428
2429 /**
2430 * @brief Set PLL1 division factor for PLL1Q
2431 * @note Used for PLL1QCLK selected for RNG and SAI
2432 * @rmtoll PLL1DIVR PLL1Q LL_RCC_PLL1_SetQ
2433 * @param PLL1Q parameter can be a value between 1 and 128
2434 */
LL_RCC_PLL1_SetQ(uint32_t PLL1Q)2435 __STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t PLL1Q)
2436 {
2437 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q, (PLL1Q - 1UL) << RCC_PLL1DIVR_PLL1Q_Pos);
2438 }
2439
2440 /**
2441 * @brief Get PLL1 division factor for PLL1Q
2442 * @note Used for PLL1QCLK selected for RNG and SAI
2443 * @rmtoll PLL1DIVR PLL1Q LL_RCC_PLL1_GetQ
2444 * @retval Between 1 and 128
2445 */
LL_RCC_PLL1_GetQ(void)2446 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void)
2447 {
2448 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1UL);
2449 }
2450
2451 /**
2452 * @brief Set PLL1 division factor for PLL1R
2453 * @note Used for PLL1RCLK selected for system clock
2454 * @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_SetR
2455 * @param PLL1R parameter can be a value between 1 and 128
2456 */
LL_RCC_PLL1_SetR(uint32_t PLL1R)2457 __STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t PLL1R)
2458 {
2459 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R, (PLL1R - 1UL) << RCC_PLL1DIVR_PLL1R_Pos);
2460 }
2461
2462 /**
2463 * @brief Get PLL1 division factor for PLL1R
2464 * @note Used for PLL1RCLK selected for system clock
2465 * @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_GetR
2466 * @retval Between 1 and 128
2467 */
LL_RCC_PLL1_GetR(void)2468 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void)
2469 {
2470 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1UL);
2471 }
2472
2473 /**
2474 * @brief Set Division factor for PLL1
2475 * @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_SetDivider
2476 * @param PLL1M parameter can be a value between 1 and 8
2477 */
LL_RCC_PLL1_SetDivider(uint32_t PLL1M)2478 __STATIC_INLINE void LL_RCC_PLL1_SetDivider(uint32_t PLL1M)
2479 {
2480 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, (PLL1M - 1UL) << RCC_PLL1CFGR_PLL1M_Pos);
2481 }
2482
2483 /**
2484 * @brief Get Division factor for PLL1
2485 * @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_GetDivider
2486 * @retval Between 1 and 8
2487 */
LL_RCC_PLL1_GetDivider(void)2488 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetDivider(void)
2489 {
2490 return (uint32_t)((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1UL);
2491 }
2492
2493 /**
2494 * @brief Enable PLL1P output
2495 * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_EnableDomain_PLL1P
2496 * @retval None
2497 */
LL_RCC_PLL1_EnableDomain_PLL1P(void)2498 __STATIC_INLINE void LL_RCC_PLL1_EnableDomain_PLL1P(void)
2499 {
2500 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN);
2501 }
2502
2503 /**
2504 * @brief Disable PLL1P output
2505 * @note In order to save power, when the PLL1PCLK of the PLL1 is
2506 * not used, should be 0
2507 * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_DisableDomain_PLL1P
2508 * @retval None
2509 */
LL_RCC_PLL1_DisableDomain_PLL1P(void)2510 __STATIC_INLINE void LL_RCC_PLL1_DisableDomain_PLL1P(void)
2511 {
2512 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN);
2513 }
2514
2515 /**
2516 * @brief Check if PLL1P output is enabled
2517 * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_IsEnabledDomain_PLL1P
2518 * @retval State of bit (1 or 0).
2519 */
LL_RCC_PLL1_IsEnabledDomain_PLL1P(void)2520 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_PLL1P(void)
2521 {
2522 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN) == RCC_PLL1CFGR_PLL1PEN) ? 1UL : 0UL);
2523 }
2524
2525 /**
2526 * @brief Enable PLL1Q output
2527 * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_EnableDomain_PLL1Q
2528 * @retval None
2529 */
LL_RCC_PLL1_EnableDomain_PLL1Q(void)2530 __STATIC_INLINE void LL_RCC_PLL1_EnableDomain_PLL1Q(void)
2531 {
2532 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN);
2533 }
2534
2535 /**
2536 * @brief Disable PLL1Q output
2537 * @note In order to save power, when the PLL1QCLK of the PLL1 is
2538 * not used, should be 0
2539 * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_DisableDomain_PLL1Q
2540 * @retval None
2541 */
LL_RCC_PLL1_DisableDomain_PLL1Q(void)2542 __STATIC_INLINE void LL_RCC_PLL1_DisableDomain_PLL1Q(void)
2543 {
2544 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN);
2545 }
2546
2547 /**
2548 * @brief Check if PLL1Q output is enabled
2549 * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_IsEnabledDomain_PLL1Q
2550 * @retval State of bit (1 or 0).
2551 */
LL_RCC_PLL1_IsEnabledDomain_PLL1Q(void)2552 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_PLL1Q(void)
2553 {
2554 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN) == RCC_PLL1CFGR_PLL1QEN) ? 1UL : 0UL);
2555 }
2556
2557 /**
2558 * @brief Enable PLL1R output mapped on SYSCLK domain
2559 * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_EnableDomain_PLL1R
2560 * @retval None
2561 */
LL_RCC_PLL1_EnableDomain_PLL1R(void)2562 __STATIC_INLINE void LL_RCC_PLL1_EnableDomain_PLL1R(void)
2563 {
2564 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN);
2565 }
2566
2567 /**
2568 * @brief Disable PLL1 output mapped on SYSCLK domain
2569 * @note Cannot be disabled if the PLL1 clock is used as the system
2570 * clock
2571 * @note In order to save power, when the PLL1RCLK of the PLL1 is
2572 * not used, PLL1 should be 0
2573 * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_DisableDomain_PLL1R
2574 * @retval None
2575 */
LL_RCC_PLL1_DisableDomain_PLL1R(void)2576 __STATIC_INLINE void LL_RCC_PLL1_DisableDomain_PLL1R(void)
2577 {
2578 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN);
2579 }
2580
2581 /**
2582 * @brief Check if PLL1R output mapped on SYSCLK domain clock is enabled
2583 * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_IsEnabledDomain_PLL1R
2584 * @retval State of bit (1 or 0).
2585 */
LL_RCC_PLL1_IsEnabledDomain_PLL1R(void)2586 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_PLL1R(void)
2587 {
2588 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN) == RCC_PLL1CFGR_PLL1REN) ? 1UL : 0UL);
2589 }
2590
2591 /**
2592 * @brief Enable PLL1 FRACN
2593 * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable
2594 * @retval None
2595 */
LL_RCC_PLL1FRACN_Enable(void)2596 __STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void)
2597 {
2598 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN);
2599 }
2600
2601 /**
2602 * @brief Check if PLL1 FRACN is enabled
2603 * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_IsEnabled
2604 * @retval State of bit (1 or 0).
2605 */
LL_RCC_PLL1FRACN_IsEnabled(void)2606 __STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void)
2607 {
2608 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) == RCC_PLL1CFGR_PLL1FRACEN) ? 1UL : 0UL);
2609 }
2610
2611 /**
2612 * @brief Disable PLL1 FRACN
2613 * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Disable
2614 * @retval None
2615 */
LL_RCC_PLL1FRACN_Disable(void)2616 __STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void)
2617 {
2618 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN);
2619 }
2620
2621 /**
2622 * @brief Set PLL1 FRACN Coefficient
2623 * @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_SetFRACN
2624 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
2625 */
LL_RCC_PLL1_SetFRACN(uint32_t FRACN)2626 __STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN)
2627 {
2628 MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN, FRACN << RCC_PLL1FRACR_PLL1FRACN_Pos);
2629 }
2630
2631 /**
2632 * @brief Get PLL1 FRACN Coefficient
2633 * @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_GetFRACN
2634 * @retval A value between 0 and 8191 (0x1FFF)
2635 */
LL_RCC_PLL1_GetFRACN(void)2636 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void)
2637 {
2638 return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN) >> RCC_PLL1FRACR_PLL1FRACN_Pos);
2639 }
2640
2641 /**
2642 * @brief Set PLL1 VCO Input Range
2643 * @note This API shall be called only when PLL1 is disabled.
2644 * @rmtoll PLL1CFGR PLL1RGE LL_RCC_PLL1_SetVCOInputRange
2645 * @param InputRange This parameter can be one of the following values:
2646 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
2647 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
2648 * @retval None
2649 */
LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)2650 __STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)
2651 {
2652 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, InputRange << RCC_PLL1CFGR_PLL1RGE_Pos);
2653 }
2654
2655 /**
2656 * @}
2657 */
2658
2659 #if defined(RCC_PRIVCFGR_NSPRIV)
2660 /** @defgroup RCC_LL_EF_PRIV Privileged mode
2661 * @{
2662 */
2663
2664 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2665 /**
2666 * @brief Enable Secure Privileged mode
2667 * @rmtoll PRIVCFGR SPRIV LL_RCC_EnableSecPrivilegedMode
2668 * @retval None
2669 */
LL_RCC_EnableSecPrivilegedMode(void)2670 __STATIC_INLINE void LL_RCC_EnableSecPrivilegedMode(void)
2671 {
2672 SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV);
2673 }
2674
2675 /**
2676 * @brief Disable Secure Privileged mode
2677 * @rmtoll PRIVCFGR SPRIV LL_RCC_DisableSecPrivilegedMode
2678 * @retval None
2679 */
LL_RCC_DisableSecPrivilegedMode(void)2680 __STATIC_INLINE void LL_RCC_DisableSecPrivilegedMode(void)
2681 {
2682 CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV);
2683 }
2684
2685 /**
2686 * @brief Check if Secure Privileged mode has been enabled or not
2687 * @rmtoll PRIVCFGR SPRIV LL_RCC_IsEnabledSecPrivilegedMode
2688 * @retval State of bit (1 or 0).
2689 */
LL_RCC_IsEnabledSecPrivilegedMode(void)2690 __STATIC_INLINE uint32_t LL_RCC_IsEnabledSecPrivilegedMode(void)
2691 {
2692 return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV) == RCC_PRIVCFGR_SPRIV) ? 1UL : 0UL);
2693 }
2694 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
2695
2696 /**
2697 * @brief Enable Non Secure Privileged mode
2698 * @rmtoll PRIVCFGR NSPRIV LL_RCC_EnableNSecPrivilegedMode
2699 * @retval None
2700 */
LL_RCC_EnableNSecPrivilegedMode(void)2701 __STATIC_INLINE void LL_RCC_EnableNSecPrivilegedMode(void)
2702 {
2703 SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
2704 }
2705
2706 /**
2707 * @brief Disable Non Secure Privileged mode
2708 * @rmtoll PRIVCFGR NSPRIV LL_RCC_DisableNSecPrivilegedMode
2709 * @retval None
2710 */
LL_RCC_DisableNSecPrivilegedMode(void)2711 __STATIC_INLINE void LL_RCC_DisableNSecPrivilegedMode(void)
2712 {
2713 CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
2714 }
2715
2716 /**
2717 * @brief Check if Non Secure Privileged mode has been enabled or not
2718 * @rmtoll PRIVCFGR NSPRIV LL_RCC_IsEnabledNSecPrivilegedMode
2719 * @retval State of bit (1 or 0).
2720 */
LL_RCC_IsEnabledNSecPrivilegedMode(void)2721 __STATIC_INLINE uint32_t LL_RCC_IsEnabledNSecPrivilegedMode(void)
2722 {
2723 return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV) == RCC_PRIVCFGR_NSPRIV) ? 1UL : 0UL);
2724 }
2725
2726 /**
2727 * @}
2728 */
2729 #endif /* RCC_PRIVCFGR_NSPRIV */
2730
2731 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
2732 * @{
2733 */
2734
2735 /**
2736 * @brief Clear LSI1 ready interrupt flag
2737 * @rmtoll CICR LSI1RDYC LL_RCC_ClearFlag_LSI1RDY
2738 * @retval None
2739 */
LL_RCC_ClearFlag_LSI1RDY(void)2740 __STATIC_INLINE void LL_RCC_ClearFlag_LSI1RDY(void)
2741 {
2742 SET_BIT(RCC->CICR, RCC_CICR_LSI1RDYC);
2743 }
2744
2745 #if defined(RCC_LSI2_SUPPORT)
2746 /**
2747 * @brief Clear LSI2 ready interrupt flag
2748 * @rmtoll CICR LSI2RDYC LL_RCC_ClearFlag_LSI2RDY
2749 * @retval None
2750 */
LL_RCC_ClearFlag_LSI2RDY(void)2751 __STATIC_INLINE void LL_RCC_ClearFlag_LSI2RDY(void)
2752 {
2753 SET_BIT(RCC->CICR, RCC_CICR_LSI2RDYC);
2754 }
2755 #endif /* RCC_BDCR1_LSI2ON */
2756
2757 /**
2758 * @brief Clear LSE ready interrupt flag
2759 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
2760 * @retval None
2761 */
LL_RCC_ClearFlag_LSERDY(void)2762 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
2763 {
2764 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
2765 }
2766
2767 /**
2768 * @brief Clear HSI ready interrupt flag
2769 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
2770 * @retval None
2771 */
LL_RCC_ClearFlag_HSIRDY(void)2772 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
2773 {
2774 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
2775 }
2776
2777 /**
2778 * @brief Clear HSE ready interrupt flag
2779 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
2780 * @retval None
2781 */
LL_RCC_ClearFlag_HSERDY(void)2782 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
2783 {
2784 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
2785 }
2786
2787 /**
2788 * @brief Clear PLL1 ready interrupt flag
2789 * @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY
2790 * @retval None
2791 */
LL_RCC_ClearFlag_PLL1RDY(void)2792 __STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void)
2793 {
2794 SET_BIT(RCC->CICR, RCC_CICR_PLL1RDYC);
2795 }
2796
2797 /**
2798 * @brief Clear Clock security system interrupt flag
2799 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
2800 * @retval None
2801 */
LL_RCC_ClearFlag_HSECSS(void)2802 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
2803 {
2804 SET_BIT(RCC->CICR, RCC_CICR_HSECSSC);
2805 }
2806
2807
2808 /**
2809 * @brief Check if LSI1 ready interrupt occurred or not
2810 * @rmtoll CIFR LSI1RDYF LL_RCC_IsActiveFlag_LSI1RDY
2811 * @retval State of bit (1 or 0).
2812 */
LL_RCC_IsActiveFlag_LSI1RDY(void)2813 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSI1RDY(void)
2814 {
2815 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSI1RDYF) == RCC_CIFR_LSI1RDYF) ? 1UL : 0UL);
2816 }
2817
2818 #if defined(RCC_LSI2_SUPPORT)
2819 /**
2820 * @brief Check if LSI2 ready interrupt occurred or not
2821 * @rmtoll CIFR LSI2RDYF LL_RCC_IsActiveFlag_LSI2RDY
2822 * @retval State of bit (1 or 0).
2823 */
LL_RCC_IsActiveFlag_LSI2RDY(void)2824 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSI2RDY(void)
2825 {
2826 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSI2RDYF) == RCC_CIFR_LSI2RDYF) ? 1UL : 0UL);
2827 }
2828 #endif /* RCC_BDCR1_LSI2ON */
2829
2830 /**
2831 * @brief Check if LSE ready interrupt occurred or not
2832 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
2833 * @retval State of bit (1 or 0).
2834 */
LL_RCC_IsActiveFlag_LSERDY(void)2835 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
2836 {
2837 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL);
2838 }
2839
2840 /**
2841 * @brief Check if HSI ready interrupt occurred or not
2842 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
2843 * @retval State of bit (1 or 0).
2844 */
LL_RCC_IsActiveFlag_HSIRDY(void)2845 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
2846 {
2847 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL);
2848 }
2849
2850 /**
2851 * @brief Check if HSE ready interrupt occurred or not
2852 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
2853 * @retval State of bit (1 or 0).
2854 */
LL_RCC_IsActiveFlag_HSERDY(void)2855 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
2856 {
2857 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL);
2858 }
2859
2860 /**
2861 * @brief Check if PLL1 ready interrupt occurred or not
2862 * @rmtoll CIFR PLL1RDYF LL_RCC_IsActiveFlag_PLL1RDY
2863 * @retval State of bit (1 or 0).
2864 */
LL_RCC_IsActiveFlag_PLL1RDY(void)2865 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)
2866 {
2867 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL1RDYF) == RCC_CIFR_PLL1RDYF) ? 1UL : 0UL);
2868 }
2869
2870 /**
2871 * @brief Check if Clock security system interrupt occurred or not
2872 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
2873 * @retval State of bit (1 or 0).
2874 */
LL_RCC_IsActiveFlag_HSECSS(void)2875 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
2876 {
2877 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == RCC_CIFR_HSECSSF) ? 1UL : 0UL);
2878 }
2879
2880 /**
2881 * @brief Check if RCC flag Independent Watchdog reset is set or not.
2882 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
2883 * @retval State of bit (1 or 0).
2884 */
LL_RCC_IsActiveFlag_IWDGRST(void)2885 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
2886 {
2887 return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL);
2888 }
2889
2890 /**
2891 * @brief Check if RCC flag Low Power reset is set or not.
2892 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
2893 * @retval State of bit (1 or 0).
2894 */
LL_RCC_IsActiveFlag_LPWRRST(void)2895 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
2896 {
2897 return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL);
2898 }
2899
2900 /**
2901 * @brief Check if RCC flag is set or not.
2902 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
2903 * @retval State of bit (1 or 0).
2904 */
LL_RCC_IsActiveFlag_OBLRST(void)2905 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
2906 {
2907 return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL);
2908 }
2909
2910 /**
2911 * @brief Check if RCC flag Pin reset is set or not.
2912 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
2913 * @retval State of bit (1 or 0).
2914 */
LL_RCC_IsActiveFlag_PINRST(void)2915 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
2916 {
2917 return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL);
2918 }
2919
2920 /**
2921 * @brief Check if RCC flag Software reset is set or not.
2922 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
2923 * @retval State of bit (1 or 0).
2924 */
LL_RCC_IsActiveFlag_SFTRST(void)2925 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
2926 {
2927 return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL);
2928 }
2929
2930 /**
2931 * @brief Check if RCC flag Window Watchdog reset is set or not.
2932 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
2933 * @retval State of bit (1 or 0).
2934 */
LL_RCC_IsActiveFlag_WWDGRST(void)2935 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
2936 {
2937 return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL);
2938 }
2939
2940 /**
2941 * @brief Check if RCC flag BOR reset is set or not.
2942 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
2943 * @retval State of bit (1 or 0).
2944 */
LL_RCC_IsActiveFlag_BORRST(void)2945 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
2946 {
2947 return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == RCC_CSR_BORRSTF) ? 1UL : 0UL);
2948 }
2949
2950 /**
2951 * @brief Set RMVF bit to clear the reset flags.
2952 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
2953 * @retval None
2954 */
LL_RCC_ClearResetFlags(void)2955 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
2956 {
2957 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
2958 }
2959
2960 /* Alias for portability */
2961 #define LL_RCC_PLL1_ConfigDomain_SYS LL_RCC_PLL1_ConfigDomain_PLL1R
2962
2963 /**
2964 * @}
2965 */
2966
2967 /** @defgroup RCC_LL_EF_IT_Management IT Management
2968 * @{
2969 */
2970
2971 /**
2972 * @brief Enable LSI1 ready interrupt
2973 * @rmtoll CIER LSI1RDYIE LL_RCC_EnableIT_LSI1RDY
2974 * @retval None
2975 */
LL_RCC_EnableIT_LSI1RDY(void)2976 __STATIC_INLINE void LL_RCC_EnableIT_LSI1RDY(void)
2977 {
2978 SET_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE);
2979 }
2980
2981 #if defined(RCC_LSI2_SUPPORT)
2982 /**
2983 * @brief Enable LSI2 ready interrupt
2984 * @rmtoll CIER LSI2RDYIE LL_RCC_EnableIT_LSI2RDY
2985 * @retval None
2986 */
LL_RCC_EnableIT_LSI2RDY(void)2987 __STATIC_INLINE void LL_RCC_EnableIT_LSI2RDY(void)
2988 {
2989 SET_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE);
2990 }
2991 #endif /* RCC_BDCR1_LSI2ON */
2992
2993 /**
2994 * @brief Enable LSE ready interrupt
2995 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
2996 * @retval None
2997 */
LL_RCC_EnableIT_LSERDY(void)2998 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
2999 {
3000 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
3001 }
3002
3003 /**
3004 * @brief Enable HSI ready interrupt
3005 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
3006 * @retval None
3007 */
LL_RCC_EnableIT_HSIRDY(void)3008 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
3009 {
3010 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
3011 }
3012
3013 /**
3014 * @brief Enable HSE ready interrupt
3015 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
3016 * @retval None
3017 */
LL_RCC_EnableIT_HSERDY(void)3018 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
3019 {
3020 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
3021 }
3022
3023 /**
3024 * @brief Enable PLL1 ready interrupt
3025 * @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY
3026 * @retval None
3027 */
LL_RCC_EnableIT_PLL1RDY(void)3028 __STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void)
3029 {
3030 SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
3031 }
3032
3033 /**
3034 * @brief Disable LSI1 ready interrupt
3035 * @rmtoll CIER LSI1RDYIE LL_RCC_DisableIT_LSI1RDY
3036 * @retval None
3037 */
LL_RCC_DisableIT_LSI1RDY(void)3038 __STATIC_INLINE void LL_RCC_DisableIT_LSI1RDY(void)
3039 {
3040 CLEAR_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE);
3041 }
3042
3043 #if defined(RCC_LSI2_SUPPORT)
3044 /**
3045 * @brief Disable LSI2 ready interrupt
3046 * @rmtoll CIER LSI2RDYIE LL_RCC_DisableIT_LSI2RDY
3047 * @retval None
3048 */
LL_RCC_DisableIT_LSI2RDY(void)3049 __STATIC_INLINE void LL_RCC_DisableIT_LSI2RDY(void)
3050 {
3051 CLEAR_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE);
3052 }
3053 #endif /* RCC_BDCR1_LSI2ON */
3054
3055 /**
3056 * @brief Disable LSE ready interrupt
3057 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
3058 * @retval None
3059 */
LL_RCC_DisableIT_LSERDY(void)3060 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
3061 {
3062 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
3063 }
3064
3065 /**
3066 * @brief Disable HSI ready interrupt
3067 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
3068 * @retval None
3069 */
LL_RCC_DisableIT_HSIRDY(void)3070 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
3071 {
3072 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
3073 }
3074
3075 /**
3076 * @brief Disable HSE ready interrupt
3077 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
3078 * @retval None
3079 */
LL_RCC_DisableIT_HSERDY(void)3080 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
3081 {
3082 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
3083 }
3084
3085 /**
3086 * @brief Disable PLL1 ready interrupt
3087 * @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY
3088 * @retval None
3089 */
LL_RCC_DisableIT_PLL1RDY(void)3090 __STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void)
3091 {
3092 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
3093 }
3094
3095 /**
3096 * @brief Checks if LSI1 ready interrupt source is enabled or disabled.
3097 * @rmtoll CIER LSI1RDYIE LL_RCC_IsEnabledIT_LSI1RDY
3098 * @retval State of bit (1 or 0).
3099 */
LL_RCC_IsEnabledIT_LSI1RDY(void)3100 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSI1RDY(void)
3101 {
3102 return ((READ_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE) == RCC_CIER_LSI1RDYIE) ? 1UL : 0UL);
3103 }
3104
3105 #if defined(RCC_LSI2_SUPPORT)
3106 /**
3107 * @brief Checks if LSI2 ready interrupt source is enabled or disabled.
3108 * @rmtoll CIER LSI2RDYIE LL_RCC_IsEnabledIT_LSI2RDY
3109 * @retval State of bit (1 or 0).
3110 */
LL_RCC_IsEnabledIT_LSI2RDY(void)3111 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSI2RDY(void)
3112 {
3113 return ((READ_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE) == RCC_CIER_LSI2RDYIE) ? 1UL : 0UL);
3114 }
3115 #endif /* RCC_BDCR1_LSI2ON */
3116
3117 /**
3118 * @brief Checks if LSE ready interrupt source is enabled or disabled.
3119 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
3120 * @retval State of bit (1 or 0).
3121 */
LL_RCC_IsEnabledIT_LSERDY(void)3122 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
3123 {
3124 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL);
3125 }
3126
3127
3128 /**
3129 * @brief Checks if HSI ready interrupt source is enabled or disabled.
3130 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
3131 * @retval State of bit (1 or 0).
3132 */
LL_RCC_IsEnabledIT_HSIRDY(void)3133 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
3134 {
3135 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL);
3136 }
3137
3138 /**
3139 * @brief Checks if HSE ready interrupt source is enabled or disabled.
3140 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
3141 * @retval State of bit (1 or 0).
3142 */
LL_RCC_IsEnabledIT_HSERDY(void)3143 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
3144 {
3145 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL);
3146 }
3147
3148 /**
3149 * @brief Checks if PLL1 ready interrupt source is enabled or disabled.
3150 * @rmtoll CIER PLL1RDYIE LL_RCC_IsEnabledIT_PLL1RDY
3151 * @retval State of bit (1 or 0).
3152 */
LL_RCC_IsEnabledIT_PLL1RDY(void)3153 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL1RDY(void)
3154 {
3155 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL);
3156 }
3157
3158 /**
3159 * @}
3160 */
3161
3162 /** @defgroup RCC_LL_EF_Security_Services Security Services
3163 * @{
3164 */
3165
3166 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3167 /**
3168 * @brief Configure RCC resources security
3169 * @note Only available from secure state when system implements security (TZEN=1)
3170 * @rmtoll SECCFGR HSISEC LL_RCC_ConfigSecure\n
3171 * SECCFGR HSESEC LL_RCC_ConfigSecure\n
3172 * SECCFGR LSISEC LL_RCC_ConfigSecure\n
3173 * SECCFGR LSESEC LL_RCC_ConfigSecure\n
3174 * SECCFGR SYSCLKSEC LL_RCC_ConfigSecure\n
3175 * SECCFGR PRESCSEC LL_RCC_ConfigSecure\n
3176 * SECCFGR PLL1SEC LL_RCC_ConfigSecure\n
3177 * SECCFGR RMVFSEC LL_RCC_ConfigSecure
3178 * @param SecureConfig This parameter can be one or a combination of the following values:
3179 * @arg @ref LL_RCC_ALL_NSEC & LL_RCC_ALL_SEC
3180 * @arg @ref LL_RCC_HSI_SEC & LL_RCC_HSI_NSEC
3181 * @arg @ref LL_RCC_HSE_SEC & LL_RCC_HSE_NSEC
3182 * @arg @ref LL_RCC_LSE_SEC & LL_RCC_LSE_NSEC
3183 * @arg @ref LL_RCC_LSI_SEC & LL_RCC_LSI_NSEC
3184 * @arg @ref LL_RCC_SYSCLK_SEC & LL_RCC_SYSCLK_NSEC
3185 * @arg @ref LL_RCC_PRESCALERS_SEC & LL_RCC_PRESCALERS_NSEC
3186 * @arg @ref LL_RCC_PLL1_SEC & LL_RCC_PLL1_NSEC
3187 * @arg @ref LL_RCC_RESET_FLAGS_SEC & LL_RCC_RESET_FLAGS_NSEC
3188 * @retval None
3189 */
LL_RCC_ConfigSecure(uint32_t SecureConfig)3190 __STATIC_INLINE void LL_RCC_ConfigSecure(uint32_t SecureConfig)
3191 {
3192 WRITE_REG(RCC->SECCFGR, SecureConfig);
3193 }
3194 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
3195
3196 /**
3197 * @brief Get RCC resources security status
3198 * @note Only available from secure state when system implements security (TZEN=1)
3199 * @rmtoll SECCFGR HSISEC LL_RCC_GetConfigSecure\n
3200 * SECCFGR HSESEC LL_RCC_GetConfigSecure\n
3201 * SECCFGR LSISEC LL_RCC_GetConfigSecure\n
3202 * SECCFGR LSESEC LL_RCC_GetConfigSecure\n
3203 * SECCFGR SYSCLKSEC LL_RCC_GetConfigSecure\n
3204 * SECCFGR PRESCSEC LL_RCC_GetConfigSecure\n
3205 * SECCFGR PLL1SEC LL_RCC_GetConfigSecure\n
3206 * SECCFGR RMVFSEC LL_RCC_GetConfigSecure
3207 * @retval Returned value can be one or a combination of the following values:
3208 * @arg @ref LL_RCC_ALL_NSEC & LL_RCC_ALL_SEC
3209 * @arg @ref LL_RCC_HSI_SEC & LL_RCC_HSI_NSEC
3210 * @arg @ref LL_RCC_HSE_SEC & LL_RCC_HSE_NSEC
3211 * @arg @ref LL_RCC_LSE_SEC & LL_RCC_LSE_NSEC
3212 * @arg @ref LL_RCC_LSI_SEC & LL_RCC_LSI_NSEC
3213 * @arg @ref LL_RCC_SYSCLK_SEC & LL_RCC_SYSCLK_NSEC
3214 * @arg @ref LL_RCC_PRESCALERS_SEC & LL_RCC_PRESCALERS_NSEC
3215 * @arg @ref LL_RCC_PLL1_SEC & LL_RCC_PLL1_NSEC
3216 * @arg @ref LL_RCC_RESET_FLAGS_SEC & LL_RCC_RESET_FLAGS_NSEC
3217 * @retval None
3218 */
LL_RCC_GetConfigSecure(void)3219 __STATIC_INLINE uint32_t LL_RCC_GetConfigSecure(void)
3220 {
3221 return (uint32_t)(READ_BIT(RCC->SECCFGR, RCC_SECURE_MASK));
3222 }
3223
3224 /**
3225 * @}
3226 */
3227
3228 #if defined(USE_FULL_LL_DRIVER)
3229 /** @defgroup RCC_LL_EF_Init De-initialization function
3230 * @{
3231 */
3232 ErrorStatus LL_RCC_DeInit(void);
3233 /**
3234 * @}
3235 */
3236
3237 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
3238 * @{
3239 */
3240 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
3241 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
3242 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
3243 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
3244 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
3245 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
3246 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
3247 uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource);
3248 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
3249 /**
3250 * @}
3251 */
3252
3253 #endif /* USE_FULL_LL_DRIVER */
3254
3255 /**
3256 * @}
3257 */
3258
3259 /**
3260 * @}
3261 */
3262
3263 #endif /* defined(RCC) */
3264
3265 /**
3266 * @}
3267 */
3268
3269 #ifdef __cplusplus
3270 }
3271 #endif
3272
3273 #endif /* STM32WBAxx_LL_RCC_H */
3274
3275
