1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WBAxx_LL_PWR_H
21 #define STM32WBAxx_LL_PWR_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif /* __cplusplus */
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbaxx.h"
29
30 /** @addtogroup STM32WBAxx_LL_Driver
31 * @{
32 */
33
34 #if defined (PWR)
35
36 /** @defgroup PWR_LL PWR
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /* Exported types ------------------------------------------------------------*/
45 /* Exported constants --------------------------------------------------------*/
46
47 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
48 * @{
49 */
50
51 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
52 * @brief Flags defines which can be used with LL_PWR_WriteReg function
53 * @{
54 */
55 #define LL_PWR_SR_CSSF PWR_SR_CSSF /*!< Clear Stop and Standby flags */
56 #define LL_PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1 /*!< Clear Wakeup flag 1 */
57 #define LL_PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2 /*!< Clear Wakeup flag 2 */
58 #define LL_PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3 /*!< Clear Wakeup flag 3 */
59 #define LL_PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4 /*!< Clear Wakeup flag 4 */
60 #define LL_PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5 /*!< Clear Wakeup flag 5 */
61 #define LL_PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6 /*!< Clear Wakeup flag 6 */
62 #define LL_PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7 /*!< Clear Wakeup flag 7 */
63 #define LL_PWR_WUSCR_CWUF8 PWR_WUSCR_CWUF8 /*!< Clear Wakeup flag 8 */
64 #define LL_PWR_WUSCR_CWUF_ALL PWR_WUSCR_CWUF /*!< Clear all Wakeup flags */
65 /**
66 * @}
67 */
68
69 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
70 * @brief Flags defines which can be used with LL_PWR_ReadReg function
71 * @{
72 */
73 #define LL_PWR_FLAG_VOSRDY PWR_VOSR_VOSRDY /*!< Voltage scaling ready flag */
74 #define LL_PWR_FLAG_STOPF PWR_SR_STOPF /*!< Stop flag */
75 #define LL_PWR_FLAG_SBF PWR_SR_SBF /*!< Standby flag */
76 #define LL_PWR_FLAG_ACTVOSRDY PWR_SVMSR_ACTVOSRDY /*!< Currently applied VOS ready flag */
77 #define LL_PWR_FLAG_PVDO PWR_SVMSR_PVDO /*!< VDD voltage detector output flag */
78 #define LL_PWR_FLAG_REGS PWR_SVMSR_REGS /*!< Regulator selection flag */
79
80 #define LL_PWR_WAKEUP_FLAG1 PWR_WUSR_WUF1 /*!< Wakeup flag 1 */
81 #define LL_PWR_WAKEUP_FLAG2 PWR_WUSR_WUF2 /*!< Wakeup flag 2 */
82 #define LL_PWR_WAKEUP_FLAG3 PWR_WUSR_WUF3 /*!< Wakeup flag 3 */
83 #define LL_PWR_WAKEUP_FLAG4 PWR_WUSR_WUF4 /*!< Wakeup flag 4 */
84 #define LL_PWR_WAKEUP_FLAG5 PWR_WUSR_WUF5 /*!< Wakeup flag 5 */
85 #define LL_PWR_WAKEUP_FLAG6 PWR_WUSR_WUF6 /*!< Wakeup flag 6 */
86 #define LL_PWR_WAKEUP_FLAG7 PWR_WUSR_WUF7 /*!< Wakeup flag 7 */
87 #define LL_PWR_WAKEUP_FLAG8 PWR_WUSR_WUF8 /*!< Wakeup flag 8 */
88 /**
89 * @}
90 */
91
92 /** @defgroup PWR_LL_EC_LOW_POWER_MODE_SELECTION Low Power Mode Selection
93 * @{
94 */
95 #define LL_PWR_MODE_STOP0 0U /*!< Stop 0 mode */
96 #define LL_PWR_MODE_STOP1 PWR_CR1_LPMS_0 /*!< Stop 1 mode */
97 #define LL_PWR_MODE_STANDBY PWR_CR1_LPMS_2 /*!< Standby mode */
98 /**
99 * @}
100 */
101
102 /** @defgroup PWR_LL_EC_SRAM1_SB_RETENTION PWR SRAM1 Retention in Standby Mode
103 * @{
104 */
105 #define LL_PWR_SRAM1_SB_NO_RETENTION 0U /*!< SRAM1 no retention in Standby mode */
106 #define LL_PWR_SRAM1_SB_FULL_RETENTION PWR_CR1_R1RSB1 /*!< SRAM1 all pages retention in Standby mode */
107 /**
108 * @}
109 */
110
111 /** @defgroup PWR_LL_EC_SRAM2_SB_RETENTION PWR SRAM2 Retention in Standby Mode
112 * @{
113 */
114 #define LL_PWR_SRAM2_SB_NO_RETENTION 0U /*!< SRAM2 no retention in Standby mode */
115 #define LL_PWR_SRAM2_SB_FULL_RETENTION PWR_CR1_R2RSB1 /*!< SRAM2 all pages retention in Standby mode */
116 /**
117 * @}
118 */
119
120 /** @defgroup PWR_LL_EC_RADIO_SB_RETENTION PWR RADIO SRAMs and Sleep Clock Retention in Standby Mode
121 * @{
122 */
123 #define LL_PWR_RADIO_SB_NO_RETENTION 0U /*!< 2.4 GHz RADIO SRAMs and sleep timer content not retained in Standby mode */
124 #define LL_PWR_RADIO_SB_FULL_RETENTION PWR_CR1_RADIORSB /*!< 2.4 GHz RADIO SRAMs and sleep timer content retained in Standby mode */
125 /**
126 * @}
127 */
128
129 /** @defgroup PWR_LL_EC_SRAM1_STOP_RETENTION PWR SRAM1 Retention in Stop Mode
130 * @{
131 */
132 #define LL_PWR_SRAM1_STOP_NO_RETENTION 0U /*!< SRAM1 no retention in Stop mode */
133 #define LL_PWR_SRAM1_STOP_FULL_RETENTION PWR_CR2_SRAM1PDS1 /*!< SRAM1 all pages retention in Stop mode */
134 /**
135 * @}
136 */
137
138 /** @defgroup PWR_LL_EC_SRAM2_STOP_RETENTION PWR SRAM2 Retention in Stop Mode
139 * @{
140 */
141 #define LL_PWR_SRAM2_STOP_NO_RETENTION 0U /*!< SRAM2 no retention in Stop mode */
142 #define LL_PWR_SRAM2_STOP_FULL_RETENTION PWR_CR2_SRAM2PDS1 /*!< SRAM2 all pages retention in Stop mode */
143 /**
144 * @}
145 */
146
147 /** @defgroup PWR_LL_EC_ICACHERAM_STOP_RETENTION PWR ICACHE SRAM Retention in Stop Mode
148 * @{
149 */
150 #define LL_PWR_ICACHERAM_STOP_NO_RETENTION 0U /*!< ICACHE SRAM no retention in Stop mode */
151 #define LL_PWR_ICACHERAM_STOP_FULL_RETENTION PWR_CR2_ICRAMPDS /*!< ICACHE SRAM full retention in Stop mode */
152 /**
153 * @}
154 */
155
156 /** @defgroup PWR_LL_EC_SMPS_PWM_MODE PWR SMPS PWM mode
157 * @{
158 */
159 #define LL_PWR_SMPS_NO_PWM_MODE 0U /*!< SMPS PWM mode disabled (high-efficiency mode) */
160 #define LL_PWR_SMPS_PWM_MODE PWR_CR2_FPWM /*!< SMPS PWM mode enabled (harmonic reduction) */
161 /**
162 * @}
163 */
164
165 /** @defgroup PWR_LL_EC_REGULATOR_SUPPLY_SELECTION PWR Regulator Supply Selection
166 * @{
167 */
168 #define LL_PWR_LDO_SUPPLY 0U /*!< LDO regulator supply */
169 #define LL_PWR_SMPS_SUPPLY PWR_CR3_REGSEL /*!< SMPS regulator supply */
170 /**
171 * @}
172 */
173
174 /** @defgroup PWR_LL_EC_REGULATOR_VDDHPA_SUPPLY_SELECTION PWR Regulator REG_VDDHPA input supply selection
175 * @{
176 */
177 #define LL_PWR_REG_VDDHPA_VDDRFPA_PIN 0U /*!< VDDRFPA pin selected as regulator REG_VDDHPA input supply */
178 #define LL_PWR_REG_VDDHPA_VDDRFPA_VDD11 PWR_RADIOSCR_REGPASEL /*!< Regulator REG_VDDHPA input supply selection between VDDRFPA and VDD11 dependent on requested regulated output voltage */
179 /**
180 * @}
181 */
182
183 /** @defgroup PWR_LL_EC_RADIO_PHY_MODE PWR 2.4 GHz RADIO PHY operating mode
184 * @{
185 */
186 #define LL_PWR_RADIO_PHY_SLEEP_MODE 0U /*!< 2.4 GHz RADIO Sleep mode */
187 #define LL_PWR_RADIO_PHY_STANDBY_MODE PWR_RADIOSCR_PHYMODE /*!< 2.4 GHz RADIO Standby mode */
188 /**
189 * @}
190 */
191
192 /** @defgroup PWR_LL_EC_RADIO_OPERATING_MODE PWR 2.4 GHz RADIO operating mode
193 * @{
194 */
195 #define LL_PWR_RADIO_DEEP_SLEEP_MODE 0U /*!< 2.4 GHz RADIO Deep Sleep mode */
196 #define LL_PWR_RADIO_SLEEP_MODE PWR_RADIOSCR_MODE_0 /*!< 2.4 GHz RADIO Sleep mode */
197 #define LL_PWR_RADIO_ACTIVE_MODE PWR_RADIOSCR_MODE_1 /*!< 2.4 GHz RADIO Active mode */
198 /**
199 * @}
200 */
201
202 /** @defgroup PWR_LL_EC_VOLTAGE_SCALING_RANGE_SELECTION PWR Voltage scaling range selection
203 * @{
204 */
205 #define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_VOSR_VOS /*!< Voltage scaling range 1 (highest frequency) */
206 #define LL_PWR_REGU_VOLTAGE_SCALE2 0U /*!< Voltage scaling range 2 (lowest power) */
207 /**
208 * @}
209 */
210
211 /** @defgroup PWR_LL_EC_PVD_LEVEL_SELECTION PWR Power Voltage Detector Level Selection
212 * @{
213 */
214 #define LL_PWR_PVDLEVEL_0 0U /*!< Voltage threshold detected by PVD 2.0 V */
215 #define LL_PWR_PVDLEVEL_1 PWR_SVMCR_PVDLS_0 /*!< Voltage threshold detected by PVD 2.2 V */
216 #define LL_PWR_PVDLEVEL_2 PWR_SVMCR_PVDLS_1 /*!< Voltage threshold detected by PVD 2.4 V */
217 #define LL_PWR_PVDLEVEL_3 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_1) /*!< Voltage threshold detected by PVD 2.5 V */
218 #define LL_PWR_PVDLEVEL_4 PWR_SVMCR_PVDLS_2 /*!< Voltage threshold detected by PVD 2.6 V */
219 #define LL_PWR_PVDLEVEL_5 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_2) /*!< Voltage threshold detected by PVD 2.8 V */
220 #define LL_PWR_PVDLEVEL_6 (PWR_SVMCR_PVDLS_1 | PWR_SVMCR_PVDLS_2) /*!< Voltage threshold detected by PVD 2.9 V */
221 #define LL_PWR_PVDLEVEL_7 PWR_SVMCR_PVDLS /*!< External input analog voltage on PVD_IN
222 pin, compared to internal VREFINT level */
223 /**
224 * @}
225 */
226
227 /** @defgroup PWR_LL_EC_WAKEUP_PIN PWR Wake Up Pin
228 * @{
229 */
230 #define LL_PWR_WAKEUP_PIN1 PWR_WUCR1_WUPEN1 /*!< Wakeup pin 1 enable */
231 #define LL_PWR_WAKEUP_PIN2 PWR_WUCR1_WUPEN2 /*!< Wakeup pin 2 enable */
232 #define LL_PWR_WAKEUP_PIN3 PWR_WUCR1_WUPEN3 /*!< Wakeup pin 3 enable */
233 #define LL_PWR_WAKEUP_PIN4 PWR_WUCR1_WUPEN4 /*!< Wakeup pin 4 enable */
234 #define LL_PWR_WAKEUP_PIN5 PWR_WUCR1_WUPEN5 /*!< Wakeup pin 5 enable */
235 #define LL_PWR_WAKEUP_PIN6 PWR_WUCR1_WUPEN6 /*!< Wakeup pin 6 enable */
236 #define LL_PWR_WAKEUP_PIN7 PWR_WUCR1_WUPEN7 /*!< Wakeup pin 7 enable */
237 #define LL_PWR_WAKEUP_PIN8 PWR_WUCR1_WUPEN8 /*!< Wakeup pin 8 enable */
238 /**
239 * @}
240 */
241
242 /** @defgroup PWR_LL_EC_WAKEUP_PIN_SELECTION PWR Wakeup Pin Selection
243 * @{
244 */
245 #define LL_PWR_WAKEUP_PIN_SELECTION_0 0UL /*!< Wakeup pin selection 0 */
246 #define LL_PWR_WAKEUP_PIN_SELECTION_1 PWR_WUCR3_WUSEL1_0 /*!< Wakeup pin selection 1 */
247 #define LL_PWR_WAKEUP_PIN_SELECTION_2 PWR_WUCR3_WUSEL1_1 /*!< Wakeup pin selection 2 */
248 #define LL_PWR_WAKEUP_PIN_SELECTION_3 PWR_WUCR3_WUSEL1 /*!< Wakeup pin selection 3 */
249 /**
250 * @}
251 */
252
253 /** @defgroup PWR_LL_EC_GPIO_STATE_RETENTION_ENABLE_SELECTION PWR GPIO State Retention Enable Port Selection
254 * @{
255 */
256 #define LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTA (uint32_t)(&(PWR->IORETENRA)) /*!< GPIO port A */
257 #define LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTB (uint32_t)(&(PWR->IORETENRB)) /*!< GPIO port B */
258 #define LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTC (uint32_t)(&(PWR->IORETENRC)) /*!< GPIO port C */
259 #define LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTH (uint32_t)(&(PWR->IORETENRH)) /*!< GPIO port H */
260 /**
261 * @}
262 */
263
264 /** @defgroup PWR_LL_EC_GPIO_STATE_RETENTION_STATUS_SELECTION PWR GPIO State Retention Status Port Selection
265 * @{
266 */
267 #define LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTA (uint32_t)(&(PWR->IORETRA)) /*!< GPIO port A */
268 #define LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTB (uint32_t)(&(PWR->IORETRB)) /*!< GPIO port B */
269 #define LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTC (uint32_t)(&(PWR->IORETRC)) /*!< GPIO port C */
270 #define LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTH (uint32_t)(&(PWR->IORETRH)) /*!< GPIO port H */
271 /**
272 * @}
273 */
274
275 /** @defgroup PWR_LL_EC_GPIO_PIN_MASK PWR GPIO Pin Mask
276 * @{
277 */
278 #define LL_PWR_GPIO_PIN_0 (0x0001U) /*!< GPIO port I/O pin 0 */
279 #define LL_PWR_GPIO_PIN_1 (0x0002U) /*!< GPIO port I/O pin 1 */
280 #define LL_PWR_GPIO_PIN_2 (0x0004U) /*!< GPIO port I/O pin 2 */
281 #define LL_PWR_GPIO_PIN_3 (0x0008U) /*!< GPIO port I/O pin 3 */
282 #define LL_PWR_GPIO_PIN_4 (0x0010U) /*!< GPIO port I/O pin 4 */
283 #define LL_PWR_GPIO_PIN_5 (0x0020U) /*!< GPIO port I/O pin 5 */
284 #define LL_PWR_GPIO_PIN_6 (0x0040U) /*!< GPIO port I/O pin 6 */
285 #define LL_PWR_GPIO_PIN_7 (0x0080U) /*!< GPIO port I/O pin 7 */
286 #define LL_PWR_GPIO_PIN_8 (0x0100U) /*!< GPIO port I/O pin 8 */
287 #define LL_PWR_GPIO_PIN_9 (0x0200U) /*!< GPIO port I/O pin 9 */
288 #define LL_PWR_GPIO_PIN_10 (0x0400U) /*!< GPIO port I/O pin 10 */
289 #define LL_PWR_GPIO_PIN_11 (0x0800U) /*!< GPIO port I/O pin 11 */
290 #define LL_PWR_GPIO_PIN_12 (0x1000U) /*!< GPIO port I/O pin 12 */
291 #define LL_PWR_GPIO_PIN_13 (0x2000U) /*!< GPIO port I/O pin 13 */
292 #define LL_PWR_GPIO_PIN_14 (0x4000U) /*!< GPIO port I/O pin 14 */
293 #define LL_PWR_GPIO_PIN_15 (0x8000U) /*!< GPIO port I/O pin 15 */
294 /**
295 * @}
296 */
297
298 /** @defgroup PWR_LL_EC_ITEMS_SECURE_ATTRIBUTE PWR Items Secure Attribute
299 * @{
300 */
301 #define LL_PWR_WAKEUP_PIN1_NSEC 0U /*!< Wake up pin 1 nsecure mode */
302 #define LL_PWR_WAKEUP_PIN1_SEC PWR_SECCFGR_WUP1SEC /*!< Wake up pin 1 secure mode */
303 #define LL_PWR_WAKEUP_PIN2_NSEC 0U /*!< Wake up pin 2 nsecure mode */
304 #define LL_PWR_WAKEUP_PIN2_SEC PWR_SECCFGR_WUP2SEC /*!< Wake up pin 2 secure mode */
305 #define LL_PWR_WAKEUP_PIN3_NSEC 0U /*!< Wake up pin 3 nsecure mode */
306 #define LL_PWR_WAKEUP_PIN3_SEC PWR_SECCFGR_WUP3SEC /*!< Wake up pin 3 secure mode */
307 #define LL_PWR_WAKEUP_PIN4_NSEC 0U /*!< Wake up pin 4 nsecure mode */
308 #define LL_PWR_WAKEUP_PIN4_SEC PWR_SECCFGR_WUP4SEC /*!< Wake up pin 4 secure mode */
309 #define LL_PWR_WAKEUP_PIN5_NSEC 0U /*!< Wake up pin 5 nsecure mode */
310 #define LL_PWR_WAKEUP_PIN5_SEC PWR_SECCFGR_WUP5SEC /*!< Wake up pin 5 secure mode */
311 #define LL_PWR_WAKEUP_PIN6_NSEC 0U /*!< Wake up pin 6 nsecure mode */
312 #define LL_PWR_WAKEUP_PIN6_SEC PWR_SECCFGR_WUP6SEC /*!< Wake up pin 6 secure mode */
313 #define LL_PWR_WAKEUP_PIN7_NSEC 0U /*!< Wake up pin 7 nsecure mode */
314 #define LL_PWR_WAKEUP_PIN7_SEC PWR_SECCFGR_WUP7SEC /*!< Wake up pin 7 secure mode */
315 #define LL_PWR_WAKEUP_PIN8_NSEC 0U /*!< Wake up pin 8 nsecure mode */
316 #define LL_PWR_WAKEUP_PIN8_SEC PWR_SECCFGR_WUP8SEC /*!< Wake up pin 8 secure mode */
317
318 #define LL_PWR_LPM_NSEC 0U /*!< Low-power modes nsecure mode */
319 #define LL_PWR_LPM_SEC PWR_SECCFGR_LPMSEC /*!< Low-power modes secure mode */
320 #define LL_PWR_VDM_NSEC 0U /*!< Voltage detection and monitoring nsecure mode */
321 #define LL_PWR_VDM_SEC PWR_SECCFGR_VDMSEC /*!< Voltage detection and monitoring secure mode */
322 #define LL_PWR_VB_NSEC 0U /*!< Backup domain nsecure mode */
323 #define LL_PWR_VB_SEC PWR_SECCFGR_VBSEC /*!< Backup domain secure mode */
324 /**
325 * @}
326 */
327
328 /**
329 * @}
330 */
331
332 /* Exported macro ------------------------------------------------------------*/
333
334 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
335 * @{
336 */
337
338 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and Read Registers Macros
339 * @{
340 */
341
342 /**
343 * @brief Write a value in PWR register.
344 * @param __REG__ Register to be written.
345 * @param __VALUE__ Value to be written in the register.
346 * @retval None.
347 */
348 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
349
350 /**
351 * @brief Read a value in PWR register.
352 * @param __REG__ Register to be read.
353 * @retval Register value.
354 */
355 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
356 /**
357 * @}
358 */
359
360 /**
361 * @}
362 */
363
364 /* Exported functions --------------------------------------------------------*/
365
366 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
367 * @{
368 */
369
370 /** @defgroup PWR_LL_EF_CONFIGURATION PWR Configuration
371 * @{
372 */
373
374 /**
375 * @brief Set system power mode.
376 * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
377 * @param Mode This parameter can be one of the following values:
378 * @arg @ref LL_PWR_MODE_STOP0
379 * @arg @ref LL_PWR_MODE_STOP1
380 * @arg @ref LL_PWR_MODE_STANDBY
381 * @retval None
382 */
LL_PWR_SetPowerMode(uint32_t Mode)383 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t Mode)
384 {
385 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, Mode);
386 }
387
388 /**
389 * @brief Get system power mode.
390 * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
391 * @retval Returned value can be one of the following values:
392 * @arg @ref LL_PWR_MODE_STOP0
393 * @arg @ref LL_PWR_MODE_STOP1
394 * @arg @ref LL_PWR_MODE_STANDBY
395 */
LL_PWR_GetPowerMode(void)396 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
397 {
398 return (READ_BIT(PWR->CR1, PWR_CR1_LPMS));
399 }
400
401 /**
402 * @brief Set the SRAM2 page(s) retention in Standby mode.
403 * @rmtoll CR1 R2RSB1 LL_PWR_SetSRAM2SBRetention
404 * @param SRAM2PageRetention This parameter can be one of the following values:
405 * @arg @ref LL_PWR_SRAM2_SB_NO_RETENTION
406 * @arg @ref LL_PWR_SRAM2_SB_FULL_RETENTION
407 * @retval None
408 */
LL_PWR_SetSRAM2SBRetention(uint32_t SRAM2PageRetention)409 __STATIC_INLINE void LL_PWR_SetSRAM2SBRetention(uint32_t SRAM2PageRetention)
410 {
411 MODIFY_REG(PWR->CR1, PWR_CR1_R2RSB1, SRAM2PageRetention);
412 }
413
414 /**
415 * @brief Get the SRAM2 page(s) retention in Standby mode.
416 * @rmtoll CR1 R2RSB1 LL_PWR_GetSRAM2SBRetention
417 * @retval Returned value can be one of the following values:
418 * @arg @ref LL_PWR_SRAM2_SB_NO_RETENTION
419 * @arg @ref LL_PWR_SRAM2_SB_FULL_RETENTION
420 */
LL_PWR_GetSRAM2SBRetention(void)421 __STATIC_INLINE uint32_t LL_PWR_GetSRAM2SBRetention(void)
422 {
423 return (READ_BIT(PWR->CR1, PWR_CR1_R2RSB1));
424 }
425
426 /**
427 * @brief Set the SRAM1 page(s) retention in Standby mode.
428 * @rmtoll CR1 R1RSB1 LL_PWR_SetSRAM1SBRetention
429 * @param SRAM1PageRetention This parameter can be one of the following values:
430 * @arg @ref LL_PWR_SRAM1_SB_NO_RETENTION
431 * @arg @ref LL_PWR_SRAM1_SB_FULL_RETENTION
432 * @retval None
433 */
LL_PWR_SetSRAM1SBRetention(uint32_t SRAM1PageRetention)434 __STATIC_INLINE void LL_PWR_SetSRAM1SBRetention(uint32_t SRAM1PageRetention)
435 {
436 MODIFY_REG(PWR->CR1, PWR_CR1_R1RSB1, SRAM1PageRetention);
437 }
438
439 /**
440 * @brief Get the SRAM1 page(s) retention in Standby mode.
441 * @rmtoll CR1 R1RSB1 LL_PWR_GetSRAM1SBRetention
442 * @retval Returned value can be one of the following values:
443 * @arg @ref LL_PWR_SRAM1_SB_NO_RETENTION
444 * @arg @ref LL_PWR_SRAM1_SB_FULL_RETENTION
445 */
LL_PWR_GetSRAM1SBRetention(void)446 __STATIC_INLINE uint32_t LL_PWR_GetSRAM1SBRetention(void)
447 {
448 return (READ_BIT(PWR->CR1, PWR_CR1_R1RSB1));
449 }
450
451 /**
452 * @brief Set the Radio retention in Standby mode.
453 * @rmtoll CR1 RADIORSB LL_PWR_SetRadioSBRetention
454 * @param RadioRetention This parameter can be one of the following values:
455 * @arg @ref LL_PWR_RADIO_SB_NO_RETENTION
456 * @arg @ref LL_PWR_RADIO_SB_FULL_RETENTION
457 * @retval None
458 */
LL_PWR_SetRadioSBRetention(uint32_t RadioRetention)459 __STATIC_INLINE void LL_PWR_SetRadioSBRetention(uint32_t RadioRetention)
460 {
461 MODIFY_REG(PWR->CR1, PWR_CR1_RADIORSB, RadioRetention);
462 }
463
464 /**
465 * @brief Get the Radio retention in Standby mode.
466 * @rmtoll CR1 RADIORSB LL_PWR_GetRadioSBRetention
467 * @retval Returned value can be one of the following values:
468 * @arg @ref LL_PWR_RADIO_SB_NO_RETENTION
469 * @arg @ref LL_PWR_RADIO_SB_FULL_RETENTION
470 */
LL_PWR_GetRadioSBRetention(void)471 __STATIC_INLINE uint32_t LL_PWR_GetRadioSBRetention(void)
472 {
473 return (READ_BIT(PWR->CR1, PWR_CR1_RADIORSB));
474 }
475
476 /**
477 * @brief Enable BOR ultra low power mode.
478 * @rmtoll CR1 UPLMEN LL_PWR_EnableUltraLowPowerMode
479 * @retval None
480 */
LL_PWR_EnableUltraLowPowerMode(void)481 __STATIC_INLINE void LL_PWR_EnableUltraLowPowerMode(void)
482 {
483 SET_BIT(PWR->CR1, PWR_CR1_ULPMEN);
484 }
485
486 /**
487 * @brief Disable BOR ultra low-power mode.
488 * @rmtoll CR1 UPLMEN LL_PWR_DisableUltraLowPowerMode
489 * @retval None
490 */
LL_PWR_DisableUltraLowPowerMode(void)491 __STATIC_INLINE void LL_PWR_DisableUltraLowPowerMode(void)
492 {
493 CLEAR_BIT(PWR->CR1, PWR_CR1_ULPMEN);
494 }
495
496 /**
497 * @brief Check if BOR ultra low power mode is enabled.
498 * @rmtoll CR1 UPLMEN LL_PWR_IsEnabledUltraLowPowerMode
499 * @retval State of bit (1 or 0).
500 */
LL_PWR_IsEnabledUltraLowPowerMode(void)501 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPowerMode(void)
502 {
503 return ((READ_BIT(PWR->CR1, PWR_CR1_ULPMEN) == (PWR_CR1_ULPMEN)) ? 1UL : 0UL);
504 }
505
506
507 /**
508 * @brief Set the SRAM1 page(s) retention in Stop mode.
509 * @rmtoll CR2 SRAM1PDS1 LL_PWR_SetSRAM1StopRetention
510 * @param SRAM1PageRetention This parameter can be one of the following values:
511 * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION
512 * @arg @ref LL_PWR_SRAM1_STOP_FULL_RETENTION
513 * @retval None
514 */
LL_PWR_SetSRAM1StopRetention(uint32_t SRAM1PageRetention)515 __STATIC_INLINE void LL_PWR_SetSRAM1StopRetention(uint32_t SRAM1PageRetention)
516 {
517 MODIFY_REG(PWR->CR2, PWR_CR2_SRAM1PDS1, ((~SRAM1PageRetention) & PWR_CR2_SRAM1PDS1));
518 }
519
520 /**
521 * @brief Get the SRAM1 page(s) retention in Stop mode.
522 * @rmtoll CR2 SRAM1PDS1 LL_PWR_GetSRAM1StopRetention
523 * @retval Returned value can be one of the following values:
524 * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION
525 * @arg @ref LL_PWR_SRAM1_STOP_FULL_RETENTION
526 */
LL_PWR_GetSRAM1StopRetention(void)527 __STATIC_INLINE uint32_t LL_PWR_GetSRAM1StopRetention(void)
528 {
529 return ((~(READ_BIT(PWR->CR2, PWR_CR2_SRAM1PDS1))) & PWR_CR2_SRAM1PDS1);
530 }
531
532 /**
533 * @brief Set the SRAM2 page(s) retention in Stop mode.
534 * @rmtoll CR2 SRAM2PDS1 LL_PWR_SetSRAM2StopRetention
535 * @param SRAM2PageRetention This parameter can be one of the following values:
536 * @arg @ref LL_PWR_SRAM2_STOP_NO_RETENTION
537 * @arg @ref LL_PWR_SRAM2_STOP_FULL_RETENTION
538 * @retval None
539 */
LL_PWR_SetSRAM2StopRetention(uint32_t SRAM2PageRetention)540 __STATIC_INLINE void LL_PWR_SetSRAM2StopRetention(uint32_t SRAM2PageRetention)
541 {
542 MODIFY_REG(PWR->CR2, PWR_CR2_SRAM2PDS1, ((~SRAM2PageRetention) & PWR_CR2_SRAM2PDS1));
543 }
544
545 /**
546 * @brief Get the SRAM2 page(s) retention in Stop mode.
547 * @rmtoll CR2 SRAM2PDS1 LL_PWR_GetSRAM2StopRetention
548 * @retval Returned value can be one of the following values:
549 * @arg @ref LL_PWR_SRAM2_STOP_NO_RETENTION
550 * @arg @ref LL_PWR_SRAM2_STOP_FULL_RETENTION
551 */
LL_PWR_GetSRAM2StopRetention(void)552 __STATIC_INLINE uint32_t LL_PWR_GetSRAM2StopRetention(void)
553 {
554 return ((~(READ_BIT(PWR->CR2, PWR_CR2_SRAM2PDS1))) & PWR_CR2_SRAM2PDS1);
555 }
556
557 /**
558 * @brief Set the ICACHE SRAM page(s) retention in Stop mode.
559 * @rmtoll CR2 ICRAMPDS LL_PWR_SetICacheRAMStopRetention
560 #if defined(STM32WBAXX_SI_CUT1_0)
561 * @note On Silicon Cut 1.0, it is mandatory to disable the ICACHE before going into
562 * stop modes otherwise an hard fault may occur when waking up from stop modes.
563 #endif
564 * @param ICRAMPageRetention This parameter can be one of the following values:
565 * @arg @ref LL_PWR_ICACHERAM_STOP_NO_RETENTION
566 * @arg @ref LL_PWR_ICACHERAM_STOP_FULL_RETENTION
567 * @retval None
568 */
LL_PWR_SetICacheRAMStopRetention(uint32_t ICRAMPageRetention)569 __STATIC_INLINE void LL_PWR_SetICacheRAMStopRetention(uint32_t ICRAMPageRetention)
570 {
571 MODIFY_REG(PWR->CR2, PWR_CR2_ICRAMPDS,
572 ((~ICRAMPageRetention) & PWR_CR2_ICRAMPDS));
573 }
574
575 /**
576 * @brief Get the ICACHE SRAM page(s) retention in Stop mode.
577 * @rmtoll CR2 ICRAMPDS LL_PWR_GetICacheRAMStopRetention
578 * @retval Returned value can be one of the following values:
579 * @arg @ref LL_PWR_ICACHERAM_STOP_NO_RETENTION
580 * @arg @ref LL_PWR_ICACHERAM_STOP_FULL_RETENTION
581 */
LL_PWR_GetICacheRAMStopRetention(void)582 __STATIC_INLINE uint32_t LL_PWR_GetICacheRAMStopRetention(void)
583 {
584 return ((~(READ_BIT(PWR->CR2, PWR_CR2_ICRAMPDS))) & PWR_CR2_ICRAMPDS);
585 }
586
587 /**
588 * @brief Enable the flash memory fast wakeup from Stop mode (Stop 0, 1).
589 * @rmtoll CR2 FLASHFWU LL_PWR_EnableFlashFastWakeUp
590 * @retval None
591 */
LL_PWR_EnableFlashFastWakeUp(void)592 __STATIC_INLINE void LL_PWR_EnableFlashFastWakeUp(void)
593 {
594 SET_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
595 }
596
597 /**
598 * @brief Disable the flash memory fast wakeup from Stop mode (Stop 0, 1).
599 * @rmtoll CR2 FLASHFWU LL_PWR_DisableFlashFastWakeUp
600 * @retval None
601 */
LL_PWR_DisableFlashFastWakeUp(void)602 __STATIC_INLINE void LL_PWR_DisableFlashFastWakeUp(void)
603 {
604 CLEAR_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
605 }
606
607 /**
608 * @brief Check if the flash memory fast wakeup from Stop mode (Stop 0, 1) is enabled.
609 * @rmtoll CR2 FLASHFWU LL_PWR_IsEnabledFlashFastWakeUp
610 * @retval State of bit (1 or 0).
611 */
LL_PWR_IsEnabledFlashFastWakeUp(void)612 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashFastWakeUp(void)
613 {
614 return ((READ_BIT(PWR->CR2, PWR_CR2_FLASHFWU) == (PWR_CR2_FLASHFWU)) ? 1UL : 0UL);
615 }
616
617 #if defined(PWR_CR3_REGSEL)
618 /**
619 * @brief Set the VCore regulator supply.
620 * @rmtoll CR3 REGSEL LL_PWR_SetRegulatorSupply
621 * @param RegulatorSupply This parameter can be one of the following values:
622 * @arg @ref LL_PWR_LDO_SUPPLY
623 * @arg @ref LL_PWR_SMPS_SUPPLY
624 * @retval None
625 */
LL_PWR_SetRegulatorSupply(uint32_t RegulatorSupply)626 __STATIC_INLINE void LL_PWR_SetRegulatorSupply(uint32_t RegulatorSupply)
627 {
628 MODIFY_REG(PWR->CR3, PWR_CR3_REGSEL, RegulatorSupply);
629 }
630
631 /**
632 * @brief Get the VCore regulator supply.
633 * @rmtoll CR3 REGSEL LL_PWR_GetRegulatorSupply
634 * @retval Returned value can be one of the following values:
635 * @arg @ref LL_PWR_LDO_SUPPLY
636 * @arg @ref LL_PWR_SMPS_SUPPLY
637 */
LL_PWR_GetRegulatorSupply(void)638 __STATIC_INLINE uint32_t LL_PWR_GetRegulatorSupply(void)
639 {
640 return (READ_BIT(PWR->CR3, PWR_CR3_REGSEL));
641 }
642 #endif /* PWR_CR3_REGSEL */
643
644 #if defined(PWR_CR2_FPWM)
645 /**
646 * @brief Enable the SMPS PWM mode.
647 * @rmtoll CR2 FPWM LL_PWR_EnableSMPSPWMMode
648 * @retval None
649 */
LL_PWR_EnableSMPSPWMMode(void)650 __STATIC_INLINE void LL_PWR_EnableSMPSPWMMode(void)
651 {
652 SET_BIT(PWR->CR2, PWR_CR2_FPWM);
653 }
654
655 /**
656 * @brief Disable the SMPS PWM mode.
657 * @rmtoll CR2 FPWM LL_PWR_DisableSMPSPWMMode
658 * @retval None
659 */
LL_PWR_DisableSMPSPWMMode(void)660 __STATIC_INLINE void LL_PWR_DisableSMPSPWMMode(void)
661 {
662 CLEAR_BIT(PWR->CR2, PWR_CR2_FPWM);
663 }
664
665 /**
666 * @brief Check if the SMPS PWM mode is enabled.
667 * @rmtoll CR2 FPWM LL_PWR_IsEnabledSMPSPWMMode
668 * @retval State of bit (1 or 0).
669 */
LL_PWR_IsEnabledSMPSPWMMode(void)670 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSMPSPWMMode(void)
671 {
672 return ((READ_BIT(PWR->CR2, PWR_CR2_FPWM) == (PWR_CR2_FPWM)) ? 1UL : 0UL);
673 }
674 #endif /* PWR_CR2_FPWM */
675
676 /**
677 * @brief Enable the fast soft start for selected regulator.
678 * @rmtoll CR3 FSTEN LL_PWR_EnableFastSoftStart
679 * @retval None
680 */
LL_PWR_EnableFastSoftStart(void)681 __STATIC_INLINE void LL_PWR_EnableFastSoftStart(void)
682 {
683 SET_BIT(PWR->CR3, PWR_CR3_FSTEN);
684 }
685
686 /**
687 * @brief Disable the fast soft start for selected regulator.
688 * @rmtoll CR3 FSTEN LL_PWR_DisableFastSoftStart
689 * @retval None
690 */
LL_PWR_DisableFastSoftStart(void)691 __STATIC_INLINE void LL_PWR_DisableFastSoftStart(void)
692 {
693 CLEAR_BIT(PWR->CR3, PWR_CR3_FSTEN);
694 }
695
696 /**
697 * @brief Check if the fast soft start for selected regulator is enabled.
698 * @rmtoll CR3 FSTEN LL_PWR_IsEnabledFastSoftStart
699 * @retval State of bit (1 or 0).
700 */
LL_PWR_IsEnabledFastSoftStart(void)701 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFastSoftStart(void)
702 {
703 return ((READ_BIT(PWR->CR3, PWR_CR3_FSTEN) == (PWR_CR3_FSTEN)) ? 1UL : 0UL);
704 }
705
706 /**
707 * @brief Set the regulator supply output voltage.
708 * @rmtoll VOSR VOS LL_PWR_SetRegulVoltageScaling
709 * @param VoltageScaling This parameter can be one of the following values:
710 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
711 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
712 * @retval None
713 */
LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)714 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
715 {
716 MODIFY_REG(PWR->VOSR, PWR_VOSR_VOS, VoltageScaling);
717 }
718
719 /**
720 * @brief Get the regulator supply output voltage.
721 * @rmtoll VOSR VOS LL_PWR_GetRegulVoltageScaling
722 * @retval Returned value can be one of the following values:
723 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
724 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
725 */
LL_PWR_GetRegulVoltageScaling(void)726 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
727 {
728 return (uint32_t)(READ_BIT(PWR->VOSR, PWR_VOSR_VOS));
729 }
730
731 /**
732 * @brief Set the Power voltage detector level.
733 * @rmtoll SVMCR PVDLS LL_PWR_SetPVDLevel
734 * @param PVDLevel This parameter can be one of the following values:
735 * @arg @ref LL_PWR_PVDLEVEL_0
736 * @arg @ref LL_PWR_PVDLEVEL_1
737 * @arg @ref LL_PWR_PVDLEVEL_2
738 * @arg @ref LL_PWR_PVDLEVEL_3
739 * @arg @ref LL_PWR_PVDLEVEL_4
740 * @arg @ref LL_PWR_PVDLEVEL_5
741 * @arg @ref LL_PWR_PVDLEVEL_6
742 * @arg @ref LL_PWR_PVDLEVEL_7
743 * @retval None
744 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)745 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
746 {
747 MODIFY_REG(PWR->SVMCR, PWR_SVMCR_PVDLS, PVDLevel);
748 }
749
750 /**
751 * @brief Get the Power voltage detector level.
752 * @rmtoll SVMCR PVDLS LL_PWR_GetPVDLevel
753 * @retval Returned value can be one of the following values:
754 * @arg @ref LL_PWR_PVDLEVEL_0
755 * @arg @ref LL_PWR_PVDLEVEL_1
756 * @arg @ref LL_PWR_PVDLEVEL_2
757 * @arg @ref LL_PWR_PVDLEVEL_3
758 * @arg @ref LL_PWR_PVDLEVEL_4
759 * @arg @ref LL_PWR_PVDLEVEL_5
760 * @arg @ref LL_PWR_PVDLEVEL_6
761 * @arg @ref LL_PWR_PVDLEVEL_7
762 */
LL_PWR_GetPVDLevel(void)763 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
764 {
765 return (READ_BIT(PWR->SVMCR, PWR_SVMCR_PVDLS));
766 }
767
768 /**
769 * @brief Enable the power voltage detector.
770 * @rmtoll SVMCR PVDE LL_PWR_EnablePVD
771 * @retval None
772 */
LL_PWR_EnablePVD(void)773 __STATIC_INLINE void LL_PWR_EnablePVD(void)
774 {
775 SET_BIT(PWR->SVMCR, PWR_SVMCR_PVDE);
776 }
777
778 /**
779 * @brief Disable the power voltage detector.
780 * @rmtoll SVMCR PVDE LL_PWR_DisablePVD
781 * @retval None
782 */
LL_PWR_DisablePVD(void)783 __STATIC_INLINE void LL_PWR_DisablePVD(void)
784 {
785 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_PVDE);
786 }
787
788 /**
789 * @brief Check if the power voltage detector is enabled.
790 * @rmtoll SVMCR PVDE LL_PWR_IsEnabledPVD
791 * @retval State of bit (1 or 0).
792 */
LL_PWR_IsEnabledPVD(void)793 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
794 {
795 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_PVDE) == (PWR_SVMCR_PVDE)) ? 1UL : 0UL);
796 }
797
798 /**
799 * @brief Enable the wake up pin_x.
800 * @rmtoll WUCR1 WUPENx LL_PWR_EnableWakeUpPin
801 * @param WakeUpPin This parameter can be a combination of the following values:
802 * @arg @ref LL_PWR_WAKEUP_PIN1
803 * @arg @ref LL_PWR_WAKEUP_PIN2
804 * @arg @ref LL_PWR_WAKEUP_PIN3
805 * @arg @ref LL_PWR_WAKEUP_PIN4
806 * @arg @ref LL_PWR_WAKEUP_PIN5
807 * @arg @ref LL_PWR_WAKEUP_PIN6
808 * @arg @ref LL_PWR_WAKEUP_PIN7
809 * @arg @ref LL_PWR_WAKEUP_PIN8
810 * @retval None
811 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)812 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
813 {
814 SET_BIT(PWR->WUCR1, WakeUpPin);
815 }
816
817 /**
818 * @brief Disable the wake up pin_x.
819 * @rmtoll WUCR1 WUPENx LL_PWR_DisableWakeUpPin
820 * @param WakeUpPin This parameter can be a combination of the following values:
821 * @arg @ref LL_PWR_WAKEUP_PIN1
822 * @arg @ref LL_PWR_WAKEUP_PIN2
823 * @arg @ref LL_PWR_WAKEUP_PIN3
824 * @arg @ref LL_PWR_WAKEUP_PIN4
825 * @arg @ref LL_PWR_WAKEUP_PIN5
826 * @arg @ref LL_PWR_WAKEUP_PIN6
827 * @arg @ref LL_PWR_WAKEUP_PIN7
828 * @arg @ref LL_PWR_WAKEUP_PIN8
829 * @retval None
830 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)831 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
832 {
833 CLEAR_BIT(PWR->WUCR1, WakeUpPin);
834 }
835
836 /**
837 * @brief Check if the wake up pin_x is enabled.
838 * @rmtoll WUCR1 WUPENx LL_PWR_IsEnabledWakeUpPin
839 * @param WakeUpPin This parameter can be one of the following values:
840 * @arg @ref LL_PWR_WAKEUP_PIN1
841 * @arg @ref LL_PWR_WAKEUP_PIN2
842 * @arg @ref LL_PWR_WAKEUP_PIN3
843 * @arg @ref LL_PWR_WAKEUP_PIN4
844 * @arg @ref LL_PWR_WAKEUP_PIN5
845 * @arg @ref LL_PWR_WAKEUP_PIN6
846 * @arg @ref LL_PWR_WAKEUP_PIN7
847 * @arg @ref LL_PWR_WAKEUP_PIN8
848 * @retval State of bit (1 or 0).
849 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)850 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
851 {
852 return ((READ_BIT(PWR->WUCR1, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
853 }
854
855 /**
856 * @brief Set the wake up pin polarity low for the event detection.
857 * @rmtoll WUCR2 WUPPx LL_PWR_SetWakeUpPinPolarityLow
858 * @param WakeUpPin This parameter can be a combination of the following values:
859 * @arg @ref LL_PWR_WAKEUP_PIN1
860 * @arg @ref LL_PWR_WAKEUP_PIN2
861 * @arg @ref LL_PWR_WAKEUP_PIN3
862 * @arg @ref LL_PWR_WAKEUP_PIN4
863 * @arg @ref LL_PWR_WAKEUP_PIN5
864 * @arg @ref LL_PWR_WAKEUP_PIN6
865 * @arg @ref LL_PWR_WAKEUP_PIN7
866 * @arg @ref LL_PWR_WAKEUP_PIN8
867 * @retval None
868 */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)869 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
870 {
871 SET_BIT(PWR->WUCR2, WakeUpPin);
872 }
873
874 /**
875 * @brief Set the wake up pin polarity high for the event detection.
876 * @rmtoll WUCR2 WUPPx LL_PWR_SetWakeUpPinPolarityHigh
877 * @param WakeUpPin This parameter can be a combination of the following values:
878 * @arg @ref LL_PWR_WAKEUP_PIN1
879 * @arg @ref LL_PWR_WAKEUP_PIN2
880 * @arg @ref LL_PWR_WAKEUP_PIN3
881 * @arg @ref LL_PWR_WAKEUP_PIN4
882 * @arg @ref LL_PWR_WAKEUP_PIN5
883 * @arg @ref LL_PWR_WAKEUP_PIN6
884 * @arg @ref LL_PWR_WAKEUP_PIN7
885 * @arg @ref LL_PWR_WAKEUP_PIN8
886 * @retval None
887 */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)888 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
889 {
890 CLEAR_BIT(PWR->WUCR2, WakeUpPin);
891 }
892
893 /**
894 * @brief Get the wake up pin polarity for the event detection.
895 * @rmtoll WUCR2 WUPPx LL_PWR_GetWakeUpPinPolarity
896 * @param WakeUpPin This parameter can be one of the following values:
897 * @arg @ref LL_PWR_WAKEUP_PIN1
898 * @arg @ref LL_PWR_WAKEUP_PIN2
899 * @arg @ref LL_PWR_WAKEUP_PIN3
900 * @arg @ref LL_PWR_WAKEUP_PIN4
901 * @arg @ref LL_PWR_WAKEUP_PIN5
902 * @arg @ref LL_PWR_WAKEUP_PIN6
903 * @arg @ref LL_PWR_WAKEUP_PIN7
904 * @arg @ref LL_PWR_WAKEUP_PIN8
905 * @retval State of bit (1 : polarity or 0 : polarity high).
906 */
LL_PWR_GetWakeUpPinPolarity(uint32_t WakeUpPin)907 __STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPolarity(uint32_t WakeUpPin)
908 {
909 return ((READ_BIT(PWR->WUCR2, WakeUpPin) == WakeUpPin) ? 1UL : 0UL);
910 }
911
912 /**
913 * @brief Set the wakeup pin_x selection 0.
914 * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal0Selection
915 * @param WakeUpPin This parameter can be one of the following values:
916 * @arg @ref LL_PWR_WAKEUP_PIN1
917 * @arg @ref LL_PWR_WAKEUP_PIN2
918 * @arg @ref LL_PWR_WAKEUP_PIN3
919 * @arg @ref LL_PWR_WAKEUP_PIN4
920 * @arg @ref LL_PWR_WAKEUP_PIN5
921 * @arg @ref LL_PWR_WAKEUP_PIN6
922 * @arg @ref LL_PWR_WAKEUP_PIN7
923 * @arg @ref LL_PWR_WAKEUP_PIN8
924 * @retval None
925 */
LL_PWR_SetWakeUpPinSignal0Selection(uint32_t WakeUpPin)926 __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal0Selection(uint32_t WakeUpPin)
927 {
928 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
929 (LL_PWR_WAKEUP_PIN_SELECTION_0 << (POSITION_VAL(WakeUpPin) * 2U)));
930 }
931
932 /**
933 * @brief Set the wakeup pin_x selection 1.
934 * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal1Selection
935 * @param WakeUpPin This parameter can be one of the following values:
936 * @arg @ref LL_PWR_WAKEUP_PIN1
937 * @arg @ref LL_PWR_WAKEUP_PIN2
938 * @arg @ref LL_PWR_WAKEUP_PIN3
939 * @arg @ref LL_PWR_WAKEUP_PIN4
940 * @arg @ref LL_PWR_WAKEUP_PIN5
941 * @arg @ref LL_PWR_WAKEUP_PIN6
942 * @arg @ref LL_PWR_WAKEUP_PIN7
943 * @arg @ref LL_PWR_WAKEUP_PIN8
944 * @retval None
945 */
LL_PWR_SetWakeUpPinSignal1Selection(uint32_t WakeUpPin)946 __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal1Selection(uint32_t WakeUpPin)
947 {
948 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
949 (LL_PWR_WAKEUP_PIN_SELECTION_1 << (POSITION_VAL(WakeUpPin) * 2U)));
950 }
951
952 /**
953 * @brief Set the wakeup pin_x selection 2.
954 * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal2Selection
955 * @param WakeUpPin This parameter can be one of the following values:
956 * @arg @ref LL_PWR_WAKEUP_PIN1
957 * @arg @ref LL_PWR_WAKEUP_PIN2
958 * @arg @ref LL_PWR_WAKEUP_PIN3
959 * @arg @ref LL_PWR_WAKEUP_PIN4
960 * @arg @ref LL_PWR_WAKEUP_PIN5
961 * @arg @ref LL_PWR_WAKEUP_PIN6
962 * @arg @ref LL_PWR_WAKEUP_PIN7
963 * @arg @ref LL_PWR_WAKEUP_PIN8
964 * @retval None
965 */
LL_PWR_SetWakeUpPinSignal2Selection(uint32_t WakeUpPin)966 __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal2Selection(uint32_t WakeUpPin)
967 {
968 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
969 (LL_PWR_WAKEUP_PIN_SELECTION_2 << (POSITION_VAL(WakeUpPin) * 2U)));
970 }
971
972 /**
973 * @brief Set the wakeup pin_x selection 3.
974 * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal3Selection
975 * @param WakeUpPin This parameter can be one of the following values:
976 * @arg @ref LL_PWR_WAKEUP_PIN1
977 * @arg @ref LL_PWR_WAKEUP_PIN2
978 * @arg @ref LL_PWR_WAKEUP_PIN3
979 * @arg @ref LL_PWR_WAKEUP_PIN4
980 * @arg @ref LL_PWR_WAKEUP_PIN5
981 * @arg @ref LL_PWR_WAKEUP_PIN6
982 * @arg @ref LL_PWR_WAKEUP_PIN7
983 * @arg @ref LL_PWR_WAKEUP_PIN8
984 * @retval None
985 */
LL_PWR_SetWakeUpPinSignal3Selection(uint32_t WakeUpPin)986 __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal3Selection(uint32_t WakeUpPin)
987 {
988 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
989 (LL_PWR_WAKEUP_PIN_SELECTION_3 << (POSITION_VAL(WakeUpPin) * 2U)));
990 }
991
992 /**
993 * @brief Get the wakeup pin_x selection.
994 * @rmtoll WUCR3 WUSELx LL_PWR_GetWakeUpPinSignalSelection
995 * @param WakeUpPin This parameter can be one of the following values:
996 * @arg @ref LL_PWR_WAKEUP_PIN1
997 * @arg @ref LL_PWR_WAKEUP_PIN2
998 * @arg @ref LL_PWR_WAKEUP_PIN3
999 * @arg @ref LL_PWR_WAKEUP_PIN4
1000 * @arg @ref LL_PWR_WAKEUP_PIN5
1001 * @arg @ref LL_PWR_WAKEUP_PIN6
1002 * @arg @ref LL_PWR_WAKEUP_PIN7
1003 * @arg @ref LL_PWR_WAKEUP_PIN8
1004 */
LL_PWR_GetWakeUpPinSignalSelection(uint32_t WakeUpPin)1005 __STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinSignalSelection(uint32_t WakeUpPin)
1006 {
1007 return (READ_BIT(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U))));
1008 }
1009
1010 /**
1011 * @brief Enable access to the backup domain.
1012 * @rmtoll DBPR DBP LL_PWR_EnableBkUpAccess
1013 * @retval None
1014 */
LL_PWR_EnableBkUpAccess(void)1015 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
1016 {
1017 SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
1018 }
1019
1020 /**
1021 * @brief Disable access to the backup domain.
1022 * @rmtoll DBPR DBP LL_PWR_DisableBkUpAccess
1023 * @retval None
1024 */
LL_PWR_DisableBkUpAccess(void)1025 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
1026 {
1027 CLEAR_BIT(PWR->DBPR, PWR_DBPR_DBP);
1028 }
1029
1030 /**
1031 * @brief Check if the access to backup domain is enabled.
1032 * @rmtoll DBPR DBP LL_PWR_IsEnabledBkUpAccess
1033 * @retval State of bit (1 or 0).
1034 */
LL_PWR_IsEnabledBkUpAccess(void)1035 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
1036 {
1037 return ((READ_BIT(PWR->DBPR, PWR_DBPR_DBP) == (PWR_DBPR_DBP)) ? 1UL : 0UL);
1038 }
1039
1040 /**
1041 * @brief Enable GPIO retention in Standby mode
1042 * @rmtoll IORETENRx ENx LL_PWR_EnableGPIOStandbyRetention
1043 * @param GPIOPort This parameter can be one of the following values:
1044 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTA
1045 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTB
1046 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTC
1047 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTH
1048 * @param GPIOPin This parameter can be a combination of the following values:
1049 * @arg @ref LL_PWR_GPIO_PIN_0
1050 * @arg @ref LL_PWR_GPIO_PIN_1
1051 * @arg @ref LL_PWR_GPIO_PIN_2
1052 * @arg @ref LL_PWR_GPIO_PIN_3
1053 * @arg @ref LL_PWR_GPIO_PIN_4
1054 * @arg @ref LL_PWR_GPIO_PIN_5
1055 * @arg @ref LL_PWR_GPIO_PIN_6
1056 * @arg @ref LL_PWR_GPIO_PIN_7
1057 * @arg @ref LL_PWR_GPIO_PIN_8
1058 * @arg @ref LL_PWR_GPIO_PIN_9
1059 * @arg @ref LL_PWR_GPIO_PIN_10
1060 * @arg @ref LL_PWR_GPIO_PIN_11
1061 * @arg @ref LL_PWR_GPIO_PIN_12
1062 * @arg @ref LL_PWR_GPIO_PIN_13
1063 * @arg @ref LL_PWR_GPIO_PIN_14
1064 * @arg @ref LL_PWR_GPIO_PIN_15
1065 * @retval None.
1066 */
LL_PWR_EnableGPIOStandbyRetention(uint32_t GPIOPort,uint32_t GPIOPin)1067 __STATIC_INLINE void LL_PWR_EnableGPIOStandbyRetention(uint32_t GPIOPort, uint32_t GPIOPin)
1068 {
1069 SET_BIT(*((__IO uint32_t *)GPIOPort), GPIOPin);
1070 }
1071
1072 /**
1073 * @brief Disable GPIO retention in Standby mode
1074 * @rmtoll IORETENRx ENx LL_PWR_DisableGPIOStandbyRetention
1075 * @param GPIOPort This parameter can be one of the following values:
1076 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTA
1077 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTB
1078 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTC
1079 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTH
1080 * @param GPIOPin This parameter can be a combinat+ion of the following values:
1081 * @arg @ref LL_PWR_GPIO_PIN_0
1082 * @arg @ref LL_PWR_GPIO_PIN_1
1083 * @arg @ref LL_PWR_GPIO_PIN_2
1084 * @arg @ref LL_PWR_GPIO_PIN_3
1085 * @arg @ref LL_PWR_GPIO_PIN_4
1086 * @arg @ref LL_PWR_GPIO_PIN_5
1087 * @arg @ref LL_PWR_GPIO_PIN_6
1088 * @arg @ref LL_PWR_GPIO_PIN_7
1089 * @arg @ref LL_PWR_GPIO_PIN_8
1090 * @arg @ref LL_PWR_GPIO_PIN_9
1091 * @arg @ref LL_PWR_GPIO_PIN_10
1092 * @arg @ref LL_PWR_GPIO_PIN_11
1093 * @arg @ref LL_PWR_GPIO_PIN_12
1094 * @arg @ref LL_PWR_GPIO_PIN_13
1095 * @arg @ref LL_PWR_GPIO_PIN_14
1096 * @arg @ref LL_PWR_GPIO_PIN_15
1097 * @retval None.
1098 */
LL_PWR_DisableGPIOStandbyRetention(uint32_t GPIOPort,uint32_t GPIOPin)1099 __STATIC_INLINE void LL_PWR_DisableGPIOStandbyRetention(uint32_t GPIOPort, uint32_t GPIOPin)
1100 {
1101 CLEAR_BIT(*((__IO uint32_t *)GPIOPort), GPIOPin);
1102 }
1103
1104 /**
1105 * @brief Check if GPIO retention is enabled in Standby mode
1106 * @rmtoll IORETENRx ENx LL_PWR_IsEnabledGPIOStandbyRetention
1107 * @param GPIOPort This parameter can be one of the following values:
1108 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTA
1109 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTB
1110 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTC
1111 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTH
1112 * @param GPIOPin This parameter can be one of the following values:
1113 * @arg @ref LL_PWR_GPIO_PIN_0
1114 * @arg @ref LL_PWR_GPIO_PIN_1
1115 * @arg @ref LL_PWR_GPIO_PIN_2
1116 * @arg @ref LL_PWR_GPIO_PIN_3
1117 * @arg @ref LL_PWR_GPIO_PIN_4
1118 * @arg @ref LL_PWR_GPIO_PIN_5
1119 * @arg @ref LL_PWR_GPIO_PIN_6
1120 * @arg @ref LL_PWR_GPIO_PIN_7
1121 * @arg @ref LL_PWR_GPIO_PIN_8
1122 * @arg @ref LL_PWR_GPIO_PIN_9
1123 * @arg @ref LL_PWR_GPIO_PIN_10
1124 * @arg @ref LL_PWR_GPIO_PIN_11
1125 * @arg @ref LL_PWR_GPIO_PIN_12
1126 * @arg @ref LL_PWR_GPIO_PIN_13
1127 * @arg @ref LL_PWR_GPIO_PIN_14
1128 * @arg @ref LL_PWR_GPIO_PIN_15
1129 * @retval State of bit (1 or 0).
1130 */
LL_PWR_IsEnabledGPIOStandbyRetention(uint32_t GPIOPort,uint32_t GPIOPin)1131 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOStandbyRetention(uint32_t GPIOPort, uint32_t GPIOPin)
1132 {
1133 return ((READ_BIT(*((__IO uint32_t *)(GPIOPort)), GPIOPin) == (GPIOPin)) ? 1UL : 0UL);
1134 }
1135
1136 /**
1137 * @brief Check if GPIO state was retained after Standby mode entry
1138 * @rmtoll IORETRx RETx LL_PWR_IsGPIOStandbyStateRetained
1139 * @param GPIOPort This parameter can be one of the following values:
1140 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTA
1141 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTB
1142 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTC
1143 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTH
1144 * @param GPIOPin This parameter can be one of the following values:
1145 * @arg @ref LL_PWR_GPIO_PIN_0
1146 * @arg @ref LL_PWR_GPIO_PIN_1
1147 * @arg @ref LL_PWR_GPIO_PIN_2
1148 * @arg @ref LL_PWR_GPIO_PIN_3
1149 * @arg @ref LL_PWR_GPIO_PIN_4
1150 * @arg @ref LL_PWR_GPIO_PIN_5
1151 * @arg @ref LL_PWR_GPIO_PIN_6
1152 * @arg @ref LL_PWR_GPIO_PIN_7
1153 * @arg @ref LL_PWR_GPIO_PIN_8
1154 * @arg @ref LL_PWR_GPIO_PIN_9
1155 * @arg @ref LL_PWR_GPIO_PIN_10
1156 * @arg @ref LL_PWR_GPIO_PIN_11
1157 * @arg @ref LL_PWR_GPIO_PIN_12
1158 * @arg @ref LL_PWR_GPIO_PIN_13
1159 * @arg @ref LL_PWR_GPIO_PIN_14
1160 * @arg @ref LL_PWR_GPIO_PIN_15
1161 * @retval State of bit (1 or 0).
1162 */
LL_PWR_IsGPIOStandbyStateRetained(uint32_t GPIOPort,uint32_t GPIOPin)1163 __STATIC_INLINE uint32_t LL_PWR_IsGPIOStandbyStateRetained(uint32_t GPIOPort, uint32_t GPIOPin)
1164 {
1165 return ((READ_BIT(*((__IO uint32_t *)(GPIOPort)), GPIOPin) == (GPIOPin)) ? 1UL : 0UL);
1166 }
1167
1168 /**
1169 * @brief Clear GPIO state retention status after Standby mode entry
1170 * @rmtoll IORETRx RETx LL_PWR_ClearGPIOStandbyRetentionStatus
1171 * @param GPIOPort This parameter can be one of the following values:
1172 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTA
1173 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTB
1174 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTC
1175 * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTH
1176 * @param GPIOPin This parameter can be one of the following values:
1177 * @arg @ref LL_PWR_GPIO_PIN_0
1178 * @arg @ref LL_PWR_GPIO_PIN_1
1179 * @arg @ref LL_PWR_GPIO_PIN_2
1180 * @arg @ref LL_PWR_GPIO_PIN_3
1181 * @arg @ref LL_PWR_GPIO_PIN_4
1182 * @arg @ref LL_PWR_GPIO_PIN_5
1183 * @arg @ref LL_PWR_GPIO_PIN_6
1184 * @arg @ref LL_PWR_GPIO_PIN_7
1185 * @arg @ref LL_PWR_GPIO_PIN_8
1186 * @arg @ref LL_PWR_GPIO_PIN_9
1187 * @arg @ref LL_PWR_GPIO_PIN_10
1188 * @arg @ref LL_PWR_GPIO_PIN_11
1189 * @arg @ref LL_PWR_GPIO_PIN_12
1190 * @arg @ref LL_PWR_GPIO_PIN_13
1191 * @arg @ref LL_PWR_GPIO_PIN_14
1192 * @arg @ref LL_PWR_GPIO_PIN_15
1193 * @retval None.
1194 */
LL_PWR_ClearGPIOStandbyRetentionStatus(uint32_t GPIOPort,uint32_t GPIOPin)1195 __STATIC_INLINE void LL_PWR_ClearGPIOStandbyRetentionStatus(uint32_t GPIOPort, uint32_t GPIOPin)
1196 {
1197 CLEAR_BIT(*((__IO uint32_t *)GPIOPort), GPIOPin);
1198 }
1199
1200 /**
1201 * @brief Get currently voltage scaling applied to VCORE.
1202 * @rmtoll SVMSR ACTVOS LL_PWR_GetRegulCurrentVOS
1203 * @retval Returned value can be one of the following values:
1204 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
1205 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
1206 */
LL_PWR_GetRegulCurrentVOS(void)1207 __STATIC_INLINE uint32_t LL_PWR_GetRegulCurrentVOS(void)
1208 {
1209 return (READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOS));
1210 }
1211 /**
1212 * @}
1213 */
1214
1215
1216 /** @defgroup PWR_LL_EF_RADIO_MANAGEMENT PWR RADIO Management
1217 * @{
1218 */
1219
1220 #if defined(PWR_RADIOSCR_REGPABYPEN)
1221 /**
1222 * @brief Enable regulator REG_VDDHPA bypass.
1223 * @rmtoll RADIOSCR REGPABYPEN LL_PWR_EnableREGVDDHPABypass
1224 * @note This bit shall only be written when the VDDHPA regulator is not used (When REGPASEL = 0)
1225 * @retval None
1226 */
LL_PWR_EnableREGVDDHPABypass(void)1227 __STATIC_INLINE void LL_PWR_EnableREGVDDHPABypass(void)
1228 {
1229 SET_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPABYPEN);
1230 }
1231
1232 /**
1233 * @brief Disable regulator REG_VDDHPA bypass.
1234 * @rmtoll RADIOSCR REGPABYPEN LL_PWR_DisableREGVDDHPABypass
1235 * @retval None
1236 */
LL_PWR_DisableREGVDDHPABypass(void)1237 __STATIC_INLINE void LL_PWR_DisableREGVDDHPABypass(void)
1238 {
1239 CLEAR_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPABYPEN);
1240 }
1241
1242 /**
1243 * @brief Check if regulator REG_VDDHPA bypass is enabled.
1244 * @rmtoll RADIOSCR REGPABYPEN LL_PWR_IsEnabledREGVDDHPABypass
1245 * @retval State of bit (1 or 0).
1246 */
LL_PWR_IsEnabledREGVDDHPABypass(void)1247 __STATIC_INLINE uint32_t LL_PWR_IsEnabledREGVDDHPABypass(void)
1248 {
1249 return ((READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPABYPEN) == (PWR_RADIOSCR_REGPABYPEN)) ? 1UL : 0UL);
1250 }
1251 #endif /* PWR_RADIOSCR_REGPABYPEN */
1252
1253 #if defined(PWR_RADIOSCR_REGPASEL)
1254 /**
1255 * @brief Set regulator REG_VDDHPA input supply.
1256 * @rmtoll RADIOSCR REGPASEL LL_PWR_SetREGVDDHPAInputSupply
1257 * @note This bit shall only be written when the VDDHPA regulator is not used (When REGPASEL = 0)
1258 * @arg @ref LL_PWR_REG_VDDHPA_VDDRFPA_PIN
1259 * @arg @ref LL_PWR_REG_VDDHPA_VDDRFPA_VDD11
1260 * @retval None
1261 */
LL_PWR_SetREGVDDHPAInputSupply(uint32_t InputSupply)1262 __STATIC_INLINE void LL_PWR_SetREGVDDHPAInputSupply(uint32_t InputSupply)
1263 {
1264 MODIFY_REG(PWR->RADIOSCR, PWR_RADIOSCR_REGPASEL, InputSupply);
1265 }
1266
1267 /**
1268 * @brief Get regulator REG_VDDHPA input supply.
1269 * @rmtoll RADIOSCR REGPASEL LL_PWR_GetREGVDDHPAInputSupply
1270 * @retval Returned value can be one of the following values:
1271 * @arg @ref LL_PWR_REG_VDDHPA_VDDRFPA_PIN
1272 * @arg @ref LL_PWR_REG_VDDHPA_VDDRFPA_VDD11
1273 */
LL_PWR_GetREGVDDHPAInputSupply(void)1274 __STATIC_INLINE uint32_t LL_PWR_GetREGVDDHPAInputSupply(void)
1275 {
1276 return (READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPASEL));
1277 }
1278 #endif /* PWR_RADIOSCR_REGPASEL */
1279
1280 /**
1281 * @brief Indicate whether the VDDHPA voltage output is ready when selecting VDDRFPA input.
1282 * @rmtoll RADIOSCR REGPARDYVDDRFPA LL_PWR_IsActiveFlag_REGPARDYVDDRFPA
1283 * @retval State of bit (1 or 0).
1284 */
LL_PWR_IsActiveFlag_REGPARDYVDDRFPA(void)1285 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGPARDYVDDRFPA(void)
1286 {
1287 return ((READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPARDYVDDRFPA) == (PWR_RADIOSCR_REGPARDYVDDRFPA)) ? 1UL : 0UL);
1288 }
1289
1290 #if defined(PWR_RADIOSCR_REGPARDYV11)
1291 /**
1292 * @brief Indicate whether the VDDHPA voltage output is ready when selecting VDD11 input.
1293 * @rmtoll RADIOSCR REGPARDYV11 LL_PWR_IsActiveFlag_REGPARDYV11
1294 * @retval State of bit (1 or 0).
1295 */
LL_PWR_IsActiveFlag_REGPARDYV11(void)1296 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGPARDYV11(void)
1297 {
1298 return ((READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPARDYV11) == (PWR_RADIOSCR_REGPARDYV11)) ? 1UL : 0UL);
1299 }
1300 #endif /* PWR_RADIOSCR_REGPARDYV11 */
1301
1302 /**
1303 * @brief Get 2.4 GHz RADIO VDDHPA control word.
1304 * @rmtoll RADIOSCR RFVDDHPA LL_PWR_GetRadioVDDHPAControlWord
1305 * @retval 4-bit control word.
1306 */
LL_PWR_GetRadioVDDHPAControlWord(void)1307 __STATIC_INLINE uint32_t LL_PWR_GetRadioVDDHPAControlWord(void)
1308 {
1309 return (READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_RFVDDHPA));
1310 }
1311
1312 /**
1313 * @brief Indicate whether the 2.4 GHz RADIO encryption function is enabled
1314 * @rmtoll RADIOSCR ENCMODE LL_PWR_IsEnabledRadioEncryption
1315 * @retval State of bit (1 or 0).
1316 */
LL_PWR_IsEnabledRadioEncryption(void)1317 __STATIC_INLINE uint32_t LL_PWR_IsEnabledRadioEncryption(void)
1318 {
1319 return ((READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_ENCMODE) == (PWR_RADIOSCR_ENCMODE)) ? 1UL : 0UL);
1320 }
1321
1322 /**
1323 * @brief Get 2.4 GHz RADIO PHY operating mode.
1324 * @rmtoll RADIOSCR PHYMODE LL_PWR_GetRadioPhyMode
1325 * @retval Returned value can be one of the following values:
1326 * @arg @ref LL_PWR_RADIO_PHY_SLEEP_MODE
1327 * @arg @ref LL_PWR_RADIO_PHY_STANDBY_MODE
1328 */
LL_PWR_GetRadioPhyMode(void)1329 __STATIC_INLINE uint32_t LL_PWR_GetRadioPhyMode(void)
1330 {
1331 return (READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_PHYMODE));
1332 }
1333
1334 /**
1335 * @brief Get 2.4 GHz RADIO operating mode.
1336 * @rmtoll RADIOSCR MODE LL_PWR_GetRadioMode
1337 * @retval Returned value can be one of the following values:
1338 * @arg @ref LL_PWR_RADIO_DEEP_SLEEP_MODE
1339 * @arg @ref LL_PWR_RADIO_SLEEP_MODE
1340 * @arg @ref LL_PWR_RADIO_ACTIVE_MODE
1341 */
LL_PWR_GetRadioMode(void)1342 __STATIC_INLINE uint32_t LL_PWR_GetRadioMode(void)
1343 {
1344 if (READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_MODE_1) != 0UL)
1345 {
1346 return LL_PWR_RADIO_ACTIVE_MODE;
1347 }
1348 else
1349 {
1350 return (READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_MODE_0));
1351 }
1352 }
1353 /**
1354 * @}
1355 */
1356
1357
1358 /** @defgroup PWR_LL_EF_FLAG_MANAGEMENT PWR FLAG Management
1359 * @{
1360 */
1361
1362 /**
1363 * @brief Indicate whether the regulator voltage output is above voltage
1364 * scaling range or not.
1365 * @rmtoll VOSR VOSRDY LL_PWR_IsActiveFlag_VOS
1366 * @retval State of bit (1 or 0).
1367 */
LL_PWR_IsActiveFlag_VOS(void)1368 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
1369 {
1370 return ((READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == (PWR_VOSR_VOSRDY)) ? 1UL : 0UL);
1371 }
1372
1373
1374 /**
1375 * @brief Indicate whether the system was in standby mode or not.
1376 * @rmtoll SR SBF LL_PWR_IsActiveFlag_SB
1377 * @retval State of bit (1 or 0).
1378 */
LL_PWR_IsActiveFlag_SB(void)1379 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
1380 {
1381 return ((READ_BIT(PWR->SR, PWR_SR_SBF) == (PWR_SR_SBF)) ? 1UL : 0UL);
1382 }
1383
1384 /**
1385 * @brief Indicate whether the system was in stop mode or not.
1386 * @rmtoll SR STOPF LL_PWR_IsActiveFlag_STOP
1387 * @retval State of bit (1 or 0).
1388 */
LL_PWR_IsActiveFlag_STOP(void)1389 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_STOP(void)
1390 {
1391 return ((READ_BIT(PWR->SR, PWR_SR_STOPF) == (PWR_SR_STOPF)) ? 1UL : 0UL);
1392 }
1393
1394
1395 #if defined(PWR_SVMSR_REGS)
1396 /**
1397 * @brief Indicate whether the regulator supply is LDO or SMPS.
1398 * @rmtoll SVMSR REGS LL_PWR_IsActiveFlag_REGULATOR
1399 * @retval State of bit (1 or 0).
1400 */
LL_PWR_IsActiveFlag_REGULATOR(void)1401 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGULATOR(void)
1402 {
1403 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_REGS) == (PWR_SVMSR_REGS)) ? 1UL : 0UL);
1404 }
1405 #endif /* PWR_SVMSR_REGS */
1406
1407 /**
1408 * @brief Indicate whether the VDD voltage is below the threshold or not.
1409 * @rmtoll SVMSR PVDO LL_PWR_IsActiveFlag_PVDO
1410 * @retval State of bit (1 or 0).
1411 */
LL_PWR_IsActiveFlag_PVDO(void)1412 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
1413 {
1414 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO) == (PWR_SVMSR_PVDO)) ? 1UL : 0UL);
1415 }
1416
1417 /**
1418 * @brief Indicate whether the regulator voltage output is equal to current
1419 * used voltage scaling range or not.
1420 * @rmtoll SVMSR ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS
1421 * @retval State of bit (1 or 0).
1422 */
LL_PWR_IsActiveFlag_ACTVOS(void)1423 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void)
1424 {
1425 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY) == (PWR_SVMSR_ACTVOSRDY)) ? 1UL : 0UL);
1426 }
1427
1428 /**
1429 * @brief Indicate whether a wakeup event is detected on wake up pin 1.
1430 * @rmtoll WUSR WUF1 LL_PWR_IsActiveFlag_WU1
1431 * @retval State of bit (1 or 0).
1432 */
LL_PWR_IsActiveFlag_WU1(void)1433 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
1434 {
1435 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == (PWR_WUSR_WUF1)) ? 1UL : 0UL);
1436 }
1437
1438 #if defined(PWR_WUSR_WUF2)
1439 /**
1440 * @brief Indicate whether a wakeup event is detected on wake up pin 2.
1441 * @rmtoll WUSR WUF2 LL_PWR_IsActiveFlag_WU2
1442 * @retval State of bit (1 or 0).
1443 */
LL_PWR_IsActiveFlag_WU2(void)1444 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
1445 {
1446 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == (PWR_WUSR_WUF2)) ? 1UL : 0UL);
1447 }
1448 #endif /* PWR_WUSR_WUF2 */
1449
1450 /**
1451 * @brief Indicate whether a wakeup event is detected on wake up pin 3.
1452 * @rmtoll WUSR WUF3 LL_PWR_IsActiveFlag_WU3
1453 * @retval State of bit (1 or 0).
1454 */
LL_PWR_IsActiveFlag_WU3(void)1455 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
1456 {
1457 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == (PWR_WUSR_WUF3)) ? 1UL : 0UL);
1458 }
1459
1460 /**
1461 * @brief Indicate whether a wakeup event is detected on wake up pin 4.
1462 * @rmtoll WUSR WUF4 LL_PWR_IsActiveFlag_WU4
1463 * @retval State of bit (1 or 0).
1464 */
LL_PWR_IsActiveFlag_WU4(void)1465 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
1466 {
1467 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == (PWR_WUSR_WUF4)) ? 1UL : 0UL);
1468 }
1469
1470 #if defined(PWR_WUSR_WUF5)
1471 /**
1472 * @brief Indicate whether a wakeup event is detected on wake up pin 5.
1473 * @rmtoll WUSR WUF5 LL_PWR_IsActiveFlag_WU5
1474 * @retval State of bit (1 or 0).
1475 */
LL_PWR_IsActiveFlag_WU5(void)1476 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
1477 {
1478 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == (PWR_WUSR_WUF5)) ? 1UL : 0UL);
1479 }
1480 #endif /* PWR_WUSR_WUF5 */
1481
1482 /**
1483 * @brief Indicate whether a wakeup event is detected on wake up pin 6.
1484 * @rmtoll WUSR WUF6 LL_PWR_IsActiveFlag_WU6
1485 * @retval State of bit (1 or 0).
1486 */
LL_PWR_IsActiveFlag_WU6(void)1487 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
1488 {
1489 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == (PWR_WUSR_WUF6)) ? 1UL : 0UL);
1490 }
1491
1492 /**
1493 * @brief Indicate whether a wakeup event is detected on wake up pin 7.
1494 * @rmtoll WUSR WUF7 LL_PWR_IsActiveFlag_WU7
1495 * @retval State of bit (1 or 0).
1496 */
LL_PWR_IsActiveFlag_WU7(void)1497 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU7(void)
1498 {
1499 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == (PWR_WUSR_WUF7)) ? 1UL : 0UL);
1500 }
1501
1502 /**
1503 * @brief Indicate whether a wakeup event is detected on wake up pin 8.
1504 * @rmtoll WUSR WUF8 LL_PWR_IsActiveFlag_WU8
1505 * @retval State of bit (1 or 0).
1506 */
LL_PWR_IsActiveFlag_WU8(void)1507 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU8(void)
1508 {
1509 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == (PWR_WUSR_WUF8)) ? 1UL : 0UL);
1510 }
1511
1512
1513 /**
1514 * @brief Clear stop flag.
1515 * @rmtoll SR CSSF LL_PWR_ClearFlag_STOP
1516 * @retval None
1517 */
LL_PWR_ClearFlag_STOP(void)1518 __STATIC_INLINE void LL_PWR_ClearFlag_STOP(void)
1519 {
1520 WRITE_REG(PWR->SR, PWR_SR_CSSF);
1521 }
1522
1523
1524 /**
1525 * @brief Clear standby flag.
1526 * @rmtoll SR CSSF LL_PWR_ClearFlag_SB
1527 * @retval None
1528 */
LL_PWR_ClearFlag_SB(void)1529 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
1530 {
1531 WRITE_REG(PWR->SR, PWR_SR_CSSF);
1532 }
1533
1534 /**
1535 * @brief Clear wake up flag 1.
1536 * @rmtoll WUSCR CWUF1 LL_PWR_ClearFlag_WU1
1537 * @retval None
1538 */
LL_PWR_ClearFlag_WU1(void)1539 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
1540 {
1541 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF1);
1542 }
1543
1544 #if defined(PWR_WUSCR_CWUF2)
1545 /**
1546 * @brief Clear wake up flag 2.
1547 * @rmtoll WUSCR CWUF2 LL_PWR_ClearFlag_WU2
1548 * @retval None
1549 */
LL_PWR_ClearFlag_WU2(void)1550 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
1551 {
1552 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF2);
1553 }
1554 #endif /* PWR_WUSCR_CWUF2 */
1555
1556 /**
1557 * @brief Clear wake up flag 3.
1558 * @rmtoll WUSCR CWUF3 LL_PWR_ClearFlag_WU3
1559 * @retval None
1560 */
LL_PWR_ClearFlag_WU3(void)1561 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
1562 {
1563 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF3);
1564 }
1565
1566 /**
1567 * @brief Clear wake up flag 4.
1568 * @rmtoll WUSCR CWUF4 LL_PWR_ClearFlag_WU4
1569 * @retval None
1570 */
LL_PWR_ClearFlag_WU4(void)1571 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
1572 {
1573 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF4);
1574 }
1575
1576 #if defined(PWR_WUSCR_CWUF5)
1577 /**
1578 * @brief Clear wake up flag 5.
1579 * @rmtoll WUSCR CWUF5 LL_PWR_ClearFlag_WU5
1580 * @retval None
1581 */
LL_PWR_ClearFlag_WU5(void)1582 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
1583 {
1584 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF5);
1585 }
1586 #endif /* PWR_WUSCR_CWUF5 */
1587
1588 /**
1589 * @brief Clear wake up flag 6.
1590 * @rmtoll WUSCR CWUF6 LL_PWR_ClearFlag_WU6
1591 * @retval None
1592 */
LL_PWR_ClearFlag_WU6(void)1593 __STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
1594 {
1595 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF6);
1596 }
1597
1598 /**
1599 * @brief Clear wake up flag 7.
1600 * @rmtoll WUSCR CWUF7 LL_PWR_ClearFlag_WU7
1601 * @retval None
1602 */
LL_PWR_ClearFlag_WU7(void)1603 __STATIC_INLINE void LL_PWR_ClearFlag_WU7(void)
1604 {
1605 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF7);
1606 }
1607
1608 /**
1609 * @brief Clear wake up flag 8.
1610 * @rmtoll WUSCR CWUF8 LL_PWR_ClearFlag_WU8
1611 * @retval None
1612 */
LL_PWR_ClearFlag_WU8(void)1613 __STATIC_INLINE void LL_PWR_ClearFlag_WU8(void)
1614 {
1615 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF8);
1616 }
1617
1618 /**
1619 * @brief Clear all wake up flags.
1620 * @rmtoll WUSCR CWUF LL_PWR_ClearFlag_WU
1621 * @retval None
1622 */
LL_PWR_ClearFlag_WU(void)1623 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
1624 {
1625 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF);
1626 }
1627
1628 /**
1629 * @}
1630 */
1631
1632 /** @defgroup PWR_LL_EF_ATTRIBUTE_MANAGEMENT PWR Attribute Management
1633 * @{
1634 */
1635
1636 #if defined(PWR_PRIVCFGR_NSPRIV)
1637 /**
1638 * @brief Enable privileged mode for nsecure items.
1639 * @rmtoll PRIVCFGR NSPRIV LL_PWR_EnableNSecurePrivilege
1640 * @retval None
1641 */
LL_PWR_EnableNSecurePrivilege(void)1642 __STATIC_INLINE void LL_PWR_EnableNSecurePrivilege(void)
1643 {
1644 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
1645 }
1646
1647 /**
1648 * @brief Disable privileged mode for nsecure items.
1649 * @rmtoll PRIVCFGR NSPRIV LL_PWR_DisableNSecurePrivilege
1650 * @retval None
1651 */
LL_PWR_DisableNSecurePrivilege(void)1652 __STATIC_INLINE void LL_PWR_DisableNSecurePrivilege(void)
1653 {
1654 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
1655 }
1656
1657 /**
1658 * @brief Check if privileged mode for nsecure items is enabled.
1659 * @rmtoll PRIVCFGR NSPRIV LL_PWR_IsEnabledNSecurePrivilege
1660 * @retval State of bit (1 or 0).
1661 */
LL_PWR_IsEnabledNSecurePrivilege(void)1662 __STATIC_INLINE uint32_t LL_PWR_IsEnabledNSecurePrivilege(void)
1663 {
1664 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV) == PWR_PRIVCFGR_NSPRIV) ? 1UL : 0UL);
1665 }
1666 #endif /* PWR_PRIVCFGR_NSPRIV */
1667
1668 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1669 /**
1670 * @brief Enable privileged mode for secure items.
1671 * @rmtoll PRIVCFGR SPRIV LL_PWR_EnableSecurePrivilege
1672 * @retval None
1673 */
LL_PWR_EnableSecurePrivilege(void)1674 __STATIC_INLINE void LL_PWR_EnableSecurePrivilege(void)
1675 {
1676 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
1677 }
1678
1679 /**
1680 * @brief Disable privileged mode for secure items.
1681 * @rmtoll PRIVCFGR SPRIV LL_PWR_DisableSecurePrivilege
1682 * @retval None
1683 */
LL_PWR_DisableSecurePrivilege(void)1684 __STATIC_INLINE void LL_PWR_DisableSecurePrivilege(void)
1685 {
1686 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
1687 }
1688 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1689
1690 #if defined(PWR_PRIVCFGR_NSPRIV)
1691 /**
1692 * @brief Check if privileged mode for secure items is enabled.
1693 * @rmtoll PRIVCFGR SPRIV LL_PWR_IsEnabledSecurePrivilege
1694 * @retval State of bit (1 or 0).
1695 */
LL_PWR_IsEnabledSecurePrivilege(void)1696 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSecurePrivilege(void)
1697 {
1698 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV) == PWR_PRIVCFGR_SPRIV) ? 1UL : 0UL);
1699 }
1700 #endif /* PWR_PRIVCFGR_NSPRIV */
1701
1702 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1703 /**
1704 * @brief Configure secure attribute mode.
1705 * @note This API can be executed only by CPU in secure mode.
1706 * @rmtoll SECCFGR WUP1SEC LL_PWR_ConfigSecure\n
1707 * SECCFGR WUP2SEC LL_PWR_ConfigSecure\n
1708 * SECCFGR WUP3SEC LL_PWR_ConfigSecure\n
1709 * SECCFGR WUP4SEC LL_PWR_ConfigSecure\n
1710 * SECCFGR WUP5SEC LL_PWR_ConfigSecure\n
1711 * SECCFGR WUP6SEC LL_PWR_ConfigSecure\n
1712 * SECCFGR WUP7SEC LL_PWR_ConfigSecure\n
1713 * SECCFGR WUP8SEC LL_PWR_ConfigSecure\n
1714 * SECCFGR LPMSEC LL_PWR_ConfigSecure\n
1715 * SECCFGR VDMSEC LL_PWR_ConfigSecure\n
1716 * SECCFGR VBSEC LL_PWR_ConfigSecure
1717 * @param SecureConfig This parameter can be the full combination
1718 * of the following values:
1719 * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC
1720 * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC
1721 * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC
1722 * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC
1723 * @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC
1724 * @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC
1725 * @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC
1726 * @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC
1727 * @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC
1728 * @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC
1729 * @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC
1730 * @retval None.
1731 */
LL_PWR_ConfigSecure(uint32_t SecureConfig)1732 __STATIC_INLINE void LL_PWR_ConfigSecure(uint32_t SecureConfig)
1733 {
1734 WRITE_REG(PWR->SECCFGR, SecureConfig);
1735 }
1736
1737 /**
1738 * @brief Get secure attribute configuration.
1739 * @note This API can be executed only by CPU in secure mode.
1740 * @rmtoll SECCFGR WUP1SEC LL_PWR_GetConfigSecure\n
1741 * SECCFGR WUP2SEC LL_PWR_GetConfigSecure\n
1742 * SECCFGR WUP3SEC LL_PWR_GetConfigSecure\n
1743 * SECCFGR WUP4SEC LL_PWR_GetConfigSecure\n
1744 * SECCFGR WUP5SEC LL_PWR_GetConfigSecure\n
1745 * SECCFGR WUP6SEC LL_PWR_GetConfigSecure\n
1746 * SECCFGR WUP7SEC LL_PWR_GetConfigSecure\n
1747 * SECCFGR WUP8SEC LL_PWR_GetConfigSecure\n
1748 * SECCFGR LPMSEC LL_PWR_GetConfigSecure\n
1749 * SECCFGR VDMSEC LL_PWR_GetConfigSecure\n
1750 * SECCFGR VBSEC LL_PWR_GetConfigSecure
1751 * @retval Returned value is the combination of the following values:
1752 * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC
1753 * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC
1754 * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC
1755 * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC
1756 * @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC
1757 * @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC
1758 * @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC
1759 * @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC
1760 * @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC
1761 * @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC
1762 * @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC
1763 */
LL_PWR_GetConfigSecure(void)1764 __STATIC_INLINE uint32_t LL_PWR_GetConfigSecure(void)
1765 {
1766 return (READ_REG(PWR->SECCFGR));
1767 }
1768 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1769 /**
1770 * @}
1771 */
1772
1773 #if defined (USE_FULL_LL_DRIVER)
1774 /** @defgroup PWR_LL_EF_Init De-initialization function
1775 * @{
1776 */
1777 ErrorStatus LL_PWR_DeInit(void);
1778 /**
1779 * @}
1780 */
1781 #endif /* defined (USE_FULL_LL_DRIVER) */
1782
1783
1784 /**
1785 * @}
1786 */
1787
1788 /**
1789 * @}
1790 */
1791
1792 #endif /* defined (PWR) */
1793
1794 /**
1795 * @}
1796 */
1797
1798 #ifdef __cplusplus
1799 }
1800 #endif /* __cplusplus */
1801
1802 #endif /* STM32WBAxx_LL_PWR_H */
1803
1804
