1 /**
2 ******************************************************************************
3 * @file stm32f1xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * Copyright (c) 2016 STMicroelectronics.
27 * All rights reserved.
28 *
29 * This software is licensed under terms that can be found in the LICENSE file in
30 * the root directory of this software component.
31 * If no LICENSE file comes with this software, it is provided AS-IS.
32 ******************************************************************************
33 */
34
35 /* Define to prevent recursive inclusion -------------------------------------*/
36 #ifndef __STM32F1xx_LL_BUS_H
37 #define __STM32F1xx_LL_BUS_H
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /* Includes ------------------------------------------------------------------*/
44 #include "stm32f1xx.h"
45
46 /** @addtogroup STM32F1xx_LL_Driver
47 * @{
48 */
49
50 #if defined(RCC)
51
52 /** @defgroup BUS_LL BUS
53 * @{
54 */
55
56 /* Private types -------------------------------------------------------------*/
57 /* Private variables ---------------------------------------------------------*/
58
59 /* Private constants ---------------------------------------------------------*/
60 #if defined(RCC_AHBRSTR_OTGFSRST) || defined(RCC_AHBRSTR_ETHMACRST)
61 #define RCC_AHBRSTR_SUPPORT
62 #endif /* RCC_AHBRSTR_OTGFSRST || RCC_AHBRSTR_ETHMACRST */
63
64 /* Private macros ------------------------------------------------------------*/
65
66 /* Exported types ------------------------------------------------------------*/
67 /* Exported constants --------------------------------------------------------*/
68 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
69 * @{
70 */
71
72 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
73 * @{
74 */
75 #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
76 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
77 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
78 #if defined(DMA2)
79 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
80 #endif /*DMA2*/
81 #if defined(ETH)
82 #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHBENR_ETHMACEN
83 #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHBENR_ETHMACRXEN
84 #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHBENR_ETHMACTXEN
85 #endif /*ETH*/
86 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
87 #if defined(FSMC_Bank1)
88 #define LL_AHB1_GRP1_PERIPH_FSMC RCC_AHBENR_FSMCEN
89 #endif /*FSMC_Bank1*/
90 #if defined(USB_OTG_FS)
91 #define LL_AHB1_GRP1_PERIPH_OTGFS RCC_AHBENR_OTGFSEN
92 #endif /*USB_OTG_FS*/
93 #if defined(SDIO)
94 #define LL_AHB1_GRP1_PERIPH_SDIO RCC_AHBENR_SDIOEN
95 #endif /*SDIO*/
96 #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
97 /**
98 * @}
99 */
100
101 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
102 * @{
103 */
104 #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
105 #define LL_APB1_GRP1_PERIPH_BKP RCC_APB1ENR_BKPEN
106 #if defined(CAN1)
107 #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
108 #endif /*CAN1*/
109 #if defined(CAN2)
110 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
111 #endif /*CAN2*/
112 #if defined(CEC)
113 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
114 #endif /*CEC*/
115 #if defined(DAC)
116 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
117 #endif /*DAC*/
118 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
119 #if defined(I2C2)
120 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
121 #endif /*I2C2*/
122 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
123 #if defined(SPI2)
124 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
125 #endif /*SPI2*/
126 #if defined(SPI3)
127 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
128 #endif /*SPI3*/
129 #if defined(TIM12)
130 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
131 #endif /*TIM12*/
132 #if defined(TIM13)
133 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
134 #endif /*TIM13*/
135 #if defined(TIM14)
136 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
137 #endif /*TIM14*/
138 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
139 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
140 #if defined(TIM4)
141 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
142 #endif /*TIM4*/
143 #if defined(TIM5)
144 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
145 #endif /*TIM5*/
146 #if defined(TIM6)
147 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
148 #endif /*TIM6*/
149 #if defined(TIM7)
150 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
151 #endif /*TIM7*/
152 #if defined(UART4)
153 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
154 #endif /*UART4*/
155 #if defined(UART5)
156 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
157 #endif /*UART5*/
158 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
159 #if defined(USART3)
160 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
161 #endif /*USART3*/
162 #if defined(USB)
163 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
164 #endif /*USB*/
165 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
166 /**
167 * @}
168 */
169
170 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
171 * @{
172 */
173 #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
174 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
175 #if defined(ADC2)
176 #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
177 #endif /*ADC2*/
178 #if defined(ADC3)
179 #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
180 #endif /*ADC3*/
181 #define LL_APB2_GRP1_PERIPH_AFIO RCC_APB2ENR_AFIOEN
182 #define LL_APB2_GRP1_PERIPH_GPIOA RCC_APB2ENR_IOPAEN
183 #define LL_APB2_GRP1_PERIPH_GPIOB RCC_APB2ENR_IOPBEN
184 #define LL_APB2_GRP1_PERIPH_GPIOC RCC_APB2ENR_IOPCEN
185 #define LL_APB2_GRP1_PERIPH_GPIOD RCC_APB2ENR_IOPDEN
186 #if defined(GPIOE)
187 #define LL_APB2_GRP1_PERIPH_GPIOE RCC_APB2ENR_IOPEEN
188 #endif /*GPIOE*/
189 #if defined(GPIOF)
190 #define LL_APB2_GRP1_PERIPH_GPIOF RCC_APB2ENR_IOPFEN
191 #endif /*GPIOF*/
192 #if defined(GPIOG)
193 #define LL_APB2_GRP1_PERIPH_GPIOG RCC_APB2ENR_IOPGEN
194 #endif /*GPIOG*/
195 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
196 #if defined(TIM10)
197 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
198 #endif /*TIM10*/
199 #if defined(TIM11)
200 #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
201 #endif /*TIM11*/
202 #if defined(TIM15)
203 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
204 #endif /*TIM15*/
205 #if defined(TIM16)
206 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
207 #endif /*TIM16*/
208 #if defined(TIM17)
209 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
210 #endif /*TIM17*/
211 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
212 #if defined(TIM8)
213 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
214 #endif /*TIM8*/
215 #if defined(TIM9)
216 #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
217 #endif /*TIM9*/
218 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
219 /**
220 * @}
221 */
222
223 /**
224 * @}
225 */
226
227 /* Exported macro ------------------------------------------------------------*/
228
229 /* Exported functions --------------------------------------------------------*/
230 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
231 * @{
232 */
233
234 /** @defgroup BUS_LL_EF_AHB1 AHB1
235 * @{
236 */
237
238 /**
239 * @brief Enable AHB1 peripherals clock.
240 * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
241 * AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
242 * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
243 * AHBENR ETHMACEN LL_AHB1_GRP1_EnableClock\n
244 * AHBENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n
245 * AHBENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n
246 * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
247 * AHBENR FSMCEN LL_AHB1_GRP1_EnableClock\n
248 * AHBENR OTGFSEN LL_AHB1_GRP1_EnableClock\n
249 * AHBENR SDIOEN LL_AHB1_GRP1_EnableClock\n
250 * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock
251 * @param Periphs This parameter can be a combination of the following values:
252 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
253 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
254 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
255 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
256 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
257 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
258 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
259 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
260 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
261 * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
262 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
263 *
264 * (*) value not defined in all devices.
265 * @retval None
266 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)267 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
268 {
269 __IO uint32_t tmpreg;
270 SET_BIT(RCC->AHBENR, Periphs);
271 /* Delay after an RCC peripheral clock enabling */
272 tmpreg = READ_BIT(RCC->AHBENR, Periphs);
273 (void)tmpreg;
274 }
275
276 /**
277 * @brief Check if AHB1 peripheral clock is enabled or not
278 * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
279 * AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
280 * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
281 * AHBENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n
282 * AHBENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n
283 * AHBENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n
284 * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
285 * AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock\n
286 * AHBENR OTGFSEN LL_AHB1_GRP1_IsEnabledClock\n
287 * AHBENR SDIOEN LL_AHB1_GRP1_IsEnabledClock\n
288 * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock
289 * @param Periphs This parameter can be a combination of the following values:
290 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
291 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
292 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
293 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
294 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
295 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
296 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
297 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
298 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
299 * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
300 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
301 *
302 * (*) value not defined in all devices.
303 * @retval State of Periphs (1 or 0).
304 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)305 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
306 {
307 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
308 }
309
310 /**
311 * @brief Disable AHB1 peripherals clock.
312 * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
313 * AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
314 * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
315 * AHBENR ETHMACEN LL_AHB1_GRP1_DisableClock\n
316 * AHBENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n
317 * AHBENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n
318 * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
319 * AHBENR FSMCEN LL_AHB1_GRP1_DisableClock\n
320 * AHBENR OTGFSEN LL_AHB1_GRP1_DisableClock\n
321 * AHBENR SDIOEN LL_AHB1_GRP1_DisableClock\n
322 * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock
323 * @param Periphs This parameter can be a combination of the following values:
324 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
325 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
326 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
327 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
328 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
329 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
330 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
331 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
332 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
333 * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
334 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
335 *
336 * (*) value not defined in all devices.
337 * @retval None
338 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)339 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
340 {
341 CLEAR_BIT(RCC->AHBENR, Periphs);
342 }
343
344 #if defined(RCC_AHBRSTR_SUPPORT)
345 /**
346 * @brief Force AHB1 peripherals reset.
347 * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n
348 * AHBRSTR OTGFSRST LL_AHB1_GRP1_ForceReset
349 * @param Periphs This parameter can be a combination of the following values:
350 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
351 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
352 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
353 *
354 * (*) value not defined in all devices.
355 * @retval None
356 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)357 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
358 {
359 SET_BIT(RCC->AHBRSTR, Periphs);
360 }
361
362 /**
363 * @brief Release AHB1 peripherals reset.
364 * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n
365 * AHBRSTR OTGFSRST LL_AHB1_GRP1_ReleaseReset
366 * @param Periphs This parameter can be a combination of the following values:
367 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
368 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
369 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
370 *
371 * (*) value not defined in all devices.
372 * @retval None
373 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)374 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
375 {
376 CLEAR_BIT(RCC->AHBRSTR, Periphs);
377 }
378 #endif /* RCC_AHBRSTR_SUPPORT */
379
380 /**
381 * @}
382 */
383
384 /** @defgroup BUS_LL_EF_APB1 APB1
385 * @{
386 */
387
388 /**
389 * @brief Enable APB1 peripherals clock.
390 * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_EnableClock\n
391 * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n
392 * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n
393 * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
394 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
395 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
396 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
397 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
398 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
399 * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
400 * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
401 * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
402 * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
403 * APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
404 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
405 * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
406 * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
407 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
408 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
409 * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
410 * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
411 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
412 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
413 * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
414 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock
415 * @param Periphs This parameter can be a combination of the following values:
416 * @arg @ref LL_APB1_GRP1_PERIPH_BKP
417 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
418 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
419 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
420 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
421 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
422 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
423 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
424 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
425 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
426 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
427 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
428 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
429 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
430 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
431 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
432 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
433 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
434 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
435 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
436 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
437 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
438 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
439 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
440 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
441 *
442 * (*) value not defined in all devices.
443 * @retval None
444 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)445 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
446 {
447 __IO uint32_t tmpreg;
448 SET_BIT(RCC->APB1ENR, Periphs);
449 /* Delay after an RCC peripheral clock enabling */
450 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
451 (void)tmpreg;
452 }
453
454 /**
455 * @brief Check if APB1 peripheral clock is enabled or not
456 * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_IsEnabledClock\n
457 * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n
458 * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n
459 * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
460 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
461 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
462 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
463 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
464 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
465 * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
466 * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
467 * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
468 * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
469 * APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
470 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
471 * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
472 * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
473 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
474 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
475 * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
476 * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
477 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
478 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
479 * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
480 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock
481 * @param Periphs This parameter can be a combination of the following values:
482 * @arg @ref LL_APB1_GRP1_PERIPH_BKP
483 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
484 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
485 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
486 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
487 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
488 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
489 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
490 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
491 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
492 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
493 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
494 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
495 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
496 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
497 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
498 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
499 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
500 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
501 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
502 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
503 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
504 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
505 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
506 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
507 *
508 * (*) value not defined in all devices.
509 * @retval State of Periphs (1 or 0).
510 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)511 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
512 {
513 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
514 }
515
516 /**
517 * @brief Disable APB1 peripherals clock.
518 * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_DisableClock\n
519 * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n
520 * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n
521 * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
522 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
523 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
524 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
525 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
526 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
527 * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
528 * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
529 * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
530 * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
531 * APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
532 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
533 * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
534 * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
535 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
536 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
537 * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
538 * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
539 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
540 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
541 * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
542 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock
543 * @param Periphs This parameter can be a combination of the following values:
544 * @arg @ref LL_APB1_GRP1_PERIPH_BKP
545 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
546 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
547 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
548 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
549 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
550 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
551 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
552 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
553 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
554 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
555 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
556 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
557 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
558 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
559 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
560 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
561 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
562 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
563 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
564 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
565 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
566 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
567 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
568 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
569 *
570 * (*) value not defined in all devices.
571 * @retval None
572 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)573 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
574 {
575 CLEAR_BIT(RCC->APB1ENR, Periphs);
576 }
577
578 /**
579 * @brief Force APB1 peripherals reset.
580 * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ForceReset\n
581 * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n
582 * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n
583 * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
584 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
585 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
586 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
587 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
588 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
589 * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
590 * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
591 * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
592 * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
593 * APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
594 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
595 * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
596 * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
597 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
598 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
599 * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
600 * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
601 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
602 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
603 * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
604 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset
605 * @param Periphs This parameter can be a combination of the following values:
606 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
607 * @arg @ref LL_APB1_GRP1_PERIPH_BKP
608 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
609 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
610 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
611 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
612 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
613 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
614 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
615 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
616 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
617 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
618 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
619 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
620 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
621 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
622 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
623 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
624 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
625 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
626 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
627 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
628 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
629 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
630 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
631 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
632 *
633 * (*) value not defined in all devices.
634 * @retval None
635 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)636 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
637 {
638 SET_BIT(RCC->APB1RSTR, Periphs);
639 }
640
641 /**
642 * @brief Release APB1 peripherals reset.
643 * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ReleaseReset\n
644 * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n
645 * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n
646 * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
647 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
648 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
649 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
650 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
651 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
652 * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
653 * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
654 * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
655 * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
656 * APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
657 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
658 * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
659 * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
660 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
661 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
662 * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
663 * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
664 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
665 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
666 * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
667 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset
668 * @param Periphs This parameter can be a combination of the following values:
669 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
670 * @arg @ref LL_APB1_GRP1_PERIPH_BKP
671 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
672 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
673 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
674 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
675 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
676 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
677 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
678 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
679 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
680 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
681 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
682 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
683 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
684 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
685 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
686 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
687 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
688 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
689 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
690 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
691 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
692 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
693 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
694 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
695 *
696 * (*) value not defined in all devices.
697 * @retval None
698 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)699 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
700 {
701 CLEAR_BIT(RCC->APB1RSTR, Periphs);
702 }
703
704 /**
705 * @}
706 */
707
708 /** @defgroup BUS_LL_EF_APB2 APB2
709 * @{
710 */
711
712 /**
713 * @brief Enable APB2 peripherals clock.
714 * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
715 * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n
716 * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n
717 * APB2ENR AFIOEN LL_APB2_GRP1_EnableClock\n
718 * APB2ENR IOPAEN LL_APB2_GRP1_EnableClock\n
719 * APB2ENR IOPBEN LL_APB2_GRP1_EnableClock\n
720 * APB2ENR IOPCEN LL_APB2_GRP1_EnableClock\n
721 * APB2ENR IOPDEN LL_APB2_GRP1_EnableClock\n
722 * APB2ENR IOPEEN LL_APB2_GRP1_EnableClock\n
723 * APB2ENR IOPFEN LL_APB2_GRP1_EnableClock\n
724 * APB2ENR IOPGEN LL_APB2_GRP1_EnableClock\n
725 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
726 * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
727 * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
728 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
729 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
730 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
731 * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
732 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
733 * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
734 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock
735 * @param Periphs This parameter can be a combination of the following values:
736 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
737 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
738 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
739 * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
740 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
741 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
742 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
743 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
744 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
745 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
746 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
747 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
748 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
749 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
750 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
751 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
752 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
753 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
754 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
755 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
756 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
757 *
758 * (*) value not defined in all devices.
759 * @retval None
760 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)761 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
762 {
763 __IO uint32_t tmpreg;
764 SET_BIT(RCC->APB2ENR, Periphs);
765 /* Delay after an RCC peripheral clock enabling */
766 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
767 (void)tmpreg;
768 }
769
770 /**
771 * @brief Check if APB2 peripheral clock is enabled or not
772 * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
773 * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n
774 * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n
775 * APB2ENR AFIOEN LL_APB2_GRP1_IsEnabledClock\n
776 * APB2ENR IOPAEN LL_APB2_GRP1_IsEnabledClock\n
777 * APB2ENR IOPBEN LL_APB2_GRP1_IsEnabledClock\n
778 * APB2ENR IOPCEN LL_APB2_GRP1_IsEnabledClock\n
779 * APB2ENR IOPDEN LL_APB2_GRP1_IsEnabledClock\n
780 * APB2ENR IOPEEN LL_APB2_GRP1_IsEnabledClock\n
781 * APB2ENR IOPFEN LL_APB2_GRP1_IsEnabledClock\n
782 * APB2ENR IOPGEN LL_APB2_GRP1_IsEnabledClock\n
783 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
784 * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
785 * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
786 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
787 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
788 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
789 * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
790 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
791 * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
792 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock
793 * @param Periphs This parameter can be a combination of the following values:
794 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
795 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
796 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
797 * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
798 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
799 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
800 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
801 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
802 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
803 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
804 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
805 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
806 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
807 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
808 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
809 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
810 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
811 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
812 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
813 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
814 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
815 *
816 * (*) value not defined in all devices.
817 * @retval State of Periphs (1 or 0).
818 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)819 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
820 {
821 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
822 }
823
824 /**
825 * @brief Disable APB2 peripherals clock.
826 * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
827 * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n
828 * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n
829 * APB2ENR AFIOEN LL_APB2_GRP1_DisableClock\n
830 * APB2ENR IOPAEN LL_APB2_GRP1_DisableClock\n
831 * APB2ENR IOPBEN LL_APB2_GRP1_DisableClock\n
832 * APB2ENR IOPCEN LL_APB2_GRP1_DisableClock\n
833 * APB2ENR IOPDEN LL_APB2_GRP1_DisableClock\n
834 * APB2ENR IOPEEN LL_APB2_GRP1_DisableClock\n
835 * APB2ENR IOPFEN LL_APB2_GRP1_DisableClock\n
836 * APB2ENR IOPGEN LL_APB2_GRP1_DisableClock\n
837 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
838 * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
839 * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
840 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
841 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
842 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
843 * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
844 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
845 * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
846 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock
847 * @param Periphs This parameter can be a combination of the following values:
848 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
849 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
850 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
851 * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
852 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
853 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
854 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
855 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
856 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
857 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
858 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
859 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
860 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
861 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
862 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
863 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
864 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
865 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
866 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
867 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
868 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
869 *
870 * (*) value not defined in all devices.
871 * @retval None
872 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)873 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
874 {
875 CLEAR_BIT(RCC->APB2ENR, Periphs);
876 }
877
878 /**
879 * @brief Force APB2 peripherals reset.
880 * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n
881 * APB2RSTR ADC2RST LL_APB2_GRP1_ForceReset\n
882 * APB2RSTR ADC3RST LL_APB2_GRP1_ForceReset\n
883 * APB2RSTR AFIORST LL_APB2_GRP1_ForceReset\n
884 * APB2RSTR IOPARST LL_APB2_GRP1_ForceReset\n
885 * APB2RSTR IOPBRST LL_APB2_GRP1_ForceReset\n
886 * APB2RSTR IOPCRST LL_APB2_GRP1_ForceReset\n
887 * APB2RSTR IOPDRST LL_APB2_GRP1_ForceReset\n
888 * APB2RSTR IOPERST LL_APB2_GRP1_ForceReset\n
889 * APB2RSTR IOPFRST LL_APB2_GRP1_ForceReset\n
890 * APB2RSTR IOPGRST LL_APB2_GRP1_ForceReset\n
891 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
892 * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
893 * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
894 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
895 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
896 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
897 * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
898 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
899 * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
900 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset
901 * @param Periphs This parameter can be a combination of the following values:
902 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
903 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
904 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
905 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
906 * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
907 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
908 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
909 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
910 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
911 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
912 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
913 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
914 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
915 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
916 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
917 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
918 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
919 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
920 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
921 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
922 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
923 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
924 *
925 * (*) value not defined in all devices.
926 * @retval None
927 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)928 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
929 {
930 SET_BIT(RCC->APB2RSTR, Periphs);
931 }
932
933 /**
934 * @brief Release APB2 peripherals reset.
935 * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n
936 * APB2RSTR ADC2RST LL_APB2_GRP1_ReleaseReset\n
937 * APB2RSTR ADC3RST LL_APB2_GRP1_ReleaseReset\n
938 * APB2RSTR AFIORST LL_APB2_GRP1_ReleaseReset\n
939 * APB2RSTR IOPARST LL_APB2_GRP1_ReleaseReset\n
940 * APB2RSTR IOPBRST LL_APB2_GRP1_ReleaseReset\n
941 * APB2RSTR IOPCRST LL_APB2_GRP1_ReleaseReset\n
942 * APB2RSTR IOPDRST LL_APB2_GRP1_ReleaseReset\n
943 * APB2RSTR IOPERST LL_APB2_GRP1_ReleaseReset\n
944 * APB2RSTR IOPFRST LL_APB2_GRP1_ReleaseReset\n
945 * APB2RSTR IOPGRST LL_APB2_GRP1_ReleaseReset\n
946 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
947 * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
948 * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
949 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
950 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
951 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
952 * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
953 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
954 * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
955 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset
956 * @param Periphs This parameter can be a combination of the following values:
957 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
958 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
959 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
960 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
961 * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
962 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
963 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
964 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
965 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
966 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
967 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
968 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
969 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
970 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
971 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
972 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
973 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
974 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
975 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
976 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
977 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
978 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
979 *
980 * (*) value not defined in all devices.
981 * @retval None
982 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)983 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
984 {
985 CLEAR_BIT(RCC->APB2RSTR, Periphs);
986 }
987
988 /**
989 * @}
990 */
991
992
993 /**
994 * @}
995 */
996
997 /**
998 * @}
999 */
1000
1001 #endif /* defined(RCC) */
1002
1003 /**
1004 * @}
1005 */
1006
1007 #ifdef __cplusplus
1008 }
1009 #endif
1010
1011 #endif /* __STM32F1xx_LL_BUS_H */
1012
1013
