1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32L4xx_LL_ADC_H
21 #define STM32L4xx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l4xx.h"
29
30 /** @addtogroup STM32L4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC group regular sequencer: */
49 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
50 /* - sequencer register offset */
51 /* - sequencer rank bits position into the selected register */
52
53 /* Internal register offset for ADC group regular sequencer configuration */
54 /* (offset placed into a spare area of literal definition) */
55 #define ADC_SQR1_REGOFFSET (0x00000000UL)
56 #define ADC_SQR2_REGOFFSET (0x00000100UL)
57 #define ADC_SQR3_REGOFFSET (0x00000200UL)
58 #define ADC_SQR4_REGOFFSET (0x00000300UL)
59
60 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \
61 | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
62 #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK*/
63 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
64
65 /* Definition of ADC group regular sequencer bits information to be inserted */
66 /* into ADC group regular sequencer ranks literals definition. */
67 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR1_SQ1" position in register */
68 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR1_SQ2" position in register */
69 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR1_SQ3" position in register */
70 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR1_SQ4" position in register */
71 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR2_SQ5" position in register */
72 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR2_SQ6" position in register */
73 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR2_SQ7" position in register */
74 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR2_SQ8" position in register */
75 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR2_SQ9" position in register */
76 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR3_SQ10" position in register */
77 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR3_SQ11" position in register */
78 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR3_SQ12" position in register */
79 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR3_SQ13" position in register */
80 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR3_SQ14" position in register */
81 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR4_SQ15" position in register */
82 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR4_SQ16" position in register */
83
84
85
86 /* Internal mask for ADC group injected sequencer: */
87 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
88 /* - data register offset */
89 /* - sequencer rank bits position into the selected register */
90
91 /* Internal register offset for ADC group injected data register */
92 /* (offset placed into a spare area of literal definition) */
93 #define ADC_JDR1_REGOFFSET (0x00000000UL)
94 #define ADC_JDR2_REGOFFSET (0x00000100UL)
95 #define ADC_JDR3_REGOFFSET (0x00000200UL)
96 #define ADC_JDR4_REGOFFSET (0x00000300UL)
97
98 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \
99 | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
100 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
101 #define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK*/
102
103 /* Definition of ADC group injected sequencer bits information to be inserted */
104 /* into ADC group injected sequencer ranks literals definition. */
105 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_JSQR_JSQ1" position in register */
106 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (14UL) /* Equivalent to bitfield "ADC_JSQR_JSQ2" position in register */
107 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_JSQR_JSQ3" position in register */
108 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (26UL) /* Equivalent to bitfield "ADC_JSQR_JSQ4" position in register */
109
110
111
112 /* Internal mask for ADC group regular trigger: */
113 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
114 /* - regular trigger source */
115 /* - regular trigger edge */
116 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for
117 compatibility with some ADC on other STM32 series
118 having this setting set by HW default value) */
119
120 /* Mask containing trigger source masks for each of possible */
121 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
122 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
123 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
124 ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \
125 ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \
126 ((ADC_CFGR_EXTSEL) << (4U * 3UL)) )
127
128 /* Mask containing trigger edge masks for each of possible */
129 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
130 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
131 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
132 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
133 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
134 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
135
136 /* Definition of ADC group regular trigger bits information. */
137 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */
138 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CFGR_EXTEN" position in register */
139
140
141
142 /* Internal mask for ADC group injected trigger: */
143 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
144 /* - injected trigger source */
145 /* - injected trigger edge */
146 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for
147 compatibility with some ADC on other STM32 series
148 having this setting set by HW default value) */
149
150 /* Mask containing trigger source masks for each of possible */
151 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
152 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
153 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
154 ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
155 ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
156 ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
157
158 /* Mask containing trigger edge masks for each of possible */
159 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
160 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
161 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
162 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
163 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
164 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
165
166 /* Definition of ADC group injected trigger bits information. */
167 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */
168 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */
169
170
171
172
173
174
175 /* Internal mask for ADC channel: */
176 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
177 /* - channel identifier defined by number */
178 /* - channel identifier defined by bitfield */
179 /* - channel differentiation between external channels (connected to */
180 /* GPIO pins) and internal channels (connected to internal paths) */
181 /* - channel sampling time defined by SMPRx register offset */
182 /* and SMPx bits positions into SMPRx register */
183 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
184 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
185 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL) /* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK"
186 position in register */
187 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \
188 | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
189 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
190 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK
191 >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
192
193 /* Channel differentiation between external and internal channels */
194 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
195 #define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case
196 of different ADC internal channels mapped on same channel
197 number on different ADC instances */
198 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
199
200 /* Internal register offset for ADC channel sampling time configuration */
201 /* (offset placed into a spare area of literal definition) */
202 #define ADC_SMPR1_REGOFFSET (0x00000000UL)
203 #define ADC_SMPR2_REGOFFSET (0x02000000UL)
204 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
205 #define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET
206 in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
207
208 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
209 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK"
210 position in register */
211
212 /* Definition of channels ID number information to be inserted into */
213 /* channels literals definition. */
214 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
215 #define ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0)
216 #define ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1)
217 #define ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
218 #define ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2)
219 #define ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
220 #define ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
221 #define ADC_CHANNEL_7_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
222 #define ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3)
223 #define ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
224 #define ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)
225 #define ADC_CHANNEL_11_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
226 #define ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)
227 #define ADC_CHANNEL_13_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
228 #define ADC_CHANNEL_14_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
229 #define ADC_CHANNEL_15_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \
230 ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
231 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4)
232 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
233 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1)
234
235 /* Definition of channels ID bitfield information to be inserted into */
236 /* channels literals definition. */
237 #define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
238 #define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
239 #define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
240 #define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
241 #define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
242 #define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
243 #define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
244 #define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
245 #define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
246 #define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
247 #define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
248 #define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
249 #define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
250 #define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
251 #define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
252 #define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
253 #define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
254 #define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
255 #define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
256
257 /* Definition of channels sampling time information to be inserted into */
258 /* channels literals definition. */
259 /* Value shifted are equivalent to bitfield "ADC_SMPRx_SMPy" position */
260 /* in register. */
261 #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
262 #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
263 #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
264 #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
265 #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
266 #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
267 #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
268 #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
269 #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
270 #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
271 #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
272 #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
273 #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
274 #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
275 #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
276 #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
277 #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
278 #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
279 #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
280
281
282 /* Internal mask for ADC mode single or differential ended: */
283 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
284 /* the relevant bits for: */
285 /* (concatenation of multiple bits used in different registers) */
286 /* - ADC calibration: calibration start, calibration factor get or set */
287 /* - ADC channels: set each ADC channel ending mode */
288 #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
289 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
290 #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
291 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen
292 to perform of shift when single mode is selected, shift value out of
293 channels bits range. */
294 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode:
295 mask of bit */
296 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode:
297 position of bit */
298 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit
299 ADC_SINGLEDIFF_CALIB_F_BIT_D to perform a shift of 4 ranks */
300
301 /* Internal mask for ADC analog watchdog: */
302 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
303 /* (concatenation of multiple bits used in different analog watchdogs, */
304 /* (feature of several watchdogs not available on all STM32 series)). */
305 /* - analog watchdog 1: monitored channel defined by number, */
306 /* selection of ADC group (ADC groups regular and-or injected). */
307 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
308 /* selection on groups. */
309
310 /* Internal register offset for ADC analog watchdog channel configuration */
311 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
312 #define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
313 #define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
314
315 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
316 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
317 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
318 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
319
320 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
321
322 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
323 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
324 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
325
326 #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET
327 in ADC_AWD_CRX_REGOFFSET_MASK */
328
329 /* Internal register offset for ADC analog watchdog threshold configuration */
330 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
331 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
332 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
333 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
334 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET
335 in ADC_AWD_TRX_REGOFFSET_MASK */
336 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate
337 threshold high: mask of bit */
338 #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate
339 threshold high: position of bit */
340 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to
341 position to perform a shift of 4 ranks */
342
343 /* Internal mask for ADC offset: */
344 /* Internal register offset for ADC offset instance configuration */
345 #define ADC_OFR1_REGOFFSET (0x00000000UL)
346 #define ADC_OFR2_REGOFFSET (0x00000001UL)
347 #define ADC_OFR3_REGOFFSET (0x00000002UL)
348 #define ADC_OFR4_REGOFFSET (0x00000003UL)
349 #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \
350 | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
351
352
353 /* ADC registers bits positions */
354 #define ADC_CFGR_RES_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CFGR_RES" position in register */
355 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS (22UL) /* Equivalent to bitfield "ADC_CFGR_AWD1SGL" position in register */
356 #define ADC_CFGR_AWD1EN_BITOFFSET_POS (23UL) /* Equivalent to bitfield "ADC_CFGR_AWD1EN" position in register */
357 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_CFGR_JAWD1EN" position in register */
358 #define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_TR1_HT1" position in register */
359
360
361 /* ADC registers bits groups */
362 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS \
363 | ADC_CR_JADSTART | ADC_CR_JADSTP \
364 | ADC_CR_ADSTART | ADC_CR_ADSTP) /* ADC register CR bits with
365 HW property "rs": Software can read as well as set this bit.
366 Writing '0' has no effect on the bit value. */
367
368
369 /* ADC internal channels related definitions */
370 /* Internal voltage reference VrefInt */
371 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of
372 parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC
373 (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
374 #define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) value
375 with which VrefInt has been calibrated in production
376 (tolerance: +-10 mV) (unit: mV). */
377 /* Temperature sensor */
378 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Address of parameter TS_CAL1: On STM32L4,
379 temperature sensor ADC raw data acquired at temperature 30 DegC
380 (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
381 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Address of parameter TS_CAL2: On STM32L4,
382 temperature sensor ADC raw data acquired at temperature defined by
383 TEMPSENSOR_CAL2_TEMP (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
384 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30L) /* Temperature at which temperature sensor
385 has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR
386 (tolerance: +-5 DegC) (unit: DegC). */
387 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
388 #define TEMPSENSOR_CAL2_TEMP (110L) /* Temperature at which temperature sensor
389 has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR
390 (tolerance: +-5 DegC) (unit: DegC). */
391 #else
392 #define TEMPSENSOR_CAL2_TEMP (130L) /* Temperature at which temperature sensor
393 has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR
394 (tolerance: +-5 DegC) (unit: DegC). */
395 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
396 #define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) value
397 with which temperature sensor has been calibrated in production
398 (tolerance +-10 mV) (unit: mV). */
399
400 /**
401 * @}
402 */
403
404
405 /* Private macros ------------------------------------------------------------*/
406 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
407 * @{
408 */
409
410 /**
411 * @brief Driver macro reserved for internal use: set a pointer to
412 * a register from a register basis from which an offset
413 * is applied.
414 * @param __REG__ Register basis from which the offset is applied.
415 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
416 * @retval Pointer to register address
417 */
418 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
419 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
420
421 /**
422 * @}
423 */
424
425
426 /* Exported types ------------------------------------------------------------*/
427 #if defined(USE_FULL_LL_DRIVER)
428 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
429 * @{
430 */
431
432 /**
433 * @brief Structure definition of some features of ADC common parameters
434 * and multimode
435 * (all ADC instances belonging to the same ADC common instance).
436 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
437 * is conditioned to ADC instances state (all ADC instances
438 * sharing the same ADC common instance):
439 * All ADC instances sharing the same ADC common instance must be
440 * disabled.
441 */
442 typedef struct
443 {
444 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
445 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
446 @note On this STM32 series, if ADC group injected is used, some clock ratio
447 constraints between ADC clock and AHB clock must be respected.
448 Refer to reference manual.
449 This feature can be modified afterwards using unitary function
450 @ref LL_ADC_SetCommonClock(). */
451
452 #if defined(ADC_MULTIMODE_SUPPORT)
453 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode
454 (for devices with several ADC instances).
455 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
456 This feature can be modified afterwards using unitary function
457 @ref LL_ADC_SetMultimode(). */
458
459 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
460 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
461 This feature can be modified afterwards using unitary function
462 @ref LL_ADC_SetMultiDMATransfer(). */
463
464 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
465 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
466 This feature can be modified afterwards using unitary function
467 @ref LL_ADC_SetMultiTwoSamplingDelay(). */
468 #endif /* ADC_MULTIMODE_SUPPORT */
469
470 } LL_ADC_CommonInitTypeDef;
471
472 /**
473 * @brief Structure definition of some features of ADC instance.
474 * @note These parameters have an impact on ADC scope: ADC instance.
475 * Affects both group regular and group injected (availability
476 * of ADC group injected depends on STM32 series).
477 * Refer to corresponding unitary functions into
478 * @ref ADC_LL_EF_Configuration_ADC_Instance .
479 * @note The setting of these parameters by function @ref LL_ADC_Init()
480 * is conditioned to ADC state:
481 * ADC instance must be disabled.
482 * This condition is applied to all ADC features, for efficiency
483 * and compatibility over all STM32 series. However, the different
484 * features can be set under different ADC state conditions
485 * (setting possible with ADC enabled without conversion on going,
486 * ADC enabled with conversion on going, ...)
487 * Each feature can be updated afterwards with a unitary function
488 * and potentially with ADC in a different state than disabled,
489 * refer to description of each function for setting
490 * conditioned to ADC state.
491 */
492 typedef struct
493 {
494 uint32_t Resolution; /*!< Set ADC resolution.
495 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
496 This feature can be modified afterwards using unitary function
497 @ref LL_ADC_SetResolution(). */
498
499 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
500 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
501 This feature can be modified afterwards using unitary function
502 @ref LL_ADC_SetDataAlignment(). */
503
504 uint32_t LowPowerMode; /*!< Set ADC low power mode.
505 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
506 This feature can be modified afterwards using unitary function
507 @ref LL_ADC_SetLowPowerMode(). */
508
509 } LL_ADC_InitTypeDef;
510
511 /**
512 * @brief Structure definition of some features of ADC group regular.
513 * @note These parameters have an impact on ADC scope: ADC group regular.
514 * Refer to corresponding unitary functions into
515 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
516 * (functions with prefix "REG").
517 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
518 * is conditioned to ADC state:
519 * ADC instance must be disabled.
520 * This condition is applied to all ADC features, for efficiency
521 * and compatibility over all STM32 series. However, the different
522 * features can be set under different ADC state conditions
523 * (setting possible with ADC enabled without conversion on going,
524 * ADC enabled with conversion on going, ...)
525 * Each feature can be updated afterwards with a unitary function
526 * and potentially with ADC in a different state than disabled,
527 * refer to description of each function for setting
528 * conditioned to ADC state.
529 */
530 typedef struct
531 {
532 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or
533 from external peripheral (timer event, external interrupt line).
534 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
535 @note On this STM32 series, setting trigger source to external trigger also
536 set trigger polarity to rising edge(default setting for compatibility
537 with some ADC on other STM32 series having this setting set by HW
538 default value).
539 In case of need to modify trigger edge, use function
540 @ref LL_ADC_REG_SetTriggerEdge().
541 This feature can be modified afterwards using unitary function
542 @ref LL_ADC_REG_SetTriggerSource(). */
543
544 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
545 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
546 This feature can be modified afterwards using unitary function
547 @ref LL_ADC_REG_SetSequencerLength(). */
548
549 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided
550 and scan conversions interrupted every selected number of ranks.
551 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
552 @note This parameter has an effect only if group regular sequencer is
553 enabled (scan length of 2 ranks or more).
554 This feature can be modified afterwards using unitary function
555 @ref LL_ADC_REG_SetSequencerDiscont(). */
556
557 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC
558 conversions are performed in single mode (one conversion per trigger) or in
559 continuous mode (after the first trigger, following conversions launched
560 successively automatically).
561 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
562 Note: It is not possible to enable both ADC group regular continuous mode
563 and discontinuous mode.
564 This feature can be modified afterwards using unitary function
565 @ref LL_ADC_REG_SetContinuousMode(). */
566
567 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer
568 by DMA, and DMA requests mode.
569 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
570 This feature can be modified afterwards using unitary function
571 @ref LL_ADC_REG_SetDMATransfer(). */
572
573 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
574 data preserved or overwritten.
575 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
576 This feature can be modified afterwards using unitary function
577 @ref LL_ADC_REG_SetOverrun(). */
578
579 } LL_ADC_REG_InitTypeDef;
580
581 /**
582 * @brief Structure definition of some features of ADC group injected.
583 * @note These parameters have an impact on ADC scope: ADC group injected.
584 * Refer to corresponding unitary functions into
585 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
586 * (functions with prefix "INJ").
587 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
588 * is conditioned to ADC state:
589 * ADC instance must be disabled.
590 * This condition is applied to all ADC features, for efficiency
591 * and compatibility over all STM32 series. However, the different
592 * features can be set under different ADC state conditions
593 * (setting possible with ADC enabled without conversion on going,
594 * ADC enabled with conversion on going, ...)
595 * Each feature can be updated afterwards with a unitary function
596 * and potentially with ADC in a different state than disabled,
597 * refer to description of each function for setting
598 * conditioned to ADC state.
599 */
600 typedef struct
601 {
602 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start)
603 or from external peripheral (timer event, external interrupt line).
604 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
605 @note On this STM32 series, setting trigger source to external trigger also
606 set trigger polarity to rising edge (default setting for
607 compatibility with some ADC on other STM32 series having this
608 setting set by HW default value).
609 In case of need to modify trigger edge, use function
610 @ref LL_ADC_INJ_SetTriggerEdge().
611 This feature can be modified afterwards using unitary function
612 @ref LL_ADC_INJ_SetTriggerSource(). */
613
614 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
615 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
616 This feature can be modified afterwards using unitary function
617 @ref LL_ADC_INJ_SetSequencerLength(). */
618
619 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided
620 and scan conversions interrupted every selected number of ranks.
621 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
622 @note This parameter has an effect only if group injected sequencer is
623 enabled (scan length of 2 ranks or more).
624 This feature can be modified afterwards using unitary function
625 @ref LL_ADC_INJ_SetSequencerDiscont(). */
626
627 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group
628 regular.
629 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
630 Note: This parameter must be set to set to independent trigger if injected
631 trigger source is set to an external trigger.
632 This feature can be modified afterwards using unitary function
633 @ref LL_ADC_INJ_SetTrigAuto(). */
634
635 } LL_ADC_INJ_InitTypeDef;
636
637 /**
638 * @}
639 */
640 #endif /* USE_FULL_LL_DRIVER */
641
642 /* Exported constants --------------------------------------------------------*/
643 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
644 * @{
645 */
646
647 /** @defgroup ADC_LL_EC_FLAG ADC flags
648 * @brief Flags defines which can be used with LL_ADC_ReadReg function
649 * @{
650 */
651 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
652 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary
653 conversion */
654 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence
655 conversions */
656 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
657 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
658 #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary
659 conversion */
660 #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence
661 conversions */
662 #define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue
663 overflow */
664 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
665 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
666 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
667 #if defined(ADC_MULTIMODE_SUPPORT)
668 #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
669 #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
670 #define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of
671 unitary conversion */
672 #define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of
673 unitary conversion */
674 #define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of
675 sequence conversions */
676 #define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of
677 sequence conversions */
678 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular
679 overrun */
680 #define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular
681 overrun */
682 #define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of
683 sampling phase */
684 #define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of
685 sampling phase */
686 #define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of
687 unitary conversion */
688 #define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of
689 unitary conversion */
690 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of
691 sequence conversions */
692 #define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of
693 sequence conversions */
694 #define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected
695 contexts queue overflow */
696 #define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected
697 contexts queue overflow */
698 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1
699 of the ADC master */
700 #define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1
701 of the ADC slave */
702 #define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2
703 of the ADC master */
704 #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2
705 of the ADC slave */
706 #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3
707 of the ADC master */
708 #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3
709 of the ADC slave */
710 #endif /* ADC_MULTIMODE_SUPPORT */
711 /**
712 * @}
713 */
714
715 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
716 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
717 * @{
718 */
719 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
720 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary
721 conversion */
722 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence
723 conversions */
724 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
725 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling
726 phase */
727 #define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary
728 conversion */
729 #define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence
730 conversions */
731 #define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue
732 overflow */
733 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
734 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
735 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
736 /**
737 * @}
738 */
739
740 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
741 * @{
742 */
743 /* List of ADC registers intended to be used (most commonly) with */
744 /* DMA transfer. */
745 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
746 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register
747 (corresponding to register DR) to be used with ADC configured in independent
748 mode. Without DMA transfer, register accessed by LL function
749 @ref LL_ADC_REG_ReadConversionData32() and other
750 functions @ref LL_ADC_REG_ReadConversionDatax() */
751 #if defined(ADC_MULTIMODE_SUPPORT)
752 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register
753 (corresponding to register CDR) to be used with ADC configured in multimode
754 (available on STM32 devices with several ADC instances).
755 Without DMA transfer, register accessed by LL function
756 @ref LL_ADC_REG_ReadMultiConversionData32() */
757 #endif /* ADC_MULTIMODE_SUPPORT */
758 /**
759 * @}
760 */
761
762 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
763 * @{
764 */
765 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from
766 AHB clock without prescaler */
767 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1) /*!< ADC synchronous clock derived from
768 AHB clock with prescaler division by 2 */
769 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from
770 AHB clock with prescaler division by 4 */
771 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without
772 prescaler */
773 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
774 prescaler division by 2 */
775 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
776 prescaler division by 4 */
777 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
778 prescaler division by 6 */
779 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock with
780 prescaler division by 8 */
781 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
782 prescaler division by 10 */
783 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
784 prescaler division by 12 */
785 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \
786 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
787 prescaler division by 16 */
788 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with
789 prescaler division by 32 */
790 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
791 prescaler division by 64 */
792 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
793 prescaler division by 128 */
794 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \
795 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
796 prescaler division by 256 */
797 /**
798 * @}
799 */
800
801 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
802 * @{
803 */
804 /* Note: Other measurement paths to internal channels may be available */
805 /* (connections to other peripherals). */
806 /* If they are not listed below, they do not require any specific */
807 /* path enable. In this case, Access to measurement path is done */
808 /* only by selecting the corresponding ADC internal channel. */
809 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
810 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
811 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel
812 temperature sensor */
813 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
814 /**
815 * @}
816 */
817
818 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
819 * @{
820 */
821 #define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */
822 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
823 #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */
824 #define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */
825 /**
826 * @}
827 */
828
829 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
830 * @{
831 */
832 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned
833 (alignment on data register LSB bit 0)*/
834 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned
835 (alignment on data register MSB bit 15)*/
836 /**
837 * @}
838 */
839
840 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
841 * @{
842 */
843 #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
844 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power
845 mode, ADC conversions are performed only when necessary
846 (when previous ADC conversion data is read).
847 See description with function @ref LL_ADC_SetLowPowerMode(). */
848 /**
849 * @}
850 */
851
852 /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset instance
853 * @{
854 */
855 #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset instance 1: ADC channel and offset level
856 to which the offset programmed will be applied (independently of channel
857 mapped on ADC group regular or injected) */
858 #define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset instance 2: ADC channel and offset level
859 to which the offset programmed will be applied (independently of channel
860 mapped on ADC group regular or injected) */
861 #define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset instance 3: ADC channel and offset level
862 to which the offset programmed will be applied (independently of channel
863 mapped on ADC group regular or injected) */
864 #define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset instance 4: ADC channel and offset level
865 to which the offset programmed will be applied (independently of channel
866 mapped on ADC group regular or injected) */
867 /**
868 * @}
869 */
870
871 /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
872 * @{
873 */
874 #define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled
875 (setting offset instance wise) */
876 #define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled
877 (setting offset instance wise) */
878 /**
879 * @}
880 */
881
882 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
883 * @{
884 */
885 #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
886 #define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32
887 devices)*/
888 #define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */
889 /**
890 * @}
891 */
892
893 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
894 * @{
895 */
896 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP \
897 | ADC_CHANNEL_0_BITFIELD) /*!< ADC channel ADCx_IN0 */
898 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP \
899 | ADC_CHANNEL_1_BITFIELD) /*!< ADC channel ADCx_IN1 */
900 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP \
901 | ADC_CHANNEL_2_BITFIELD) /*!< ADC channel ADCx_IN2 */
902 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP \
903 | ADC_CHANNEL_3_BITFIELD) /*!< ADC channel ADCx_IN3 */
904 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP \
905 | ADC_CHANNEL_4_BITFIELD) /*!< ADC channel ADCx_IN4 */
906 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP \
907 | ADC_CHANNEL_5_BITFIELD) /*!< ADC channel ADCx_IN5 */
908 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP \
909 | ADC_CHANNEL_6_BITFIELD) /*!< ADC channel ADCx_IN6 */
910 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP \
911 | ADC_CHANNEL_7_BITFIELD) /*!< ADC channel ADCx_IN7 */
912 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP \
913 | ADC_CHANNEL_8_BITFIELD) /*!< ADC channel ADCx_IN8 */
914 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP \
915 | ADC_CHANNEL_9_BITFIELD) /*!< ADC channel ADCx_IN9 */
916 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP \
917 | ADC_CHANNEL_10_BITFIELD) /*!< ADC channel ADCx_IN10 */
918 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP \
919 | ADC_CHANNEL_11_BITFIELD) /*!< ADC channel ADCx_IN11 */
920 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP \
921 | ADC_CHANNEL_12_BITFIELD) /*!< ADC channel ADCx_IN12 */
922 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP \
923 | ADC_CHANNEL_13_BITFIELD) /*!< ADC channel ADCx_IN13 */
924 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP \
925 | ADC_CHANNEL_14_BITFIELD) /*!< ADC channel ADCx_IN14 */
926 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP \
927 | ADC_CHANNEL_15_BITFIELD) /*!< ADC channel ADCx_IN15 */
928 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | \
929 ADC_CHANNEL_16_BITFIELD) /*!< ADC channel ADCx_IN16 */
930 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | \
931 ADC_CHANNEL_17_BITFIELD) /*!< ADC channel ADCx_IN17 */
932 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | \
933 ADC_CHANNEL_18_BITFIELD) /*!< ADC channel ADCx_IN18 */
934 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
935 connected to VrefInt: Internal voltage reference.
936 On STM32L4, ADC channel available only on ADC instance: ADC1. */
937 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
938 connected to internal temperature sensor.
939 On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. */
940 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
941 connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3
942 to have channel voltage always below Vdda.
943 On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. */
944 #if defined(ADC1) && !defined(ADC2)
945 #define LL_ADC_CHANNEL_DAC1CH1 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | \
946 ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel
947 connected to DAC1 channel 1, channel specific to ADC1. This channel is
948 shared with ADC internal channel connected to internal temperature sensor,
949 selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */
950 #define LL_ADC_CHANNEL_DAC1CH2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | \
951 ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel
952 connected to DAC1 channel 2, channel specific to ADC1. This channel is
953 shared with ADC internal channel connected to Vbat,
954 selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */
955 #elif defined(ADC2)
956 #define LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | \
957 ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel
958 connected to DAC1 channel 1, channel specific to ADC2 */
959 #define LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | \
960 ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel
961 connected to DAC1 channel 2, channel specific to ADC2 */
962 #if defined(ADC3)
963 #define LL_ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
964 connected to DAC1 channel 1, channel specific to ADC3 */
965 #define LL_ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
966 connected to DAC1 channel 2, channel specific to ADC3 */
967 #endif /* ADC3 */
968 #endif /* ADC1 && !ADC2 */
969 /**
970 * @}
971 */
972
973 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
974 * @{
975 */
976 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular
977 conversion trigger internal: SW start. */
978 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | \
979 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
980 conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to
981 rising edge (default setting). */
982 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | \
983 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
984 conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to
985 rising edge (default setting). */
986 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
987 conversion trigger from external peripheral: TIM1 channel 1 event (capture
988 compare: input capture or output capture). Trigger edge set to rising edge
989 (default setting). */
990 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
991 conversion trigger from external peripheral: TIM1 channel 2 event (capture
992 compare: input capture or output capture). Trigger edge set to rising edge
993 (default setting). */
994 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
995 conversion trigger from external peripheral: TIM1 channel 3 event (capture
996 compare: input capture or output capture). Trigger edge set to rising edge
997 (default setting). */
998 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | \
999 ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1000 conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to
1001 rising edge (default setting). */
1002 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
1003 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1004 conversion trigger from external peripheral: TIM2 channel 2 event (capture
1005 compare: input capture or output capture). Trigger edge set to rising edge
1006 (default setting). */
1007 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1008 conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to
1009 rising edge (default setting). */
1010 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
1011 ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
1012 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1013 conversion trigger from external peripheral: TIM3 channel 4 event (capture
1014 compare: input capture or output capture). Trigger edge set to rising edge
1015 (default setting). */
1016 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
1017 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1018 conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to
1019 rising edge (default setting). */
1020 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \
1021 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1022 conversion trigger from external peripheral: TIM4 channel 4 event (capture
1023 compare: input capture or output capture). Trigger edge set to
1024 rising edge (default setting). */
1025 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
1026 ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1027 conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to
1028 rising edge (default setting). */
1029 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
1030 ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1031 conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to
1032 rising edge (default setting). */
1033 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1034 conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to
1035 rising edge (default setting). */
1036 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
1037 ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1038 conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to
1039 rising edge (default setting). */
1040 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
1041 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1042 conversion trigger from external peripheral: external interrupt line 11.
1043 Trigger edge set to rising edge (default setting). */
1044 /**
1045 * @}
1046 */
1047
1048 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
1049 * @{
1050 */
1051 #define LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion
1052 trigger polarity set to rising edge */
1053 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1) /*!< ADC group regular conversion
1054 trigger polarity set to falling edge */
1055 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion
1056 trigger polarity set to both rising and falling edges */
1057 /**
1058 * @}
1059 */
1060
1061 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
1062 * @{
1063 */
1064 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions performed in single mode:
1065 one conversion per trigger */
1066 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions performed in continuous mode:
1067 after the first trigger, following conversions launched successively
1068 automatically */
1069 /**
1070 * @}
1071 */
1072
1073 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
1074 * @{
1075 */
1076 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
1077 #define LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA
1078 in limited mode (one shot mode): DMA transfer requests are stopped when
1079 number of DMA data transfers (number of ADC conversions) is reached.
1080 This ADC mode is intended to be used with DMA mode non-circular. */
1081 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are
1082 transferred by DMA, in unlimited mode: DMA transfer requests are unlimited,
1083 whatever number of DMA data transferred (number of ADC conversions).
1084 This ADC mode is intended to be used with DMA mode circular. */
1085 /**
1086 * @}
1087 */
1088
1089 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
1090 /** @defgroup ADC_LL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data
1091 * @{
1092 */
1093 #define LL_ADC_REG_DFSDM_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */
1094 #define LL_ADC_REG_DFSDM_TRANSFER_ENABLE (ADC_CFGR_DFSDMCFG) /*!< ADC conversion data are transferred to DFSDM for
1095 post processing. The ADC conversion data format must be 16-bit signed and
1096 right aligned, refer to reference manual.
1097 DFSDM transfer cannot be used if DMA transfer is enabled. */
1098 /**
1099 * @}
1100 */
1101 #endif /* ADC_CFGR_DFSDMCFG */
1102
1103 #if defined(ADC_SMPR1_SMPPLUS)
1104 /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration
1105 * @{
1106 */
1107 #define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000UL) /*!< ADC sampling time let to default settings. */
1108 #define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock
1109 cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped
1110 with selection sampling time 2.5 ADC clock cycles, whatever channels mapped
1111 on ADC groups regular or injected). */
1112 /**
1113 * @}
1114 */
1115 #endif /* ADC_SMPR1_SMPPLUS */
1116
1117 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
1118 * @{
1119 */
1120 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun:
1121 data preserved */
1122 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun:
1123 data overwritten */
1124 /**
1125 * @}
1126 */
1127
1128 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
1129 * @{
1130 */
1131 #define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable
1132 (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1133 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1134 with 2 ranks in the sequence */
1135 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_SQR1_L_1) /*!< ADC group regular sequencer enable
1136 with 3 ranks in the sequence */
1137 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1138 with 4 ranks in the sequence */
1139 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_SQR1_L_2) /*!< ADC group regular sequencer enable
1140 with 5 ranks in the sequence */
1141 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1142 with 6 ranks in the sequence */
1143 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable
1144 with 7 ranks in the sequence */
1145 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_1 \
1146 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1147 with 8 ranks in the sequence */
1148 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3) /*!< ADC group regular sequencer enable
1149 with 9 ranks in the sequence */
1150 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1151 with 10 ranks in the sequence */
1152 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable
1153 with 11 ranks in the sequence */
1154 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 \
1155 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1156 with 12 ranks in the sequence */
1157 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2) /*!< ADC group regular sequencer enable
1158 with 13 ranks in the sequence */
1159 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
1160 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1161 with 14 ranks in the sequence */
1162 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
1163 | ADC_SQR1_L_1) /*!< ADC group regular sequencerenable
1164 with 15 ranks in the sequence */
1165 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
1166 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1167 with 16 ranks in the sequence */
1168 /**
1169 * @}
1170 */
1171
1172 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
1173 * @{
1174 */
1175 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer
1176 discontinuous mode disable */
1177 #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1178 discontinuous mode enable with sequence interruption every rank */
1179 #define LL_ADC_REG_SEQ_DISCONT_2RANKS (ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1180 discontinuous mode enabled with sequence interruption every 2 ranks */
1181 #define LL_ADC_REG_SEQ_DISCONT_3RANKS (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1182 discontinuous mode enable with sequence interruption every 3 ranks */
1183 #define LL_ADC_REG_SEQ_DISCONT_4RANKS (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 \
1184 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1185 discontinuous mode enable with sequence interruption every 4 ranks */
1186 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1187 discontinuous mode enable with sequence interruption every 5 ranks */
1188 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 \
1189 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1190 discontinuous mode enable with sequence interruption every 6 ranks */
1191 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 \
1192 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1193 discontinuous mode enable with sequence interruption every 7 ranks */
1194 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 \
1195 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1196 discontinuous mode enable with sequence interruption every 8 ranks */
1197 /**
1198 * @}
1199 */
1200
1201 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
1202 * @{
1203 */
1204 #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group
1205 regular sequencer rank 1 */
1206 #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group
1207 regular sequencer rank 2 */
1208 #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group
1209 regular sequencer rank 3 */
1210 #define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group
1211 regular sequencer rank 4 */
1212 #define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group
1213 regular sequencer rank 5 */
1214 #define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group
1215 regular sequencer rank 6 */
1216 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group
1217 regular sequencer rank 7 */
1218 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group
1219 regular sequencer rank 8 */
1220 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group
1221 regular sequencer rank 9 */
1222 #define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group
1223 regular sequencer rank 10 */
1224 #define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group
1225 regular sequencer rank 11 */
1226 #define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group
1227 regular sequencer rank 12 */
1228 #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group
1229 regular sequencer rank 13 */
1230 #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group
1231 regular sequencer rank 14 */
1232 #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group
1233 regular sequencer rank 15 */
1234 #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group
1235 regular sequencer rank 16 */
1236 /**
1237 * @}
1238 */
1239
1240 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
1241 * @{
1242 */
1243 #define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected
1244 conversion trigger internal: SW start. */
1245 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1246 conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to
1247 rising edge (default setting). */
1248 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1249 conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to
1250 rising edge (default setting). */
1251 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1252 conversion trigger from external peripheral: TIM1 channel 4 event (capture
1253 compare: input capture or output capture). Trigger edge set to rising edge
1254 (default setting). */
1255 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1256 conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to
1257 rising edge (default setting). */
1258 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
1259 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1260 conversion trigger from external peripheral: TIM2 channel 1 event (capture
1261 compare: input capture or output capture). Trigger edge set to rising edge
1262 (default setting). */
1263 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
1264 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1265 conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to
1266 rising edge (default setting). */
1267 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
1268 ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1269 conversion trigger from external peripheral: TIM3 channel 1 event (capture
1270 compare: input capture or output capture). Trigger edge set to rising edge
1271 (default setting). */
1272 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
1273 ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1274 conversion trigger from external peripheral: TIM3 channel 3 event (capture
1275 compare: input capture or output capture). Trigger edge set to rising edge
1276 (default setting). */
1277 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1278 conversion trigger from external peripheral: TIM3 channel 4 event (capture
1279 compare: input capture or output capture). Trigger edge set to rising edge
1280 (default setting). */
1281 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | \
1282 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1283 conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to
1284 rising edge (default setting). */
1285 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
1286 ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1287 conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to
1288 rising edge (default setting). */
1289 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
1290 ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1291 conversion trigger from external peripheral: TIM8 channel 4 event (capture
1292 compare: input capture or output capture). Trigger edge set to rising edge
1293 (default setting). */
1294 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | \
1295 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1296 conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to
1297 rising edge (default setting). */
1298 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
1299 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1300 conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to
1301 rising edge (default setting). */
1302 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
1303 ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
1304 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1305 conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to
1306 rising edge (default setting). */
1307 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
1308 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1309 conversion trigger from external peripheral: external interrupt line 15.
1310 Trigger edge set to rising edge (default setting). */
1311 /**
1312 * @}
1313 */
1314
1315 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
1316 * @{
1317 */
1318 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion
1319 trigger polarity set to rising edge */
1320 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion
1321 trigger polarity set to falling edge */
1322 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion
1323 trigger polarity set to both rising and falling edges */
1324 /**
1325 * @}
1326 */
1327
1328 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
1329 * @{
1330 */
1331 #define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent.
1332 Setting mandatory if ADC group injected injected trigger source is set to
1333 an external trigger. */
1334 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group
1335 regular. Setting compliant only with group injected trigger source set to
1336 SW start, without any further action on ADC group injected conversion start
1337 or stop: in this case, ADC group injected is controlled only from ADC group
1338 regular. */
1339 /**
1340 * @}
1341 */
1342
1343 /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode
1344 * @{
1345 */
1346 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled
1347 and can contain up to 2 contexts. When all contexts have been processed,
1348 the queue maintains the last context active perpetually. */
1349 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled
1350 and can contain up to 2 contexts. When all contexts have been processed,
1351 the queue is empty and injected group triggers are disabled. */
1352 #define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled:
1353 only 1 sequence can be configured and is active perpetually. */
1354 /**
1355 * @}
1356 */
1357
1358 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
1359 * @{
1360 */
1361 #define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable
1362 (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1363 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable
1364 with 2 ranks in the sequence */
1365 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable
1366 with 3 ranks in the sequence */
1367 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable
1368 with 4 ranks in the sequence */
1369 /**
1370 * @}
1371 */
1372
1373 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
1374 * @{
1375 */
1376 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode
1377 disable */
1378 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode
1379 enable with sequence interruption every rank */
1380 /**
1381 * @}
1382 */
1383
1384 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
1385 * @{
1386 */
1387 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET \
1388 | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 1 */
1389 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET \
1390 | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 2 */
1391 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET \
1392 | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 3 */
1393 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET \
1394 | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 4 */
1395 /**
1396 * @}
1397 */
1398
1399 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
1400 * @{
1401 */
1402 #define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */
1403 #define LL_ADC_SAMPLINGTIME_6CYCLES_5 (ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */
1404 #define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR2_SMP10_1) /*!< Sampling time 12.5 ADC clock cycles */
1405 #define LL_ADC_SAMPLINGTIME_24CYCLES_5 (ADC_SMPR2_SMP10_1 \
1406 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */
1407 #define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2) /*!< Sampling time 47.5 ADC clock cycles */
1408 #define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 \
1409 | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
1410 #define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 \
1411 | ADC_SMPR2_SMP10_1) /*!< Sampling time 247.5 ADC clock cycles */
1412 #define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 \
1413 | ADC_SMPR2_SMP10_1 \
1414 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */
1415 /**
1416 * @}
1417 */
1418
1419 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
1420 * @{
1421 */
1422 #define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending
1423 set to single ended (literal also used to set calibration mode) */
1424 #define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending
1425 set to differential (literal also used to set calibration mode) */
1426 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending
1427 set to both single ended and differential (literal used only to set
1428 calibration factors) */
1429 /**
1430 * @}
1431 */
1432
1433 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
1434 * @{
1435 */
1436 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \
1437 | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
1438 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK \
1439 | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
1440 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK \
1441 | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
1442 /**
1443 * @}
1444 */
1445
1446 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
1447 * @{
1448 */
1449 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring
1450 disabled */
1451 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK \
1452 | ADC_CFGR_AWD1EN) /*!< ADC analog watchdog monitoring
1453 of all channels, converted by group regular only */
1454 #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK \
1455 | ADC_CFGR_JAWD1EN) /*!< ADC analog watchdog monitoring
1456 of all channels, converted by group injected only */
1457 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK \
1458 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN) /*!< ADC analog watchdog monitoring
1459 of all channels, converted by either group regular or injected */
1460 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \
1461 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1462 of ADC channel ADCx_IN0, converted by group regular only */
1463 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \
1464 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1465 of ADC channel ADCx_IN0, converted by group injected only */
1466 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \
1467 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1468 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1469 of ADC channel ADCx_IN0, converted by either group regular or injected */
1470 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \
1471 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1472 of ADC channel ADCx_IN1, converted by group regular only */
1473 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \
1474 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1475 of ADC channel ADCx_IN1, converted by group injected only */
1476 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \
1477 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1478 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1479 of ADC channel ADCx_IN1, converted by either group regular or injected */
1480 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \
1481 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1482 of ADC channel ADCx_IN2, converted by group regular only */
1483 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \
1484 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1485 of ADC channel ADCx_IN2, converted by group injected only */
1486 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \
1487 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1488 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1489 of ADC channel ADCx_IN2, converted by either group regular or injected */
1490 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \
1491 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1492 of ADC channel ADCx_IN3, converted by group regular only */
1493 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \
1494 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1495 of ADC channel ADCx_IN3, converted by group injected only */
1496 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \
1497 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1498 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1499 of ADC channel ADCx_IN3, converted by either group regular or injected */
1500 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \
1501 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1502 of ADC channel ADCx_IN4, converted by group regular only */
1503 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \
1504 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1505 of ADC channel ADCx_IN4, converted by group injected only */
1506 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \
1507 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1508 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1509 of ADC channel ADCx_IN4, converted by either group regular or injected */
1510 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \
1511 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1512 of ADC channel ADCx_IN5, converted by group regular only */
1513 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \
1514 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1515 of ADC channel ADCx_IN5, converted by group injected only */
1516 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \
1517 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1518 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1519 of ADC channel ADCx_IN5, converted by either group regular or injected */
1520 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \
1521 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1522 of ADC channel ADCx_IN6, converted by group regular only */
1523 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \
1524 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1525 of ADC channel ADCx_IN6, converted by group injected only */
1526 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \
1527 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1528 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1529 of ADC channel ADCx_IN6, converted by either group regular or injected */
1530 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \
1531 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1532 of ADC channel ADCx_IN7, converted by group regular only */
1533 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \
1534 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1535 of ADC channel ADCx_IN7, converted by group injected only */
1536 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \
1537 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1538 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1539 of ADC channel ADCx_IN7, converted by either group regular or injected */
1540 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \
1541 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1542 of ADC channel ADCx_IN8, converted by group regular only */
1543 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \
1544 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1545 of ADC channel ADCx_IN8, converted by group injected only */
1546 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \
1547 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1548 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1549 of ADC channel ADCx_IN8, converted by either group regular or injected */
1550 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \
1551 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1552 of ADC channel ADCx_IN9, converted by group regular only */
1553 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \
1554 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1555 of ADC channel ADCx_IN9, converted by group injected only */
1556 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \
1557 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1558 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1559 of ADC channel ADCx_IN9, converted by either group regular or injected */
1560 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \
1561 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1562 of ADC channel ADCx_IN10, converted by group regular only */
1563 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \
1564 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1565 of ADC channel ADCx_IN10, converted by group injected only */
1566 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)\
1567 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1568 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1569 of ADC channel ADCx_IN10, converted by either group regular or injected */
1570 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
1571 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1572 of ADC channel ADCx_IN11, converted by group regular only */
1573 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
1574 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1575 of ADC channel ADCx_IN11, converted by group injected only */
1576 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
1577 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1578 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1579 of ADC channel ADCx_IN11, converted by either group regular or injected */
1580 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
1581 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1582 of ADC channel ADCx_IN12, converted by group regular only */
1583 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
1584 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1585 of ADC channel ADCx_IN12, converted by group injected only */
1586 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
1587 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1588 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1589 of ADC channel ADCx_IN12, converted by either group regular or injected */
1590 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
1591 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1592 of ADC channel ADCx_IN13, converted by group regular only */
1593 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
1594 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1595 of ADC channel ADCx_IN13, converted by group injected only */
1596 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
1597 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1598 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1599 of ADC channel ADCx_IN13, converted by either group regular or injected */
1600 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
1601 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1602 of ADC channel ADCx_IN14, converted by group regular only */
1603 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
1604 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1605 of ADC channel ADCx_IN14, converted by group only */
1606 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
1607 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1608 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1609 of ADC channel ADCx_IN14, converted by either group regular or injected */
1610 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
1611 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1612 monitoring of ADC channel ADCx_IN15, converted by group regular only */
1613 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
1614 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1615 of ADC channel ADCx_IN15, converted by group injected only */
1616 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
1617 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1618 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1619 of ADC channel ADCx_IN15, converted by either group
1620 regular or injected */
1621 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
1622 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1623 of ADC channel ADCx_IN16, converted by group regular only */
1624 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
1625 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1626 of ADC channel ADCx_IN16, converted by group injected only */
1627 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
1628 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1629 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1630 of ADC channel ADCx_IN16, converted by either group regular or injected */
1631 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
1632 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1633 of ADC channel ADCx_IN17, converted by group regular only */
1634 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
1635 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1636 of ADC channel ADCx_IN17, converted by group injected only */
1637 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
1638 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1639 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1640 of ADC channel ADCx_IN17, converted by either group regular or injected */
1641 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
1642 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1643 of ADC channel ADCx_IN18, converted by group regular only */
1644 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
1645 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1646 of ADC channel ADCx_IN18, converted by group injected only */
1647 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
1648 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1649 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1650 of ADC channel ADCx_IN18, converted by either group
1651 regular or injected */
1652 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \
1653 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1654 of ADC internal channel connected to VrefInt: Internal
1655 voltage reference, converted by group regular only */
1656 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \
1657 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1658 of ADC internal channel connected to VrefInt: Internal
1659 voltage reference, converted by group injected only */
1660 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \
1661 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1662 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1663 of ADC internal channel connected to VrefInt: Internal
1664 voltage reference, converted by either group regular or injected */
1665 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \
1666 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1667 of ADC internal channel connected to internal temperature sensor,
1668 converted by group regular only */
1669 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \
1670 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1671 of ADC internal channel connected to internal temperature sensor,
1672 converted by group injected only */
1673 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \
1674 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1675 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1676 of ADC internal channel connected to internal temperature sensor,
1677 converted by either group regular or injected */
1678 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \
1679 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1680 of ADC internal channel connected to Vbat/3: Vbat
1681 voltage through a divider ladder of factor 1/3 to have channel voltage
1682 always below Vdda, converted by group regular only */
1683 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \
1684 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1685 of ADC internal channel connected to Vbat/3: Vbat
1686 voltage through a divider ladder of factor 1/3 to have channel voltage
1687 always below Vdda, converted by group injected only */
1688 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \
1689 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog
1690 of ADC internal channel connected to Vbat/3: Vbat
1691 voltage through a divider ladder of factor 1/3 to have channel voltage
1692 always below Vdda */
1693 #if defined(ADC1) && !defined(ADC2)
1694 #define LL_ADC_AWD_CH_DAC1CH1_REG ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) \
1695 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1696 of ADC internal channel connected to DAC1 channel 1,
1697 channel specific to ADC1, converted by group regular only */
1698 #define LL_ADC_AWD_CH_DAC1CH1_INJ ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) \
1699 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1700 of ADC internal channel connected to DAC1 channel 1,
1701 channel specific to ADC1, converted by group injected only */
1702 #define LL_ADC_AWD_CH_DAC1CH1_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) \
1703 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1704 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1705 of ADC internal channel connected to DAC1 channel 1,
1706 channel specific to ADC1, converted by either group regular or injected */
1707 #define LL_ADC_AWD_CH_DAC1CH2_REG ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) \
1708 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1709 of ADC internal channel connected to DAC1 channel 2,
1710 channel specific to ADC1, converted by group regular only */
1711 #define LL_ADC_AWD_CH_DAC1CH2_INJ ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) \
1712 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1713 of ADC internal channel connected to DAC1 channel 2,
1714 channel specific to ADC1, converted by group injected only */
1715 #define LL_ADC_AWD_CH_DAC1CH2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) \
1716 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1717 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1718 of ADC internal channel connected to DAC1 channel 2,
1719 channel specific to ADC1, converted by either group regular or injected */
1720 #elif defined(ADC2)
1721 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) \
1722 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1723 of ADC internal channel connected to DAC1 channel 1,
1724 channel specific to ADC2, converted by group regular only */
1725 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) \
1726 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1727 of ADC internal channel connected to DAC1 channel 1,
1728 channel specific to ADC2, converted by group injected only */
1729 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) \
1730 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1731 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1732 of ADC internal channel connected to DAC1 channel 1,
1733 channel specific to ADC2, converted by either group regular or injected */
1734 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) \
1735 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1736 of ADC internal channel connected to DAC1 channel 2,
1737 channel specific to ADC2, converted by group regular only */
1738 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) \
1739 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1740 of ADC internal channel connected to DAC1 channel 2,
1741 channel specific to ADC2, converted by group injected only */
1742 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) \
1743 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1744 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1745 of ADC internal channel connected to DAC1 channel 2,
1746 channel specific to ADC2, converted by either group regular or injected */
1747 #if defined(ADC3)
1748 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) \
1749 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1750 of ADC internal channel connected to DAC1 channel 1,
1751 channel specific to ADC3, converted by group regular only */
1752 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) \
1753 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1754 of ADC internal channel connected to DAC1 channel 1,
1755 channel specific to ADC3, converted by group injected only */
1756 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) \
1757 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1758 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1759 of ADC internal channel connected to DAC1 channel 1,
1760 channel specific to ADC3, converted by either group regular or injected */
1761 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) \
1762 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1763 of ADC internal channel connected to DAC1 channel 2,
1764 channel specific to ADC3, converted by group regular only */
1765 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) \
1766 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1767 of ADC internal channel connected to DAC1 channel 2,
1768 channel specific to ADC3, converted by group injected only */
1769 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) \
1770 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1771 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1772 of ADC internal channel connected to DAC1 channel 2,
1773 channel specific to ADC3, converted by either group regular or injected */
1774 #endif /* ADC3 */
1775 #endif /* ADC1 && !ADC2 */
1776 /**
1777 * @}
1778 */
1779
1780 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
1781 * @{
1782 */
1783 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1) /*!< ADC analog watchdog threshold high */
1784 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
1785 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 \
1786 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low
1787 concatenated into the same data */
1788 /**
1789 * @}
1790 */
1791
1792 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
1793 * @{
1794 */
1795 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
1796 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED (ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
1797 ADC group regular. If group injected interrupts group regular:
1798 when ADC group injected is triggered, the oversampling on ADC group regular
1799 is temporary stopped and continued afterwards. */
1800 #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
1801 ADC group regular. If group injected interrupts group regular:
1802 when ADC group injected is triggered, the oversampling on ADC group regular
1803 is resumed from start (oversampler buffer reset). */
1804 #define LL_ADC_OVS_GRP_INJECTED (ADC_CFGR2_JOVSE) /*!< ADC oversampling on conversions of
1805 ADC group injected. */
1806 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED (ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
1807 both ADC groups regular and injected. If group injected interrupting group
1808 regular: when ADC group injected is triggered, the oversampling on ADC group
1809 regular is resumed from start (oversampler buffer reset). */
1810 /**
1811 * @}
1812 */
1813
1814 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
1815 * @{
1816 */
1817 #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode
1818 (all conversions of oversampling ratio are done from 1 trigger) */
1819 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous
1820 mode (each conversion of oversampling ratio needs a trigger) */
1821 /**
1822 * @}
1823 */
1824
1825 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
1826 * @{
1827 */
1828 #define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2
1829 (sum of conversions data computed to result as oversampling conversion data
1830 (before potential shift) */
1831 #define LL_ADC_OVS_RATIO_4 (ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4
1832 (sum of conversions data computed to result as oversampling conversion data
1833 (before potential shift) */
1834 #define LL_ADC_OVS_RATIO_8 (ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 8
1835 (sum of conversions data computed to result as oversampling conversion data
1836 (before potential shift) */
1837 #define LL_ADC_OVS_RATIO_16 (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16
1838 (sum of conversions data computed to result as oversampling conversion data
1839 (before potential shift) */
1840 #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2) /*!< ADC oversampling ratio of 32
1841 (sum of conversions data computed to result as oversampling conversion data
1842 (before potential shift) */
1843 #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64
1844 (sum of conversions data computed to result as oversampling conversion data
1845 (before potential shift) */
1846 #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128
1847 (sum of conversions data computed to result as oversampling conversion data
1848 (before potential shift) */
1849 #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 \
1850 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256
1851 (sum of conversions data computed to result as oversampling conversion data
1852 (before potential shift) */
1853 /**
1854 * @}
1855 */
1856
1857 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data right shift
1858 * @{
1859 */
1860 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift
1861 (sum of the ADC conversions data is not divided to result as oversampling
1862 conversion data) */
1863 #define LL_ADC_OVS_SHIFT_RIGHT_1 (ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 1
1864 (sum of the ADC conversions data (after OVS ratio) is divided by 2
1865 to result as oversampling conversion data) */
1866 #define LL_ADC_OVS_SHIFT_RIGHT_2 (ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 2
1867 (sum of the ADC conversions data (after OVS ratio) is divided by 4
1868 to result as oversampling conversion data) */
1869 #define LL_ADC_OVS_SHIFT_RIGHT_3 (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3
1870 (sum of the ADC conversions data (after OVS ratio) is divided by 8
1871 to result as oversampling conversion data) */
1872 #define LL_ADC_OVS_SHIFT_RIGHT_4 (ADC_CFGR2_OVSS_2) /*!< ADC oversampling right shift of 4
1873 (sum of the ADC conversions data (after OVS ratio) is divided by 16
1874 to result as oversampling conversion data) */
1875 #define LL_ADC_OVS_SHIFT_RIGHT_5 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5
1876 (sum of the ADC conversions data (after OVS ratio) is divided by 32
1877 to result as oversampling conversion data) */
1878 #define LL_ADC_OVS_SHIFT_RIGHT_6 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6
1879 (sum of the ADC conversions data (after OVS ratio) is divided by 64
1880 to result as oversampling conversion data) */
1881 #define LL_ADC_OVS_SHIFT_RIGHT_7 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \
1882 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 7
1883 (sum of the ADC conversions data (after OVS ratio) is divided by 128
1884 to result as oversampling conversion data) */
1885 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3) /*!< ADC oversampling right shift of 8
1886 (sum of the ADC conversions data (after OVS ratio) is divided by 256
1887 to result as oversampling conversion data) */
1888 /**
1889 * @}
1890 */
1891
1892 #if defined(ADC_MULTIMODE_SUPPORT)
1893 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
1894 * @{
1895 */
1896 #define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC
1897 independent mode) */
1898 #define LL_ADC_MULTI_DUAL_REG_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: group regular
1899 simultaneous */
1900 #define LL_ADC_MULTI_DUAL_REG_INTERL (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 \
1901 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group
1902 regular interleaved */
1903 #define LL_ADC_MULTI_DUAL_INJ_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected
1904 simultaneous */
1905 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected
1906 alternate trigger. Works only with external triggers (not SW start) */
1907 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM (ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group
1908 regular simultaneous + group injected simultaneous */
1909 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT (ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: Combined group
1910 regular simultaneous + group injected alternate trigger */
1911 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM (ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group
1912 regular interleaved + group injected simultaneous */
1913 /**
1914 * @}
1915 */
1916
1917 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
1918 * @{
1919 */
1920 #define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular
1921 conversions are transferred by DMA: each ADC uses its own DMA channel,
1922 with its individual DMA transfer settings */
1923 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B (ADC_CCR_MDMA_1) /*!< ADC multimode group regular
1924 conversions are transferred by DMA, one DMA channel for both ADC(DMA of
1925 ADC master), in limited mode (one shot mode): DMA transfer requests
1926 are stopped when number of DMA data transfers (number of ADC conversions)
1927 is reached. This ADC mode is intended to be used with DMA mode
1928 non-circular. Setting for ADC resolution of 12 and 10 bits */
1929 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B (ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular
1930 conversions are transferred by DMA, one DMA channel for both ADC(DMA of
1931 ADC master), in limited mode (one shot mode): DMA transfer requests
1932 are stopped when number of DMA data transfers (number of ADC conversions)
1933 is reached. This ADC mode is intended to be used with DMA mode
1934 non-circular. Setting for ADC resolution of 8 and 6 bits */
1935 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1) /*!< ADC multimode group regular
1936 conversions are transferred by DMA, one DMA channel for both ADC(DMA of
1937 ADC master), in unlimited mode: DMA transfer requests are unlimited,
1938 whatever number of DMA data transferred (number of ADC conversions).
1939 This ADC mode is intended to be used with DMA mode circular.
1940 Setting for ADC resolution of 12 and 10 bits */
1941 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 \
1942 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular
1943 conversions are transferred by DMA, one DMA channel for both ADC (DMA of
1944 ADC master), in unlimited mode: DMA transfer requests are unlimited,
1945 whatever number of DMA data transferred (number of ADC conversions).
1946 This ADC mode is intended to be used with DMA mode circular.
1947 Setting for ADC resolution of 8 and 6 bits */
1948 /**
1949 * @}
1950 */
1951
1952 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
1953 * @{
1954 */
1955 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode delay between two
1956 sampling phases: 1 ADC clock cycle */
1957 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES (ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
1958 sampling phases: 2 ADC clock cycles */
1959 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES (ADC_CCR_DELAY_1) /*!< ADC multimode delay between two
1960 sampling phases: 3 ADC clock cycles */
1961 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES (ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
1962 sampling phases: 4 ADC clock cycles */
1963 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES (ADC_CCR_DELAY_2) /*!< ADC multimode delay between two
1964 sampling phases: 5 ADC clock cycles */
1965 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
1966 sampling phases: 6 ADC clock cycles */
1967 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1) /*!< ADC multimode delay between two
1968 sampling phases: 7 ADC clock cycles */
1969 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 \
1970 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
1971 sampling phases: 8 ADC clock cycles */
1972 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3) /*!< ADC multimode delay between two
1973 sampling phases: 9 ADC clock cycles */
1974 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
1975 sampling phases: 10 ADC clock cycles */
1976 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1) /*!< ADC multimode delay between two
1977 sampling phases: 11 ADC clock cycles */
1978 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 \
1979 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
1980 sampling phases: 12 ADC clock cycles */
1981 /**
1982 * @}
1983 */
1984
1985 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
1986 * @{
1987 */
1988 #define LL_ADC_MULTI_MASTER (ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC
1989 instances: ADC master */
1990 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV) /*!< In multimode, selection among several ADC
1991 instances: ADC slave */
1992 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV \
1993 | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC
1994 instances: both ADC master and ADC slave */
1995 /**
1996 * @}
1997 */
1998
1999 #endif /* ADC_MULTIMODE_SUPPORT */
2000
2001 /** @defgroup ADC_LL_EC_LEGACY ADC literals legacy naming
2002 * @{
2003 */
2004 #define LL_ADC_REG_TRIG_SW_START (LL_ADC_REG_TRIG_SOFTWARE)
2005 #define LL_ADC_REG_TRIG_EXT_TIM1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1)
2006 #define LL_ADC_REG_TRIG_EXT_TIM1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2)
2007 #define LL_ADC_REG_TRIG_EXT_TIM1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3)
2008 #define LL_ADC_REG_TRIG_EXT_TIM2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2)
2009 #define LL_ADC_REG_TRIG_EXT_TIM3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4)
2010 #define LL_ADC_REG_TRIG_EXT_TIM4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4)
2011
2012 #define LL_ADC_INJ_TRIG_SW_START (LL_ADC_INJ_TRIG_SOFTWARE)
2013 #define LL_ADC_INJ_TRIG_EXT_TIM1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)
2014 #define LL_ADC_INJ_TRIG_EXT_TIM2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)
2015 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)
2016 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)
2017 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)
2018 #define LL_ADC_INJ_TRIG_EXT_TIM8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)
2019
2020 #define LL_ADC_OVS_DATA_SHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)
2021 #define LL_ADC_OVS_DATA_SHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)
2022 #define LL_ADC_OVS_DATA_SHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)
2023 #define LL_ADC_OVS_DATA_SHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)
2024 #define LL_ADC_OVS_DATA_SHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)
2025 #define LL_ADC_OVS_DATA_SHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)
2026 #define LL_ADC_OVS_DATA_SHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)
2027 #define LL_ADC_OVS_DATA_SHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)
2028 #define LL_ADC_OVS_DATA_SHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)
2029
2030 /**
2031 * @}
2032 */
2033
2034 /** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper macro
2035 * @{
2036 */
2037 #define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro
2038 @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on
2039 calibration parameters. This value is coded on 16 bits
2040 (to fit on signed word or double word) and corresponds
2041 to an inconsistent temperature value. */
2042 /**
2043 * @}
2044 */
2045
2046 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
2047 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
2048 * not timeout values.
2049 * For details on delays values, refer to descriptions in source code
2050 * above each literal definition.
2051 * @{
2052 */
2053
2054 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
2055 /* not timeout values. */
2056 /* Timeout values for ADC operations are dependent to device clock */
2057 /* configuration (system clock versus ADC clock), */
2058 /* and therefore must be defined in user application. */
2059 /* Indications for estimation of ADC timeout delays, for this */
2060 /* STM32 series: */
2061 /* - ADC calibration time: maximum delay is 112/fADC. */
2062 /* (refer to device datasheet, parameter "tCAL") */
2063 /* - ADC enable time: maximum delay is 1 conversion cycle. */
2064 /* (refer to device datasheet, parameter "tSTAB") */
2065 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
2066 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
2067 /* cycles */
2068 /* - ADC conversion time: duration depending on ADC clock and ADC */
2069 /* configuration. */
2070 /* (refer to device reference manual, section "Timing") */
2071
2072 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
2073 /* Delay set to maximum value (refer to device datasheet, */
2074 /* parameter "tADCVREG_STUP"). */
2075 /* Unit: us */
2076 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage
2077 regulator start-up time) */
2078
2079 /* Delay for internal voltage reference stabilization time. */
2080 /* Delay set to maximum value (refer to device datasheet, */
2081 /* parameter "tstart_vrefint"). */
2082 /* Unit: us */
2083 #define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization
2084 time */
2085
2086 /* Delay for temperature sensor stabilization time. */
2087 /* Literal set to maximum value (refer to device datasheet, */
2088 /* parameter "tSTART"). */
2089 /* Unit: us */
2090 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */
2091 #define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization
2092 time (starting from ADC enable, refer to
2093 @ref LL_ADC_Enable()) */
2094
2095 /* Delay required between ADC end of calibration and ADC enable. */
2096 /* Note: On this STM32 series, a minimum number of ADC clock cycles */
2097 /* are required between ADC end of calibration and ADC enable. */
2098 /* Wait time can be computed in user application by waiting for the */
2099 /* equivalent number of CPU cycles, by taking into account */
2100 /* ratio of CPU clock versus ADC clock prescalers. */
2101 /* Unit: ADC clock cycles. */
2102 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration
2103 and ADC enable */
2104
2105 /**
2106 * @}
2107 */
2108
2109 /**
2110 * @}
2111 */
2112
2113
2114 /* Exported macro ------------------------------------------------------------*/
2115 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
2116 * @{
2117 */
2118
2119 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
2120 * @{
2121 */
2122
2123 /**
2124 * @brief Write a value in ADC register
2125 * @param __INSTANCE__ ADC Instance
2126 * @param __REG__ Register to be written
2127 * @param __VALUE__ Value to be written in the register
2128 * @retval None
2129 */
2130 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
2131
2132 /**
2133 * @brief Read a value in ADC register
2134 * @param __INSTANCE__ ADC Instance
2135 * @param __REG__ Register to be read
2136 * @retval Register value
2137 */
2138 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
2139 /**
2140 * @}
2141 */
2142
2143 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
2144 * @{
2145 */
2146
2147 /**
2148 * @brief Helper macro to get ADC channel number in decimal format
2149 * from literals LL_ADC_CHANNEL_x.
2150 * @note Example:
2151 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
2152 * will return decimal number "4".
2153 * @note The input can be a value from functions where a channel
2154 * number is returned, either defined with number
2155 * or with bitfield (only one bit must be set).
2156 * @param __CHANNEL__ This parameter can be one of the following values:
2157 * @arg @ref LL_ADC_CHANNEL_0
2158 * @arg @ref LL_ADC_CHANNEL_1 (7)
2159 * @arg @ref LL_ADC_CHANNEL_2 (7)
2160 * @arg @ref LL_ADC_CHANNEL_3 (7)
2161 * @arg @ref LL_ADC_CHANNEL_4 (7)
2162 * @arg @ref LL_ADC_CHANNEL_5 (7)
2163 * @arg @ref LL_ADC_CHANNEL_6
2164 * @arg @ref LL_ADC_CHANNEL_7
2165 * @arg @ref LL_ADC_CHANNEL_8
2166 * @arg @ref LL_ADC_CHANNEL_9
2167 * @arg @ref LL_ADC_CHANNEL_10
2168 * @arg @ref LL_ADC_CHANNEL_11
2169 * @arg @ref LL_ADC_CHANNEL_12
2170 * @arg @ref LL_ADC_CHANNEL_13
2171 * @arg @ref LL_ADC_CHANNEL_14
2172 * @arg @ref LL_ADC_CHANNEL_15
2173 * @arg @ref LL_ADC_CHANNEL_16
2174 * @arg @ref LL_ADC_CHANNEL_17
2175 * @arg @ref LL_ADC_CHANNEL_18
2176 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2177 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
2178 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
2179 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
2180 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
2181 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
2182 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
2183 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
2184 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
2185 *
2186 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
2187 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
2188 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
2189 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
2190 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
2191 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
2192 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
2193 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
2194 * @retval Value between Min_Data=0 and Max_Data=18
2195 */
2196 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
2197 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \
2198 ( \
2199 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
2200 ) \
2201 : \
2202 ( \
2203 (uint32_t)POSITION_VAL((__CHANNEL__)) \
2204 ) \
2205 )
2206
2207 /**
2208 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
2209 * from number in decimal format.
2210 * @note Example:
2211 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
2212 * will return a data equivalent to "LL_ADC_CHANNEL_4".
2213 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
2214 * @retval Returned value can be one of the following values:
2215 * @arg @ref LL_ADC_CHANNEL_0
2216 * @arg @ref LL_ADC_CHANNEL_1 (7)
2217 * @arg @ref LL_ADC_CHANNEL_2 (7)
2218 * @arg @ref LL_ADC_CHANNEL_3 (7)
2219 * @arg @ref LL_ADC_CHANNEL_4 (7)
2220 * @arg @ref LL_ADC_CHANNEL_5 (7)
2221 * @arg @ref LL_ADC_CHANNEL_6
2222 * @arg @ref LL_ADC_CHANNEL_7
2223 * @arg @ref LL_ADC_CHANNEL_8
2224 * @arg @ref LL_ADC_CHANNEL_9
2225 * @arg @ref LL_ADC_CHANNEL_10
2226 * @arg @ref LL_ADC_CHANNEL_11
2227 * @arg @ref LL_ADC_CHANNEL_12
2228 * @arg @ref LL_ADC_CHANNEL_13
2229 * @arg @ref LL_ADC_CHANNEL_14
2230 * @arg @ref LL_ADC_CHANNEL_15
2231 * @arg @ref LL_ADC_CHANNEL_16
2232 * @arg @ref LL_ADC_CHANNEL_17
2233 * @arg @ref LL_ADC_CHANNEL_18
2234 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2235 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
2236 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
2237 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
2238 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
2239 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
2240 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
2241 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
2242 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
2243 *
2244 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
2245 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
2246 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
2247 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
2248 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
2249 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
2250 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
2251 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to
2252 * 4.21 Ms/s)).\n
2253 * (1, 2, 3, 4) For ADC channel read back from ADC register,
2254 * comparison with internal channel parameter to be done
2255 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2256 */
2257 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
2258 (((__DECIMAL_NB__) <= 9UL) ? \
2259 ( \
2260 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
2261 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
2262 (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
2263 ) \
2264 : \
2265 ( \
2266 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
2267 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
2268 (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
2269 ) \
2270 )
2271
2272 /**
2273 * @brief Helper macro to determine whether the selected channel
2274 * corresponds to literal definitions of driver.
2275 * @note The different literal definitions of ADC channels are:
2276 * - ADC internal channel:
2277 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
2278 * - ADC external channel (channel connected to a GPIO pin):
2279 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
2280 * @note The channel parameter must be a value defined from literal
2281 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
2282 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
2283 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
2284 * must not be a value from functions where a channel number is
2285 * returned from ADC registers,
2286 * because internal and external channels share the same channel
2287 * number in ADC registers. The differentiation is made only with
2288 * parameters definitions of driver.
2289 * @param __CHANNEL__ This parameter can be one of the following values:
2290 * @arg @ref LL_ADC_CHANNEL_0
2291 * @arg @ref LL_ADC_CHANNEL_1 (7)
2292 * @arg @ref LL_ADC_CHANNEL_2 (7)
2293 * @arg @ref LL_ADC_CHANNEL_3 (7)
2294 * @arg @ref LL_ADC_CHANNEL_4 (7)
2295 * @arg @ref LL_ADC_CHANNEL_5 (7)
2296 * @arg @ref LL_ADC_CHANNEL_6
2297 * @arg @ref LL_ADC_CHANNEL_7
2298 * @arg @ref LL_ADC_CHANNEL_8
2299 * @arg @ref LL_ADC_CHANNEL_9
2300 * @arg @ref LL_ADC_CHANNEL_10
2301 * @arg @ref LL_ADC_CHANNEL_11
2302 * @arg @ref LL_ADC_CHANNEL_12
2303 * @arg @ref LL_ADC_CHANNEL_13
2304 * @arg @ref LL_ADC_CHANNEL_14
2305 * @arg @ref LL_ADC_CHANNEL_15
2306 * @arg @ref LL_ADC_CHANNEL_16
2307 * @arg @ref LL_ADC_CHANNEL_17
2308 * @arg @ref LL_ADC_CHANNEL_18
2309 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2310 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
2311 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
2312 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
2313 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
2314 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
2315 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
2316 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
2317 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
2318 *
2319 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
2320 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
2321 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
2322 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
2323 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
2324 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
2325 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
2326 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
2327 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel
2328 connected to a GPIO pin).
2329 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
2330 */
2331 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
2332 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
2333
2334 /**
2335 * @brief Helper macro to convert a channel defined from parameter
2336 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
2337 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
2338 * to its equivalent parameter definition of a ADC external channel
2339 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
2340 * @note The channel parameter can be, additionally to a value
2341 * defined from parameter definition of a ADC internal channel
2342 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
2343 * a value defined from parameter definition of
2344 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
2345 * or a value from functions where a channel number is returned
2346 * from ADC registers.
2347 * @param __CHANNEL__ This parameter can be one of the following values:
2348 * @arg @ref LL_ADC_CHANNEL_0
2349 * @arg @ref LL_ADC_CHANNEL_1 (7)
2350 * @arg @ref LL_ADC_CHANNEL_2 (7)
2351 * @arg @ref LL_ADC_CHANNEL_3 (7)
2352 * @arg @ref LL_ADC_CHANNEL_4 (7)
2353 * @arg @ref LL_ADC_CHANNEL_5 (7)
2354 * @arg @ref LL_ADC_CHANNEL_6
2355 * @arg @ref LL_ADC_CHANNEL_7
2356 * @arg @ref LL_ADC_CHANNEL_8
2357 * @arg @ref LL_ADC_CHANNEL_9
2358 * @arg @ref LL_ADC_CHANNEL_10
2359 * @arg @ref LL_ADC_CHANNEL_11
2360 * @arg @ref LL_ADC_CHANNEL_12
2361 * @arg @ref LL_ADC_CHANNEL_13
2362 * @arg @ref LL_ADC_CHANNEL_14
2363 * @arg @ref LL_ADC_CHANNEL_15
2364 * @arg @ref LL_ADC_CHANNEL_16
2365 * @arg @ref LL_ADC_CHANNEL_17
2366 * @arg @ref LL_ADC_CHANNEL_18
2367 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2368 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
2369 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
2370 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
2371 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
2372 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
2373 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
2374 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
2375 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
2376 *
2377 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
2378 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
2379 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
2380 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
2381 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
2382 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
2383 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
2384 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
2385 * @retval Returned value can be one of the following values:
2386 * @arg @ref LL_ADC_CHANNEL_0
2387 * @arg @ref LL_ADC_CHANNEL_1
2388 * @arg @ref LL_ADC_CHANNEL_2
2389 * @arg @ref LL_ADC_CHANNEL_3
2390 * @arg @ref LL_ADC_CHANNEL_4
2391 * @arg @ref LL_ADC_CHANNEL_5
2392 * @arg @ref LL_ADC_CHANNEL_6
2393 * @arg @ref LL_ADC_CHANNEL_7
2394 * @arg @ref LL_ADC_CHANNEL_8
2395 * @arg @ref LL_ADC_CHANNEL_9
2396 * @arg @ref LL_ADC_CHANNEL_10
2397 * @arg @ref LL_ADC_CHANNEL_11
2398 * @arg @ref LL_ADC_CHANNEL_12
2399 * @arg @ref LL_ADC_CHANNEL_13
2400 * @arg @ref LL_ADC_CHANNEL_14
2401 * @arg @ref LL_ADC_CHANNEL_15
2402 * @arg @ref LL_ADC_CHANNEL_16
2403 * @arg @ref LL_ADC_CHANNEL_17
2404 * @arg @ref LL_ADC_CHANNEL_18
2405 */
2406 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
2407 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
2408
2409 /**
2410 * @brief Helper macro to determine whether the internal channel
2411 * selected is available on the ADC instance selected.
2412 * @note The channel parameter must be a value defined from parameter
2413 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
2414 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
2415 * must not be a value defined from parameter definition of
2416 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
2417 * or a value from functions where a channel number is
2418 * returned from ADC registers,
2419 * because internal and external channels share the same channel
2420 * number in ADC registers. The differentiation is made only with
2421 * parameters definitions of driver.
2422 * @param __ADC_INSTANCE__ ADC instance
2423 * @param __CHANNEL__ This parameter can be one of the following values:
2424 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2425 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
2426 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
2427 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
2428 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
2429 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
2430 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
2431 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
2432 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
2433 *
2434 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
2435 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
2436 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
2437 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
2438 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
2439 * (6) On STM32L4, parameter available on devices with several ADC instances.
2440 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
2441 * Value "1" if the internal channel selected is available on the ADC instance selected.
2442 */
2443 #if defined (ADC1) && defined (ADC2) && defined (ADC3)
2444 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
2445 (((__ADC_INSTANCE__) == ADC1) ? \
2446 ( \
2447 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
2448 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
2449 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
2450 ) \
2451 : \
2452 ((__ADC_INSTANCE__) == ADC2) ? \
2453 ( \
2454 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
2455 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \
2456 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \
2457 ) \
2458 : \
2459 ((__ADC_INSTANCE__) == ADC3) ? \
2460 ( \
2461 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
2462 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
2463 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
2464 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC3) || \
2465 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC3) \
2466 ) \
2467 : \
2468 (0UL) \
2469 )
2470 #elif defined (ADC1) && defined (ADC2)
2471 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
2472 (((__ADC_INSTANCE__) == ADC1) ? \
2473 ( \
2474 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
2475 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
2476 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
2477 ) \
2478 : \
2479 ((__ADC_INSTANCE__) == ADC2) ? \
2480 ( \
2481 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
2482 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \
2483 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \
2484 ) \
2485 : \
2486 (0UL) \
2487 )
2488 #elif defined (ADC1)
2489 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
2490 ( \
2491 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
2492 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
2493 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
2494 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1) || \
2495 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2) \
2496 )
2497 #endif /* defined (ADC1) && defined (ADC2) && defined (ADC3) */
2498
2499 /**
2500 * @brief Helper macro to define ADC analog watchdog parameter:
2501 * define a single channel to monitor with analog watchdog
2502 * from sequencer channel and groups definition.
2503 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
2504 * Example:
2505 * LL_ADC_SetAnalogWDMonitChannels(
2506 * ADC1, LL_ADC_AWD1,
2507 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
2508 * @param __CHANNEL__ This parameter can be one of the following values:
2509 * @arg @ref LL_ADC_CHANNEL_0
2510 * @arg @ref LL_ADC_CHANNEL_1 (7)
2511 * @arg @ref LL_ADC_CHANNEL_2 (7)
2512 * @arg @ref LL_ADC_CHANNEL_3 (7)
2513 * @arg @ref LL_ADC_CHANNEL_4 (7)
2514 * @arg @ref LL_ADC_CHANNEL_5 (7)
2515 * @arg @ref LL_ADC_CHANNEL_6
2516 * @arg @ref LL_ADC_CHANNEL_7
2517 * @arg @ref LL_ADC_CHANNEL_8
2518 * @arg @ref LL_ADC_CHANNEL_9
2519 * @arg @ref LL_ADC_CHANNEL_10
2520 * @arg @ref LL_ADC_CHANNEL_11
2521 * @arg @ref LL_ADC_CHANNEL_12
2522 * @arg @ref LL_ADC_CHANNEL_13
2523 * @arg @ref LL_ADC_CHANNEL_14
2524 * @arg @ref LL_ADC_CHANNEL_15
2525 * @arg @ref LL_ADC_CHANNEL_16
2526 * @arg @ref LL_ADC_CHANNEL_17
2527 * @arg @ref LL_ADC_CHANNEL_18
2528 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2529 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
2530 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
2531 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
2532 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
2533 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
2534 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
2535 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
2536 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
2537 *
2538 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
2539 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
2540 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
2541 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
2542 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
2543 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
2544 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
2545 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to
2546 * 4.21 Ms/s)).\n
2547 * (1, 2, 3, 4) For ADC channel read back from ADC register,
2548 * comparison with internal channel parameter to be done
2549 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2550 * @param __GROUP__ This parameter can be one of the following values:
2551 * @arg @ref LL_ADC_GROUP_REGULAR
2552 * @arg @ref LL_ADC_GROUP_INJECTED
2553 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
2554 * @retval Returned value can be one of the following values:
2555 * @arg @ref LL_ADC_AWD_DISABLE
2556 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
2557 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
2558 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
2559 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
2560 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
2561 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
2562 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
2563 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
2564 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
2565 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
2566 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
2567 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
2568 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
2569 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
2570 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
2571 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
2572 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
2573 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
2574 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
2575 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
2576 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
2577 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
2578 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
2579 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
2580 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
2581 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
2582 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
2583 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
2584 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
2585 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
2586 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
2587 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
2588 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
2589 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
2590 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
2591 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
2592 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
2593 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
2594 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
2595 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
2596 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
2597 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
2598 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
2599 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
2600 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
2601 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
2602 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
2603 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
2604 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
2605 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
2606 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
2607 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
2608 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
2609 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
2610 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
2611 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
2612 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
2613 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
2614 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
2615 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
2616 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
2617 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
2618 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
2619 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(4)
2620 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(4)
2621 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (4)
2622 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(4)
2623 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(4)
2624 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (4)
2625 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG (0)(2)(5)
2626 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_INJ (0)(2)(5)
2627 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG_INJ (2)(5)
2628 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG (0)(2)(5)
2629 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_INJ (0)(2)(5)
2630 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG_INJ (2)(5)
2631 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)(6)
2632 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)(6)
2633 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)(6)
2634 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)(6)
2635 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)(6)
2636 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)(6)
2637 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG (0)(3)(6)
2638 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ (0)(3)(6)
2639 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ (3)(6)
2640 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG (0)(3)(6)
2641 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ (0)(3)(6)
2642 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ (3)(6)
2643 *
2644 * (0) On STM32L4, parameter available only on analog watchdog number: AWD1.\n
2645 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
2646 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
2647 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
2648 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
2649 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
2650 * (6) On STM32L4, parameter available on devices with several ADC instances.
2651 */
2652 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
2653 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
2654 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2655 : \
2656 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
2657 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
2658 : \
2659 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2660 )
2661
2662 /**
2663 * @brief Helper macro to set the value of ADC analog watchdog threshold high
2664 * or low in function of ADC resolution, when ADC resolution is
2665 * different of 12 bits.
2666 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
2667 * or @ref LL_ADC_SetAnalogWDThresholds().
2668 * Example, with a ADC resolution of 8 bits, to set the value of
2669 * analog watchdog threshold high (on 8 bits):
2670 * LL_ADC_SetAnalogWDThresholds
2671 * (< ADCx param >,
2672 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
2673 * );
2674 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2675 * @arg @ref LL_ADC_RESOLUTION_12B
2676 * @arg @ref LL_ADC_RESOLUTION_10B
2677 * @arg @ref LL_ADC_RESOLUTION_8B
2678 * @arg @ref LL_ADC_RESOLUTION_6B
2679 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
2680 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2681 */
2682 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
2683 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2684
2685 /**
2686 * @brief Helper macro to get the value of ADC analog watchdog threshold high
2687 * or low in function of ADC resolution, when ADC resolution is
2688 * different of 12 bits.
2689 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2690 * Example, with a ADC resolution of 8 bits, to get the value of
2691 * analog watchdog threshold high (on 8 bits):
2692 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
2693 * (LL_ADC_RESOLUTION_8B,
2694 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
2695 * );
2696 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2697 * @arg @ref LL_ADC_RESOLUTION_12B
2698 * @arg @ref LL_ADC_RESOLUTION_10B
2699 * @arg @ref LL_ADC_RESOLUTION_8B
2700 * @arg @ref LL_ADC_RESOLUTION_6B
2701 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
2702 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2703 */
2704 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
2705 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2706
2707 /**
2708 * @brief Helper macro to get the ADC analog watchdog threshold high
2709 * or low from raw value containing both thresholds concatenated.
2710 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2711 * Example, to get analog watchdog threshold high from the register raw value:
2712 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
2713 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
2714 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
2715 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
2716 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2717 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2718 */
2719 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
2720 (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \
2721 & LL_ADC_AWD_THRESHOLD_LOW)
2722
2723 /**
2724 * @brief Helper macro to set the ADC calibration value with both single ended
2725 * and differential modes calibration factors concatenated.
2726 * @note To be used with function @ref LL_ADC_SetCalibrationFactor().
2727 * Example, to set calibration factors single ended to 0x55
2728 * and differential ended to 0x2A:
2729 * LL_ADC_SetCalibrationFactor(
2730 * ADC1,
2731 * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
2732 * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
2733 * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
2734 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2735 */
2736 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
2737 (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
2738
2739 #if defined(ADC_MULTIMODE_SUPPORT)
2740 /**
2741 * @brief Helper macro to get the ADC multimode conversion data of ADC master
2742 * or ADC slave from raw value with both ADC conversion data concatenated.
2743 * @note This macro is intended to be used when multimode transfer by DMA
2744 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
2745 * In this case the transferred data need to processed with this macro
2746 * to separate the conversion data of ADC master and ADC slave.
2747 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
2748 * @arg @ref LL_ADC_MULTI_MASTER
2749 * @arg @ref LL_ADC_MULTI_SLAVE
2750 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
2751 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2752 */
2753 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
2754 (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
2755 #endif /* ADC_MULTIMODE_SUPPORT */
2756
2757 #if defined(ADC_MULTIMODE_SUPPORT)
2758 /**
2759 * @brief Helper macro to select, from a ADC instance, to which ADC instance
2760 * it has a dependence in multimode (ADC master of the corresponding
2761 * ADC common instance).
2762 * @note In case of device with multimode available and a mix of
2763 * ADC instances compliant and not compliant with multimode feature,
2764 * ADC instances not compliant with multimode feature are
2765 * considered as master instances (do not depend to
2766 * any other ADC instance).
2767 * @param __ADCx__ ADC instance
2768 * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
2769 */
2770 #if defined(ADC2)
2771 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2772 ((((__ADCx__) == ADC2))? \
2773 (ADC1) \
2774 : \
2775 (__ADCx__) \
2776 )
2777 #else
2778 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2779 (__ADCx__)
2780 #endif /* ADC2 */
2781 #endif /* ADC_MULTIMODE_SUPPORT */
2782
2783 /**
2784 * @brief Helper macro to select the ADC common instance
2785 * to which is belonging the selected ADC instance.
2786 * @note ADC common register instance can be used for:
2787 * - Set parameters common to several ADC instances
2788 * - Multimode (for devices with several ADC instances)
2789 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2790 * @param __ADCx__ ADC instance
2791 * @retval ADC common register instance
2792 */
2793 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
2794 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2795 (ADC123_COMMON)
2796 #elif defined(ADC1) && defined(ADC2)
2797 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2798 (ADC12_COMMON)
2799 #else
2800 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2801 (ADC1_COMMON)
2802 #endif /* defined(ADC1) && defined(ADC2) && defined(ADC3) */
2803
2804 /**
2805 * @brief Helper macro to check if all ADC instances sharing the same
2806 * ADC common instance are disabled.
2807 * @note This check is required by functions with setting conditioned to
2808 * ADC state:
2809 * All ADC instances of the ADC common group must be disabled.
2810 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2811 * @note On devices with only 1 ADC common instance, parameter of this macro
2812 * is useless and can be ignored (parameter kept for compatibility
2813 * with devices featuring several ADC common instances).
2814 * @param __ADCXY_COMMON__ ADC common instance
2815 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2816 * @retval Value "0" if all ADC instances sharing the same ADC common instance
2817 * are disabled.
2818 * Value "1" if at least one ADC instance sharing the same ADC common instance
2819 * is enabled.
2820 */
2821 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
2822 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2823 (LL_ADC_IsEnabled(ADC1) | \
2824 LL_ADC_IsEnabled(ADC2) | \
2825 LL_ADC_IsEnabled(ADC3) )
2826 #elif defined(ADC1) && defined(ADC2)
2827 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2828 (LL_ADC_IsEnabled(ADC1) | \
2829 LL_ADC_IsEnabled(ADC2) )
2830 #else
2831 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2832 (LL_ADC_IsEnabled(ADC1))
2833 #endif /* defined(ADC1) && defined(ADC2) && defined(ADC3) */
2834
2835 /**
2836 * @brief Helper macro to define the ADC conversion data full-scale digital
2837 * value corresponding to the selected ADC resolution.
2838 * @note ADC conversion data full-scale corresponds to voltage range
2839 * determined by analog voltage references Vref+ and Vref-
2840 * (refer to reference manual).
2841 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2842 * @arg @ref LL_ADC_RESOLUTION_12B
2843 * @arg @ref LL_ADC_RESOLUTION_10B
2844 * @arg @ref LL_ADC_RESOLUTION_8B
2845 * @arg @ref LL_ADC_RESOLUTION_6B
2846 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
2847 */
2848 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2849 (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
2850
2851 /**
2852 * @brief Helper macro to convert the ADC conversion data from
2853 * a resolution to another resolution.
2854 * @param __DATA__ ADC conversion data to be converted
2855 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
2856 * This parameter can be one of the following values:
2857 * @arg @ref LL_ADC_RESOLUTION_12B
2858 * @arg @ref LL_ADC_RESOLUTION_10B
2859 * @arg @ref LL_ADC_RESOLUTION_8B
2860 * @arg @ref LL_ADC_RESOLUTION_6B
2861 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
2862 * This parameter can be one of the following values:
2863 * @arg @ref LL_ADC_RESOLUTION_12B
2864 * @arg @ref LL_ADC_RESOLUTION_10B
2865 * @arg @ref LL_ADC_RESOLUTION_8B
2866 * @arg @ref LL_ADC_RESOLUTION_6B
2867 * @retval ADC conversion data to the requested resolution
2868 */
2869 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
2870 __ADC_RESOLUTION_CURRENT__,\
2871 __ADC_RESOLUTION_TARGET__) \
2872 (((__DATA__) \
2873 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2874 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2875 )
2876
2877 /**
2878 * @brief Helper macro to calculate the voltage (unit: mVolt)
2879 * corresponding to a ADC conversion data (unit: digital value).
2880 * @note Analog reference voltage (Vref+) must be either known from
2881 * user board environment or can be calculated using ADC measurement
2882 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2883 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2884 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
2885 * (unit: digital value).
2886 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2887 * @arg @ref LL_ADC_RESOLUTION_12B
2888 * @arg @ref LL_ADC_RESOLUTION_10B
2889 * @arg @ref LL_ADC_RESOLUTION_8B
2890 * @arg @ref LL_ADC_RESOLUTION_6B
2891 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2892 */
2893 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
2894 __ADC_DATA__,\
2895 __ADC_RESOLUTION__) \
2896 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
2897 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2898 )
2899
2900 /* Legacy define */
2901 #define __LL_ADC_CALC_DATA_VOLTAGE() __LL_ADC_CALC_DATA_TO_VOLTAGE()
2902
2903 /**
2904 * @brief Helper macro to calculate analog reference voltage (Vref+)
2905 * (unit: mVolt) from ADC conversion data of internal voltage
2906 * reference VrefInt.
2907 * @note Computation is using VrefInt calibration value
2908 * stored in system memory for each device during production.
2909 * @note This voltage depends on user board environment: voltage level
2910 * connected to pin Vref+.
2911 * On devices with small package, the pin Vref+ is not present
2912 * and internally bonded to pin Vdda.
2913 * @note On this STM32 series, calibration data of internal voltage reference
2914 * VrefInt corresponds to a resolution of 12 bits,
2915 * this is the recommended ADC resolution to convert voltage of
2916 * internal voltage reference VrefInt.
2917 * Otherwise, this macro performs the processing to scale
2918 * ADC conversion data to 12 bits.
2919 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
2920 * of internal voltage reference VrefInt (unit: digital value).
2921 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2922 * @arg @ref LL_ADC_RESOLUTION_12B
2923 * @arg @ref LL_ADC_RESOLUTION_10B
2924 * @arg @ref LL_ADC_RESOLUTION_8B
2925 * @arg @ref LL_ADC_RESOLUTION_6B
2926 * @retval Analog reference voltage (unit: mV)
2927 */
2928 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
2929 __ADC_RESOLUTION__) \
2930 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
2931 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
2932 (__ADC_RESOLUTION__), \
2933 LL_ADC_RESOLUTION_12B) \
2934 )
2935
2936 /**
2937 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2938 * from ADC conversion data of internal temperature sensor.
2939 * @note Computation is using temperature sensor calibration values
2940 * stored in system memory for each device during production.
2941 * @note Calculation formula:
2942 * Temperature = ((TS_ADC_DATA - TS_CAL1)
2943 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
2944 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
2945 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2946 * Avg_Slope = (TS_CAL2 - TS_CAL1)
2947 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
2948 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
2949 * TEMP_DEGC_CAL1 (calibrated in factory)
2950 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
2951 * TEMP_DEGC_CAL2 (calibrated in factory)
2952 * Caution: Calculation relevancy under reserve that calibration
2953 * parameters are correct (address and data).
2954 * To calculate temperature using temperature sensor
2955 * datasheet typical values (generic values less, therefore
2956 * less accurate than calibrated values),
2957 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
2958 * @note As calculation input, the analog reference voltage (Vref+) must be
2959 * defined as it impacts the ADC LSB equivalent voltage.
2960 * @note Analog reference voltage (Vref+) must be either known from
2961 * user board environment or can be calculated using ADC measurement
2962 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2963 * @note On this STM32 series, calibration data of temperature sensor
2964 * corresponds to a resolution of 12 bits,
2965 * this is the recommended ADC resolution to convert voltage of
2966 * temperature sensor.
2967 * Otherwise, this macro performs the processing to scale
2968 * ADC conversion data to 12 bits.
2969 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2970 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
2971 * temperature sensor (unit: digital value).
2972 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
2973 * sensor voltage has been measured.
2974 * This parameter can be one of the following values:
2975 * @arg @ref LL_ADC_RESOLUTION_12B
2976 * @arg @ref LL_ADC_RESOLUTION_10B
2977 * @arg @ref LL_ADC_RESOLUTION_8B
2978 * @arg @ref LL_ADC_RESOLUTION_6B
2979 * @retval Temperature (unit: degree Celsius)
2980 * In case or error, value LL_ADC_TEMPERATURE_CALC_ERROR is returned (inconsistent temperature value)
2981 */
2982 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
2983 __TEMPSENSOR_ADC_DATA__,\
2984 __ADC_RESOLUTION__)\
2985 ((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ? \
2986 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
2987 (__ADC_RESOLUTION__), \
2988 LL_ADC_RESOLUTION_12B) \
2989 * (__VREFANALOG_VOLTAGE__)) \
2990 / TEMPSENSOR_CAL_VREFANALOG) \
2991 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
2992 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
2993 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
2994 ) + TEMPSENSOR_CAL1_TEMP \
2995 ) \
2996 : \
2997 ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR) \
2998 )
2999
3000 /**
3001 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
3002 * from ADC conversion data of internal temperature sensor.
3003 * @note Computation is using temperature sensor typical values
3004 * (refer to device datasheet).
3005 * @note Calculation formula:
3006 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
3007 * / Avg_Slope + CALx_TEMP
3008 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
3009 * (unit: digital value)
3010 * Avg_Slope = temperature sensor slope
3011 * (unit: uV/Degree Celsius)
3012 * TS_TYP_CALx_VOLT = temperature sensor digital value at
3013 * temperature CALx_TEMP (unit: mV)
3014 * Caution: Calculation relevancy under reserve the temperature sensor
3015 * of the current device has characteristics in line with
3016 * datasheet typical values.
3017 * If temperature sensor calibration values are available on
3018 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
3019 * temperature calculation will be more accurate using
3020 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
3021 * @note As calculation input, the analog reference voltage (Vref+) must be
3022 * defined as it impacts the ADC LSB equivalent voltage.
3023 * @note Analog reference voltage (Vref+) must be either known from
3024 * user board environment or can be calculated using ADC measurement
3025 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
3026 * @note ADC measurement data must correspond to a resolution of 12 bits
3027 * (full scale digital value 4095). If not the case, the data must be
3028 * preliminarily rescaled to an equivalent resolution of 12 bits.
3029 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
3030 * (unit: uV/DegCelsius).
3031 * On STM32L4, refer to device datasheet parameter "Avg_Slope".
3032 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value
3033 * (at temperature and Vref+ defined in parameters below) (unit: mV).
3034 * On STM32L4, refer to datasheet parameter "V30" (corresponding to TS_CAL1).
3035 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage
3036 * (see parameter above) is corresponding (unit: mV)
3037 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value (unit: mV)
3038 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
3039 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
3040 * This parameter can be one of the following values:
3041 * @arg @ref LL_ADC_RESOLUTION_12B
3042 * @arg @ref LL_ADC_RESOLUTION_10B
3043 * @arg @ref LL_ADC_RESOLUTION_8B
3044 * @arg @ref LL_ADC_RESOLUTION_6B
3045 * @retval Temperature (unit: degree Celsius)
3046 */
3047 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
3048 __TEMPSENSOR_TYP_CALX_V__,\
3049 __TEMPSENSOR_CALX_TEMP__,\
3050 __VREFANALOG_VOLTAGE__,\
3051 __TEMPSENSOR_ADC_DATA__,\
3052 __ADC_RESOLUTION__) \
3053 (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
3054 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
3055 * 1000UL) \
3056 - \
3057 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
3058 * 1000UL) \
3059 ) \
3060 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
3061 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
3062 )
3063
3064 /**
3065 * @}
3066 */
3067
3068 /**
3069 * @}
3070 */
3071
3072
3073 /* Exported functions --------------------------------------------------------*/
3074 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
3075 * @{
3076 */
3077
3078 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
3079 * @{
3080 */
3081 /* Note: LL ADC functions to set DMA transfer are located into sections of */
3082 /* configuration of ADC instance, groups and multimode (if available): */
3083 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
3084
3085 /**
3086 * @brief Function to help to configure DMA transfer from ADC: retrieve the
3087 * ADC register address from ADC instance and a list of ADC registers
3088 * intended to be used (most commonly) with DMA transfer.
3089 * @note These ADC registers are data registers:
3090 * when ADC conversion data is available in ADC data registers,
3091 * ADC generates a DMA transfer request.
3092 * @note This macro is intended to be used with LL DMA driver, refer to
3093 * function "LL_DMA_ConfigAddresses()".
3094 * Example:
3095 * LL_DMA_ConfigAddresses(DMA1,
3096 * LL_DMA_CHANNEL_1,
3097 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
3098 * (uint32_t)&< array or variable >,
3099 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
3100 * @note For devices with several ADC: in multimode, some devices
3101 * use a different data register outside of ADC instance scope
3102 * (common data register). This macro manages this register difference,
3103 * only ADC instance has to be set as parameter.
3104 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
3105 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
3106 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
3107 * @param ADCx ADC instance
3108 * @param Register This parameter can be one of the following values:
3109 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
3110 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
3111 *
3112 * (1) Available on devices with several ADC instances.
3113 * @retval ADC register address
3114 */
3115 #if defined(ADC_MULTIMODE_SUPPORT)
LL_ADC_DMA_GetRegAddr(const ADC_TypeDef * ADCx,uint32_t Register)3116 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
3117 {
3118 uint32_t data_reg_addr;
3119
3120 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
3121 {
3122 /* Retrieve address of register DR */
3123 data_reg_addr = (uint32_t) &(ADCx->DR);
3124 }
3125 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
3126 {
3127 /* Retrieve address of register CDR */
3128 data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
3129 }
3130
3131 return data_reg_addr;
3132 }
3133 #else
LL_ADC_DMA_GetRegAddr(const ADC_TypeDef * ADCx,uint32_t Register)3134 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
3135 {
3136 /* Prevent unused argument(s) compilation warning */
3137 (void)(Register);
3138
3139 /* Retrieve address of register DR */
3140 return (uint32_t) &(ADCx->DR);
3141 }
3142 #endif /* ADC_MULTIMODE_SUPPORT */
3143
3144 /**
3145 * @}
3146 */
3147
3148 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several
3149 * ADC instances
3150 * @{
3151 */
3152
3153 /**
3154 * @brief Set parameter common to several ADC: Clock source and prescaler.
3155 * @note On this STM32 series, if ADC group injected is used, some
3156 * clock ratio constraints between ADC clock and AHB clock
3157 * must be respected.
3158 * Refer to reference manual.
3159 * @note On this STM32 series, setting of this feature is conditioned to
3160 * ADC state:
3161 * All ADC instances of the ADC common group must be disabled.
3162 * This check can be done with function @ref LL_ADC_IsEnabled() for each
3163 * ADC instance or by using helper macro helper macro
3164 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
3165 * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
3166 * CCR PRESC LL_ADC_SetCommonClock
3167 * @param ADCxy_COMMON ADC common instance
3168 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3169 * @param CommonClock This parameter can be one of the following values:
3170 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
3171 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
3172 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
3173 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
3174 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
3175 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
3176 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
3177 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
3178 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
3179 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
3180 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
3181 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
3182 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
3183 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
3184 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
3185 * @retval None
3186 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)3187 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
3188 {
3189 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
3190 }
3191
3192 /**
3193 * @brief Get parameter common to several ADC: Clock source and prescaler.
3194 * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
3195 * CCR PRESC LL_ADC_GetCommonClock
3196 * @param ADCxy_COMMON ADC common instance
3197 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3198 * @retval Returned value can be one of the following values:
3199 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
3200 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
3201 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
3202 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
3203 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
3204 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
3205 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
3206 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
3207 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
3208 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
3209 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
3210 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
3211 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
3212 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
3213 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
3214 */
LL_ADC_GetCommonClock(const ADC_Common_TypeDef * ADCxy_COMMON)3215 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON)
3216 {
3217 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
3218 }
3219
3220 /**
3221 * @brief Set parameter common to several ADC: measurement path to
3222 * internal channels (VrefInt, temperature sensor, ...).
3223 * Configure all paths (overwrite current configuration).
3224 * @note One or several values can be selected.
3225 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3226 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3227 * The values not selected are removed from configuration.
3228 * @note Stabilization time of measurement path to internal channel:
3229 * After enabling internal paths, before starting ADC conversion,
3230 * a delay is required for internal voltage reference and
3231 * temperature sensor stabilization time.
3232 * Refer to device datasheet.
3233 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
3234 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
3235 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
3236 * @note ADC internal channel sampling time constraint:
3237 * For ADC conversion of internal channels,
3238 * a sampling time minimum value is required.
3239 * Refer to device datasheet.
3240 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
3241 * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
3242 * CCR VBATEN LL_ADC_SetCommonPathInternalCh
3243 * @param ADCxy_COMMON ADC common instance
3244 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3245 * @param PathInternal This parameter can be a combination of the following values:
3246 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3247 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3248 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3249 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3250 * @retval None
3251 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)3252 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
3253 {
3254 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
3255 }
3256
3257 /**
3258 * @brief Set parameter common to several ADC: measurement path to
3259 * internal channels (VrefInt, temperature sensor, ...).
3260 * Add paths to the current configuration.
3261 * @note One or several values can be selected.
3262 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3263 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3264 * @note Stabilization time of measurement path to internal channel:
3265 * After enabling internal paths, before starting ADC conversion,
3266 * a delay is required for internal voltage reference and
3267 * temperature sensor stabilization time.
3268 * Refer to device datasheet.
3269 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
3270 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
3271 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
3272 * @note ADC internal channel sampling time constraint:
3273 * For ADC conversion of internal channels,
3274 * a sampling time minimum value is required.
3275 * Refer to device datasheet.
3276 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
3277 * CCR TSEN LL_ADC_SetCommonPathInternalChAdd\n
3278 * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd
3279 * @param ADCxy_COMMON ADC common instance
3280 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3281 * @param PathInternal This parameter can be a combination of the following values:
3282 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3283 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3284 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3285 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3286 * @retval None
3287 */
LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)3288 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
3289 {
3290 SET_BIT(ADCxy_COMMON->CCR, PathInternal);
3291 }
3292
3293 /**
3294 * @brief Set parameter common to several ADC: measurement path to
3295 * internal channels (VrefInt, temperature sensor, ...).
3296 * Remove paths to the current configuration.
3297 * @note One or several values can be selected.
3298 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3299 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3300 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
3301 * CCR TSEN LL_ADC_SetCommonPathInternalChRem\n
3302 * CCR VBATEN LL_ADC_SetCommonPathInternalChRem
3303 * @param ADCxy_COMMON ADC common instance
3304 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3305 * @param PathInternal This parameter can be a combination of the following values:
3306 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3307 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3308 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3309 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3310 * @retval None
3311 */
LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)3312 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
3313 {
3314 CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
3315 }
3316
3317 /**
3318 * @brief Get parameter common to several ADC: measurement path to internal
3319 * channels (VrefInt, temperature sensor, ...).
3320 * @note One or several values can be selected.
3321 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3322 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3323 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
3324 * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
3325 * CCR VBATEN LL_ADC_GetCommonPathInternalCh
3326 * @param ADCxy_COMMON ADC common instance
3327 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3328 * @retval Returned value can be a combination of the following values:
3329 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3330 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3331 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3332 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3333 */
LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef * ADCxy_COMMON)3334 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
3335 {
3336 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
3337 }
3338
3339 /**
3340 * @}
3341 */
3342
3343 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
3344 * @{
3345 */
3346
3347 /**
3348 * @brief Set ADC calibration factor in the mode single-ended
3349 * or differential (for devices with differential mode available).
3350 * @note This function is intended to set calibration parameters
3351 * without having to perform a new calibration using
3352 * @ref LL_ADC_StartCalibration().
3353 * @note For devices with differential mode available:
3354 * Calibration of offset is specific to each of
3355 * single-ended and differential modes
3356 * (calibration factor must be specified for each of these
3357 * differential modes, if used afterwards and if the application
3358 * requires their calibration).
3359 * @note In case of setting calibration factors of both modes single ended
3360 * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
3361 * both calibration factors must be concatenated.
3362 * To perform this processing, use helper macro
3363 * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
3364 * @note On this STM32 series, setting of this feature is conditioned to
3365 * ADC state:
3366 * ADC must be enabled, without calibration on going, without conversion
3367 * on going on group regular.
3368 * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n
3369 * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
3370 * @param ADCx ADC instance
3371 * @param SingleDiff This parameter can be one of the following values:
3372 * @arg @ref LL_ADC_SINGLE_ENDED
3373 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
3374 * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
3375 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
3376 * @retval None
3377 */
LL_ADC_SetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t SingleDiff,uint32_t CalibrationFactor)3378 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
3379 {
3380 MODIFY_REG(ADCx->CALFACT,
3381 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
3382 CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK)
3383 >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)
3384 & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
3385 }
3386
3387 /**
3388 * @brief Get ADC calibration factor in the mode single-ended
3389 * or differential (for devices with differential mode available).
3390 * @note Calibration factors are set by hardware after performing
3391 * a calibration run using function @ref LL_ADC_StartCalibration().
3392 * @note For devices with differential mode available:
3393 * Calibration of offset is specific to each of
3394 * single-ended and differential modes
3395 * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n
3396 * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
3397 * @param ADCx ADC instance
3398 * @param SingleDiff This parameter can be one of the following values:
3399 * @arg @ref LL_ADC_SINGLE_ENDED
3400 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
3401 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
3402 */
LL_ADC_GetCalibrationFactor(const ADC_TypeDef * ADCx,uint32_t SingleDiff)3403 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx, uint32_t SingleDiff)
3404 {
3405 /* Retrieve bits with position in register depending on parameter */
3406 /* "SingleDiff". */
3407 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
3408 /* containing other bits reserved for other purpose. */
3409 return (uint32_t)(READ_BIT(ADCx->CALFACT,
3410 (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK))
3411 >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >>
3412 ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
3413 }
3414
3415 /**
3416 * @brief Set ADC resolution.
3417 * Refer to reference manual for alignments formats
3418 * dependencies to ADC resolutions.
3419 * @note On this STM32 series, setting of this feature is conditioned to
3420 * ADC state:
3421 * ADC must be disabled or enabled without conversion on going
3422 * on either groups regular or injected.
3423 * @rmtoll CFGR RES LL_ADC_SetResolution
3424 * @param ADCx ADC instance
3425 * @param Resolution This parameter can be one of the following values:
3426 * @arg @ref LL_ADC_RESOLUTION_12B
3427 * @arg @ref LL_ADC_RESOLUTION_10B
3428 * @arg @ref LL_ADC_RESOLUTION_8B
3429 * @arg @ref LL_ADC_RESOLUTION_6B
3430 * @retval None
3431 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)3432 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
3433 {
3434 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
3435 }
3436
3437 /**
3438 * @brief Get ADC resolution.
3439 * Refer to reference manual for alignments formats
3440 * dependencies to ADC resolutions.
3441 * @rmtoll CFGR RES LL_ADC_GetResolution
3442 * @param ADCx ADC instance
3443 * @retval Returned value can be one of the following values:
3444 * @arg @ref LL_ADC_RESOLUTION_12B
3445 * @arg @ref LL_ADC_RESOLUTION_10B
3446 * @arg @ref LL_ADC_RESOLUTION_8B
3447 * @arg @ref LL_ADC_RESOLUTION_6B
3448 */
LL_ADC_GetResolution(const ADC_TypeDef * ADCx)3449 __STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx)
3450 {
3451 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
3452 }
3453
3454 /**
3455 * @brief Set ADC conversion data alignment.
3456 * @note Refer to reference manual for alignments formats
3457 * dependencies to ADC resolutions.
3458 * @note On this STM32 series, setting of this feature is conditioned to
3459 * ADC state:
3460 * ADC must be disabled or enabled without conversion on going
3461 * on either groups regular or injected.
3462 * @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment
3463 * @param ADCx ADC instance
3464 * @param DataAlignment This parameter can be one of the following values:
3465 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
3466 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
3467 * @retval None
3468 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)3469 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
3470 {
3471 MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
3472 }
3473
3474 /**
3475 * @brief Get ADC conversion data alignment.
3476 * @note Refer to reference manual for alignments formats
3477 * dependencies to ADC resolutions.
3478 * @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment
3479 * @param ADCx ADC instance
3480 * @retval Returned value can be one of the following values:
3481 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
3482 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
3483 */
LL_ADC_GetDataAlignment(const ADC_TypeDef * ADCx)3484 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx)
3485 {
3486 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
3487 }
3488
3489 /**
3490 * @brief Set ADC low power mode.
3491 * @note Description of ADC low power modes:
3492 * - ADC low power mode "auto wait": Dynamic low power mode,
3493 * ADC conversions occurrences are limited to the minimum necessary
3494 * in order to reduce power consumption.
3495 * New ADC conversion starts only when the previous
3496 * unitary conversion data (for ADC group regular)
3497 * or previous sequence conversions data (for ADC group injected)
3498 * has been retrieved by user software.
3499 * In the meantime, ADC remains idle: does not performs any
3500 * other conversion.
3501 * This mode allows to automatically adapt the ADC conversions
3502 * triggers to the speed of the software that reads the data.
3503 * Moreover, this avoids risk of overrun for low frequency
3504 * applications.
3505 * How to use this low power mode:
3506 * - It is not recommended to use with interruption or DMA
3507 * since these modes have to clear immediately the EOC flag
3508 * (by CPU to free the IRQ pending event or by DMA).
3509 * Auto wait will work but fort a very short time, discarding
3510 * its intended benefit (except specific case of high load of CPU
3511 * or DMA transfers which can justify usage of auto wait).
3512 * - Do use with polling: 1. Start conversion,
3513 * 2. Later on, when conversion data is needed: poll for end of
3514 * conversion to ensure that conversion is completed and
3515 * retrieve ADC conversion data. This will trig another
3516 * ADC conversion start.
3517 * @note With ADC low power mode "auto wait", the ADC conversion data read
3518 * is corresponding to previous ADC conversion start, independently
3519 * of delay during which ADC was idle.
3520 * Therefore, the ADC conversion data may be outdated: does not
3521 * correspond to the current voltage level on the selected
3522 * ADC channel.
3523 * @note On this STM32 series, setting of this feature is conditioned to
3524 * ADC state:
3525 * ADC must be disabled or enabled without conversion on going
3526 * on either groups regular or injected.
3527 * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
3528 * @param ADCx ADC instance
3529 * @param LowPowerMode This parameter can be one of the following values:
3530 * @arg @ref LL_ADC_LP_MODE_NONE
3531 * @arg @ref LL_ADC_LP_AUTOWAIT
3532 * @retval None
3533 */
LL_ADC_SetLowPowerMode(ADC_TypeDef * ADCx,uint32_t LowPowerMode)3534 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
3535 {
3536 MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
3537 }
3538
3539 /**
3540 * @brief Get ADC low power mode:
3541 * @note Description of ADC low power modes:
3542 * - ADC low power mode "auto wait": Dynamic low power mode,
3543 * ADC conversions occurrences are limited to the minimum necessary
3544 * in order to reduce power consumption.
3545 * New ADC conversion starts only when the previous
3546 * unitary conversion data (for ADC group regular)
3547 * or previous sequence conversions data (for ADC group injected)
3548 * has been retrieved by user software.
3549 * In the meantime, ADC remains idle: does not performs any
3550 * other conversion.
3551 * This mode allows to automatically adapt the ADC conversions
3552 * triggers to the speed of the software that reads the data.
3553 * Moreover, this avoids risk of overrun for low frequency
3554 * applications.
3555 * How to use this low power mode:
3556 * - It is not recommended to use with interruption or DMA
3557 * since these modes have to clear immediately the EOC flag
3558 * (by CPU to free the IRQ pending event or by DMA).
3559 * Auto wait will work but fort a very short time, discarding
3560 * its intended benefit (except specific case of high load of CPU
3561 * or DMA transfers which can justify usage of auto wait).
3562 * - Do use with polling: 1. Start conversion,
3563 * 2. Later on, when conversion data is needed: poll for end of
3564 * conversion to ensure that conversion is completed and
3565 * retrieve ADC conversion data. This will trig another
3566 * ADC conversion start.
3567 * @note With ADC low power mode "auto wait", the ADC conversion data read
3568 * is corresponding to previous ADC conversion start, independently
3569 * of delay during which ADC was idle.
3570 * Therefore, the ADC conversion data may be outdated: does not
3571 * correspond to the current voltage level on the selected
3572 * ADC channel.
3573 * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
3574 * @param ADCx ADC instance
3575 * @retval Returned value can be one of the following values:
3576 * @arg @ref LL_ADC_LP_MODE_NONE
3577 * @arg @ref LL_ADC_LP_AUTOWAIT
3578 */
LL_ADC_GetLowPowerMode(const ADC_TypeDef * ADCx)3579 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx)
3580 {
3581 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
3582 }
3583
3584 /**
3585 * @brief Set ADC selected offset instance 1, 2, 3 or 4.
3586 * @note This function set the 2 items of offset configuration:
3587 * - ADC channel to which the offset programmed will be applied
3588 * (independently of channel mapped on ADC group regular
3589 * or group injected)
3590 * - Offset level (offset to be subtracted from the raw
3591 * converted data).
3592 * @note Caution: Offset format is dependent to ADC resolution:
3593 * offset has to be left-aligned on bit 11, the LSB (right bits)
3594 * are set to 0.
3595 * @note This function enables the offset, by default. It can be forced
3596 * to disable state using function LL_ADC_SetOffsetState().
3597 * @note If a channel is mapped on several offsets numbers, only the offset
3598 * with the lowest value is considered for the subtraction.
3599 * @note On this STM32 series, setting of this feature is conditioned to
3600 * ADC state:
3601 * ADC must be disabled or enabled without conversion on going
3602 * on either groups regular or injected.
3603 * @note On STM32L4, some fast channels are available: fast analog inputs
3604 * coming from GPIO pads (ADC_IN1..5).
3605 * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
3606 * OFR1 OFFSET1 LL_ADC_SetOffset\n
3607 * OFR1 OFFSET1_EN LL_ADC_SetOffset\n
3608 * OFR2 OFFSET2_CH LL_ADC_SetOffset\n
3609 * OFR2 OFFSET2 LL_ADC_SetOffset\n
3610 * OFR2 OFFSET2_EN LL_ADC_SetOffset\n
3611 * OFR3 OFFSET3_CH LL_ADC_SetOffset\n
3612 * OFR3 OFFSET3 LL_ADC_SetOffset\n
3613 * OFR3 OFFSET3_EN LL_ADC_SetOffset\n
3614 * OFR4 OFFSET4_CH LL_ADC_SetOffset\n
3615 * OFR4 OFFSET4 LL_ADC_SetOffset\n
3616 * OFR4 OFFSET4_EN LL_ADC_SetOffset
3617 * @param ADCx ADC instance
3618 * @param Offsety This parameter can be one of the following values:
3619 * @arg @ref LL_ADC_OFFSET_1
3620 * @arg @ref LL_ADC_OFFSET_2
3621 * @arg @ref LL_ADC_OFFSET_3
3622 * @arg @ref LL_ADC_OFFSET_4
3623 * @param Channel This parameter can be one of the following values:
3624 * @arg @ref LL_ADC_CHANNEL_0
3625 * @arg @ref LL_ADC_CHANNEL_1 (7)
3626 * @arg @ref LL_ADC_CHANNEL_2 (7)
3627 * @arg @ref LL_ADC_CHANNEL_3 (7)
3628 * @arg @ref LL_ADC_CHANNEL_4 (7)
3629 * @arg @ref LL_ADC_CHANNEL_5 (7)
3630 * @arg @ref LL_ADC_CHANNEL_6
3631 * @arg @ref LL_ADC_CHANNEL_7
3632 * @arg @ref LL_ADC_CHANNEL_8
3633 * @arg @ref LL_ADC_CHANNEL_9
3634 * @arg @ref LL_ADC_CHANNEL_10
3635 * @arg @ref LL_ADC_CHANNEL_11
3636 * @arg @ref LL_ADC_CHANNEL_12
3637 * @arg @ref LL_ADC_CHANNEL_13
3638 * @arg @ref LL_ADC_CHANNEL_14
3639 * @arg @ref LL_ADC_CHANNEL_15
3640 * @arg @ref LL_ADC_CHANNEL_16
3641 * @arg @ref LL_ADC_CHANNEL_17
3642 * @arg @ref LL_ADC_CHANNEL_18
3643 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3644 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
3645 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
3646 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
3647 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
3648 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
3649 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
3650 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
3651 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
3652 *
3653 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
3654 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
3655 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
3656 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
3657 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
3658 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
3659 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
3660 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
3661 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
3662 * @retval None
3663 */
LL_ADC_SetOffset(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t Channel,uint32_t OffsetLevel)3664 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
3665 {
3666 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3667
3668 MODIFY_REG(*preg,
3669 ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
3670 ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
3671 }
3672
3673 /**
3674 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
3675 * Channel to which the offset programmed will be applied
3676 * (independently of channel mapped on ADC group regular
3677 * or group injected)
3678 * @note Usage of the returned channel number:
3679 * - To reinject this channel into another function LL_ADC_xxx:
3680 * the returned channel number is only partly formatted on definition
3681 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3682 * with parts of literals LL_ADC_CHANNEL_x or using
3683 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3684 * Then the selected literal LL_ADC_CHANNEL_x can be used
3685 * as parameter for another function.
3686 * - To get the channel number in decimal format:
3687 * process the returned value with the helper macro
3688 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3689 * @note On STM32L4, some fast channels are available: fast analog inputs
3690 * coming from GPIO pads (ADC_IN1..5).
3691 * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
3692 * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
3693 * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
3694 * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
3695 * @param ADCx ADC instance
3696 * @param Offsety This parameter can be one of the following values:
3697 * @arg @ref LL_ADC_OFFSET_1
3698 * @arg @ref LL_ADC_OFFSET_2
3699 * @arg @ref LL_ADC_OFFSET_3
3700 * @arg @ref LL_ADC_OFFSET_4
3701 * @retval Returned value can be one of the following values:
3702 * @arg @ref LL_ADC_CHANNEL_0
3703 * @arg @ref LL_ADC_CHANNEL_1 (7)
3704 * @arg @ref LL_ADC_CHANNEL_2 (7)
3705 * @arg @ref LL_ADC_CHANNEL_3 (7)
3706 * @arg @ref LL_ADC_CHANNEL_4 (7)
3707 * @arg @ref LL_ADC_CHANNEL_5 (7)
3708 * @arg @ref LL_ADC_CHANNEL_6
3709 * @arg @ref LL_ADC_CHANNEL_7
3710 * @arg @ref LL_ADC_CHANNEL_8
3711 * @arg @ref LL_ADC_CHANNEL_9
3712 * @arg @ref LL_ADC_CHANNEL_10
3713 * @arg @ref LL_ADC_CHANNEL_11
3714 * @arg @ref LL_ADC_CHANNEL_12
3715 * @arg @ref LL_ADC_CHANNEL_13
3716 * @arg @ref LL_ADC_CHANNEL_14
3717 * @arg @ref LL_ADC_CHANNEL_15
3718 * @arg @ref LL_ADC_CHANNEL_16
3719 * @arg @ref LL_ADC_CHANNEL_17
3720 * @arg @ref LL_ADC_CHANNEL_18
3721 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3722 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
3723 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
3724 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
3725 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
3726 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
3727 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
3728 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
3729 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
3730 *
3731 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
3732 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
3733 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
3734 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
3735 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
3736 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
3737 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
3738 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to
3739 * 4.21 Ms/s)).\n
3740 * (1, 2, 3, 4) For ADC channel read back from ADC register,
3741 * comparison with internal channel parameter to be done
3742 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3743 */
LL_ADC_GetOffsetChannel(const ADC_TypeDef * ADCx,uint32_t Offsety)3744 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety)
3745 {
3746 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3747
3748 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
3749 }
3750
3751 /**
3752 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
3753 * Offset level (offset to be subtracted from the raw
3754 * converted data).
3755 * @note Caution: Offset format is dependent to ADC resolution:
3756 * offset has to be left-aligned on bit 11, the LSB (right bits)
3757 * are set to 0.
3758 * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
3759 * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
3760 * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
3761 * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
3762 * @param ADCx ADC instance
3763 * @param Offsety This parameter can be one of the following values:
3764 * @arg @ref LL_ADC_OFFSET_1
3765 * @arg @ref LL_ADC_OFFSET_2
3766 * @arg @ref LL_ADC_OFFSET_3
3767 * @arg @ref LL_ADC_OFFSET_4
3768 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3769 */
LL_ADC_GetOffsetLevel(const ADC_TypeDef * ADCx,uint32_t Offsety)3770 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t Offsety)
3771 {
3772 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3773
3774 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
3775 }
3776
3777 /**
3778 * @brief Set for the ADC selected offset instance 1, 2, 3 or 4:
3779 * force offset state disable or enable
3780 * without modifying offset channel or offset value.
3781 * @note This function should be needed only in case of offset to be
3782 * enabled-disabled dynamically, and should not be needed in other cases:
3783 * function LL_ADC_SetOffset() automatically enables the offset.
3784 * @note On this STM32 series, setting of this feature is conditioned to
3785 * ADC state:
3786 * ADC must be disabled or enabled without conversion on going
3787 * on either groups regular or injected.
3788 * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n
3789 * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n
3790 * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n
3791 * OFR4 OFFSET4_EN LL_ADC_SetOffsetState
3792 * @param ADCx ADC instance
3793 * @param Offsety This parameter can be one of the following values:
3794 * @arg @ref LL_ADC_OFFSET_1
3795 * @arg @ref LL_ADC_OFFSET_2
3796 * @arg @ref LL_ADC_OFFSET_3
3797 * @arg @ref LL_ADC_OFFSET_4
3798 * @param OffsetState This parameter can be one of the following values:
3799 * @arg @ref LL_ADC_OFFSET_DISABLE
3800 * @arg @ref LL_ADC_OFFSET_ENABLE
3801 * @retval None
3802 */
LL_ADC_SetOffsetState(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetState)3803 __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
3804 {
3805 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3806
3807 MODIFY_REG(*preg,
3808 ADC_OFR1_OFFSET1_EN,
3809 OffsetState);
3810 }
3811
3812 /**
3813 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
3814 * offset state disabled or enabled.
3815 * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n
3816 * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n
3817 * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n
3818 * OFR4 OFFSET4_EN LL_ADC_GetOffsetState
3819 * @param ADCx ADC instance
3820 * @param Offsety This parameter can be one of the following values:
3821 * @arg @ref LL_ADC_OFFSET_1
3822 * @arg @ref LL_ADC_OFFSET_2
3823 * @arg @ref LL_ADC_OFFSET_3
3824 * @arg @ref LL_ADC_OFFSET_4
3825 * @retval Returned value can be one of the following values:
3826 * @arg @ref LL_ADC_OFFSET_DISABLE
3827 * @arg @ref LL_ADC_OFFSET_ENABLE
3828 */
LL_ADC_GetOffsetState(const ADC_TypeDef * ADCx,uint32_t Offsety)3829 __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(const ADC_TypeDef *ADCx, uint32_t Offsety)
3830 {
3831 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3832
3833 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
3834 }
3835
3836 #if defined(ADC_SMPR1_SMPPLUS)
3837 /**
3838 * @brief Set ADC sampling time common configuration impacting
3839 * settings of sampling time channel wise.
3840 * @note On this STM32 series, setting of this feature is conditioned to
3841 * ADC state:
3842 * ADC must be disabled or enabled without conversion on going
3843 * on either groups regular or injected.
3844 * @rmtoll SMPR1 SMPPLUS LL_ADC_SetSamplingTimeCommonConfig
3845 * @param ADCx ADC instance
3846 * @param SamplingTimeCommonConfig This parameter can be one of the following values:
3847 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
3848 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
3849 * @retval None
3850 */
LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef * ADCx,uint32_t SamplingTimeCommonConfig)3851 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
3852 {
3853 MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
3854 }
3855
3856 /**
3857 * @brief Get ADC sampling time common configuration impacting
3858 * settings of sampling time channel wise.
3859 * @rmtoll SMPR1 SMPPLUS LL_ADC_GetSamplingTimeCommonConfig
3860 * @param ADCx ADC instance
3861 * @retval Returned value can be one of the following values:
3862 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
3863 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
3864 */
LL_ADC_GetSamplingTimeCommonConfig(const ADC_TypeDef * ADCx)3865 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(const ADC_TypeDef *ADCx)
3866 {
3867 return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS));
3868 }
3869 #endif /* ADC_SMPR1_SMPPLUS */
3870
3871 /**
3872 * @}
3873 */
3874
3875 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
3876 * @{
3877 */
3878
3879 /**
3880 * @brief Set ADC group regular conversion trigger source:
3881 * internal (SW start) or from external peripheral (timer event,
3882 * external interrupt line).
3883 * @note On this STM32 series, setting trigger source to external trigger
3884 * also set trigger polarity to rising edge
3885 * (default setting for compatibility with some ADC on other
3886 * STM32 series having this setting set by HW default value).
3887 * In case of need to modify trigger edge, use
3888 * function @ref LL_ADC_REG_SetTriggerEdge().
3889 * @note Availability of parameters of trigger sources from timer
3890 * depends on timers availability on the selected device.
3891 * @note On this STM32 series, setting of this feature is conditioned to
3892 * ADC state:
3893 * ADC must be disabled or enabled without conversion on going
3894 * on group regular.
3895 * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
3896 * CFGR EXTEN LL_ADC_REG_SetTriggerSource
3897 * @param ADCx ADC instance
3898 * @param TriggerSource This parameter can be one of the following values:
3899 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3900 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3901 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3902 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
3903 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
3904 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3905 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3906 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
3907 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3908 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
3909 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3910 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
3911 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3912 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
3913 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
3914 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3915 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
3916 * @retval None
3917 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)3918 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3919 {
3920 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
3921 }
3922
3923 /**
3924 * @brief Get ADC group regular conversion trigger source:
3925 * internal (SW start) or from external peripheral (timer event,
3926 * external interrupt line).
3927 * @note To determine whether group regular trigger source is
3928 * internal (SW start) or external, without detail
3929 * of which peripheral is selected as external trigger,
3930 * (equivalent to
3931 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
3932 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
3933 * @note Availability of parameters of trigger sources from timer
3934 * depends on timers availability on the selected device.
3935 * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
3936 * CFGR EXTEN LL_ADC_REG_GetTriggerSource
3937 * @param ADCx ADC instance
3938 * @retval Returned value can be one of the following values:
3939 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3940 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3941 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3942 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
3943 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
3944 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3945 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3946 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
3947 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3948 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
3949 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3950 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
3951 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3952 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
3953 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
3954 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3955 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
3956 */
LL_ADC_REG_GetTriggerSource(const ADC_TypeDef * ADCx)3957 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx)
3958 {
3959 __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
3960
3961 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3962 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
3963 uint32_t shift_exten = ((trigger_source & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
3964
3965 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
3966 /* to match with triggers literals definition. */
3967 return ((trigger_source
3968 & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR_EXTSEL)
3969 | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR_EXTEN)
3970 );
3971 }
3972
3973 /**
3974 * @brief Get ADC group regular conversion trigger source internal (SW start)
3975 * or external.
3976 * @note In case of group regular trigger source set to external trigger,
3977 * to determine which peripheral is selected as external trigger,
3978 * use function @ref LL_ADC_REG_GetTriggerSource().
3979 * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
3980 * @param ADCx ADC instance
3981 * @retval Value "0" if trigger source external trigger
3982 * Value "1" if trigger source SW start.
3983 */
LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)3984 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
3985 {
3986 return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
3987 }
3988
3989 /**
3990 * @brief Set ADC group regular conversion trigger polarity.
3991 * @note Applicable only for trigger source set to external trigger.
3992 * @note On this STM32 series, setting of this feature is conditioned to
3993 * ADC state:
3994 * ADC must be disabled or enabled without conversion on going
3995 * on group regular.
3996 * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
3997 * @param ADCx ADC instance
3998 * @param ExternalTriggerEdge This parameter can be one of the following values:
3999 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
4000 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
4001 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
4002 * @retval None
4003 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)4004 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4005 {
4006 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
4007 }
4008
4009 /**
4010 * @brief Get ADC group regular conversion trigger polarity.
4011 * @note Applicable only for trigger source set to external trigger.
4012 * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
4013 * @param ADCx ADC instance
4014 * @retval Returned value can be one of the following values:
4015 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
4016 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
4017 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
4018 */
LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef * ADCx)4019 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx)
4020 {
4021 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
4022 }
4023
4024 /**
4025 * @brief Set ADC group regular sequencer length and scan direction.
4026 * @note Description of ADC group regular sequencer features:
4027 * - For devices with sequencer fully configurable
4028 * (function "LL_ADC_REG_SetSequencerRanks()" available):
4029 * sequencer length and each rank affectation to a channel
4030 * are configurable.
4031 * This function performs configuration of:
4032 * - Sequence length: Number of ranks in the scan sequence.
4033 * - Sequence direction: Unless specified in parameters, sequencer
4034 * scan direction is forward (from rank 1 to rank n).
4035 * Sequencer ranks are selected using
4036 * function "LL_ADC_REG_SetSequencerRanks()".
4037 * - For devices with sequencer not fully configurable
4038 * (function "LL_ADC_REG_SetSequencerChannels()" available):
4039 * sequencer length and each rank affectation to a channel
4040 * are defined by channel number.
4041 * This function performs configuration of:
4042 * - Sequence length: Number of ranks in the scan sequence is
4043 * defined by number of channels set in the sequence,
4044 * rank of each channel is fixed by channel HW number.
4045 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
4046 * - Sequence direction: Unless specified in parameters, sequencer
4047 * scan direction is forward (from lowest channel number to
4048 * highest channel number).
4049 * Sequencer ranks are selected using
4050 * function "LL_ADC_REG_SetSequencerChannels()".
4051 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4052 * ADC conversion on only 1 channel.
4053 * @note On this STM32 series, setting of this feature is conditioned to
4054 * ADC state:
4055 * ADC must be disabled or enabled without conversion on going
4056 * on group regular.
4057 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
4058 * @param ADCx ADC instance
4059 * @param SequencerNbRanks This parameter can be one of the following values:
4060 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
4061 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
4062 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
4063 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
4064 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
4065 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
4066 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
4067 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
4068 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
4069 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
4070 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
4071 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
4072 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
4073 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
4074 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
4075 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
4076 * @retval None
4077 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)4078 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4079 {
4080 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
4081 }
4082
4083 /**
4084 * @brief Get ADC group regular sequencer length and scan direction.
4085 * @note Description of ADC group regular sequencer features:
4086 * - For devices with sequencer fully configurable
4087 * (function "LL_ADC_REG_SetSequencerRanks()" available):
4088 * sequencer length and each rank affectation to a channel
4089 * are configurable.
4090 * This function retrieves:
4091 * - Sequence length: Number of ranks in the scan sequence.
4092 * - Sequence direction: Unless specified in parameters, sequencer
4093 * scan direction is forward (from rank 1 to rank n).
4094 * Sequencer ranks are selected using
4095 * function "LL_ADC_REG_SetSequencerRanks()".
4096 * - For devices with sequencer not fully configurable
4097 * (function "LL_ADC_REG_SetSequencerChannels()" available):
4098 * sequencer length and each rank affectation to a channel
4099 * are defined by channel number.
4100 * This function retrieves:
4101 * - Sequence length: Number of ranks in the scan sequence is
4102 * defined by number of channels set in the sequence,
4103 * rank of each channel is fixed by channel HW number.
4104 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
4105 * - Sequence direction: Unless specified in parameters, sequencer
4106 * scan direction is forward (from lowest channel number to
4107 * highest channel number).
4108 * Sequencer ranks are selected using
4109 * function "LL_ADC_REG_SetSequencerChannels()".
4110 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4111 * ADC conversion on only 1 channel.
4112 * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
4113 * @param ADCx ADC instance
4114 * @retval Returned value can be one of the following values:
4115 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
4116 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
4117 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
4118 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
4119 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
4120 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
4121 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
4122 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
4123 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
4124 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
4125 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
4126 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
4127 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
4128 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
4129 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
4130 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
4131 */
LL_ADC_REG_GetSequencerLength(const ADC_TypeDef * ADCx)4132 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx)
4133 {
4134 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
4135 }
4136
4137 /**
4138 * @brief Set ADC group regular sequencer discontinuous mode:
4139 * sequence subdivided and scan conversions interrupted every selected
4140 * number of ranks.
4141 * @note It is not possible to enable both ADC group regular
4142 * continuous mode and sequencer discontinuous mode.
4143 * @note It is not possible to enable both ADC auto-injected mode
4144 * and ADC group regular sequencer discontinuous mode.
4145 * @note On this STM32 series, setting of this feature is conditioned to
4146 * ADC state:
4147 * ADC must be disabled or enabled without conversion on going
4148 * on group regular.
4149 * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
4150 * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
4151 * @param ADCx ADC instance
4152 * @param SeqDiscont This parameter can be one of the following values:
4153 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
4154 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
4155 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
4156 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
4157 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
4158 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
4159 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
4160 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
4161 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
4162 * @retval None
4163 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)4164 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4165 {
4166 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
4167 }
4168
4169 /**
4170 * @brief Get ADC group regular sequencer discontinuous mode:
4171 * sequence subdivided and scan conversions interrupted every selected
4172 * number of ranks.
4173 * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
4174 * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
4175 * @param ADCx ADC instance
4176 * @retval Returned value can be one of the following values:
4177 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
4178 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
4179 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
4180 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
4181 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
4182 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
4183 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
4184 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
4185 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
4186 */
LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef * ADCx)4187 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx)
4188 {
4189 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
4190 }
4191
4192 /**
4193 * @brief Set ADC group regular sequence: channel on the selected
4194 * scan sequence rank.
4195 * @note This function performs configuration of:
4196 * - Channels ordering into each rank of scan sequence:
4197 * whatever channel can be placed into whatever rank.
4198 * @note On this STM32 series, ADC group regular sequencer is
4199 * fully configurable: sequencer length and each rank
4200 * affectation to a channel are configurable.
4201 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
4202 * @note Depending on devices and packages, some channels may not be available.
4203 * Refer to device datasheet for channels availability.
4204 * @note On this STM32 series, to measure internal channels (VrefInt,
4205 * TempSensor, ...), measurement paths to internal channels must be
4206 * enabled separately.
4207 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4208 * @note On this STM32 series, setting of this feature is conditioned to
4209 * ADC state:
4210 * ADC must be disabled or enabled without conversion on going
4211 * on group regular.
4212 * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
4213 * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
4214 * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
4215 * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
4216 * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
4217 * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
4218 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
4219 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
4220 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
4221 * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
4222 * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
4223 * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
4224 * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
4225 * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
4226 * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
4227 * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
4228 * @param ADCx ADC instance
4229 * @param Rank This parameter can be one of the following values:
4230 * @arg @ref LL_ADC_REG_RANK_1
4231 * @arg @ref LL_ADC_REG_RANK_2
4232 * @arg @ref LL_ADC_REG_RANK_3
4233 * @arg @ref LL_ADC_REG_RANK_4
4234 * @arg @ref LL_ADC_REG_RANK_5
4235 * @arg @ref LL_ADC_REG_RANK_6
4236 * @arg @ref LL_ADC_REG_RANK_7
4237 * @arg @ref LL_ADC_REG_RANK_8
4238 * @arg @ref LL_ADC_REG_RANK_9
4239 * @arg @ref LL_ADC_REG_RANK_10
4240 * @arg @ref LL_ADC_REG_RANK_11
4241 * @arg @ref LL_ADC_REG_RANK_12
4242 * @arg @ref LL_ADC_REG_RANK_13
4243 * @arg @ref LL_ADC_REG_RANK_14
4244 * @arg @ref LL_ADC_REG_RANK_15
4245 * @arg @ref LL_ADC_REG_RANK_16
4246 * @param Channel This parameter can be one of the following values:
4247 * @arg @ref LL_ADC_CHANNEL_0
4248 * @arg @ref LL_ADC_CHANNEL_1 (7)
4249 * @arg @ref LL_ADC_CHANNEL_2 (7)
4250 * @arg @ref LL_ADC_CHANNEL_3 (7)
4251 * @arg @ref LL_ADC_CHANNEL_4 (7)
4252 * @arg @ref LL_ADC_CHANNEL_5 (7)
4253 * @arg @ref LL_ADC_CHANNEL_6
4254 * @arg @ref LL_ADC_CHANNEL_7
4255 * @arg @ref LL_ADC_CHANNEL_8
4256 * @arg @ref LL_ADC_CHANNEL_9
4257 * @arg @ref LL_ADC_CHANNEL_10
4258 * @arg @ref LL_ADC_CHANNEL_11
4259 * @arg @ref LL_ADC_CHANNEL_12
4260 * @arg @ref LL_ADC_CHANNEL_13
4261 * @arg @ref LL_ADC_CHANNEL_14
4262 * @arg @ref LL_ADC_CHANNEL_15
4263 * @arg @ref LL_ADC_CHANNEL_16
4264 * @arg @ref LL_ADC_CHANNEL_17
4265 * @arg @ref LL_ADC_CHANNEL_18
4266 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4267 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4268 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4269 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4270 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4271 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4272 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4273 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4274 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4275 *
4276 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4277 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4278 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4279 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4280 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4281 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4282 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4283 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4284 * @retval None
4285 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)4286 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4287 {
4288 /* Set bits with content of parameter "Channel" with bits position */
4289 /* in register and register position depending on parameter "Rank". */
4290 /* Parameters "Rank" and "Channel" are used with masks because containing */
4291 /* other bits reserved for other purpose. */
4292 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
4293 ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
4294
4295 MODIFY_REG(*preg,
4296 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
4297 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
4298 << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
4299 }
4300
4301 /**
4302 * @brief Get ADC group regular sequence: channel on the selected
4303 * scan sequence rank.
4304 * @note On this STM32 series, ADC group regular sequencer is
4305 * fully configurable: sequencer length and each rank
4306 * affectation to a channel are configurable.
4307 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
4308 * @note Depending on devices and packages, some channels may not be available.
4309 * Refer to device datasheet for channels availability.
4310 * @note Usage of the returned channel number:
4311 * - To reinject this channel into another function LL_ADC_xxx:
4312 * the returned channel number is only partly formatted on definition
4313 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4314 * with parts of literals LL_ADC_CHANNEL_x or using
4315 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4316 * Then the selected literal LL_ADC_CHANNEL_x can be used
4317 * as parameter for another function.
4318 * - To get the channel number in decimal format:
4319 * process the returned value with the helper macro
4320 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4321 * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
4322 * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
4323 * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
4324 * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
4325 * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
4326 * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
4327 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
4328 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
4329 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
4330 * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
4331 * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
4332 * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
4333 * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
4334 * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
4335 * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
4336 * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
4337 * @param ADCx ADC instance
4338 * @param Rank This parameter can be one of the following values:
4339 * @arg @ref LL_ADC_REG_RANK_1
4340 * @arg @ref LL_ADC_REG_RANK_2
4341 * @arg @ref LL_ADC_REG_RANK_3
4342 * @arg @ref LL_ADC_REG_RANK_4
4343 * @arg @ref LL_ADC_REG_RANK_5
4344 * @arg @ref LL_ADC_REG_RANK_6
4345 * @arg @ref LL_ADC_REG_RANK_7
4346 * @arg @ref LL_ADC_REG_RANK_8
4347 * @arg @ref LL_ADC_REG_RANK_9
4348 * @arg @ref LL_ADC_REG_RANK_10
4349 * @arg @ref LL_ADC_REG_RANK_11
4350 * @arg @ref LL_ADC_REG_RANK_12
4351 * @arg @ref LL_ADC_REG_RANK_13
4352 * @arg @ref LL_ADC_REG_RANK_14
4353 * @arg @ref LL_ADC_REG_RANK_15
4354 * @arg @ref LL_ADC_REG_RANK_16
4355 * @retval Returned value can be one of the following values:
4356 * @arg @ref LL_ADC_CHANNEL_0
4357 * @arg @ref LL_ADC_CHANNEL_1 (7)
4358 * @arg @ref LL_ADC_CHANNEL_2 (7)
4359 * @arg @ref LL_ADC_CHANNEL_3 (7)
4360 * @arg @ref LL_ADC_CHANNEL_4 (7)
4361 * @arg @ref LL_ADC_CHANNEL_5 (7)
4362 * @arg @ref LL_ADC_CHANNEL_6
4363 * @arg @ref LL_ADC_CHANNEL_7
4364 * @arg @ref LL_ADC_CHANNEL_8
4365 * @arg @ref LL_ADC_CHANNEL_9
4366 * @arg @ref LL_ADC_CHANNEL_10
4367 * @arg @ref LL_ADC_CHANNEL_11
4368 * @arg @ref LL_ADC_CHANNEL_12
4369 * @arg @ref LL_ADC_CHANNEL_13
4370 * @arg @ref LL_ADC_CHANNEL_14
4371 * @arg @ref LL_ADC_CHANNEL_15
4372 * @arg @ref LL_ADC_CHANNEL_16
4373 * @arg @ref LL_ADC_CHANNEL_17
4374 * @arg @ref LL_ADC_CHANNEL_18
4375 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4376 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4377 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4378 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4379 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4380 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4381 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4382 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4383 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4384 *
4385 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4386 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4387 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4388 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4389 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4390 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4391 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4392 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to
4393 * 4.21 Ms/s)).\n
4394 * (1, 2, 3, 4) For ADC channel read back from ADC register,
4395 * comparison with internal channel parameter to be done
4396 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4397 */
LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)4398 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
4399 {
4400 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
4401 ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
4402
4403 return (uint32_t)((READ_BIT(*preg,
4404 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
4405 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4406 );
4407 }
4408
4409 /**
4410 * @brief Set ADC continuous conversion mode on ADC group regular.
4411 * @note Description of ADC continuous conversion mode:
4412 * - single mode: one conversion per trigger
4413 * - continuous mode: after the first trigger, following
4414 * conversions launched successively automatically.
4415 * @note It is not possible to enable both ADC group regular
4416 * continuous mode and sequencer discontinuous mode.
4417 * @note On this STM32 series, setting of this feature is conditioned to
4418 * ADC state:
4419 * ADC must be disabled or enabled without conversion on going
4420 * on group regular.
4421 * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
4422 * @param ADCx ADC instance
4423 * @param Continuous This parameter can be one of the following values:
4424 * @arg @ref LL_ADC_REG_CONV_SINGLE
4425 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
4426 * @retval None
4427 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)4428 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
4429 {
4430 MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
4431 }
4432
4433 /**
4434 * @brief Get ADC continuous conversion mode on ADC group regular.
4435 * @note Description of ADC continuous conversion mode:
4436 * - single mode: one conversion per trigger
4437 * - continuous mode: after the first trigger, following
4438 * conversions launched successively automatically.
4439 * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
4440 * @param ADCx ADC instance
4441 * @retval Returned value can be one of the following values:
4442 * @arg @ref LL_ADC_REG_CONV_SINGLE
4443 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
4444 */
LL_ADC_REG_GetContinuousMode(const ADC_TypeDef * ADCx)4445 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx)
4446 {
4447 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
4448 }
4449
4450 /**
4451 * @brief Set ADC group regular conversion data transfer: no transfer or
4452 * transfer by DMA, and DMA requests mode.
4453 * @note If transfer by DMA selected, specifies the DMA requests
4454 * mode:
4455 * - Limited mode (One shot mode): DMA transfer requests are stopped
4456 * when number of DMA data transfers (number of
4457 * ADC conversions) is reached.
4458 * This ADC mode is intended to be used with DMA mode non-circular.
4459 * - Unlimited mode: DMA transfer requests are unlimited,
4460 * whatever number of DMA data transfers (number of
4461 * ADC conversions).
4462 * This ADC mode is intended to be used with DMA mode circular.
4463 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
4464 * mode non-circular:
4465 * when DMA transfers size will be reached, DMA will stop transfers of
4466 * ADC conversions data ADC will raise an overrun error
4467 * (overrun flag and interruption if enabled).
4468 * @note For devices with several ADC instances: ADC multimode DMA
4469 * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
4470 * @note To configure DMA source address (peripheral address),
4471 * use function @ref LL_ADC_DMA_GetRegAddr().
4472 * @note On this STM32 series, setting of this feature is conditioned to
4473 * ADC state:
4474 * ADC must be disabled or enabled without conversion on going
4475 * on either groups regular or injected.
4476 * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n
4477 * CFGR DMACFG LL_ADC_REG_SetDMATransfer
4478 * @param ADCx ADC instance
4479 * @param DMATransfer This parameter can be one of the following values:
4480 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
4481 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
4482 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
4483 * @retval None
4484 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)4485 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
4486 {
4487 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
4488 }
4489
4490 /**
4491 * @brief Get ADC group regular conversion data transfer: no transfer or
4492 * transfer by DMA, and DMA requests mode.
4493 * @note If transfer by DMA selected, specifies the DMA requests
4494 * mode:
4495 * - Limited mode (One shot mode): DMA transfer requests are stopped
4496 * when number of DMA data transfers (number of
4497 * ADC conversions) is reached.
4498 * This ADC mode is intended to be used with DMA mode non-circular.
4499 * - Unlimited mode: DMA transfer requests are unlimited,
4500 * whatever number of DMA data transfers (number of
4501 * ADC conversions).
4502 * This ADC mode is intended to be used with DMA mode circular.
4503 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
4504 * mode non-circular:
4505 * when DMA transfers size will be reached, DMA will stop transfers of
4506 * ADC conversions data ADC will raise an overrun error
4507 * (overrun flag and interruption if enabled).
4508 * @note For devices with several ADC instances: ADC multimode DMA
4509 * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
4510 * @note To configure DMA source address (peripheral address),
4511 * use function @ref LL_ADC_DMA_GetRegAddr().
4512 * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n
4513 * CFGR DMACFG LL_ADC_REG_GetDMATransfer
4514 * @param ADCx ADC instance
4515 * @retval Returned value can be one of the following values:
4516 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
4517 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
4518 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
4519 */
LL_ADC_REG_GetDMATransfer(const ADC_TypeDef * ADCx)4520 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx)
4521 {
4522 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
4523 }
4524
4525 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
4526 /**
4527 * @brief Set ADC group regular conversion data transfer to DFSDM.
4528 * @note DFSDM transfer cannot be used if DMA transfer is enabled.
4529 * @note To configure DFSDM source address (peripheral address),
4530 * use the same function as for DMA transfer:
4531 * function @ref LL_ADC_DMA_GetRegAddr().
4532 * @note On this STM32 series, setting of this feature is conditioned to
4533 * ADC state:
4534 * ADC must be disabled or enabled without conversion on going
4535 * on either groups regular or injected.
4536 * @rmtoll CFGR DFSDMCFG LL_ADC_REG_GetDFSDMTransfer
4537 * @param ADCx ADC instance
4538 * @param DFSDMTransfer This parameter can be one of the following values:
4539 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_NONE
4540 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_ENABLE
4541 * @retval None
4542 */
LL_ADC_REG_SetDFSDMTransfer(ADC_TypeDef * ADCx,uint32_t DFSDMTransfer)4543 __STATIC_INLINE void LL_ADC_REG_SetDFSDMTransfer(ADC_TypeDef *ADCx, uint32_t DFSDMTransfer)
4544 {
4545 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DFSDMCFG, DFSDMTransfer);
4546 }
4547
4548 /**
4549 * @brief Get ADC group regular conversion data transfer to DFSDM.
4550 * @rmtoll CFGR DFSDMCFG LL_ADC_REG_GetDFSDMTransfer
4551 * @param ADCx ADC instance
4552 * @retval Returned value can be one of the following values:
4553 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_NONE
4554 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_ENABLE
4555 */
LL_ADC_REG_GetDFSDMTransfer(const ADC_TypeDef * ADCx)4556 __STATIC_INLINE uint32_t LL_ADC_REG_GetDFSDMTransfer(const ADC_TypeDef *ADCx)
4557 {
4558 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DFSDMCFG));
4559 }
4560 #endif /* ADC_CFGR_DFSDMCFG */
4561
4562 /**
4563 * @brief Set ADC group regular behavior in case of overrun:
4564 * data preserved or overwritten.
4565 * @note Compatibility with devices without feature overrun:
4566 * other devices without this feature have a behavior
4567 * equivalent to data overwritten.
4568 * The default setting of overrun is data preserved.
4569 * Therefore, for compatibility with all devices, parameter
4570 * overrun should be set to data overwritten.
4571 * @note On this STM32 series, setting of this feature is conditioned to
4572 * ADC state:
4573 * ADC must be disabled or enabled without conversion on going
4574 * on group regular.
4575 * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
4576 * @param ADCx ADC instance
4577 * @param Overrun This parameter can be one of the following values:
4578 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
4579 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
4580 * @retval None
4581 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)4582 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
4583 {
4584 MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
4585 }
4586
4587 /**
4588 * @brief Get ADC group regular behavior in case of overrun:
4589 * data preserved or overwritten.
4590 * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
4591 * @param ADCx ADC instance
4592 * @retval Returned value can be one of the following values:
4593 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
4594 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
4595 */
LL_ADC_REG_GetOverrun(const ADC_TypeDef * ADCx)4596 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx)
4597 {
4598 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
4599 }
4600
4601 /**
4602 * @}
4603 */
4604
4605 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
4606 * @{
4607 */
4608
4609 /**
4610 * @brief Set ADC group injected conversion trigger source:
4611 * internal (SW start) or from external peripheral (timer event,
4612 * external interrupt line).
4613 * @note On this STM32 series, setting trigger source to external trigger
4614 * also set trigger polarity to rising edge
4615 * (default setting for compatibility with some ADC on other
4616 * STM32 series having this setting set by HW default value).
4617 * In case of need to modify trigger edge, use
4618 * function @ref LL_ADC_INJ_SetTriggerEdge().
4619 * @note Availability of parameters of trigger sources from timer
4620 * depends on timers availability on the selected device.
4621 * @note On this STM32 series, setting of this feature is conditioned to
4622 * ADC state:
4623 * ADC must not be disabled. Can be enabled with or without conversion
4624 * on going on either groups regular or injected.
4625 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
4626 * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
4627 * @param ADCx ADC instance
4628 * @param TriggerSource This parameter can be one of the following values:
4629 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4630 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4631 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4632 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4633 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4634 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
4635 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4636 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
4637 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
4638 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
4639 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4640 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4641 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
4642 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
4643 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
4644 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4645 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
4646 * @retval None
4647 */
LL_ADC_INJ_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)4648 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
4649 {
4650 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
4651 }
4652
4653 /**
4654 * @brief Get ADC group injected conversion trigger source:
4655 * internal (SW start) or from external peripheral (timer event,
4656 * external interrupt line).
4657 * @note To determine whether group injected trigger source is
4658 * internal (SW start) or external, without detail
4659 * of which peripheral is selected as external trigger,
4660 * (equivalent to
4661 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
4662 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
4663 * @note Availability of parameters of trigger sources from timer
4664 * depends on timers availability on the selected device.
4665 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
4666 * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
4667 * @param ADCx ADC instance
4668 * @retval Returned value can be one of the following values:
4669 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4670 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4671 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4672 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4673 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4674 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
4675 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4676 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
4677 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
4678 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
4679 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4680 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4681 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
4682 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
4683 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
4684 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4685 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
4686 */
LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef * ADCx)4687 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx)
4688 {
4689 __IO uint32_t trigger_source = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
4690
4691 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
4692 /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
4693 uint32_t shift_jexten = ((trigger_source & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
4694
4695 /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
4696 /* to match with triggers literals definition. */
4697 return ((trigger_source
4698 & (ADC_INJ_TRIG_SOURCE_MASK >> shift_jexten) & ADC_JSQR_JEXTSEL)
4699 | ((ADC_INJ_TRIG_EDGE_MASK >> shift_jexten) & ADC_JSQR_JEXTEN)
4700 );
4701 }
4702
4703 /**
4704 * @brief Get ADC group injected conversion trigger source internal (SW start)
4705 or external
4706 * @note In case of group injected trigger source set to external trigger,
4707 * to determine which peripheral is selected as external trigger,
4708 * use function @ref LL_ADC_INJ_GetTriggerSource.
4709 * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
4710 * @param ADCx ADC instance
4711 * @retval Value "0" if trigger source external trigger
4712 * Value "1" if trigger source SW start.
4713 */
LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)4714 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
4715 {
4716 return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
4717 }
4718
4719 /**
4720 * @brief Set ADC group injected conversion trigger polarity.
4721 * Applicable only for trigger source set to external trigger.
4722 * @note On this STM32 series, setting of this feature is conditioned to
4723 * ADC state:
4724 * ADC must not be disabled. Can be enabled with or without conversion
4725 * on going on either groups regular or injected.
4726 * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
4727 * @param ADCx ADC instance
4728 * @param ExternalTriggerEdge This parameter can be one of the following values:
4729 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4730 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4731 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4732 * @retval None
4733 */
LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)4734 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4735 {
4736 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
4737 }
4738
4739 /**
4740 * @brief Get ADC group injected conversion trigger polarity.
4741 * Applicable only for trigger source set to external trigger.
4742 * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
4743 * @param ADCx ADC instance
4744 * @retval Returned value can be one of the following values:
4745 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4746 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4747 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4748 */
LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef * ADCx)4749 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx)
4750 {
4751 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
4752 }
4753
4754 /**
4755 * @brief Set ADC group injected sequencer length and scan direction.
4756 * @note This function performs configuration of:
4757 * - Sequence length: Number of ranks in the scan sequence.
4758 * - Sequence direction: Unless specified in parameters, sequencer
4759 * scan direction is forward (from rank 1 to rank n).
4760 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4761 * ADC conversion on only 1 channel.
4762 * @note On this STM32 series, setting of this feature is conditioned to
4763 * ADC state:
4764 * ADC must not be disabled. Can be enabled with or without conversion
4765 * on going on either groups regular or injected.
4766 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
4767 * @param ADCx ADC instance
4768 * @param SequencerNbRanks This parameter can be one of the following values:
4769 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4770 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4771 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4772 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4773 * @retval None
4774 */
LL_ADC_INJ_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)4775 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4776 {
4777 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
4778 }
4779
4780 /**
4781 * @brief Get ADC group injected sequencer length and scan direction.
4782 * @note This function retrieves:
4783 * - Sequence length: Number of ranks in the scan sequence.
4784 * - Sequence direction: Unless specified in parameters, sequencer
4785 * scan direction is forward (from rank 1 to rank n).
4786 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4787 * ADC conversion on only 1 channel.
4788 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
4789 * @param ADCx ADC instance
4790 * @retval Returned value can be one of the following values:
4791 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4792 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4793 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4794 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4795 */
LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef * ADCx)4796 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx)
4797 {
4798 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
4799 }
4800
4801 /**
4802 * @brief Set ADC group injected sequencer discontinuous mode:
4803 * sequence subdivided and scan conversions interrupted every selected
4804 * number of ranks.
4805 * @note It is not possible to enable both ADC group injected
4806 * auto-injected mode and sequencer discontinuous mode.
4807 * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
4808 * @param ADCx ADC instance
4809 * @param SeqDiscont This parameter can be one of the following values:
4810 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4811 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4812 * @retval None
4813 */
LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)4814 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4815 {
4816 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
4817 }
4818
4819 /**
4820 * @brief Get ADC group injected sequencer discontinuous mode:
4821 * sequence subdivided and scan conversions interrupted every selected
4822 * number of ranks.
4823 * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
4824 * @param ADCx ADC instance
4825 * @retval Returned value can be one of the following values:
4826 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4827 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4828 */
LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef * ADCx)4829 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx)
4830 {
4831 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
4832 }
4833
4834 /**
4835 * @brief Set ADC group injected sequence: channel on the selected
4836 * sequence rank.
4837 * @note Depending on devices and packages, some channels may not be available.
4838 * Refer to device datasheet for channels availability.
4839 * @note On this STM32 series, to measure internal channels (VrefInt,
4840 * TempSensor, ...), measurement paths to internal channels must be
4841 * enabled separately.
4842 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4843 * @note On STM32L4, some fast channels are available: fast analog inputs
4844 * coming from GPIO pads (ADC_IN1..5).
4845 * @note On this STM32 series, setting of this feature is conditioned to
4846 * ADC state:
4847 * ADC must not be disabled. Can be enabled with or without conversion
4848 * on going on either groups regular or injected.
4849 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
4850 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
4851 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
4852 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
4853 * @param ADCx ADC instance
4854 * @param Rank This parameter can be one of the following values:
4855 * @arg @ref LL_ADC_INJ_RANK_1
4856 * @arg @ref LL_ADC_INJ_RANK_2
4857 * @arg @ref LL_ADC_INJ_RANK_3
4858 * @arg @ref LL_ADC_INJ_RANK_4
4859 * @param Channel This parameter can be one of the following values:
4860 * @arg @ref LL_ADC_CHANNEL_0
4861 * @arg @ref LL_ADC_CHANNEL_1 (7)
4862 * @arg @ref LL_ADC_CHANNEL_2 (7)
4863 * @arg @ref LL_ADC_CHANNEL_3 (7)
4864 * @arg @ref LL_ADC_CHANNEL_4 (7)
4865 * @arg @ref LL_ADC_CHANNEL_5 (7)
4866 * @arg @ref LL_ADC_CHANNEL_6
4867 * @arg @ref LL_ADC_CHANNEL_7
4868 * @arg @ref LL_ADC_CHANNEL_8
4869 * @arg @ref LL_ADC_CHANNEL_9
4870 * @arg @ref LL_ADC_CHANNEL_10
4871 * @arg @ref LL_ADC_CHANNEL_11
4872 * @arg @ref LL_ADC_CHANNEL_12
4873 * @arg @ref LL_ADC_CHANNEL_13
4874 * @arg @ref LL_ADC_CHANNEL_14
4875 * @arg @ref LL_ADC_CHANNEL_15
4876 * @arg @ref LL_ADC_CHANNEL_16
4877 * @arg @ref LL_ADC_CHANNEL_17
4878 * @arg @ref LL_ADC_CHANNEL_18
4879 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4880 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4881 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4882 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4883 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4884 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4885 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4886 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4887 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4888 *
4889 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4890 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4891 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4892 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4893 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4894 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4895 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4896 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4897 * @retval None
4898 */
LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)4899 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4900 {
4901 /* Set bits with content of parameter "Channel" with bits position */
4902 /* in register depending on parameter "Rank". */
4903 /* Parameters "Rank" and "Channel" are used with masks because containing */
4904 /* other bits reserved for other purpose. */
4905 MODIFY_REG(ADCx->JSQR,
4906 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
4907 << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
4908 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
4909 << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
4910 }
4911
4912 /**
4913 * @brief Get ADC group injected sequence: channel on the selected
4914 * sequence rank.
4915 * @note Depending on devices and packages, some channels may not be available.
4916 * Refer to device datasheet for channels availability.
4917 * @note Usage of the returned channel number:
4918 * - To reinject this channel into another function LL_ADC_xxx:
4919 * the returned channel number is only partly formatted on definition
4920 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4921 * with parts of literals LL_ADC_CHANNEL_x or using
4922 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4923 * Then the selected literal LL_ADC_CHANNEL_x can be used
4924 * as parameter for another function.
4925 * - To get the channel number in decimal format:
4926 * process the returned value with the helper macro
4927 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4928 * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
4929 * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
4930 * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
4931 * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
4932 * @param ADCx ADC instance
4933 * @param Rank This parameter can be one of the following values:
4934 * @arg @ref LL_ADC_INJ_RANK_1
4935 * @arg @ref LL_ADC_INJ_RANK_2
4936 * @arg @ref LL_ADC_INJ_RANK_3
4937 * @arg @ref LL_ADC_INJ_RANK_4
4938 * @retval Returned value can be one of the following values:
4939 * @arg @ref LL_ADC_CHANNEL_0
4940 * @arg @ref LL_ADC_CHANNEL_1 (7)
4941 * @arg @ref LL_ADC_CHANNEL_2 (7)
4942 * @arg @ref LL_ADC_CHANNEL_3 (7)
4943 * @arg @ref LL_ADC_CHANNEL_4 (7)
4944 * @arg @ref LL_ADC_CHANNEL_5 (7)
4945 * @arg @ref LL_ADC_CHANNEL_6
4946 * @arg @ref LL_ADC_CHANNEL_7
4947 * @arg @ref LL_ADC_CHANNEL_8
4948 * @arg @ref LL_ADC_CHANNEL_9
4949 * @arg @ref LL_ADC_CHANNEL_10
4950 * @arg @ref LL_ADC_CHANNEL_11
4951 * @arg @ref LL_ADC_CHANNEL_12
4952 * @arg @ref LL_ADC_CHANNEL_13
4953 * @arg @ref LL_ADC_CHANNEL_14
4954 * @arg @ref LL_ADC_CHANNEL_15
4955 * @arg @ref LL_ADC_CHANNEL_16
4956 * @arg @ref LL_ADC_CHANNEL_17
4957 * @arg @ref LL_ADC_CHANNEL_18
4958 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4959 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4960 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4961 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4962 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4963 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4964 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4965 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4966 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4967 *
4968 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4969 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4970 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4971 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4972 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4973 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4974 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4975 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to
4976 * 4.21 Ms/s)).\n
4977 * (1, 2, 3, 4) For ADC channel read back from ADC register,
4978 * comparison with internal channel parameter to be done
4979 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4980 */
LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)4981 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
4982 {
4983 return (uint32_t)((READ_BIT(ADCx->JSQR,
4984 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
4985 << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
4986 >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4987 );
4988 }
4989
4990 /**
4991 * @brief Set ADC group injected conversion trigger:
4992 * independent or from ADC group regular.
4993 * @note This mode can be used to extend number of data registers
4994 * updated after one ADC conversion trigger and with data
4995 * permanently kept (not erased by successive conversions of scan of
4996 * ADC sequencer ranks), up to 5 data registers:
4997 * 1 data register on ADC group regular, 4 data registers
4998 * on ADC group injected.
4999 * @note If ADC group injected injected trigger source is set to an
5000 * external trigger, this feature must be must be set to
5001 * independent trigger.
5002 * ADC group injected automatic trigger is compliant only with
5003 * group injected trigger source set to SW start, without any
5004 * further action on ADC group injected conversion start or stop:
5005 * in this case, ADC group injected is controlled only
5006 * from ADC group regular.
5007 * @note It is not possible to enable both ADC group injected
5008 * auto-injected mode and sequencer discontinuous mode.
5009 * @note On this STM32 series, setting of this feature is conditioned to
5010 * ADC state:
5011 * ADC must be disabled or enabled without conversion on going
5012 * on either groups regular or injected.
5013 * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
5014 * @param ADCx ADC instance
5015 * @param TrigAuto This parameter can be one of the following values:
5016 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
5017 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
5018 * @retval None
5019 */
LL_ADC_INJ_SetTrigAuto(ADC_TypeDef * ADCx,uint32_t TrigAuto)5020 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
5021 {
5022 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
5023 }
5024
5025 /**
5026 * @brief Get ADC group injected conversion trigger:
5027 * independent or from ADC group regular.
5028 * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
5029 * @param ADCx ADC instance
5030 * @retval Returned value can be one of the following values:
5031 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
5032 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
5033 */
LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef * ADCx)5034 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx)
5035 {
5036 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
5037 }
5038
5039 /**
5040 * @brief Set ADC group injected contexts queue mode.
5041 * @note A context is a setting of group injected sequencer:
5042 * - group injected trigger
5043 * - sequencer length
5044 * - sequencer ranks
5045 * If contexts queue is disabled:
5046 * - only 1 sequence can be configured
5047 * and is active perpetually.
5048 * If contexts queue is enabled:
5049 * - up to 2 contexts can be queued
5050 * and are checked in and out as a FIFO stack (first-in, first-out).
5051 * - If a new context is set when queues is full, error is triggered
5052 * by interruption "Injected Queue Overflow".
5053 * - Two behaviors are possible when all contexts have been processed:
5054 * the contexts queue can maintain the last context active perpetually
5055 * or can be empty and injected group triggers are disabled.
5056 * - Triggers can be only external (not internal SW start)
5057 * - Caution: The sequence must be fully configured in one time
5058 * (one write of register JSQR makes a check-in of a new context
5059 * into the queue).
5060 * Therefore functions to set separately injected trigger and
5061 * sequencer channels cannot be used, register JSQR must be set
5062 * using function @ref LL_ADC_INJ_ConfigQueueContext().
5063 * @note This parameter can be modified only when no conversion is on going
5064 * on either groups regular or injected.
5065 * @note A modification of the context mode (bit JQDIS) causes the contexts
5066 * queue to be flushed and the register JSQR is cleared.
5067 * @note On this STM32 series, setting of this feature is conditioned to
5068 * ADC state:
5069 * ADC must be disabled or enabled without conversion on going
5070 * on either groups regular or injected.
5071 * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n
5072 * CFGR JQDIS LL_ADC_INJ_SetQueueMode
5073 * @param ADCx ADC instance
5074 * @param QueueMode This parameter can be one of the following values:
5075 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
5076 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
5077 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
5078 * @retval None
5079 */
LL_ADC_INJ_SetQueueMode(ADC_TypeDef * ADCx,uint32_t QueueMode)5080 __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
5081 {
5082 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
5083 }
5084
5085 /**
5086 * @brief Get ADC group injected context queue mode.
5087 * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n
5088 * CFGR JQDIS LL_ADC_INJ_GetQueueMode
5089 * @param ADCx ADC instance
5090 * @retval Returned value can be one of the following values:
5091 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
5092 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
5093 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
5094 */
LL_ADC_INJ_GetQueueMode(const ADC_TypeDef * ADCx)5095 __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(const ADC_TypeDef *ADCx)
5096 {
5097 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
5098 }
5099
5100 /**
5101 * @brief Set one context on ADC group injected that will be checked in
5102 * contexts queue.
5103 * @note A context is a setting of group injected sequencer:
5104 * - group injected trigger
5105 * - sequencer length
5106 * - sequencer ranks
5107 * This function is intended to be used when contexts queue is enabled,
5108 * because the sequence must be fully configured in one time
5109 * (functions to set separately injected trigger and sequencer channels
5110 * cannot be used):
5111 * Refer to function @ref LL_ADC_INJ_SetQueueMode().
5112 * @note In the contexts queue, only the active context can be read.
5113 * The parameters of this function can be read using functions:
5114 * @arg @ref LL_ADC_INJ_GetTriggerSource()
5115 * @arg @ref LL_ADC_INJ_GetTriggerEdge()
5116 * @arg @ref LL_ADC_INJ_GetSequencerRanks()
5117 * @note On this STM32 series, to measure internal channels (VrefInt,
5118 * TempSensor, ...), measurement paths to internal channels must be
5119 * enabled separately.
5120 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
5121 * @note On STM32L4, some fast channels are available: fast analog inputs
5122 * coming from GPIO pads (ADC_IN1..5).
5123 * @note On this STM32 series, setting of this feature is conditioned to
5124 * ADC state:
5125 * ADC must not be disabled. Can be enabled with or without conversion
5126 * on going on either groups regular or injected.
5127 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
5128 * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
5129 * JSQR JL LL_ADC_INJ_ConfigQueueContext\n
5130 * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
5131 * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
5132 * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
5133 * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
5134 * @param ADCx ADC instance
5135 * @param TriggerSource This parameter can be one of the following values:
5136 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
5137 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
5138 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
5139 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
5140 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
5141 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
5142 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
5143 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
5144 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
5145 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
5146 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
5147 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
5148 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
5149 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
5150 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
5151 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
5152 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
5153 * @param ExternalTriggerEdge This parameter can be one of the following values:
5154 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
5155 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
5156 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
5157 *
5158 * Note: This parameter is discarded in case of SW start:
5159 * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
5160 * @param SequencerNbRanks This parameter can be one of the following values:
5161 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
5162 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
5163 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
5164 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
5165 * @param Rank1_Channel This parameter can be one of the following values:
5166 * @arg @ref LL_ADC_CHANNEL_0
5167 * @arg @ref LL_ADC_CHANNEL_1 (7)
5168 * @arg @ref LL_ADC_CHANNEL_2 (7)
5169 * @arg @ref LL_ADC_CHANNEL_3 (7)
5170 * @arg @ref LL_ADC_CHANNEL_4 (7)
5171 * @arg @ref LL_ADC_CHANNEL_5 (7)
5172 * @arg @ref LL_ADC_CHANNEL_6
5173 * @arg @ref LL_ADC_CHANNEL_7
5174 * @arg @ref LL_ADC_CHANNEL_8
5175 * @arg @ref LL_ADC_CHANNEL_9
5176 * @arg @ref LL_ADC_CHANNEL_10
5177 * @arg @ref LL_ADC_CHANNEL_11
5178 * @arg @ref LL_ADC_CHANNEL_12
5179 * @arg @ref LL_ADC_CHANNEL_13
5180 * @arg @ref LL_ADC_CHANNEL_14
5181 * @arg @ref LL_ADC_CHANNEL_15
5182 * @arg @ref LL_ADC_CHANNEL_16
5183 * @arg @ref LL_ADC_CHANNEL_17
5184 * @arg @ref LL_ADC_CHANNEL_18
5185 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5186 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
5187 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
5188 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
5189 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
5190 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
5191 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
5192 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
5193 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
5194 *
5195 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
5196 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
5197 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
5198 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
5199 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
5200 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
5201 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
5202 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
5203 * @param Rank2_Channel This parameter can be one of the following values:
5204 * @arg @ref LL_ADC_CHANNEL_0
5205 * @arg @ref LL_ADC_CHANNEL_1 (7)
5206 * @arg @ref LL_ADC_CHANNEL_2 (7)
5207 * @arg @ref LL_ADC_CHANNEL_3 (7)
5208 * @arg @ref LL_ADC_CHANNEL_4 (7)
5209 * @arg @ref LL_ADC_CHANNEL_5 (7)
5210 * @arg @ref LL_ADC_CHANNEL_6
5211 * @arg @ref LL_ADC_CHANNEL_7
5212 * @arg @ref LL_ADC_CHANNEL_8
5213 * @arg @ref LL_ADC_CHANNEL_9
5214 * @arg @ref LL_ADC_CHANNEL_10
5215 * @arg @ref LL_ADC_CHANNEL_11
5216 * @arg @ref LL_ADC_CHANNEL_12
5217 * @arg @ref LL_ADC_CHANNEL_13
5218 * @arg @ref LL_ADC_CHANNEL_14
5219 * @arg @ref LL_ADC_CHANNEL_15
5220 * @arg @ref LL_ADC_CHANNEL_16
5221 * @arg @ref LL_ADC_CHANNEL_17
5222 * @arg @ref LL_ADC_CHANNEL_18
5223 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5224 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
5225 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
5226 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
5227 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
5228 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
5229 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
5230 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
5231 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
5232 *
5233 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
5234 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
5235 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
5236 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
5237 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
5238 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
5239 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
5240 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
5241 * @param Rank3_Channel This parameter can be one of the following values:
5242 * @arg @ref LL_ADC_CHANNEL_0
5243 * @arg @ref LL_ADC_CHANNEL_1 (7)
5244 * @arg @ref LL_ADC_CHANNEL_2 (7)
5245 * @arg @ref LL_ADC_CHANNEL_3 (7)
5246 * @arg @ref LL_ADC_CHANNEL_4 (7)
5247 * @arg @ref LL_ADC_CHANNEL_5 (7)
5248 * @arg @ref LL_ADC_CHANNEL_6
5249 * @arg @ref LL_ADC_CHANNEL_7
5250 * @arg @ref LL_ADC_CHANNEL_8
5251 * @arg @ref LL_ADC_CHANNEL_9
5252 * @arg @ref LL_ADC_CHANNEL_10
5253 * @arg @ref LL_ADC_CHANNEL_11
5254 * @arg @ref LL_ADC_CHANNEL_12
5255 * @arg @ref LL_ADC_CHANNEL_13
5256 * @arg @ref LL_ADC_CHANNEL_14
5257 * @arg @ref LL_ADC_CHANNEL_15
5258 * @arg @ref LL_ADC_CHANNEL_16
5259 * @arg @ref LL_ADC_CHANNEL_17
5260 * @arg @ref LL_ADC_CHANNEL_18
5261 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5262 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
5263 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
5264 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
5265 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
5266 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
5267 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
5268 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
5269 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
5270 *
5271 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
5272 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
5273 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
5274 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
5275 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
5276 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
5277 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
5278 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
5279 * @param Rank4_Channel This parameter can be one of the following values:
5280 * @arg @ref LL_ADC_CHANNEL_0
5281 * @arg @ref LL_ADC_CHANNEL_1 (7)
5282 * @arg @ref LL_ADC_CHANNEL_2 (7)
5283 * @arg @ref LL_ADC_CHANNEL_3 (7)
5284 * @arg @ref LL_ADC_CHANNEL_4 (7)
5285 * @arg @ref LL_ADC_CHANNEL_5 (7)
5286 * @arg @ref LL_ADC_CHANNEL_6
5287 * @arg @ref LL_ADC_CHANNEL_7
5288 * @arg @ref LL_ADC_CHANNEL_8
5289 * @arg @ref LL_ADC_CHANNEL_9
5290 * @arg @ref LL_ADC_CHANNEL_10
5291 * @arg @ref LL_ADC_CHANNEL_11
5292 * @arg @ref LL_ADC_CHANNEL_12
5293 * @arg @ref LL_ADC_CHANNEL_13
5294 * @arg @ref LL_ADC_CHANNEL_14
5295 * @arg @ref LL_ADC_CHANNEL_15
5296 * @arg @ref LL_ADC_CHANNEL_16
5297 * @arg @ref LL_ADC_CHANNEL_17
5298 * @arg @ref LL_ADC_CHANNEL_18
5299 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5300 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
5301 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
5302 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
5303 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
5304 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
5305 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
5306 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
5307 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
5308 *
5309 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
5310 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
5311 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
5312 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
5313 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
5314 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
5315 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
5316 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
5317 * @retval None
5318 */
LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef * ADCx,uint32_t TriggerSource,uint32_t ExternalTriggerEdge,uint32_t SequencerNbRanks,uint32_t Rank1_Channel,uint32_t Rank2_Channel,uint32_t Rank3_Channel,uint32_t Rank4_Channel)5319 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
5320 uint32_t TriggerSource,
5321 uint32_t ExternalTriggerEdge,
5322 uint32_t SequencerNbRanks,
5323 uint32_t Rank1_Channel,
5324 uint32_t Rank2_Channel,
5325 uint32_t Rank3_Channel,
5326 uint32_t Rank4_Channel)
5327 {
5328 /* Set bits with content of parameter "Rankx_Channel" with bits position */
5329 /* in register depending on literal "LL_ADC_INJ_RANK_x". */
5330 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
5331 /* because containing other bits reserved for other purpose. */
5332 /* If parameter "TriggerSource" is set to SW start, then parameter */
5333 /* "ExternalTriggerEdge" is discarded. */
5334 uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
5335 MODIFY_REG(ADCx->JSQR,
5336 ADC_JSQR_JEXTSEL |
5337 ADC_JSQR_JEXTEN |
5338 ADC_JSQR_JSQ4 |
5339 ADC_JSQR_JSQ3 |
5340 ADC_JSQR_JSQ2 |
5341 ADC_JSQR_JSQ1 |
5342 ADC_JSQR_JL,
5343 (TriggerSource & ADC_JSQR_JEXTSEL) |
5344 (ExternalTriggerEdge * (is_trigger_not_sw)) |
5345 (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
5346 << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5347 (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
5348 << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5349 (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
5350 << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5351 (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
5352 << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5353 SequencerNbRanks
5354 );
5355 }
5356
5357 /**
5358 * @}
5359 */
5360
5361 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
5362 * @{
5363 */
5364
5365 /**
5366 * @brief Set sampling time of the selected ADC channel
5367 * Unit: ADC clock cycles.
5368 * @note On this device, sampling time is on channel scope: independently
5369 * of channel mapped on ADC group regular or injected.
5370 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
5371 * converted:
5372 * sampling time constraints must be respected (sampling time can be
5373 * adjusted in function of ADC clock frequency and sampling time
5374 * setting).
5375 * Refer to device datasheet for timings values (parameters TS_vrefint,
5376 * TS_temp, ...).
5377 * @note Conversion time is the addition of sampling time and processing time.
5378 * On this STM32 series, ADC processing time is:
5379 * - 12.5 ADC clock cycles at ADC resolution 12 bits
5380 * - 10.5 ADC clock cycles at ADC resolution 10 bits
5381 * - 8.5 ADC clock cycles at ADC resolution 8 bits
5382 * - 6.5 ADC clock cycles at ADC resolution 6 bits
5383 * @note In case of ADC conversion of internal channel (VrefInt,
5384 * temperature sensor, ...), a sampling time minimum value
5385 * is required.
5386 * Refer to device datasheet.
5387 * @note On this STM32 series, setting of this feature is conditioned to
5388 * ADC state:
5389 * ADC must be disabled or enabled without conversion on going
5390 * on either groups regular or injected.
5391 * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
5392 * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
5393 * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
5394 * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
5395 * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
5396 * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
5397 * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
5398 * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
5399 * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
5400 * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
5401 * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
5402 * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
5403 * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
5404 * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
5405 * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
5406 * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
5407 * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
5408 * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
5409 * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
5410 * @param ADCx ADC instance
5411 * @param Channel This parameter can be one of the following values:
5412 * @arg @ref LL_ADC_CHANNEL_0
5413 * @arg @ref LL_ADC_CHANNEL_1 (7)
5414 * @arg @ref LL_ADC_CHANNEL_2 (7)
5415 * @arg @ref LL_ADC_CHANNEL_3 (7)
5416 * @arg @ref LL_ADC_CHANNEL_4 (7)
5417 * @arg @ref LL_ADC_CHANNEL_5 (7)
5418 * @arg @ref LL_ADC_CHANNEL_6
5419 * @arg @ref LL_ADC_CHANNEL_7
5420 * @arg @ref LL_ADC_CHANNEL_8
5421 * @arg @ref LL_ADC_CHANNEL_9
5422 * @arg @ref LL_ADC_CHANNEL_10
5423 * @arg @ref LL_ADC_CHANNEL_11
5424 * @arg @ref LL_ADC_CHANNEL_12
5425 * @arg @ref LL_ADC_CHANNEL_13
5426 * @arg @ref LL_ADC_CHANNEL_14
5427 * @arg @ref LL_ADC_CHANNEL_15
5428 * @arg @ref LL_ADC_CHANNEL_16
5429 * @arg @ref LL_ADC_CHANNEL_17
5430 * @arg @ref LL_ADC_CHANNEL_18
5431 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5432 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
5433 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
5434 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
5435 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
5436 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
5437 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
5438 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
5439 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
5440 *
5441 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
5442 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
5443 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
5444 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
5445 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
5446 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
5447 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
5448 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
5449 * @param SamplingTime This parameter can be one of the following values:
5450 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
5451 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
5452 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
5453 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
5454 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
5455 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
5456 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
5457 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
5458 *
5459 * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
5460 * can be replaced by 3.5 ADC clock cycles.
5461 * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
5462 * @retval None
5463 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTime)5464 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
5465 {
5466 /* Set bits with content of parameter "SamplingTime" with bits position */
5467 /* in register and register position depending on parameter "Channel". */
5468 /* Parameter "Channel" is used with masks because containing */
5469 /* other bits reserved for other purpose. */
5470 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1,
5471 ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
5472
5473 MODIFY_REG(*preg,
5474 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
5475 SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
5476 }
5477
5478 /**
5479 * @brief Get sampling time of the selected ADC channel
5480 * Unit: ADC clock cycles.
5481 * @note On this device, sampling time is on channel scope: independently
5482 * of channel mapped on ADC group regular or injected.
5483 * @note Conversion time is the addition of sampling time and processing time.
5484 * On this STM32 series, ADC processing time is:
5485 * - 12.5 ADC clock cycles at ADC resolution 12 bits
5486 * - 10.5 ADC clock cycles at ADC resolution 10 bits
5487 * - 8.5 ADC clock cycles at ADC resolution 8 bits
5488 * - 6.5 ADC clock cycles at ADC resolution 6 bits
5489 * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
5490 * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
5491 * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
5492 * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
5493 * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
5494 * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
5495 * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
5496 * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
5497 * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
5498 * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
5499 * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
5500 * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
5501 * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
5502 * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
5503 * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
5504 * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
5505 * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
5506 * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
5507 * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
5508 * @param ADCx ADC instance
5509 * @param Channel This parameter can be one of the following values:
5510 * @arg @ref LL_ADC_CHANNEL_0
5511 * @arg @ref LL_ADC_CHANNEL_1 (7)
5512 * @arg @ref LL_ADC_CHANNEL_2 (7)
5513 * @arg @ref LL_ADC_CHANNEL_3 (7)
5514 * @arg @ref LL_ADC_CHANNEL_4 (7)
5515 * @arg @ref LL_ADC_CHANNEL_5 (7)
5516 * @arg @ref LL_ADC_CHANNEL_6
5517 * @arg @ref LL_ADC_CHANNEL_7
5518 * @arg @ref LL_ADC_CHANNEL_8
5519 * @arg @ref LL_ADC_CHANNEL_9
5520 * @arg @ref LL_ADC_CHANNEL_10
5521 * @arg @ref LL_ADC_CHANNEL_11
5522 * @arg @ref LL_ADC_CHANNEL_12
5523 * @arg @ref LL_ADC_CHANNEL_13
5524 * @arg @ref LL_ADC_CHANNEL_14
5525 * @arg @ref LL_ADC_CHANNEL_15
5526 * @arg @ref LL_ADC_CHANNEL_16
5527 * @arg @ref LL_ADC_CHANNEL_17
5528 * @arg @ref LL_ADC_CHANNEL_18
5529 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
5530 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
5531 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
5532 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
5533 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
5534 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
5535 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
5536 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
5537 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
5538 *
5539 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
5540 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
5541 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
5542 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
5543 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
5544 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
5545 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
5546 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
5547 * @retval Returned value can be one of the following values:
5548 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
5549 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
5550 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
5551 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
5552 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
5553 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
5554 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
5555 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
5556 *
5557 * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
5558 * can be replaced by 3.5 ADC clock cycles.
5559 * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
5560 */
LL_ADC_GetChannelSamplingTime(const ADC_TypeDef * ADCx,uint32_t Channel)5561 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
5562 {
5563 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK)
5564 >> ADC_SMPRX_REGOFFSET_POS));
5565
5566 return (uint32_t)(READ_BIT(*preg,
5567 ADC_SMPR1_SMP0
5568 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
5569 >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
5570 );
5571 }
5572
5573 /**
5574 * @brief Set mode single-ended or differential input of the selected
5575 * ADC channel.
5576 * @note Channel ending is on channel scope: independently of channel mapped
5577 * on ADC group regular or injected.
5578 * In differential mode: Differential measurement is carried out
5579 * between the selected channel 'i' (positive input) and
5580 * channel 'i+1' (negative input). Only channel 'i' has to be
5581 * configured, channel 'i+1' is configured automatically.
5582 * @note Refer to Reference Manual to ensure the selected channel is
5583 * available in differential mode.
5584 * For example, internal channels (VrefInt, TempSensor, ...) are
5585 * not available in differential mode.
5586 * @note When configuring a channel 'i' in differential mode,
5587 * the channel 'i+1' is not usable separately.
5588 * @note On STM32L4, channels 16, 17, 18 of ADC1, ADC2, ADC3 (if available)
5589 * are internally fixed to single-ended inputs configuration.
5590 * @note For ADC channels configured in differential mode, both inputs
5591 * should be biased at (Vref+)/2 +/-200mV.
5592 * (Vref+ is the analog voltage reference)
5593 * @note On this STM32 series, setting of this feature is conditioned to
5594 * ADC state:
5595 * ADC must be ADC disabled.
5596 * @note One or several values can be selected.
5597 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5598 * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
5599 * @param ADCx ADC instance
5600 * @param Channel This parameter can be one of the following values:
5601 * @arg @ref LL_ADC_CHANNEL_1
5602 * @arg @ref LL_ADC_CHANNEL_2
5603 * @arg @ref LL_ADC_CHANNEL_3
5604 * @arg @ref LL_ADC_CHANNEL_4
5605 * @arg @ref LL_ADC_CHANNEL_5
5606 * @arg @ref LL_ADC_CHANNEL_6
5607 * @arg @ref LL_ADC_CHANNEL_7
5608 * @arg @ref LL_ADC_CHANNEL_8
5609 * @arg @ref LL_ADC_CHANNEL_9
5610 * @arg @ref LL_ADC_CHANNEL_10
5611 * @arg @ref LL_ADC_CHANNEL_11
5612 * @arg @ref LL_ADC_CHANNEL_12
5613 * @arg @ref LL_ADC_CHANNEL_13
5614 * @arg @ref LL_ADC_CHANNEL_14
5615 * @arg @ref LL_ADC_CHANNEL_15
5616 * @param SingleDiff This parameter can be a combination of the following values:
5617 * @arg @ref LL_ADC_SINGLE_ENDED
5618 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
5619 * @retval None
5620 */
LL_ADC_SetChannelSingleDiff(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SingleDiff)5621 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
5622 {
5623 /* Bits of channels in single or differential mode are set only for */
5624 /* differential mode (for single mode, mask of bits allowed to be set is */
5625 /* shifted out of range of bits of channels in single or differential mode. */
5626 MODIFY_REG(ADCx->DIFSEL,
5627 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
5628 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)
5629 & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
5630 }
5631
5632 /**
5633 * @brief Get mode single-ended or differential input of the selected
5634 * ADC channel.
5635 * @note When configuring a channel 'i' in differential mode,
5636 * the channel 'i+1' is not usable separately.
5637 * Therefore, to ensure a channel is configured in single-ended mode,
5638 * the configuration of channel itself and the channel 'i-1' must be
5639 * read back (to ensure that the selected channel channel has not been
5640 * configured in differential mode by the previous channel).
5641 * @note Refer to Reference Manual to ensure the selected channel is
5642 * available in differential mode.
5643 * For example, internal channels (VrefInt, TempSensor, ...) are
5644 * not available in differential mode.
5645 * @note When configuring a channel 'i' in differential mode,
5646 * the channel 'i+1' is not usable separately.
5647 * @note On STM32L4, channels 16, 17, 18 of ADC1, ADC2, ADC3 (if available)
5648 * are internally fixed to single-ended inputs configuration.
5649 * @note One or several values can be selected. In this case, the value
5650 * returned is null if all channels are in single ended-mode.
5651 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5652 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
5653 * @param ADCx ADC instance
5654 * @param Channel This parameter can be a combination of the following values:
5655 * @arg @ref LL_ADC_CHANNEL_1
5656 * @arg @ref LL_ADC_CHANNEL_2
5657 * @arg @ref LL_ADC_CHANNEL_3
5658 * @arg @ref LL_ADC_CHANNEL_4
5659 * @arg @ref LL_ADC_CHANNEL_5
5660 * @arg @ref LL_ADC_CHANNEL_6
5661 * @arg @ref LL_ADC_CHANNEL_7
5662 * @arg @ref LL_ADC_CHANNEL_8
5663 * @arg @ref LL_ADC_CHANNEL_9
5664 * @arg @ref LL_ADC_CHANNEL_10
5665 * @arg @ref LL_ADC_CHANNEL_11
5666 * @arg @ref LL_ADC_CHANNEL_12
5667 * @arg @ref LL_ADC_CHANNEL_13
5668 * @arg @ref LL_ADC_CHANNEL_14
5669 * @arg @ref LL_ADC_CHANNEL_15
5670 * @retval 0: channel in single-ended mode, else: channel in differential mode
5671 */
LL_ADC_GetChannelSingleDiff(const ADC_TypeDef * ADCx,uint32_t Channel)5672 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, uint32_t Channel)
5673 {
5674 return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
5675 }
5676
5677 /**
5678 * @}
5679 */
5680
5681 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
5682 * @{
5683 */
5684
5685 /**
5686 * @brief Set ADC analog watchdog monitored channels:
5687 * a single channel, multiple channels or all channels,
5688 * on ADC groups regular and-or injected.
5689 * @note Once monitored channels are selected, analog watchdog
5690 * is enabled.
5691 * @note In case of need to define a single channel to monitor
5692 * with analog watchdog from sequencer channel definition,
5693 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
5694 * @note On this STM32 series, there are 2 kinds of analog watchdog
5695 * instance:
5696 * - AWD standard (instance AWD1):
5697 * - channels monitored: can monitor 1 channel or all channels.
5698 * - groups monitored: ADC groups regular and-or injected.
5699 * - resolution: resolution is not limited (corresponds to
5700 * ADC resolution configured).
5701 * - AWD flexible (instances AWD2, AWD3):
5702 * - channels monitored: flexible on channels monitored, selection is
5703 * channel wise, from from 1 to all channels.
5704 * Specificity of this analog watchdog: Multiple channels can
5705 * be selected. For example:
5706 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5707 * - groups monitored: not selection possible (monitoring on both
5708 * groups regular and injected).
5709 * Channels selected are monitored on groups regular and injected:
5710 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5711 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5712 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5713 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5714 * the 2 LSB are ignored.
5715 * @note On this STM32 series, setting of this feature is conditioned to
5716 * ADC state:
5717 * ADC must be disabled or enabled without conversion on going
5718 * on either groups regular or injected.
5719 * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
5720 * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
5721 * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5722 * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5723 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
5724 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
5725 * @param ADCx ADC instance
5726 * @param AWDy This parameter can be one of the following values:
5727 * @arg @ref LL_ADC_AWD1
5728 * @arg @ref LL_ADC_AWD2
5729 * @arg @ref LL_ADC_AWD3
5730 * @param AWDChannelGroup This parameter can be one of the following values:
5731 * @arg @ref LL_ADC_AWD_DISABLE
5732 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5733 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5734 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5735 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5736 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5737 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5738 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5739 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5740 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5741 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5742 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5743 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5744 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5745 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5746 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5747 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5748 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5749 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5750 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5751 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5752 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5753 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5754 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5755 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5756 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5757 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5758 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5759 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5760 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5761 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5762 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5763 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5764 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5765 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5766 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5767 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5768 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5769 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5770 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5771 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5772 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5773 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5774 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5775 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5776 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5777 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5778 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5779 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5780 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5781 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5782 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5783 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5784 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5785 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5786 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5787 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5788 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5789 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5790 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5791 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5792 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
5793 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
5794 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
5795 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(4)
5796 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(4)
5797 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (4)
5798 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(4)
5799 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(4)
5800 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (4)
5801 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG (0)(2)(5)
5802 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_INJ (0)(2)(5)
5803 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG_INJ (2)(5)
5804 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG (0)(2)(5)
5805 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_INJ (0)(2)(5)
5806 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG_INJ (2)(5)
5807 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)(6)
5808 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)(6)
5809 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)(6)
5810 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)(6)
5811 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)(6)
5812 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)(6)
5813 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG (0)(3)(6)
5814 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ (0)(3)(6)
5815 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ (3)(6)
5816 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG (0)(3)(6)
5817 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ (0)(3)(6)
5818 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ (3)(6)
5819 *
5820 * (0) On STM32L4, parameter available only on analog watchdog number: AWD1.\n
5821 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
5822 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
5823 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
5824 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
5825 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
5826 * (6) On STM32L4, parameter available on devices with several ADC instances.
5827 * @retval None
5828 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDChannelGroup)5829 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
5830 {
5831 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
5832 /* in register and register position depending on parameter "AWDy". */
5833 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
5834 /* containing other bits reserved for other purpose. */
5835 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR,
5836 ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5837 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
5838 * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5839
5840 MODIFY_REG(*preg,
5841 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
5842 AWDChannelGroup & AWDy);
5843 }
5844
5845 /**
5846 * @brief Get ADC analog watchdog monitored channel.
5847 * @note Usage of the returned channel number:
5848 * - To reinject this channel into another function LL_ADC_xxx:
5849 * the returned channel number is only partly formatted on definition
5850 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
5851 * with parts of literals LL_ADC_CHANNEL_x or using
5852 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5853 * Then the selected literal LL_ADC_CHANNEL_x can be used
5854 * as parameter for another function.
5855 * - To get the channel number in decimal format:
5856 * process the returned value with the helper macro
5857 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5858 * Applicable only when the analog watchdog is set to monitor
5859 * one channel.
5860 * @note On this STM32 series, there are 2 kinds of analog watchdog
5861 * instance:
5862 * - AWD standard (instance AWD1):
5863 * - channels monitored: can monitor 1 channel or all channels.
5864 * - groups monitored: ADC groups regular and-or injected.
5865 * - resolution: resolution is not limited (corresponds to
5866 * ADC resolution configured).
5867 * - AWD flexible (instances AWD2, AWD3):
5868 * - channels monitored: flexible on channels monitored, selection is
5869 * channel wise, from from 1 to all channels.
5870 * Specificity of this analog watchdog: Multiple channels can
5871 * be selected. For example:
5872 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5873 * - groups monitored: not selection possible (monitoring on both
5874 * groups regular and injected).
5875 * Channels selected are monitored on groups regular and injected:
5876 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5877 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5878 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5879 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5880 * the 2 LSB are ignored.
5881 * @note On this STM32 series, setting of this feature is conditioned to
5882 * ADC state:
5883 * ADC must be disabled or enabled without conversion on going
5884 * on either groups regular or injected.
5885 * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
5886 * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
5887 * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5888 * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5889 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
5890 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
5891 * @param ADCx ADC instance
5892 * @param AWDy This parameter can be one of the following values:
5893 * @arg @ref LL_ADC_AWD1
5894 * @arg @ref LL_ADC_AWD2 (1)
5895 * @arg @ref LL_ADC_AWD3 (1)
5896 *
5897 * (1) On this AWD number, monitored channel can be retrieved
5898 * if only 1 channel is programmed (or none or all channels).
5899 * This function cannot retrieve monitored channel if
5900 * multiple channels are programmed simultaneously
5901 * by bitfield.
5902 * @retval Returned value can be one of the following values:
5903 * @arg @ref LL_ADC_AWD_DISABLE
5904 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5905 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5906 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5907 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5908 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5909 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5910 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5911 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5912 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5913 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5914 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5915 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5916 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5917 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5918 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5919 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5920 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5921 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5922 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5923 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5924 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5925 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5926 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5927 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5928 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5929 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5930 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5931 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5932 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5933 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5934 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5935 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5936 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5937 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5938 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5939 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5940 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5941 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5942 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5943 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5944 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5945 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5946 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5947 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5948 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5949 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5950 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5951 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5952 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5953 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5954 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5955 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5956 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5957 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5958 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5959 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5960 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5961 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5962 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5963 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5964 *
5965 * (0) On STM32L4, parameter available only on analog watchdog number: AWD1.
5966 */
LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef * ADCx,uint32_t AWDy)5967 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy)
5968 {
5969 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR,
5970 ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5971 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
5972 * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5973
5974 uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
5975
5976 /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */
5977 /* (parameter value LL_ADC_AWD_DISABLE). */
5978 /* Else, the selected AWD is enabled and is monitoring a group of channels */
5979 /* or a single channel. */
5980 if (analog_wd_monit_channels != 0UL)
5981 {
5982 if (AWDy == LL_ADC_AWD1)
5983 {
5984 if ((analog_wd_monit_channels & ADC_CFGR_AWD1SGL) == 0UL)
5985 {
5986 /* AWD monitoring a group of channels */
5987 analog_wd_monit_channels = ((analog_wd_monit_channels
5988 | (ADC_AWD_CR23_CHANNEL_MASK)
5989 )
5990 & (~(ADC_CFGR_AWD1CH))
5991 );
5992 }
5993 else
5994 {
5995 /* AWD monitoring a single channel */
5996 analog_wd_monit_channels = (analog_wd_monit_channels
5997 | (ADC_AWD2CR_AWD2CH_0 << (analog_wd_monit_channels >> ADC_CFGR_AWD1CH_Pos))
5998 );
5999 }
6000 }
6001 else
6002 {
6003 if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
6004 {
6005 /* AWD monitoring a group of channels */
6006 analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK
6007 | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
6008 );
6009 }
6010 else
6011 {
6012 /* AWD monitoring a single channel */
6013 /* AWD monitoring a group of channels */
6014 analog_wd_monit_channels = (analog_wd_monit_channels
6015 | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
6016 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) << ADC_CFGR_AWD1CH_Pos)
6017 );
6018 }
6019 }
6020 }
6021
6022 return analog_wd_monit_channels;
6023 }
6024
6025 /**
6026 * @brief Set ADC analog watchdog thresholds value of both thresholds
6027 * high and low.
6028 * @note If value of only one threshold high or low must be set,
6029 * use function @ref LL_ADC_SetAnalogWDThresholds().
6030 * @note In case of ADC resolution different of 12 bits,
6031 * analog watchdog thresholds data require a specific shift.
6032 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
6033 * @note On this STM32 series, there are 2 kinds of analog watchdog
6034 * instance:
6035 * - AWD standard (instance AWD1):
6036 * - channels monitored: can monitor 1 channel or all channels.
6037 * - groups monitored: ADC groups regular and-or injected.
6038 * - resolution: resolution is not limited (corresponds to
6039 * ADC resolution configured).
6040 * - AWD flexible (instances AWD2, AWD3):
6041 * - channels monitored: flexible on channels monitored, selection is
6042 * channel wise, from from 1 to all channels.
6043 * Specificity of this analog watchdog: Multiple channels can
6044 * be selected. For example:
6045 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
6046 * - groups monitored: not selection possible (monitoring on both
6047 * groups regular and injected).
6048 * Channels selected are monitored on groups regular and injected:
6049 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
6050 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
6051 * - resolution: resolution is limited to 8 bits: if ADC resolution is
6052 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
6053 * the 2 LSB are ignored.
6054 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
6055 * impacted: the comparison of analog watchdog thresholds is done on
6056 * oversampling final computation (after ratio and shift application):
6057 * ADC data register bitfield [15:4] (12 most significant bits).
6058 * Examples:
6059 * - Oversampling ratio and shift selected to have ADC conversion data
6060 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
6061 * ADC analog watchdog thresholds must be divided by 16.
6062 * - Oversampling ratio and shift selected to have ADC conversion data
6063 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
6064 * ADC analog watchdog thresholds must be divided by 4.
6065 * - Oversampling ratio and shift selected to have ADC conversion data
6066 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
6067 * ADC analog watchdog thresholds match directly to ADC data register.
6068 * @note On this STM32 series, setting of this feature is conditioned to
6069 * ADC state:
6070 * ADC must be disabled or enabled without conversion on going
6071 * on either groups regular or injected.
6072 * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
6073 * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
6074 * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
6075 * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
6076 * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
6077 * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
6078 * @param ADCx ADC instance
6079 * @param AWDy This parameter can be one of the following values:
6080 * @arg @ref LL_ADC_AWD1
6081 * @arg @ref LL_ADC_AWD2
6082 * @arg @ref LL_ADC_AWD3
6083 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
6084 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
6085 * @retval None
6086 */
LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdHighValue,uint32_t AWDThresholdLowValue)6087 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
6088 uint32_t AWDThresholdLowValue)
6089 {
6090 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
6091 /* position in register and register position depending on parameter */
6092 /* "AWDy". */
6093 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
6094 /* containing other bits reserved for other purpose. */
6095 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
6096 ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6097
6098 MODIFY_REG(*preg,
6099 ADC_TR1_HT1 | ADC_TR1_LT1,
6100 (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
6101 }
6102
6103 /**
6104 * @brief Set ADC analog watchdog threshold value of threshold
6105 * high or low.
6106 * @note If values of both thresholds high or low must be set,
6107 * use function @ref LL_ADC_ConfigAnalogWDThresholds().
6108 * @note In case of ADC resolution different of 12 bits,
6109 * analog watchdog thresholds data require a specific shift.
6110 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
6111 * @note On this STM32 series, there are 2 kinds of analog watchdog
6112 * instance:
6113 * - AWD standard (instance AWD1):
6114 * - channels monitored: can monitor 1 channel or all channels.
6115 * - groups monitored: ADC groups regular and-or injected.
6116 * - resolution: resolution is not limited (corresponds to
6117 * ADC resolution configured).
6118 * - AWD flexible (instances AWD2, AWD3):
6119 * - channels monitored: flexible on channels monitored, selection is
6120 * channel wise, from from 1 to all channels.
6121 * Specificity of this analog watchdog: Multiple channels can
6122 * be selected. For example:
6123 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
6124 * - groups monitored: not selection possible (monitoring on both
6125 * groups regular and injected).
6126 * Channels selected are monitored on groups regular and injected:
6127 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
6128 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
6129 * - resolution: resolution is limited to 8 bits: if ADC resolution is
6130 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
6131 * the 2 LSB are ignored.
6132 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
6133 * impacted: the comparison of analog watchdog thresholds is done on
6134 * oversampling final computation (after ratio and shift application):
6135 * ADC data register bitfield [15:4] (12 most significant bits).
6136 * Examples:
6137 * - Oversampling ratio and shift selected to have ADC conversion data
6138 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
6139 * ADC analog watchdog thresholds must be divided by 16.
6140 * - Oversampling ratio and shift selected to have ADC conversion data
6141 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
6142 * ADC analog watchdog thresholds must be divided by 4.
6143 * - Oversampling ratio and shift selected to have ADC conversion data
6144 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
6145 * ADC analog watchdog thresholds match directly to ADC data register.
6146 * @note On this STM32 series, setting of this feature is conditioned to
6147 * ADC state:
6148 * ADC must be disabled or enabled without conversion on going
6149 * on either ADC groups regular or injected.
6150 * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
6151 * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
6152 * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
6153 * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
6154 * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
6155 * TR3 LT3 LL_ADC_SetAnalogWDThresholds
6156 * @param ADCx ADC instance
6157 * @param AWDy This parameter can be one of the following values:
6158 * @arg @ref LL_ADC_AWD1
6159 * @arg @ref LL_ADC_AWD2
6160 * @arg @ref LL_ADC_AWD3
6161 * @param AWDThresholdsHighLow This parameter can be one of the following values:
6162 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
6163 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
6164 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
6165 * @retval None
6166 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)6167 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
6168 uint32_t AWDThresholdValue)
6169 {
6170 /* Set bits with content of parameter "AWDThresholdValue" with bits */
6171 /* position in register and register position depending on parameters */
6172 /* "AWDThresholdsHighLow" and "AWDy". */
6173 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
6174 /* containing other bits reserved for other purpose. */
6175 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
6176 ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6177
6178 MODIFY_REG(*preg,
6179 AWDThresholdsHighLow,
6180 AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
6181 }
6182
6183 /**
6184 * @brief Get ADC analog watchdog threshold value of threshold high,
6185 * threshold low or raw data with ADC thresholds high and low
6186 * concatenated.
6187 * @note If raw data with ADC thresholds high and low is retrieved,
6188 * the data of each threshold high or low can be isolated
6189 * using helper macro:
6190 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
6191 * @note In case of ADC resolution different of 12 bits,
6192 * analog watchdog thresholds data require a specific shift.
6193 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
6194 * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
6195 * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
6196 * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
6197 * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
6198 * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
6199 * TR3 LT3 LL_ADC_GetAnalogWDThresholds
6200 * @param ADCx ADC instance
6201 * @param AWDy This parameter can be one of the following values:
6202 * @arg @ref LL_ADC_AWD1
6203 * @arg @ref LL_ADC_AWD2
6204 * @arg @ref LL_ADC_AWD3
6205 * @param AWDThresholdsHighLow This parameter can be one of the following values:
6206 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
6207 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
6208 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
6209 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6210 */
LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow)6211 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx,
6212 uint32_t AWDy, uint32_t AWDThresholdsHighLow)
6213 {
6214 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
6215 ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6216
6217 return (uint32_t)(READ_BIT(*preg,
6218 (AWDThresholdsHighLow | ADC_TR1_LT1))
6219 >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
6220 & ~(AWDThresholdsHighLow & ADC_TR1_LT1)));
6221 }
6222
6223 /**
6224 * @}
6225 */
6226
6227 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
6228 * @{
6229 */
6230
6231 /**
6232 * @brief Set ADC oversampling scope: ADC groups regular and-or injected
6233 * (availability of ADC group injected depends on STM32 series).
6234 * @note If both groups regular and injected are selected,
6235 * specify behavior of ADC group injected interrupting
6236 * group regular: when ADC group injected is triggered,
6237 * the oversampling on ADC group regular is either
6238 * temporary stopped and continued, or resumed from start
6239 * (oversampler buffer reset).
6240 * @note On this STM32 series, setting of this feature is conditioned to
6241 * ADC state:
6242 * ADC must be disabled or enabled without conversion on going
6243 * on either groups regular or injected.
6244 * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n
6245 * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n
6246 * CFGR2 ROVSM LL_ADC_SetOverSamplingScope
6247 * @param ADCx ADC instance
6248 * @param OvsScope This parameter can be one of the following values:
6249 * @arg @ref LL_ADC_OVS_DISABLE
6250 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
6251 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
6252 * @arg @ref LL_ADC_OVS_GRP_INJECTED
6253 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
6254 * @retval None
6255 */
LL_ADC_SetOverSamplingScope(ADC_TypeDef * ADCx,uint32_t OvsScope)6256 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
6257 {
6258 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
6259 }
6260
6261 /**
6262 * @brief Get ADC oversampling scope: ADC groups regular and-or injected
6263 * (availability of ADC group injected depends on STM32 series).
6264 * @note If both groups regular and injected are selected,
6265 * specify behavior of ADC group injected interrupting
6266 * group regular: when ADC group injected is triggered,
6267 * the oversampling on ADC group regular is either
6268 * temporary stopped and continued, or resumed from start
6269 * (oversampler buffer reset).
6270 * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n
6271 * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n
6272 * CFGR2 ROVSM LL_ADC_GetOverSamplingScope
6273 * @param ADCx ADC instance
6274 * @retval Returned value can be one of the following values:
6275 * @arg @ref LL_ADC_OVS_DISABLE
6276 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
6277 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
6278 * @arg @ref LL_ADC_OVS_GRP_INJECTED
6279 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
6280 */
LL_ADC_GetOverSamplingScope(const ADC_TypeDef * ADCx)6281 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx)
6282 {
6283 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
6284 }
6285
6286 /**
6287 * @brief Set ADC oversampling discontinuous mode (triggered mode)
6288 * on the selected ADC group.
6289 * @note Number of oversampled conversions are done either in:
6290 * - continuous mode (all conversions of oversampling ratio
6291 * are done from 1 trigger)
6292 * - discontinuous mode (each conversion of oversampling ratio
6293 * needs a trigger)
6294 * @note On this STM32 series, setting of this feature is conditioned to
6295 * ADC state:
6296 * ADC must be disabled or enabled without conversion on going
6297 * on group regular.
6298 * @note On this STM32 series, oversampling discontinuous mode
6299 * (triggered mode) can be used only when oversampling is
6300 * set on group regular only and in resumed mode.
6301 * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
6302 * @param ADCx ADC instance
6303 * @param OverSamplingDiscont This parameter can be one of the following values:
6304 * @arg @ref LL_ADC_OVS_REG_CONT
6305 * @arg @ref LL_ADC_OVS_REG_DISCONT
6306 * @retval None
6307 */
LL_ADC_SetOverSamplingDiscont(ADC_TypeDef * ADCx,uint32_t OverSamplingDiscont)6308 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
6309 {
6310 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
6311 }
6312
6313 /**
6314 * @brief Get ADC oversampling discontinuous mode (triggered mode)
6315 * on the selected ADC group.
6316 * @note Number of oversampled conversions are done either in:
6317 * - continuous mode (all conversions of oversampling ratio
6318 * are done from 1 trigger)
6319 * - discontinuous mode (each conversion of oversampling ratio
6320 * needs a trigger)
6321 * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
6322 * @param ADCx ADC instance
6323 * @retval Returned value can be one of the following values:
6324 * @arg @ref LL_ADC_OVS_REG_CONT
6325 * @arg @ref LL_ADC_OVS_REG_DISCONT
6326 */
LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef * ADCx)6327 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx)
6328 {
6329 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
6330 }
6331
6332 /**
6333 * @brief Set ADC oversampling
6334 * (impacting both ADC groups regular and injected)
6335 * @note This function set the 2 items of oversampling configuration:
6336 * - ratio
6337 * - shift
6338 * @note On this STM32 series, setting of this feature is conditioned to
6339 * ADC state:
6340 * ADC must be disabled or enabled without conversion on going
6341 * on either groups regular or injected.
6342 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
6343 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
6344 * @param ADCx ADC instance
6345 * @param Ratio This parameter can be one of the following values:
6346 * @arg @ref LL_ADC_OVS_RATIO_2
6347 * @arg @ref LL_ADC_OVS_RATIO_4
6348 * @arg @ref LL_ADC_OVS_RATIO_8
6349 * @arg @ref LL_ADC_OVS_RATIO_16
6350 * @arg @ref LL_ADC_OVS_RATIO_32
6351 * @arg @ref LL_ADC_OVS_RATIO_64
6352 * @arg @ref LL_ADC_OVS_RATIO_128
6353 * @arg @ref LL_ADC_OVS_RATIO_256
6354 * @param Shift This parameter can be one of the following values:
6355 * @arg @ref LL_ADC_OVS_SHIFT_NONE
6356 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
6357 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
6358 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
6359 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
6360 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
6361 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
6362 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
6363 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
6364 * @retval None
6365 */
LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef * ADCx,uint32_t Ratio,uint32_t Shift)6366 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
6367 {
6368 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
6369 }
6370
6371 /**
6372 * @brief Get ADC oversampling ratio
6373 * (impacting both ADC groups regular and injected)
6374 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
6375 * @param ADCx ADC instance
6376 * @retval Ratio This parameter can be one of the following values:
6377 * @arg @ref LL_ADC_OVS_RATIO_2
6378 * @arg @ref LL_ADC_OVS_RATIO_4
6379 * @arg @ref LL_ADC_OVS_RATIO_8
6380 * @arg @ref LL_ADC_OVS_RATIO_16
6381 * @arg @ref LL_ADC_OVS_RATIO_32
6382 * @arg @ref LL_ADC_OVS_RATIO_64
6383 * @arg @ref LL_ADC_OVS_RATIO_128
6384 * @arg @ref LL_ADC_OVS_RATIO_256
6385 */
LL_ADC_GetOverSamplingRatio(const ADC_TypeDef * ADCx)6386 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx)
6387 {
6388 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
6389 }
6390
6391 /**
6392 * @brief Get ADC oversampling shift
6393 * (impacting both ADC groups regular and injected)
6394 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
6395 * @param ADCx ADC instance
6396 * @retval Shift This parameter can be one of the following values:
6397 * @arg @ref LL_ADC_OVS_SHIFT_NONE
6398 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
6399 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
6400 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
6401 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
6402 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
6403 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
6404 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
6405 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
6406 */
LL_ADC_GetOverSamplingShift(const ADC_TypeDef * ADCx)6407 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx)
6408 {
6409 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
6410 }
6411
6412 /**
6413 * @}
6414 */
6415
6416 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
6417 * @{
6418 */
6419
6420 #if defined(ADC_MULTIMODE_SUPPORT)
6421 /**
6422 * @brief Set ADC multimode configuration to operate in independent mode
6423 * or multimode (for devices with several ADC instances).
6424 * @note If multimode configuration: the selected ADC instance is
6425 * either master or slave depending on hardware.
6426 * Refer to reference manual.
6427 * @note On this STM32 series, setting of this feature is conditioned to
6428 * ADC state:
6429 * All ADC instances of the ADC common group must be disabled.
6430 * This check can be done with function @ref LL_ADC_IsEnabled() for each
6431 * ADC instance or by using helper macro
6432 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
6433 * @rmtoll CCR DUAL LL_ADC_SetMultimode
6434 * @param ADCxy_COMMON ADC common instance
6435 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6436 * @param Multimode This parameter can be one of the following values:
6437 * @arg @ref LL_ADC_MULTI_INDEPENDENT
6438 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
6439 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
6440 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
6441 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
6442 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
6443 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
6444 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
6445 * @retval None
6446 */
LL_ADC_SetMultimode(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t Multimode)6447 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
6448 {
6449 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
6450 }
6451
6452 /**
6453 * @brief Get ADC multimode configuration to operate in independent mode
6454 * or multimode (for devices with several ADC instances).
6455 * @note If multimode configuration: the selected ADC instance is
6456 * either master or slave depending on hardware.
6457 * Refer to reference manual.
6458 * @rmtoll CCR DUAL LL_ADC_GetMultimode
6459 * @param ADCxy_COMMON ADC common instance
6460 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6461 * @retval Returned value can be one of the following values:
6462 * @arg @ref LL_ADC_MULTI_INDEPENDENT
6463 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
6464 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
6465 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
6466 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
6467 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
6468 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
6469 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
6470 */
LL_ADC_GetMultimode(const ADC_Common_TypeDef * ADCxy_COMMON)6471 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON)
6472 {
6473 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
6474 }
6475
6476 /**
6477 * @brief Set ADC multimode conversion data transfer: no transfer
6478 * or transfer by DMA.
6479 * @note If ADC multimode transfer by DMA is not selected:
6480 * each ADC uses its own DMA channel, with its individual
6481 * DMA transfer settings.
6482 * If ADC multimode transfer by DMA is selected:
6483 * One DMA channel is used for both ADC (DMA of ADC master)
6484 * Specifies the DMA requests mode:
6485 * - Limited mode (One shot mode): DMA transfer requests are stopped
6486 * when number of DMA data transfers (number of
6487 * ADC conversions) is reached.
6488 * This ADC mode is intended to be used with DMA mode non-circular.
6489 * - Unlimited mode: DMA transfer requests are unlimited,
6490 * whatever number of DMA data transfers (number of
6491 * ADC conversions).
6492 * This ADC mode is intended to be used with DMA mode circular.
6493 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
6494 * mode non-circular:
6495 * when DMA transfers size will be reached, DMA will stop transfers of
6496 * ADC conversions data ADC will raise an overrun error
6497 * (overrun flag and interruption if enabled).
6498 * @note How to retrieve multimode conversion data:
6499 * Whatever multimode transfer by DMA setting: using function
6500 * @ref LL_ADC_REG_ReadMultiConversionData32().
6501 * If ADC multimode transfer by DMA is selected: conversion data
6502 * is a raw data with ADC master and slave concatenated.
6503 * A macro is available to get the conversion data of
6504 * ADC master or ADC slave: see helper macro
6505 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6506 * @note On this STM32 series, setting of this feature is conditioned to
6507 * ADC state:
6508 * All ADC instances of the ADC common group must be disabled
6509 * or enabled without conversion on going on group regular.
6510 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
6511 * CCR DMACFG LL_ADC_SetMultiDMATransfer
6512 * @param ADCxy_COMMON ADC common instance
6513 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6514 * @param MultiDMATransfer This parameter can be one of the following values:
6515 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
6516 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
6517 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
6518 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
6519 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
6520 * @retval None
6521 */
LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiDMATransfer)6522 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
6523 {
6524 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);
6525 }
6526
6527 /**
6528 * @brief Get ADC multimode conversion data transfer: no transfer
6529 * or transfer by DMA.
6530 * @note If ADC multimode transfer by DMA is not selected:
6531 * each ADC uses its own DMA channel, with its individual
6532 * DMA transfer settings.
6533 * If ADC multimode transfer by DMA is selected:
6534 * One DMA channel is used for both ADC (DMA of ADC master)
6535 * Specifies the DMA requests mode:
6536 * - Limited mode (One shot mode): DMA transfer requests are stopped
6537 * when number of DMA data transfers (number of
6538 * ADC conversions) is reached.
6539 * This ADC mode is intended to be used with DMA mode non-circular.
6540 * - Unlimited mode: DMA transfer requests are unlimited,
6541 * whatever number of DMA data transfers (number of
6542 * ADC conversions).
6543 * This ADC mode is intended to be used with DMA mode circular.
6544 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
6545 * mode non-circular:
6546 * when DMA transfers size will be reached, DMA will stop transfers of
6547 * ADC conversions data ADC will raise an overrun error
6548 * (overrun flag and interruption if enabled).
6549 * @note How to retrieve multimode conversion data:
6550 * Whatever multimode transfer by DMA setting: using function
6551 * @ref LL_ADC_REG_ReadMultiConversionData32().
6552 * If ADC multimode transfer by DMA is selected: conversion data
6553 * is a raw data with ADC master and slave concatenated.
6554 * A macro is available to get the conversion data of
6555 * ADC master or ADC slave: see helper macro
6556 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6557 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
6558 * CCR DMACFG LL_ADC_GetMultiDMATransfer
6559 * @param ADCxy_COMMON ADC common instance
6560 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6561 * @retval Returned value can be one of the following values:
6562 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
6563 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
6564 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
6565 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
6566 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
6567 */
LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef * ADCxy_COMMON)6568 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON)
6569 {
6570 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
6571 }
6572
6573 /**
6574 * @brief Set ADC multimode delay between 2 sampling phases.
6575 * @note The sampling delay range depends on ADC resolution:
6576 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
6577 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
6578 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
6579 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
6580 * @note On this STM32 series, setting of this feature is conditioned to
6581 * ADC state:
6582 * All ADC instances of the ADC common group must be disabled.
6583 * This check can be done with function @ref LL_ADC_IsEnabled() for each
6584 * ADC instance or by using helper macro helper macro
6585 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
6586 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
6587 * @param ADCxy_COMMON ADC common instance
6588 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6589 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
6590 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
6591 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
6592 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
6593 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
6594 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
6595 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
6596 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
6597 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
6598 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
6599 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
6600 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
6601 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
6602 *
6603 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
6604 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
6605 * (3) Parameter available only if ADC resolution is 12 bits.
6606 * @retval None
6607 */
LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiTwoSamplingDelay)6608 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
6609 {
6610 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
6611 }
6612
6613 /**
6614 * @brief Get ADC multimode delay between 2 sampling phases.
6615 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
6616 * @param ADCxy_COMMON ADC common instance
6617 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6618 * @retval Returned value can be one of the following values:
6619 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
6620 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
6621 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
6622 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
6623 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
6624 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
6625 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
6626 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
6627 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
6628 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
6629 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
6630 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
6631 *
6632 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
6633 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
6634 * (3) Parameter available only if ADC resolution is 12 bits.
6635 */
LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef * ADCxy_COMMON)6636 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON)
6637 {
6638 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
6639 }
6640 #endif /* ADC_MULTIMODE_SUPPORT */
6641
6642 /**
6643 * @}
6644 */
6645 /** @defgroup ADC_LL_EF_Configuration_Leg_Functions Configuration of ADC alternate functions name
6646 * @{
6647 */
6648 /* Old functions name kept for legacy purpose, to be replaced by the */
6649 /* current functions name. */
LL_ADC_REG_SetTrigSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)6650 __STATIC_INLINE void LL_ADC_REG_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
6651 {
6652 LL_ADC_REG_SetTriggerSource(ADCx, TriggerSource);
6653 }
LL_ADC_INJ_SetTrigSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)6654 __STATIC_INLINE void LL_ADC_INJ_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
6655 {
6656 LL_ADC_INJ_SetTriggerSource(ADCx, TriggerSource);
6657 }
6658
6659 /**
6660 * @}
6661 */
6662
6663 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
6664 * @{
6665 */
6666
6667 /**
6668 * @brief Put ADC instance in deep power down state.
6669 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
6670 * state, the internal analog calibration is lost. After exiting from
6671 * deep power down, calibration must be relaunched or calibration factor
6672 * (preliminarily saved) must be set back into calibration register.
6673 * @note On this STM32 series, setting of this feature is conditioned to
6674 * ADC state:
6675 * ADC must be ADC disabled.
6676 * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
6677 * @param ADCx ADC instance
6678 * @retval None
6679 */
LL_ADC_EnableDeepPowerDown(ADC_TypeDef * ADCx)6680 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
6681 {
6682 /* Note: Write register with some additional bits forced to state reset */
6683 /* instead of modifying only the selected bit for this function, */
6684 /* to not interfere with bits with HW property "rs". */
6685 MODIFY_REG(ADCx->CR,
6686 ADC_CR_BITS_PROPERTY_RS,
6687 ADC_CR_DEEPPWD);
6688 }
6689
6690 /**
6691 * @brief Disable ADC deep power down mode.
6692 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
6693 * state, the internal analog calibration is lost. After exiting from
6694 * deep power down, calibration must be relaunched or calibration factor
6695 * (preliminarily saved) must be set back into calibration register.
6696 * @note On this STM32 series, setting of this feature is conditioned to
6697 * ADC state:
6698 * ADC must be ADC disabled.
6699 * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
6700 * @param ADCx ADC instance
6701 * @retval None
6702 */
LL_ADC_DisableDeepPowerDown(ADC_TypeDef * ADCx)6703 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
6704 {
6705 /* Note: Write register with some additional bits forced to state reset */
6706 /* instead of modifying only the selected bit for this function, */
6707 /* to not interfere with bits with HW property "rs". */
6708 CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
6709 }
6710
6711 /**
6712 * @brief Get the selected ADC instance deep power down state.
6713 * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
6714 * @param ADCx ADC instance
6715 * @retval 0: deep power down is disabled, 1: deep power down is enabled.
6716 */
LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef * ADCx)6717 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx)
6718 {
6719 return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
6720 }
6721
6722 /**
6723 * @brief Enable ADC instance internal voltage regulator.
6724 * @note On this STM32 series, after ADC internal voltage regulator enable,
6725 * a delay for ADC internal voltage regulator stabilization
6726 * is required before performing a ADC calibration or ADC enable.
6727 * Refer to device datasheet, parameter tADCVREG_STUP.
6728 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
6729 * @note On this STM32 series, setting of this feature is conditioned to
6730 * ADC state:
6731 * ADC must be ADC disabled.
6732 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
6733 * @param ADCx ADC instance
6734 * @retval None
6735 */
LL_ADC_EnableInternalRegulator(ADC_TypeDef * ADCx)6736 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
6737 {
6738 /* Note: Write register with some additional bits forced to state reset */
6739 /* instead of modifying only the selected bit for this function, */
6740 /* to not interfere with bits with HW property "rs". */
6741 MODIFY_REG(ADCx->CR,
6742 ADC_CR_BITS_PROPERTY_RS,
6743 ADC_CR_ADVREGEN);
6744 }
6745
6746 /**
6747 * @brief Disable ADC internal voltage regulator.
6748 * @note On this STM32 series, setting of this feature is conditioned to
6749 * ADC state:
6750 * ADC must be ADC disabled.
6751 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
6752 * @param ADCx ADC instance
6753 * @retval None
6754 */
LL_ADC_DisableInternalRegulator(ADC_TypeDef * ADCx)6755 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
6756 {
6757 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
6758 }
6759
6760 /**
6761 * @brief Get the selected ADC instance internal voltage regulator state.
6762 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
6763 * @param ADCx ADC instance
6764 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
6765 */
LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef * ADCx)6766 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx)
6767 {
6768 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
6769 }
6770
6771 /**
6772 * @brief Enable the selected ADC instance.
6773 * @note On this STM32 series, after ADC enable, a delay for
6774 * ADC internal analog stabilization is required before performing a
6775 * ADC conversion start.
6776 * Refer to device datasheet, parameter tSTAB.
6777 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6778 * is enabled and when conversion clock is active.
6779 * (not only core clock: this ADC has a dual clock domain)
6780 * @note On this STM32 series, setting of this feature is conditioned to
6781 * ADC state:
6782 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
6783 * @rmtoll CR ADEN LL_ADC_Enable
6784 * @param ADCx ADC instance
6785 * @retval None
6786 */
LL_ADC_Enable(ADC_TypeDef * ADCx)6787 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
6788 {
6789 /* Note: Write register with some additional bits forced to state reset */
6790 /* instead of modifying only the selected bit for this function, */
6791 /* to not interfere with bits with HW property "rs". */
6792 MODIFY_REG(ADCx->CR,
6793 ADC_CR_BITS_PROPERTY_RS,
6794 ADC_CR_ADEN);
6795 }
6796
6797 /**
6798 * @brief Disable the selected ADC instance.
6799 * @note On this STM32 series, setting of this feature is conditioned to
6800 * ADC state:
6801 * ADC must be not disabled. Must be enabled without conversion on going
6802 * on either groups regular or injected.
6803 * @rmtoll CR ADDIS LL_ADC_Disable
6804 * @param ADCx ADC instance
6805 * @retval None
6806 */
LL_ADC_Disable(ADC_TypeDef * ADCx)6807 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
6808 {
6809 /* Note: Write register with some additional bits forced to state reset */
6810 /* instead of modifying only the selected bit for this function, */
6811 /* to not interfere with bits with HW property "rs". */
6812 MODIFY_REG(ADCx->CR,
6813 ADC_CR_BITS_PROPERTY_RS,
6814 ADC_CR_ADDIS);
6815 }
6816
6817 /**
6818 * @brief Get the selected ADC instance enable state.
6819 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6820 * is enabled and when conversion clock is active.
6821 * (not only core clock: this ADC has a dual clock domain)
6822 * @rmtoll CR ADEN LL_ADC_IsEnabled
6823 * @param ADCx ADC instance
6824 * @retval 0: ADC is disabled, 1: ADC is enabled.
6825 */
LL_ADC_IsEnabled(const ADC_TypeDef * ADCx)6826 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
6827 {
6828 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
6829 }
6830
6831 /**
6832 * @brief Get the selected ADC instance disable state.
6833 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
6834 * @param ADCx ADC instance
6835 * @retval 0: no ADC disable command on going.
6836 */
LL_ADC_IsDisableOngoing(const ADC_TypeDef * ADCx)6837 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
6838 {
6839 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
6840 }
6841
6842 /**
6843 * @brief Start ADC calibration in the mode single-ended
6844 * or differential (for devices with differential mode available).
6845 * @note On this STM32 series, a minimum number of ADC clock cycles
6846 * are required between ADC end of calibration and ADC enable.
6847 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
6848 * @note For devices with differential mode available:
6849 * Calibration of offset is specific to each of
6850 * single-ended and differential modes
6851 * (calibration run must be performed for each of these
6852 * differential modes, if used afterwards and if the application
6853 * requires their calibration).
6854 * @note On this STM32 series, setting of this feature is conditioned to
6855 * ADC state:
6856 * ADC must be ADC disabled.
6857 * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
6858 * CR ADCALDIF LL_ADC_StartCalibration
6859 * @param ADCx ADC instance
6860 * @param SingleDiff This parameter can be one of the following values:
6861 * @arg @ref LL_ADC_SINGLE_ENDED
6862 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
6863 * @retval None
6864 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx,uint32_t SingleDiff)6865 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
6866 {
6867 /* Note: Write register with some additional bits forced to state reset */
6868 /* instead of modifying only the selected bit for this function, */
6869 /* to not interfere with bits with HW property "rs". */
6870 MODIFY_REG(ADCx->CR,
6871 ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
6872 ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
6873 }
6874
6875 /**
6876 * @brief Get ADC calibration state.
6877 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
6878 * @param ADCx ADC instance
6879 * @retval 0: calibration complete, 1: calibration in progress.
6880 */
LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef * ADCx)6881 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx)
6882 {
6883 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
6884 }
6885
6886 /**
6887 * @}
6888 */
6889
6890 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
6891 * @{
6892 */
6893
6894 /**
6895 * @brief Start ADC group regular conversion.
6896 * @note On this STM32 series, this function is relevant for both
6897 * internal trigger (SW start) and external trigger:
6898 * - If ADC trigger has been set to software start, ADC conversion
6899 * starts immediately.
6900 * - If ADC trigger has been set to external trigger, ADC conversion
6901 * will start at next trigger event (on the selected trigger edge)
6902 * following the ADC start conversion command.
6903 * @note On this STM32 series, setting of this feature is conditioned to
6904 * ADC state:
6905 * ADC must be enabled without conversion on going on group regular,
6906 * without conversion stop command on going on group regular,
6907 * without ADC disable command on going.
6908 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
6909 * @param ADCx ADC instance
6910 * @retval None
6911 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)6912 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
6913 {
6914 /* Note: Write register with some additional bits forced to state reset */
6915 /* instead of modifying only the selected bit for this function, */
6916 /* to not interfere with bits with HW property "rs". */
6917 MODIFY_REG(ADCx->CR,
6918 ADC_CR_BITS_PROPERTY_RS,
6919 ADC_CR_ADSTART);
6920 }
6921
6922 /**
6923 * @brief Stop ADC group regular conversion.
6924 * @note On this STM32 series, setting of this feature is conditioned to
6925 * ADC state:
6926 * ADC must be enabled with conversion on going on group regular,
6927 * without ADC disable command on going.
6928 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
6929 * @param ADCx ADC instance
6930 * @retval None
6931 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)6932 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
6933 {
6934 /* Note: Write register with some additional bits forced to state reset */
6935 /* instead of modifying only the selected bit for this function, */
6936 /* to not interfere with bits with HW property "rs". */
6937 MODIFY_REG(ADCx->CR,
6938 ADC_CR_BITS_PROPERTY_RS,
6939 ADC_CR_ADSTP);
6940 }
6941
6942 /**
6943 * @brief Get ADC group regular conversion state.
6944 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
6945 * @param ADCx ADC instance
6946 * @retval 0: no conversion is on going on ADC group regular.
6947 */
LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef * ADCx)6948 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
6949 {
6950 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
6951 }
6952
6953 /**
6954 * @brief Get ADC group regular command of conversion stop state
6955 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
6956 * @param ADCx ADC instance
6957 * @retval 0: no command of conversion stop is on going on ADC group regular.
6958 */
LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef * ADCx)6959 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
6960 {
6961 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
6962 }
6963
6964 /**
6965 * @brief Get ADC group regular conversion data, range fit for
6966 * all ADC configurations: all ADC resolutions and
6967 * all oversampling increased data width (for devices
6968 * with feature oversampling).
6969 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
6970 * @param ADCx ADC instance
6971 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6972 */
LL_ADC_REG_ReadConversionData32(const ADC_TypeDef * ADCx)6973 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx)
6974 {
6975 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6976 }
6977
6978 /**
6979 * @brief Get ADC group regular conversion data, range fit for
6980 * ADC resolution 12 bits.
6981 * @note For devices with feature oversampling: Oversampling
6982 * can increase data width, function for extended range
6983 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6984 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
6985 * @param ADCx ADC instance
6986 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6987 */
LL_ADC_REG_ReadConversionData12(const ADC_TypeDef * ADCx)6988 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx)
6989 {
6990 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6991 }
6992
6993 /**
6994 * @brief Get ADC group regular conversion data, range fit for
6995 * ADC resolution 10 bits.
6996 * @note For devices with feature oversampling: Oversampling
6997 * can increase data width, function for extended range
6998 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6999 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
7000 * @param ADCx ADC instance
7001 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
7002 */
LL_ADC_REG_ReadConversionData10(const ADC_TypeDef * ADCx)7003 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx)
7004 {
7005 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7006 }
7007
7008 /**
7009 * @brief Get ADC group regular conversion data, range fit for
7010 * ADC resolution 8 bits.
7011 * @note For devices with feature oversampling: Oversampling
7012 * can increase data width, function for extended range
7013 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
7014 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
7015 * @param ADCx ADC instance
7016 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
7017 */
LL_ADC_REG_ReadConversionData8(const ADC_TypeDef * ADCx)7018 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx)
7019 {
7020 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7021 }
7022
7023 /**
7024 * @brief Get ADC group regular conversion data, range fit for
7025 * ADC resolution 6 bits.
7026 * @note For devices with feature oversampling: Oversampling
7027 * can increase data width, function for extended range
7028 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
7029 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
7030 * @param ADCx ADC instance
7031 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
7032 */
LL_ADC_REG_ReadConversionData6(const ADC_TypeDef * ADCx)7033 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx)
7034 {
7035 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
7036 }
7037
7038 #if defined(ADC_MULTIMODE_SUPPORT)
7039 /**
7040 * @brief Get ADC multimode conversion data of ADC master, ADC slave
7041 * or raw data with ADC master and slave concatenated.
7042 * @note If raw data with ADC master and slave concatenated is retrieved,
7043 * a macro is available to get the conversion data of
7044 * ADC master or ADC slave: see helper macro
7045 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
7046 * (however this macro is mainly intended for multimode
7047 * transfer by DMA, because this function can do the same
7048 * by getting multimode conversion data of ADC master or ADC slave
7049 * separately).
7050 * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
7051 * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
7052 * @param ADCxy_COMMON ADC common instance
7053 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7054 * @param ConversionData This parameter can be one of the following values:
7055 * @arg @ref LL_ADC_MULTI_MASTER
7056 * @arg @ref LL_ADC_MULTI_SLAVE
7057 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
7058 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
7059 */
LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef * ADCxy_COMMON,uint32_t ConversionData)7060 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef *ADCxy_COMMON,
7061 uint32_t ConversionData)
7062 {
7063 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
7064 ConversionData)
7065 >> (POSITION_VAL(ConversionData) & 0x1FUL)
7066 );
7067 }
7068 #endif /* ADC_MULTIMODE_SUPPORT */
7069
7070 /**
7071 * @}
7072 */
7073
7074 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
7075 * @{
7076 */
7077
7078 /**
7079 * @brief Start ADC group injected conversion.
7080 * @note On this STM32 series, this function is relevant for both
7081 * internal trigger (SW start) and external trigger:
7082 * - If ADC trigger has been set to software start, ADC conversion
7083 * starts immediately.
7084 * - If ADC trigger has been set to external trigger, ADC conversion
7085 * will start at next trigger event (on the selected trigger edge)
7086 * following the ADC start conversion command.
7087 * @note On this STM32 series, setting of this feature is conditioned to
7088 * ADC state:
7089 * ADC must be enabled without conversion on going on group injected,
7090 * without conversion stop command on going on group injected,
7091 * without ADC disable command on going.
7092 * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
7093 * @param ADCx ADC instance
7094 * @retval None
7095 */
LL_ADC_INJ_StartConversion(ADC_TypeDef * ADCx)7096 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
7097 {
7098 /* Note: Write register with some additional bits forced to state reset */
7099 /* instead of modifying only the selected bit for this function, */
7100 /* to not interfere with bits with HW property "rs". */
7101 MODIFY_REG(ADCx->CR,
7102 ADC_CR_BITS_PROPERTY_RS,
7103 ADC_CR_JADSTART);
7104 }
7105
7106 /**
7107 * @brief Stop ADC group injected conversion.
7108 * @note On this STM32 series, setting of this feature is conditioned to
7109 * ADC state:
7110 * ADC must be enabled with conversion on going on group injected,
7111 * without ADC disable command on going.
7112 * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
7113 * @param ADCx ADC instance
7114 * @retval None
7115 */
LL_ADC_INJ_StopConversion(ADC_TypeDef * ADCx)7116 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
7117 {
7118 /* Note: Write register with some additional bits forced to state reset */
7119 /* instead of modifying only the selected bit for this function, */
7120 /* to not interfere with bits with HW property "rs". */
7121 MODIFY_REG(ADCx->CR,
7122 ADC_CR_BITS_PROPERTY_RS,
7123 ADC_CR_JADSTP);
7124 }
7125
7126 /**
7127 * @brief Get ADC group injected conversion state.
7128 * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
7129 * @param ADCx ADC instance
7130 * @retval 0: no conversion is on going on ADC group injected.
7131 */
LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef * ADCx)7132 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx)
7133 {
7134 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
7135 }
7136
7137 /**
7138 * @brief Get ADC group injected command of conversion stop state
7139 * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
7140 * @param ADCx ADC instance
7141 * @retval 0: no command of conversion stop is on going on ADC group injected.
7142 */
LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef * ADCx)7143 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
7144 {
7145 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
7146 }
7147
7148 /**
7149 * @brief Get ADC group injected conversion data, range fit for
7150 * all ADC configurations: all ADC resolutions and
7151 * all oversampling increased data width (for devices
7152 * with feature oversampling).
7153 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
7154 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
7155 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
7156 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
7157 * @param ADCx ADC instance
7158 * @param Rank This parameter can be one of the following values:
7159 * @arg @ref LL_ADC_INJ_RANK_1
7160 * @arg @ref LL_ADC_INJ_RANK_2
7161 * @arg @ref LL_ADC_INJ_RANK_3
7162 * @arg @ref LL_ADC_INJ_RANK_4
7163 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
7164 */
LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef * ADCx,uint32_t Rank)7165 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank)
7166 {
7167 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
7168 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7169
7170 return (uint32_t)(READ_BIT(*preg,
7171 ADC_JDR1_JDATA)
7172 );
7173 }
7174
7175 /**
7176 * @brief Get ADC group injected conversion data, range fit for
7177 * ADC resolution 12 bits.
7178 * @note For devices with feature oversampling: Oversampling
7179 * can increase data width, function for extended range
7180 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7181 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
7182 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
7183 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
7184 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
7185 * @param ADCx ADC instance
7186 * @param Rank This parameter can be one of the following values:
7187 * @arg @ref LL_ADC_INJ_RANK_1
7188 * @arg @ref LL_ADC_INJ_RANK_2
7189 * @arg @ref LL_ADC_INJ_RANK_3
7190 * @arg @ref LL_ADC_INJ_RANK_4
7191 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
7192 */
LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef * ADCx,uint32_t Rank)7193 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank)
7194 {
7195 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
7196 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7197
7198 return (uint16_t)(READ_BIT(*preg,
7199 ADC_JDR1_JDATA)
7200 );
7201 }
7202
7203 /**
7204 * @brief Get ADC group injected conversion data, range fit for
7205 * ADC resolution 10 bits.
7206 * @note For devices with feature oversampling: Oversampling
7207 * can increase data width, function for extended range
7208 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7209 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
7210 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
7211 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
7212 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
7213 * @param ADCx ADC instance
7214 * @param Rank This parameter can be one of the following values:
7215 * @arg @ref LL_ADC_INJ_RANK_1
7216 * @arg @ref LL_ADC_INJ_RANK_2
7217 * @arg @ref LL_ADC_INJ_RANK_3
7218 * @arg @ref LL_ADC_INJ_RANK_4
7219 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
7220 */
LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef * ADCx,uint32_t Rank)7221 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank)
7222 {
7223 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
7224 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7225
7226 return (uint16_t)(READ_BIT(*preg,
7227 ADC_JDR1_JDATA)
7228 );
7229 }
7230
7231 /**
7232 * @brief Get ADC group injected conversion data, range fit for
7233 * ADC resolution 8 bits.
7234 * @note For devices with feature oversampling: Oversampling
7235 * can increase data width, function for extended range
7236 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7237 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
7238 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
7239 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
7240 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
7241 * @param ADCx ADC instance
7242 * @param Rank This parameter can be one of the following values:
7243 * @arg @ref LL_ADC_INJ_RANK_1
7244 * @arg @ref LL_ADC_INJ_RANK_2
7245 * @arg @ref LL_ADC_INJ_RANK_3
7246 * @arg @ref LL_ADC_INJ_RANK_4
7247 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
7248 */
LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef * ADCx,uint32_t Rank)7249 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank)
7250 {
7251 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
7252 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7253
7254 return (uint8_t)(READ_BIT(*preg,
7255 ADC_JDR1_JDATA)
7256 );
7257 }
7258
7259 /**
7260 * @brief Get ADC group injected conversion data, range fit for
7261 * ADC resolution 6 bits.
7262 * @note For devices with feature oversampling: Oversampling
7263 * can increase data width, function for extended range
7264 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7265 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
7266 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
7267 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
7268 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
7269 * @param ADCx ADC instance
7270 * @param Rank This parameter can be one of the following values:
7271 * @arg @ref LL_ADC_INJ_RANK_1
7272 * @arg @ref LL_ADC_INJ_RANK_2
7273 * @arg @ref LL_ADC_INJ_RANK_3
7274 * @arg @ref LL_ADC_INJ_RANK_4
7275 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
7276 */
LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef * ADCx,uint32_t Rank)7277 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef *ADCx, uint32_t Rank)
7278 {
7279 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
7280 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7281
7282 return (uint8_t)(READ_BIT(*preg,
7283 ADC_JDR1_JDATA)
7284 );
7285 }
7286
7287 /**
7288 * @}
7289 */
7290
7291 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
7292 * @{
7293 */
7294
7295 /**
7296 * @brief Get flag ADC ready.
7297 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
7298 * is enabled and when conversion clock is active.
7299 * (not only core clock: this ADC has a dual clock domain)
7300 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
7301 * @param ADCx ADC instance
7302 * @retval State of bit (1 or 0).
7303 */
LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef * ADCx)7304 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx)
7305 {
7306 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
7307 }
7308
7309 /**
7310 * @brief Get flag ADC group regular end of unitary conversion.
7311 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
7312 * @param ADCx ADC instance
7313 * @retval State of bit (1 or 0).
7314 */
LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef * ADCx)7315 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx)
7316 {
7317 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
7318 }
7319
7320 /**
7321 * @brief Get flag ADC group regular end of sequence conversions.
7322 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
7323 * @param ADCx ADC instance
7324 * @retval State of bit (1 or 0).
7325 */
LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef * ADCx)7326 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx)
7327 {
7328 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
7329 }
7330
7331 /**
7332 * @brief Get flag ADC group regular overrun.
7333 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
7334 * @param ADCx ADC instance
7335 * @retval State of bit (1 or 0).
7336 */
LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef * ADCx)7337 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx)
7338 {
7339 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
7340 }
7341
7342 /**
7343 * @brief Get flag ADC group regular end of sampling phase.
7344 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
7345 * @param ADCx ADC instance
7346 * @retval State of bit (1 or 0).
7347 */
LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef * ADCx)7348 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx)
7349 {
7350 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
7351 }
7352
7353 /**
7354 * @brief Get flag ADC group injected end of unitary conversion.
7355 * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
7356 * @param ADCx ADC instance
7357 * @retval State of bit (1 or 0).
7358 */
LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef * ADCx)7359 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx)
7360 {
7361 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
7362 }
7363
7364 /**
7365 * @brief Get flag ADC group injected end of sequence conversions.
7366 * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
7367 * @param ADCx ADC instance
7368 * @retval State of bit (1 or 0).
7369 */
LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef * ADCx)7370 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx)
7371 {
7372 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
7373 }
7374
7375 /**
7376 * @brief Get flag ADC group injected contexts queue overflow.
7377 * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
7378 * @param ADCx ADC instance
7379 * @retval State of bit (1 or 0).
7380 */
LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef * ADCx)7381 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef *ADCx)
7382 {
7383 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
7384 }
7385
7386 /**
7387 * @brief Get flag ADC analog watchdog 1 flag
7388 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
7389 * @param ADCx ADC instance
7390 * @retval State of bit (1 or 0).
7391 */
LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef * ADCx)7392 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx)
7393 {
7394 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
7395 }
7396
7397 /**
7398 * @brief Get flag ADC analog watchdog 2.
7399 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
7400 * @param ADCx ADC instance
7401 * @retval State of bit (1 or 0).
7402 */
LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef * ADCx)7403 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx)
7404 {
7405 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
7406 }
7407
7408 /**
7409 * @brief Get flag ADC analog watchdog 3.
7410 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
7411 * @param ADCx ADC instance
7412 * @retval State of bit (1 or 0).
7413 */
LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef * ADCx)7414 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx)
7415 {
7416 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
7417 }
7418
7419 /**
7420 * @brief Clear flag ADC ready.
7421 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
7422 * is enabled and when conversion clock is active.
7423 * (not only core clock: this ADC has a dual clock domain)
7424 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
7425 * @param ADCx ADC instance
7426 * @retval None
7427 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)7428 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
7429 {
7430 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
7431 }
7432
7433 /**
7434 * @brief Clear flag ADC group regular end of unitary conversion.
7435 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
7436 * @param ADCx ADC instance
7437 * @retval None
7438 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)7439 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
7440 {
7441 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
7442 }
7443
7444 /**
7445 * @brief Clear flag ADC group regular end of sequence conversions.
7446 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
7447 * @param ADCx ADC instance
7448 * @retval None
7449 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)7450 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
7451 {
7452 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
7453 }
7454
7455 /**
7456 * @brief Clear flag ADC group regular overrun.
7457 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
7458 * @param ADCx ADC instance
7459 * @retval None
7460 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)7461 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
7462 {
7463 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
7464 }
7465
7466 /**
7467 * @brief Clear flag ADC group regular end of sampling phase.
7468 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
7469 * @param ADCx ADC instance
7470 * @retval None
7471 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)7472 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
7473 {
7474 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
7475 }
7476
7477 /**
7478 * @brief Clear flag ADC group injected end of unitary conversion.
7479 * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
7480 * @param ADCx ADC instance
7481 * @retval None
7482 */
LL_ADC_ClearFlag_JEOC(ADC_TypeDef * ADCx)7483 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
7484 {
7485 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
7486 }
7487
7488 /**
7489 * @brief Clear flag ADC group injected end of sequence conversions.
7490 * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
7491 * @param ADCx ADC instance
7492 * @retval None
7493 */
LL_ADC_ClearFlag_JEOS(ADC_TypeDef * ADCx)7494 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
7495 {
7496 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
7497 }
7498
7499 /**
7500 * @brief Clear flag ADC group injected contexts queue overflow.
7501 * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
7502 * @param ADCx ADC instance
7503 * @retval None
7504 */
LL_ADC_ClearFlag_JQOVF(ADC_TypeDef * ADCx)7505 __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
7506 {
7507 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
7508 }
7509
7510 /**
7511 * @brief Clear flag ADC analog watchdog 1.
7512 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
7513 * @param ADCx ADC instance
7514 * @retval None
7515 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)7516 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
7517 {
7518 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
7519 }
7520
7521 /**
7522 * @brief Clear flag ADC analog watchdog 2.
7523 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
7524 * @param ADCx ADC instance
7525 * @retval None
7526 */
LL_ADC_ClearFlag_AWD2(ADC_TypeDef * ADCx)7527 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
7528 {
7529 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
7530 }
7531
7532 /**
7533 * @brief Clear flag ADC analog watchdog 3.
7534 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
7535 * @param ADCx ADC instance
7536 * @retval None
7537 */
LL_ADC_ClearFlag_AWD3(ADC_TypeDef * ADCx)7538 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
7539 {
7540 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
7541 }
7542
7543 #if defined(ADC_MULTIMODE_SUPPORT)
7544 /**
7545 * @brief Get flag multimode ADC ready of the ADC master.
7546 * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
7547 * @param ADCxy_COMMON ADC common instance
7548 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7549 * @retval State of bit (1 or 0).
7550 */
LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef * ADCxy_COMMON)7551 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON)
7552 {
7553 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
7554 }
7555
7556 /**
7557 * @brief Get flag multimode ADC ready of the ADC slave.
7558 * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
7559 * @param ADCxy_COMMON ADC common instance
7560 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7561 * @retval State of bit (1 or 0).
7562 */
LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef * ADCxy_COMMON)7563 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON)
7564 {
7565 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
7566 }
7567
7568 /**
7569 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master.
7570 * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
7571 * @param ADCxy_COMMON ADC common instance
7572 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7573 * @retval State of bit (1 or 0).
7574 */
LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef * ADCxy_COMMON)7575 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef *ADCxy_COMMON)
7576 {
7577 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
7578 }
7579
7580 /**
7581 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
7582 * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
7583 * @param ADCxy_COMMON ADC common instance
7584 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7585 * @retval State of bit (1 or 0).
7586 */
LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef * ADCxy_COMMON)7587 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef *ADCxy_COMMON)
7588 {
7589 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
7590 }
7591
7592 /**
7593 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
7594 * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
7595 * @param ADCxy_COMMON ADC common instance
7596 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7597 * @retval State of bit (1 or 0).
7598 */
LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef * ADCxy_COMMON)7599 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7600 {
7601 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
7602 }
7603
7604 /**
7605 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
7606 * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
7607 * @param ADCxy_COMMON ADC common instance
7608 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7609 * @retval State of bit (1 or 0).
7610 */
LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef * ADCxy_COMMON)7611 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7612 {
7613 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
7614 }
7615
7616 /**
7617 * @brief Get flag multimode ADC group regular overrun of the ADC master.
7618 * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
7619 * @param ADCxy_COMMON ADC common instance
7620 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7621 * @retval State of bit (1 or 0).
7622 */
LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef * ADCxy_COMMON)7623 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
7624 {
7625 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
7626 }
7627
7628 /**
7629 * @brief Get flag multimode ADC group regular overrun of the ADC slave.
7630 * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
7631 * @param ADCxy_COMMON ADC common instance
7632 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7633 * @retval State of bit (1 or 0).
7634 */
LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef * ADCxy_COMMON)7635 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
7636 {
7637 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
7638 }
7639
7640 /**
7641 * @brief Get flag multimode ADC group regular end of sampling of the ADC master.
7642 * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
7643 * @param ADCxy_COMMON ADC common instance
7644 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7645 * @retval State of bit (1 or 0).
7646 */
LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef * ADCxy_COMMON)7647 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON)
7648 {
7649 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
7650 }
7651
7652 /**
7653 * @brief Get flag multimode ADC group regular end of sampling of the ADC slave.
7654 * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
7655 * @param ADCxy_COMMON ADC common instance
7656 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7657 * @retval State of bit (1 or 0).
7658 */
LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef * ADCxy_COMMON)7659 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON)
7660 {
7661 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
7662 }
7663
7664 /**
7665 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master.
7666 * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
7667 * @param ADCxy_COMMON ADC common instance
7668 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7669 * @retval State of bit (1 or 0).
7670 */
LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef * ADCxy_COMMON)7671 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON)
7672 {
7673 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
7674 }
7675
7676 /**
7677 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
7678 * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
7679 * @param ADCxy_COMMON ADC common instance
7680 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7681 * @retval State of bit (1 or 0).
7682 */
LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef * ADCxy_COMMON)7683 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON)
7684 {
7685 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
7686 }
7687
7688 /**
7689 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
7690 * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
7691 * @param ADCxy_COMMON ADC common instance
7692 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7693 * @retval State of bit (1 or 0).
7694 */
LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef * ADCxy_COMMON)7695 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7696 {
7697 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
7698 }
7699
7700 /**
7701 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
7702 * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
7703 * @param ADCxy_COMMON ADC common instance
7704 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7705 * @retval State of bit (1 or 0).
7706 */
LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef * ADCxy_COMMON)7707 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7708 {
7709 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
7710 }
7711
7712 /**
7713 * @brief Get flag multimode ADC group injected context queue overflow of the ADC master.
7714 * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
7715 * @param ADCxy_COMMON ADC common instance
7716 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7717 * @retval State of bit (1 or 0).
7718 */
LL_ADC_IsActiveFlag_MST_JQOVF(const ADC_Common_TypeDef * ADCxy_COMMON)7719 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON)
7720 {
7721 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);
7722 }
7723
7724 /**
7725 * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave.
7726 * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
7727 * @param ADCxy_COMMON ADC common instance
7728 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7729 * @retval State of bit (1 or 0).
7730 */
LL_ADC_IsActiveFlag_SLV_JQOVF(const ADC_Common_TypeDef * ADCxy_COMMON)7731 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON)
7732 {
7733 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);
7734 }
7735
7736 /**
7737 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
7738 * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
7739 * @param ADCxy_COMMON ADC common instance
7740 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7741 * @retval State of bit (1 or 0).
7742 */
LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef * ADCxy_COMMON)7743 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
7744 {
7745 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
7746 }
7747
7748 /**
7749 * @brief Get flag multimode analog watchdog 1 of the ADC slave.
7750 * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
7751 * @param ADCxy_COMMON ADC common instance
7752 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7753 * @retval State of bit (1 or 0).
7754 */
LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef * ADCxy_COMMON)7755 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
7756 {
7757 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
7758 }
7759
7760 /**
7761 * @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
7762 * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
7763 * @param ADCxy_COMMON ADC common instance
7764 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7765 * @retval State of bit (1 or 0).
7766 */
LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef * ADCxy_COMMON)7767 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON)
7768 {
7769 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
7770 }
7771
7772 /**
7773 * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
7774 * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
7775 * @param ADCxy_COMMON ADC common instance
7776 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7777 * @retval State of bit (1 or 0).
7778 */
LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef * ADCxy_COMMON)7779 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON)
7780 {
7781 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
7782 }
7783
7784 /**
7785 * @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
7786 * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
7787 * @param ADCxy_COMMON ADC common instance
7788 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7789 * @retval State of bit (1 or 0).
7790 */
LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef * ADCxy_COMMON)7791 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON)
7792 {
7793 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
7794 }
7795
7796 /**
7797 * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
7798 * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
7799 * @param ADCxy_COMMON ADC common instance
7800 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7801 * @retval State of bit (1 or 0).
7802 */
LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef * ADCxy_COMMON)7803 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON)
7804 {
7805 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
7806 }
7807 #endif /* ADC_MULTIMODE_SUPPORT */
7808
7809 /**
7810 * @}
7811 */
7812
7813 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
7814 * @{
7815 */
7816
7817 /**
7818 * @brief Enable ADC ready.
7819 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
7820 * @param ADCx ADC instance
7821 * @retval None
7822 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)7823 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
7824 {
7825 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7826 }
7827
7828 /**
7829 * @brief Enable interruption ADC group regular end of unitary conversion.
7830 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
7831 * @param ADCx ADC instance
7832 * @retval None
7833 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)7834 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
7835 {
7836 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
7837 }
7838
7839 /**
7840 * @brief Enable interruption ADC group regular end of sequence conversions.
7841 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
7842 * @param ADCx ADC instance
7843 * @retval None
7844 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)7845 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
7846 {
7847 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
7848 }
7849
7850 /**
7851 * @brief Enable ADC group regular interruption overrun.
7852 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
7853 * @param ADCx ADC instance
7854 * @retval None
7855 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)7856 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
7857 {
7858 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
7859 }
7860
7861 /**
7862 * @brief Enable interruption ADC group regular end of sampling.
7863 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
7864 * @param ADCx ADC instance
7865 * @retval None
7866 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)7867 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
7868 {
7869 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7870 }
7871
7872 /**
7873 * @brief Enable interruption ADC group injected end of unitary conversion.
7874 * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
7875 * @param ADCx ADC instance
7876 * @retval None
7877 */
LL_ADC_EnableIT_JEOC(ADC_TypeDef * ADCx)7878 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
7879 {
7880 SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7881 }
7882
7883 /**
7884 * @brief Enable interruption ADC group injected end of sequence conversions.
7885 * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
7886 * @param ADCx ADC instance
7887 * @retval None
7888 */
LL_ADC_EnableIT_JEOS(ADC_TypeDef * ADCx)7889 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
7890 {
7891 SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7892 }
7893
7894 /**
7895 * @brief Enable interruption ADC group injected context queue overflow.
7896 * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
7897 * @param ADCx ADC instance
7898 * @retval None
7899 */
LL_ADC_EnableIT_JQOVF(ADC_TypeDef * ADCx)7900 __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
7901 {
7902 SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
7903 }
7904
7905 /**
7906 * @brief Enable interruption ADC analog watchdog 1.
7907 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
7908 * @param ADCx ADC instance
7909 * @retval None
7910 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)7911 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
7912 {
7913 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7914 }
7915
7916 /**
7917 * @brief Enable interruption ADC analog watchdog 2.
7918 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
7919 * @param ADCx ADC instance
7920 * @retval None
7921 */
LL_ADC_EnableIT_AWD2(ADC_TypeDef * ADCx)7922 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
7923 {
7924 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
7925 }
7926
7927 /**
7928 * @brief Enable interruption ADC analog watchdog 3.
7929 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
7930 * @param ADCx ADC instance
7931 * @retval None
7932 */
LL_ADC_EnableIT_AWD3(ADC_TypeDef * ADCx)7933 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
7934 {
7935 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
7936 }
7937
7938 /**
7939 * @brief Disable interruption ADC ready.
7940 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
7941 * @param ADCx ADC instance
7942 * @retval None
7943 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)7944 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
7945 {
7946 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7947 }
7948
7949 /**
7950 * @brief Disable interruption ADC group regular end of unitary conversion.
7951 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
7952 * @param ADCx ADC instance
7953 * @retval None
7954 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)7955 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
7956 {
7957 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
7958 }
7959
7960 /**
7961 * @brief Disable interruption ADC group regular end of sequence conversions.
7962 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
7963 * @param ADCx ADC instance
7964 * @retval None
7965 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)7966 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
7967 {
7968 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
7969 }
7970
7971 /**
7972 * @brief Disable interruption ADC group regular overrun.
7973 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
7974 * @param ADCx ADC instance
7975 * @retval None
7976 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)7977 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
7978 {
7979 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
7980 }
7981
7982 /**
7983 * @brief Disable interruption ADC group regular end of sampling.
7984 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
7985 * @param ADCx ADC instance
7986 * @retval None
7987 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)7988 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
7989 {
7990 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7991 }
7992
7993 /**
7994 * @brief Disable interruption ADC group regular end of unitary conversion.
7995 * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
7996 * @param ADCx ADC instance
7997 * @retval None
7998 */
LL_ADC_DisableIT_JEOC(ADC_TypeDef * ADCx)7999 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
8000 {
8001 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
8002 }
8003
8004 /**
8005 * @brief Disable interruption ADC group injected end of sequence conversions.
8006 * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
8007 * @param ADCx ADC instance
8008 * @retval None
8009 */
LL_ADC_DisableIT_JEOS(ADC_TypeDef * ADCx)8010 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
8011 {
8012 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
8013 }
8014
8015 /**
8016 * @brief Disable interruption ADC group injected context queue overflow.
8017 * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
8018 * @param ADCx ADC instance
8019 * @retval None
8020 */
LL_ADC_DisableIT_JQOVF(ADC_TypeDef * ADCx)8021 __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
8022 {
8023 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
8024 }
8025
8026 /**
8027 * @brief Disable interruption ADC analog watchdog 1.
8028 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
8029 * @param ADCx ADC instance
8030 * @retval None
8031 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)8032 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
8033 {
8034 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
8035 }
8036
8037 /**
8038 * @brief Disable interruption ADC analog watchdog 2.
8039 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
8040 * @param ADCx ADC instance
8041 * @retval None
8042 */
LL_ADC_DisableIT_AWD2(ADC_TypeDef * ADCx)8043 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
8044 {
8045 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
8046 }
8047
8048 /**
8049 * @brief Disable interruption ADC analog watchdog 3.
8050 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
8051 * @param ADCx ADC instance
8052 * @retval None
8053 */
LL_ADC_DisableIT_AWD3(ADC_TypeDef * ADCx)8054 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
8055 {
8056 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
8057 }
8058
8059 /**
8060 * @brief Get state of interruption ADC ready
8061 * (0: interrupt disabled, 1: interrupt enabled).
8062 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
8063 * @param ADCx ADC instance
8064 * @retval State of bit (1 or 0).
8065 */
LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef * ADCx)8066 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx)
8067 {
8068 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
8069 }
8070
8071 /**
8072 * @brief Get state of interruption ADC group regular end of unitary conversion
8073 * (0: interrupt disabled, 1: interrupt enabled).
8074 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
8075 * @param ADCx ADC instance
8076 * @retval State of bit (1 or 0).
8077 */
LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef * ADCx)8078 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx)
8079 {
8080 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
8081 }
8082
8083 /**
8084 * @brief Get state of interruption ADC group regular end of sequence conversions
8085 * (0: interrupt disabled, 1: interrupt enabled).
8086 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
8087 * @param ADCx ADC instance
8088 * @retval State of bit (1 or 0).
8089 */
LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef * ADCx)8090 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx)
8091 {
8092 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
8093 }
8094
8095 /**
8096 * @brief Get state of interruption ADC group regular overrun
8097 * (0: interrupt disabled, 1: interrupt enabled).
8098 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
8099 * @param ADCx ADC instance
8100 * @retval State of bit (1 or 0).
8101 */
LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef * ADCx)8102 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx)
8103 {
8104 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
8105 }
8106
8107 /**
8108 * @brief Get state of interruption ADC group regular end of sampling
8109 * (0: interrupt disabled, 1: interrupt enabled).
8110 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
8111 * @param ADCx ADC instance
8112 * @retval State of bit (1 or 0).
8113 */
LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef * ADCx)8114 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx)
8115 {
8116 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
8117 }
8118
8119 /**
8120 * @brief Get state of interruption ADC group injected end of unitary conversion
8121 * (0: interrupt disabled, 1: interrupt enabled).
8122 * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
8123 * @param ADCx ADC instance
8124 * @retval State of bit (1 or 0).
8125 */
LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef * ADCx)8126 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx)
8127 {
8128 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
8129 }
8130
8131 /**
8132 * @brief Get state of interruption ADC group injected end of sequence conversions
8133 * (0: interrupt disabled, 1: interrupt enabled).
8134 * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
8135 * @param ADCx ADC instance
8136 * @retval State of bit (1 or 0).
8137 */
LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef * ADCx)8138 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx)
8139 {
8140 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
8141 }
8142
8143 /**
8144 * @brief Get state of interruption ADC group injected context queue overflow interrupt state
8145 * (0: interrupt disabled, 1: interrupt enabled).
8146 * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
8147 * @param ADCx ADC instance
8148 * @retval State of bit (1 or 0).
8149 */
LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef * ADCx)8150 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef *ADCx)
8151 {
8152 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
8153 }
8154
8155 /**
8156 * @brief Get state of interruption ADC analog watchdog 1
8157 * (0: interrupt disabled, 1: interrupt enabled).
8158 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
8159 * @param ADCx ADC instance
8160 * @retval State of bit (1 or 0).
8161 */
LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef * ADCx)8162 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx)
8163 {
8164 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
8165 }
8166
8167 /**
8168 * @brief Get state of interruption Get ADC analog watchdog 2
8169 * (0: interrupt disabled, 1: interrupt enabled).
8170 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
8171 * @param ADCx ADC instance
8172 * @retval State of bit (1 or 0).
8173 */
LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef * ADCx)8174 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx)
8175 {
8176 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
8177 }
8178
8179 /**
8180 * @brief Get state of interruption Get ADC analog watchdog 3
8181 * (0: interrupt disabled, 1: interrupt enabled).
8182 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
8183 * @param ADCx ADC instance
8184 * @retval State of bit (1 or 0).
8185 */
LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef * ADCx)8186 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx)
8187 {
8188 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
8189 }
8190
8191 /**
8192 * @}
8193 */
8194
8195 #if defined(USE_FULL_LL_DRIVER)
8196 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
8197 * @{
8198 */
8199
8200 /* Initialization of some features of ADC common parameters and multimode */
8201 ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON);
8202 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
8203 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
8204
8205 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
8206 /* (availability of ADC group injected depends on STM32 series) */
8207 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
8208
8209 /* Initialization of some features of ADC instance */
8210 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct);
8211 void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct);
8212
8213 /* Initialization of some features of ADC instance and ADC group regular */
8214 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
8215 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
8216
8217 /* Initialization of some features of ADC instance and ADC group injected */
8218 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
8219 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
8220
8221 /**
8222 * @}
8223 */
8224 #endif /* USE_FULL_LL_DRIVER */
8225
8226 /**
8227 * @}
8228 */
8229
8230 /**
8231 * @}
8232 */
8233
8234 #endif /* ADC1 || ADC2 || ADC3 */
8235
8236 /**
8237 * @}
8238 */
8239
8240 #ifdef __cplusplus
8241 }
8242 #endif
8243
8244 #endif /* STM32L4xx_LL_ADC_H */
8245
