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Searched refs:HISR (Results 1 – 25 of 97) sorted by relevance

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/hal_stm32-3.7.0/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_ll_dma.h1718 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4)); in LL_DMA_IsActiveFlag_HT4()
1729 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5)); in LL_DMA_IsActiveFlag_HT5()
1740 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6)); in LL_DMA_IsActiveFlag_HT6()
1751 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7)); in LL_DMA_IsActiveFlag_HT7()
1806 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4)); in LL_DMA_IsActiveFlag_TC4()
1817 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5)); in LL_DMA_IsActiveFlag_TC5()
1828 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6)); in LL_DMA_IsActiveFlag_TC6()
1839 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7)); in LL_DMA_IsActiveFlag_TC7()
1894 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4)); in LL_DMA_IsActiveFlag_TE4()
1905 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5)); in LL_DMA_IsActiveFlag_TE5()
[all …]
Dstm32f7xx_hal_dma.h516 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
518 …((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->…
/hal_stm32-3.7.0/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_ll_dma.h1685 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4)); in LL_DMA_IsActiveFlag_HT4()
1696 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5)); in LL_DMA_IsActiveFlag_HT5()
1707 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6)); in LL_DMA_IsActiveFlag_HT6()
1718 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7)); in LL_DMA_IsActiveFlag_HT7()
1773 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4)); in LL_DMA_IsActiveFlag_TC4()
1784 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5)); in LL_DMA_IsActiveFlag_TC5()
1795 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6)); in LL_DMA_IsActiveFlag_TC6()
1806 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7)); in LL_DMA_IsActiveFlag_TC7()
1861 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4)); in LL_DMA_IsActiveFlag_TE4()
1872 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5)); in LL_DMA_IsActiveFlag_TE5()
[all …]
Dstm32f2xx_hal_dma.h532 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
534 …((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->…
/hal_stm32-3.7.0/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_ll_dma.h1695 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4)); in LL_DMA_IsActiveFlag_HT4()
1706 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5)); in LL_DMA_IsActiveFlag_HT5()
1717 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6)); in LL_DMA_IsActiveFlag_HT6()
1728 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7)); in LL_DMA_IsActiveFlag_HT7()
1783 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4)); in LL_DMA_IsActiveFlag_TC4()
1794 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5)); in LL_DMA_IsActiveFlag_TC5()
1805 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6)); in LL_DMA_IsActiveFlag_TC6()
1816 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7)); in LL_DMA_IsActiveFlag_TC7()
1871 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4)); in LL_DMA_IsActiveFlag_TE4()
1882 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5)); in LL_DMA_IsActiveFlag_TE5()
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Dstm32f4xx_hal_dma.h542 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
544 …((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->…
/hal_stm32-3.7.0/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_dma.h2119 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF4) == (DMA_HISR_HTIF4)) ? 1UL : 0UL); in LL_DMA_IsActiveFlag_HT4()
2130 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF5) == (DMA_HISR_HTIF5)) ? 1UL : 0UL); in LL_DMA_IsActiveFlag_HT5()
2141 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF6) == (DMA_HISR_HTIF6)) ? 1UL : 0UL); in LL_DMA_IsActiveFlag_HT6()
2152 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF7) == (DMA_HISR_HTIF7)) ? 1UL : 0UL); in LL_DMA_IsActiveFlag_HT7()
2207 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF4) == (DMA_HISR_TCIF4)) ? 1UL : 0UL); in LL_DMA_IsActiveFlag_TC4()
2218 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF5) == (DMA_HISR_TCIF5)) ? 1UL : 0UL); in LL_DMA_IsActiveFlag_TC5()
2229 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF6) == (DMA_HISR_TCIF6)) ? 1UL : 0UL); in LL_DMA_IsActiveFlag_TC6()
2240 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF7) == (DMA_HISR_TCIF7)) ? 1UL : 0UL); in LL_DMA_IsActiveFlag_TC7()
2295 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF4) == (DMA_HISR_TEIF4)) ? 1UL : 0UL); in LL_DMA_IsActiveFlag_TE4()
2306 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF5) == (DMA_HISR_TEIF5)) ? 1UL : 0UL); in LL_DMA_IsActiveFlag_TE5()
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Dstm32h7xx_hal_dma.h1021 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3 )? (DMA2->HISR & (__FLAG__)) :\
1023 …((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3 )? (DMA1->HISR & (__FLAG__)) : (DMA…
1027 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
1029 …((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->…
/hal_stm32-3.7.0/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_dma.h1976 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF4) == (DMA_HISR_HTIF4)) ? 1UL : 0UL); in LL_DMA_IsActiveFlag_HT4()
1987 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF5) == (DMA_HISR_HTIF5)) ? 1UL : 0UL); in LL_DMA_IsActiveFlag_HT5()
1998 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF6) == (DMA_HISR_HTIF6)) ? 1UL : 0UL); in LL_DMA_IsActiveFlag_HT6()
2009 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF7) == (DMA_HISR_HTIF7)) ? 1UL : 0UL); in LL_DMA_IsActiveFlag_HT7()
2064 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF4) == (DMA_HISR_TCIF4)) ? 1UL : 0UL); in LL_DMA_IsActiveFlag_TC4()
2075 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF5) == (DMA_HISR_TCIF5)) ? 1UL : 0UL); in LL_DMA_IsActiveFlag_TC5()
2086 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF6) == (DMA_HISR_TCIF6)) ? 1UL : 0UL); in LL_DMA_IsActiveFlag_TC6()
2097 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF7) == (DMA_HISR_TCIF7)) ? 1UL : 0UL); in LL_DMA_IsActiveFlag_TC7()
2152 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF4) == (DMA_HISR_TEIF4)) ? 1UL : 0UL); in LL_DMA_IsActiveFlag_TE4()
2163 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF5) == (DMA_HISR_TEIF5)) ? 1UL : 0UL); in LL_DMA_IsActiveFlag_TE5()
[all …]
Dstm32mp1xx_hal_dma.h721 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
723 …((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->…
/hal_stm32-3.7.0/stm32cube/stm32f4xx/soc/
Dstm32f410cx.h244 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ member
Dstm32f410rx.h244 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ member
Dstm32f410tx.h241 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ member
Dstm32f401xc.h226 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ member
Dstm32f401xe.h226 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ member
Dstm32f411xe.h227 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ member
Dstm32f412cx.h347 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ member
Dstm32f405xx.h337 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ member
Dstm32f412vx.h348 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ member
Dstm32f412zx.h348 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ member
Dstm32f413xx.h386 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ member
Dstm32f415xx.h336 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ member
Dstm32f412rx.h348 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ member
/hal_stm32-3.7.0/stm32cube/stm32f2xx/soc/
Dstm32f205xx.h334 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ member
Dstm32f215xx.h335 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ member

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