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Searched refs:GTZC_CFGR4_MPCBB1_REG_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-3.7.0/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_hal_gtzc.h206 #define GTZC_PERIPH_MPCBB1_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB1_REG_Pos)
/hal_stm32-3.7.0/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_hal_gtzc.h381 #define GTZC_PERIPH_MPCBB1_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB1_REG_Pos)
/hal_stm32-3.7.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_gtzc.h327 #define GTZC_PERIPH_MPCBB1_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB1_REG_Pos)
/hal_stm32-3.7.0/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h15885 #define GTZC_CFGR4_MPCBB1_REG_Pos (25U) macro
15886 #define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
16254 #define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
16406 #define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
16558 #define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
Dstm32h562xx.h17219 #define GTZC_CFGR4_MPCBB1_REG_Pos (25U) macro
17220 #define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
17702 #define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
17892 #define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
18082 #define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
Dstm32h533xx.h16436 #define GTZC_CFGR4_MPCBB1_REG_Pos (25U) macro
16437 #define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
16819 #define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
16977 #define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
17135 #define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
Dstm32h563xx.h19321 #define GTZC_CFGR4_MPCBB1_REG_Pos (25U) macro
19322 #define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
19822 #define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
20018 #define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
20214 #define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
Dstm32h573xx.h19872 #define GTZC_CFGR4_MPCBB1_REG_Pos (25U) macro
19873 #define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
20387 #define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
20589 #define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
20791 #define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
Dstm32h503xx.h10937 #define GTZC_CFGR4_MPCBB1_REG_Pos (25U) macro
10938 #define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
/hal_stm32-3.7.0/stm32cube/stm32u5xx/soc/
Dstm32u535xx.h17928 #define GTZC_CFGR4_MPCBB1_REG_Pos (25U) macro
17929 #define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
18318 #define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
18480 #define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
18640 #define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
Dstm32u545xx.h18488 #define GTZC_CFGR4_MPCBB1_REG_Pos (25U) macro
18489 #define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
18898 #define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
19068 #define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
19236 #define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
Dstm32u575xx.h19538 #define GTZC_CFGR4_MPCBB1_REG_Pos (25U) macro
19539 #define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
19984 #define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
20170 #define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
20356 #define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
Dstm32u585xx.h20158 #define GTZC_CFGR4_MPCBB1_REG_Pos (25U) macro
20159 #define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
20626 #define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
20822 #define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
21018 #define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
Dstm32u5f7xx.h22332 #define GTZC_CFGR4_MPCBB1_REG_Pos (25U) macro
22333 #define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
22854 #define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
23072 #define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
23290 #define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
Dstm32u595xx.h20723 #define GTZC_CFGR4_MPCBB1_REG_Pos (25U) macro
20724 #define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
21205 #define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
21407 #define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
21609 #define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
Dstm32u5a5xx.h21343 #define GTZC_CFGR4_MPCBB1_REG_Pos (25U) macro
21344 #define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
21847 #define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
22059 #define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
22271 #define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
Dstm32u599xx.h24507 #define GTZC_CFGR4_MPCBB1_REG_Pos (25U) macro
24508 #define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
25019 #define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
25231 #define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
25443 #define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
Dstm32u5g7xx.h22952 #define GTZC_CFGR4_MPCBB1_REG_Pos (25U) macro
22953 #define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
23496 #define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
23724 #define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
23952 #define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
Dstm32u5g9xx.h26095 #define GTZC_CFGR4_MPCBB1_REG_Pos (25U) macro
26096 #define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
26645 #define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
26875 #define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
27105 #define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
Dstm32u5f9xx.h25475 #define GTZC_CFGR4_MPCBB1_REG_Pos (25U) macro
25476 #define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
26003 #define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
26223 #define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
26443 #define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
Dstm32u5a9xx.h25127 #define GTZC_CFGR4_MPCBB1_REG_Pos (25U) macro
25128 #define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
25661 #define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
25883 #define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
26105 #define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos
/hal_stm32-3.7.0/stm32cube/stm32wbaxx/soc/
Dstm32wba52xx.h5707 #define GTZC_CFGR4_MPCBB1_REG_Pos GTZC_TZIC_IER4_MPCBB1IE_Pos macro
5708 #define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
Dstm32wba54xx.h5896 #define GTZC_CFGR4_MPCBB1_REG_Pos GTZC_TZIC_IER4_MPCBB1IE_Pos macro
5897 #define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
Dstm32wba55xx.h5896 #define GTZC_CFGR4_MPCBB1_REG_Pos GTZC_TZIC_IER4_MPCBB1IE_Pos macro
5897 #define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)