Home
last modified time | relevance | path

Searched refs:DMA_CLLR_USA (Results 1 – 25 of 38) sorted by relevance

12

/hal_stm32-3.7.0/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_dma.h755 #define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory :
2993 (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConfigLinkUpdate()
3217 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); in LL_DMA_EnableCSARUpdate()
3239 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); in LL_DMA_DisableCSARUpdate()
3261 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA) in LL_DMA_IsEnabledCSARUpdate()
3262 == (DMA_CLLR_USA)) ? 1UL : 0UL); in LL_DMA_IsEnabledCSARUpdate()
/hal_stm32-3.7.0/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_dma.h936 #define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory :
4678 … (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ in LL_DMA_ConfigLinkUpdate()
4902 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); in LL_DMA_EnableCSARUpdate()
4924 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); in LL_DMA_DisableCSARUpdate()
4946 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA) in LL_DMA_IsEnabledCSARUpdate()
4947 == (DMA_CLLR_USA)) ? 1UL : 0UL); in LL_DMA_IsEnabledCSARUpdate()
/hal_stm32-3.7.0/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_dma.h930 #define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory :
4586 … (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ in LL_DMA_ConfigLinkUpdate()
4890 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); in LL_DMA_EnableCSARUpdate()
4920 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); in LL_DMA_DisableCSARUpdate()
4950 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA) in LL_DMA_IsEnabledCSARUpdate()
4951 == (DMA_CLLR_USA)) ? 1UL : 0UL); in LL_DMA_IsEnabledCSARUpdate()
/hal_stm32-3.7.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_dma.h947 #define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory :
4766 … (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ in LL_DMA_ConfigLinkUpdate()
5070 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); in LL_DMA_EnableCSARUpdate()
5100 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); in LL_DMA_DisableCSARUpdate()
5130 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA) in LL_DMA_IsEnabledCSARUpdate()
5131 == (DMA_CLLR_USA)) ? 1UL : 0UL); in LL_DMA_IsEnabledCSARUpdate()
/hal_stm32-3.7.0/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_ll_dma.c853 … DMA_CLLR_UB1 | DMA_CLLR_USA | \ in LL_DMA_CreateLinkNode()
876 … DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConnectLinkNode()
Dstm32wbaxx_hal_dma_ex.c3830 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4011 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToDynamic()
4076 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToStatic()
/hal_stm32-3.7.0/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_dma.c1081 … DMA_CLLR_UB1 | DMA_CLLR_USA | \ in LL_DMA_CreateLinkNode()
1109 … DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConnectLinkNode()
Dstm32h5xx_hal_dma_ex.c4202 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4218 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4400 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToDynamic()
4465 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToStatic()
/hal_stm32-3.7.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_dma.c1127 … DMA_CLLR_UB1 | DMA_CLLR_USA | \ in LL_DMA_CreateLinkNode()
1155 … DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConnectLinkNode()
Dstm32u5xx_hal_dma_ex.c4200 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4216 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4398 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToDynamic()
4463 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToStatic()
/hal_stm32-3.7.0/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_ll_dma.c1132 … DMA_CLLR_UB1 | DMA_CLLR_USA | \ in LL_DMA_CreateLinkNode()
1161 … DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ in LL_DMA_ConnectLinkNode()
Dstm32h7rsxx_hal_dma_ex.c4150 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4166 …*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_U… in DMA_List_GetCLLRNodeInfo()
4348 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToDynamic()
4413 uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, in DMA_List_ConvertNodeToStatic()
/hal_stm32-3.7.0/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h2362 #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update sou… macro
Dstm32wba52xx.h2946 #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update sou… macro
Dstm32wba54xx.h3129 #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update sou… macro
Dstm32wba55xx.h3129 #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update sou… macro
/hal_stm32-3.7.0/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h4004 #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update sou… macro
Dstm32h523xx.h5368 #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update sou… macro
Dstm32h562xx.h5789 #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update sou… macro
Dstm32h533xx.h5776 #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update sou… macro
/hal_stm32-3.7.0/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h5159 #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update sou… macro
Dstm32h7s3xx.h5604 #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update sou… macro
/hal_stm32-3.7.0/stm32cube/stm32u5xx/soc/
Dstm32u535xx.h6049 #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update sou… macro
Dstm32u545xx.h6449 #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update sou… macro
Dstm32u575xx.h6447 #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update sou… macro

12