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Searched refs:DMA_CLLR_ULL (Results 1 – 25 of 38) sorted by relevance

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/hal_stm32-3.7.0/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_dma.h759 #define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory :
2994 … DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA))); in LL_DMA_ConfigLinkUpdate()
3352 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); in LL_DMA_EnableCLLRUpdate()
3374 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); in LL_DMA_DisableCLLRUpdate()
3396 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL) in LL_DMA_IsEnabledCLLRUpdate()
3397 == (DMA_CLLR_ULL)) ? 1UL : 0UL); in LL_DMA_IsEnabledCLLRUpdate()
/hal_stm32-3.7.0/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_dma.h944 #define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory :
4679 …DMA_CLLR_UB2 | DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA… in LL_DMA_ConfigLinkUpdate()
5134 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); in LL_DMA_EnableCLLRUpdate()
5156 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); in LL_DMA_DisableCLLRUpdate()
5178 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL) in LL_DMA_IsEnabledCLLRUpdate()
5179 == (DMA_CLLR_ULL)) ? 1UL : 0UL); in LL_DMA_IsEnabledCLLRUpdate()
/hal_stm32-3.7.0/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_dma.h938 #define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory :
4587 …DMA_CLLR_UB2 | DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA… in LL_DMA_ConfigLinkUpdate()
5182 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); in LL_DMA_EnableCLLRUpdate()
5212 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); in LL_DMA_DisableCLLRUpdate()
5242 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL) in LL_DMA_IsEnabledCLLRUpdate()
5243 == (DMA_CLLR_ULL)) ? 1UL : 0UL); in LL_DMA_IsEnabledCLLRUpdate()
/hal_stm32-3.7.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_dma.h955 #define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory :
4767 …DMA_CLLR_UB2 | DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA… in LL_DMA_ConfigLinkUpdate()
5362 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); in LL_DMA_EnableCLLRUpdate()
5392 …_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); in LL_DMA_DisableCLLRUpdate()
5422 …D_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL) in LL_DMA_IsEnabledCLLRUpdate()
5423 == (DMA_CLLR_ULL)) ? 1UL : 0UL); in LL_DMA_IsEnabledCLLRUpdate()
/hal_stm32-3.7.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_dma_ex.c4201 DMA_CLLR_UB2 | DMA_CLLR_ULL; in DMA_List_GetCLLRNodeInfo()
4216 …llr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_ULL; in DMA_List_GetCLLRNodeInfo()
4399 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToDynamic()
4464 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToStatic()
4610 ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] &= ~DMA_CLLR_ULL; in DMA_List_UpdateDynamicQueueNodesCLLR()
Dstm32u5xx_ll_dma.c1128 … DMA_CLLR_UDA | DMA_CLLR_ULL))); in LL_DMA_CreateLinkNode()
1156 … DMA_CLLR_UT3 | DMA_CLLR_UB2 | DMA_CLLR_ULL))); in LL_DMA_ConnectLinkNode()
/hal_stm32-3.7.0/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_dma_ex.c4151 DMA_CLLR_UB2 | DMA_CLLR_ULL; in DMA_List_GetCLLRNodeInfo()
4166 …llr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_ULL; in DMA_List_GetCLLRNodeInfo()
4349 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToDynamic()
4414 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToStatic()
4560 ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] &= ~DMA_CLLR_ULL; in DMA_List_UpdateDynamicQueueNodesCLLR()
Dstm32h7rsxx_ll_dma.c1133 … DMA_CLLR_UDA | DMA_CLLR_ULL))); in LL_DMA_CreateLinkNode()
1162 … DMA_CLLR_UT3 | DMA_CLLR_UB2 | DMA_CLLR_ULL))); in LL_DMA_ConnectLinkNode()
/hal_stm32-3.7.0/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_ll_dma.c854 … DMA_CLLR_UDA | DMA_CLLR_ULL))); in LL_DMA_CreateLinkNode()
877 DMA_CLLR_ULL))); in LL_DMA_ConnectLinkNode()
Dstm32wbaxx_hal_dma_ex.c3830 …llr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_ULL; in DMA_List_GetCLLRNodeInfo()
4012 DMA_CLLR_UDA, DMA_CLLR_ULL in DMA_List_ConvertNodeToDynamic()
4077 DMA_CLLR_UDA, DMA_CLLR_ULL in DMA_List_ConvertNodeToStatic()
4223 ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] &= ~DMA_CLLR_ULL; in DMA_List_UpdateDynamicQueueNodesCLLR()
/hal_stm32-3.7.0/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_dma_ex.c4203 DMA_CLLR_UB2 | DMA_CLLR_ULL; in DMA_List_GetCLLRNodeInfo()
4218 …llr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_ULL; in DMA_List_GetCLLRNodeInfo()
4401 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToDynamic()
4466 DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL in DMA_List_ConvertNodeToStatic()
4612 ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] &= ~DMA_CLLR_ULL; in DMA_List_UpdateDynamicQueueNodesCLLR()
Dstm32h5xx_ll_dma.c1082 … DMA_CLLR_UDA | DMA_CLLR_ULL))); in LL_DMA_CreateLinkNode()
1110 … DMA_CLLR_UT3 | DMA_CLLR_UB2 | DMA_CLLR_ULL))); in LL_DMA_ConnectLinkNode()
/hal_stm32-3.7.0/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h2356 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
Dstm32wba52xx.h2940 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
Dstm32wba54xx.h3123 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
Dstm32wba55xx.h3123 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
/hal_stm32-3.7.0/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h3992 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
Dstm32h523xx.h5356 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
Dstm32h562xx.h5777 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
Dstm32h533xx.h5764 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
/hal_stm32-3.7.0/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h5147 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
Dstm32h7s3xx.h5592 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
/hal_stm32-3.7.0/stm32cube/stm32u5xx/soc/
Dstm32u535xx.h6037 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
Dstm32u545xx.h6437 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro
Dstm32u575xx.h6435 #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update lin… macro

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