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Searched refs:DDRPHYC_DTPR1_TFAW_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-3.7.0/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h8910 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
8911 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
8913 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
8914 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
8915 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
8916 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
8917 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
8918 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
Dstm32mp151dxx_cm4.h8876 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
8877 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
8879 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
8880 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
8881 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
8882 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
8883 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
8884 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
Dstm32mp151fxx_cm4.h9073 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
9074 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
9076 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
9077 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
9078 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
9079 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
9080 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
9081 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
Dstm32mp151axx_ca7.h8910 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
8911 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
8913 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
8914 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
8915 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
8916 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
8917 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
8918 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
Dstm32mp151cxx_cm4.h9073 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
9074 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
9076 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
9077 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
9078 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
9079 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
9080 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
9081 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
Dstm32mp151fxx_ca7.h9107 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
9108 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
9110 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
9111 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
9112 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
9113 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
9114 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
9115 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
Dstm32mp151cxx_ca7.h9107 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
9108 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
9110 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
9111 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
9112 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
9113 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
9114 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
9115 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
Dstm32mp151axx_cm4.h8876 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
8877 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
8879 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
8880 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
8881 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
8882 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
8883 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
8884 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
Dstm32mp153dxx_ca7.h10461 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
10462 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
10464 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
10465 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
10466 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
10467 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
10468 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
10469 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
Dstm32mp153cxx_cm4.h10624 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
10625 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
10627 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
10628 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
10629 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
10630 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
10631 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
10632 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
Dstm32mp153dxx_cm4.h10427 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
10428 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
10430 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
10431 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
10432 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
10433 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
10434 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
10435 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
Dstm32mp153fxx_ca7.h10658 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
10659 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
10661 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
10662 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
10663 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
10664 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
10665 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
10666 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
Dstm32mp153fxx_cm4.h10624 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
10625 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
10627 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
10628 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
10629 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
10630 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
10631 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
10632 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
Dstm32mp153cxx_ca7.h10658 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
10659 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
10661 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
10662 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
10663 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
10664 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
10665 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
10666 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
Dstm32mp153axx_cm4.h10427 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
10428 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
10430 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
10431 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
10432 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
10433 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
10434 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
10435 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
Dstm32mp153axx_ca7.h10461 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
10462 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
10464 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
10465 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
10466 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
10467 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
10468 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
10469 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
Dstm32mp157axx_ca7.h10576 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
10577 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
10579 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
10580 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
10581 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
10582 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
10583 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
10584 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
Dstm32mp157axx_cm4.h10542 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
10543 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
10545 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
10546 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
10547 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
10548 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
10549 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
10550 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
Dstm32mp157cxx_ca7.h10773 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
10774 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
10776 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
10777 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
10778 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
10779 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
10780 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
10781 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
Dstm32mp157cxx_cm4.h10739 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
10740 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
10742 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
10743 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
10744 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
10745 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
10746 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
10747 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
Dstm32mp157dxx_ca7.h10576 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
10577 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
10579 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
10580 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
10581 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
10582 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
10583 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
10584 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
Dstm32mp157dxx_cm4.h10542 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
10543 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
10545 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
10546 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
10547 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
10548 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
10549 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
10550 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
Dstm32mp157fxx_ca7.h10773 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
10774 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
10776 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
10777 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
10778 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
10779 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
10780 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
10781 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */
Dstm32mp157fxx_cm4.h10739 #define DDRPHYC_DTPR1_TFAW_Pos (3U) macro
10740 #define DDRPHYC_DTPR1_TFAW_Msk (0x3FUL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */
10742 #define DDRPHYC_DTPR1_TFAW_0 (0x1UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */
10743 #define DDRPHYC_DTPR1_TFAW_1 (0x2UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */
10744 #define DDRPHYC_DTPR1_TFAW_2 (0x4UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */
10745 #define DDRPHYC_DTPR1_TFAW_3 (0x8UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */
10746 #define DDRPHYC_DTPR1_TFAW_4 (0x10UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */
10747 #define DDRPHYC_DTPR1_TFAW_5 (0x20UL << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */