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Searched refs:C2MISR (Results 1 – 25 of 46) sorted by relevance

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/hal_stm32-3.7.0/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_hal_hsem.c382 statusreg = HSEM->C2MISR;/*Use interrupt line 1 for CPU2 Master*/ in HAL_HSEM_IRQHandler()
/hal_stm32-3.7.0/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_hsem.c394 statusreg = HSEM->C2MISR;/*Use interrupt line 1 for CPU2 Master*/ in HAL_HSEM_IRQHandler()
/hal_stm32-3.7.0/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_hsem.h877 return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); in LL_HSEM_IsActiveFlag_C2MISR()
/hal_stm32-3.7.0/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_hsem.h861 return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); in LL_HSEM_IsActiveFlag_C2MISR()
/hal_stm32-3.7.0/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_hsem.h856 return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); in LL_HSEM_IsActiveFlag_C2MISR()
/hal_stm32-3.7.0/stm32cube/stm32wlxx/soc/
Dstm32wl54xx.h528 …__IO uint32_t C2MISR; /*!< HSEM CPU2 masked interrupt status register , Address offset: 11C… member
Dstm32wl5mxx.h528 …__IO uint32_t C2MISR; /*!< HSEM CPU2 masked interrupt status register , Address offset: 11C… member
Dstm32wl55xx.h528 …__IO uint32_t C2MISR; /*!< HSEM CPU2 masked interrupt status register , Address offset: 11C… member
/hal_stm32-3.7.0/stm32cube/stm32wbxx/soc/
Dstm32wb30xx.h725 …__IO uint32_t C2MISR; /*!< HSEM CPU2 masked interrupt status register , Address offset: 1… member
Dstm32wb50xx.h726 …__IO uint32_t C2MISR; /*!< HSEM CPU2 masked interrupt status register , Address offset: 1… member
Dstm32wb1mxx.h742 …__IO uint32_t C2MISR; /*!< HSEM CPU2 masked interrupt status register , Address offset: 1… member
Dstm32wb35xx.h857 …__IO uint32_t C2MISR; /*!< HSEM CPU2 masked interrupt status register , Address offset: 1… member
Dstm32wb55xx.h895 …__IO uint32_t C2MISR; /*!< HSEM CPU2 masked interrupt status register , Address offset: 1… member
Dstm32wb5mxx.h895 …__IO uint32_t C2MISR; /*!< HSEM CPU2 masked interrupt status register , Address offset: 1… member
/hal_stm32-3.7.0/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h732 …__IO uint32_t C2MISR; /*!< HSEM CPU2 masked interrupt status register , Address offset: 1… member
Dstm32wb15xx.h742 …__IO uint32_t C2MISR; /*!< HSEM CPU2 masked interrupt status register , Address offset: 1… member
/hal_stm32-3.7.0/stm32cube/stm32h7xx/soc/
Dstm32h755xx.h1532 …__IO uint32_t C2MISR; /*!< HSEM Interrupt 1 Masked Status register , Address offset: 11Ch… member
Dstm32h745xx.h1531 …__IO uint32_t C2MISR; /*!< HSEM Interrupt 1 Masked Status register , Address offset: 11Ch… member
Dstm32h745xg.h1531 …__IO uint32_t C2MISR; /*!< HSEM Interrupt 1 Masked Status register , Address offset: 11Ch… member
Dstm32h747xx.h1612 …__IO uint32_t C2MISR; /*!< HSEM Interrupt 1 Masked Status register , Address offset: 11Ch… member
Dstm32h747xg.h1612 …__IO uint32_t C2MISR; /*!< HSEM Interrupt 1 Masked Status register , Address offset: 11Ch… member
Dstm32h757xx.h1613 …__IO uint32_t C2MISR; /*!< HSEM Interrupt 1 Masked Status register , Address offset: 11Ch… member
/hal_stm32-3.7.0/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h2132 …__IO uint32_t C2MISR; /*!< HSEM Interrupt 1 Masked Status register , Address offset: 11Ch… member
Dstm32mp151dxx_cm4.h2098 …__IO uint32_t C2MISR; /*!< HSEM Interrupt 1 Masked Status register , Address offset: 11Ch… member
Dstm32mp151fxx_cm4.h2098 …__IO uint32_t C2MISR; /*!< HSEM Interrupt 1 Masked Status register , Address offset: 11Ch… member

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