/hal_stm32-3.7.0/stm32cube/stm32f0xx/soc/ |
D | stm32f030x8.h | 688 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 689 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
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D | stm32f030x6.h | 672 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 673 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
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D | stm32f070x6.h | 717 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 718 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
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D | stm32f038xx.h | 681 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 682 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
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D | stm32f070xb.h | 740 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 741 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
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D | stm32f030xc.h | 704 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 705 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
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D | stm32f031x6.h | 682 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 683 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
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D | stm32f058xx.h | 787 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 788 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
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D | stm32f051x8.h | 788 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 789 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
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D | stm32f071xb.h | 822 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 823 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
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/hal_stm32-3.7.0/stm32cube/stm32c0xx/soc/ |
D | stm32c031xx.h | 792 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 793 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
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D | stm32c011xx.h | 788 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 789 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
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/hal_stm32-3.7.0/stm32cube/stm32wbxx/soc/Include/ |
D | stm32wb10xx.h | 1130 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 1131 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ 1200 #define ADC_CFGR_AWD1EN_Pos ADC_CFGR1_AWD1EN_Pos
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D | stm32wb15xx.h | 1145 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 1146 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ 1215 #define ADC_CFGR_AWD1EN_Pos ADC_CFGR1_AWD1EN_Pos
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/hal_stm32-3.7.0/stm32cube/stm32wbxx/soc/ |
D | stm32wb1mxx.h | 1145 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 1146 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ 1215 #define ADC_CFGR_AWD1EN_Pos ADC_CFGR1_AWD1EN_Pos
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/hal_stm32-3.7.0/stm32cube/stm32g0xx/soc/ |
D | stm32g070xx.h | 863 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 864 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
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D | stm32g030xx.h | 841 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 842 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
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D | stm32g050xx.h | 860 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 861 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
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D | stm32g031xx.h | 884 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 885 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
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D | stm32g041xx.h | 931 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 932 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
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D | stm32g051xx.h | 947 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 948 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
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D | stm32g061xx.h | 994 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 995 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
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D | stm32g071xx.h | 996 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 997 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
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D | stm32g081xx.h | 1043 #define ADC_CFGR1_AWD1EN_Pos (23U) macro 1044 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
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/hal_stm32-3.7.0/stm32cube/stm32u5xx/drivers/include/ |
D | stm32u5xx_ll_adc.h | 471 #define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR1_AWD1EN_Pos)
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