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Searched refs:ADC_AWD3TR_HT3_Pos (Results 1 – 25 of 35) sorted by relevance

12

/hal_stm32-3.7.0/stm32cube/stm32c0xx/soc/
Dstm32c031xx.h1201 #define ADC_AWD3TR_HT3_Pos (16U) macro
1202 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
1204 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
1205 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
1206 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
1207 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
1208 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
1209 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
1210 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
1211 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
[all …]
Dstm32c011xx.h1197 #define ADC_AWD3TR_HT3_Pos (16U) macro
1198 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
1200 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
1201 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
1202 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
1203 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
1204 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
1205 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
1206 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
1207 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
[all …]
/hal_stm32-3.7.0/stm32cube/stm32g0xx/soc/
Dstm32g070xx.h1260 #define ADC_AWD3TR_HT3_Pos (16U) macro
1261 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
1263 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
1264 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
1265 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
1266 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
1267 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
1268 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
1269 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
1270 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
[all …]
Dstm32g030xx.h1238 #define ADC_AWD3TR_HT3_Pos (16U) macro
1239 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
1241 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
1242 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
1243 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
1244 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
1245 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
1246 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
1247 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
1248 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
[all …]
Dstm32g050xx.h1257 #define ADC_AWD3TR_HT3_Pos (16U) macro
1258 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
1260 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
1261 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
1262 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
1263 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
1264 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
1265 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
1266 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
1267 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
[all …]
Dstm32g031xx.h1281 #define ADC_AWD3TR_HT3_Pos (16U) macro
1282 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
1284 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
1285 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
1286 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
1287 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
1288 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
1289 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
1290 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
1291 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
[all …]
Dstm32g041xx.h1328 #define ADC_AWD3TR_HT3_Pos (16U) macro
1329 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
1331 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
1332 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
1333 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
1334 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
1335 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
1336 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
1337 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
1338 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
[all …]
Dstm32g051xx.h1344 #define ADC_AWD3TR_HT3_Pos (16U) macro
1345 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
1347 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
1348 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
1349 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
1350 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
1351 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
1352 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
1353 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
1354 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
[all …]
Dstm32g061xx.h1391 #define ADC_AWD3TR_HT3_Pos (16U) macro
1392 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
1394 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
1395 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
1396 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
1397 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
1398 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
1399 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
1400 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
1401 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
[all …]
Dstm32g071xx.h1393 #define ADC_AWD3TR_HT3_Pos (16U) macro
1394 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
1396 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
1397 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
1398 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
1399 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
1400 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
1401 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
1402 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
1403 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
[all …]
Dstm32g081xx.h1440 #define ADC_AWD3TR_HT3_Pos (16U) macro
1441 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
1443 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
1444 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
1445 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
1446 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
1447 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
1448 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
1449 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
1450 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
[all …]
Dstm32g0b0xx.h1342 #define ADC_AWD3TR_HT3_Pos (16U) macro
1343 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
1345 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
1346 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
1347 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
1348 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
1349 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
1350 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
1351 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
1352 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
[all …]
Dstm32g0b1xx.h1560 #define ADC_AWD3TR_HT3_Pos (16U) macro
1561 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
1563 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
1564 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
1565 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
1566 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
1567 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
1568 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
1569 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
1570 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
[all …]
Dstm32g0c1xx.h1607 #define ADC_AWD3TR_HT3_Pos (16U) macro
1608 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
1610 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
1611 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
1612 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
1613 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
1614 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
1615 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
1616 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
1617 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
[all …]
/hal_stm32-3.7.0/stm32cube/stm32wlxx/soc/
Dstm32wle5xx.h1564 #define ADC_AWD3TR_HT3_Pos (16U) macro
1565 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
1567 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
1568 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
1569 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
1570 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
1571 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
1572 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
1573 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
1574 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
[all …]
Dstm32wle4xx.h1564 #define ADC_AWD3TR_HT3_Pos (16U) macro
1565 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
1567 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
1568 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
1569 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
1570 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
1571 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
1572 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
1573 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
1574 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
[all …]
Dstm32wl54xx.h1746 #define ADC_AWD3TR_HT3_Pos (16U) macro
1747 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
1749 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
1750 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
1751 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
1752 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
1753 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
1754 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
1755 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
1756 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
[all …]
Dstm32wl5mxx.h1746 #define ADC_AWD3TR_HT3_Pos (16U) macro
1747 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
1749 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
1750 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
1751 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
1752 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
1753 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
1754 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
1755 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
1756 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
[all …]
Dstm32wl55xx.h1746 #define ADC_AWD3TR_HT3_Pos (16U) macro
1747 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
1749 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
1750 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
1751 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
1752 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
1753 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
1754 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
1755 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
1756 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
[all …]
/hal_stm32-3.7.0/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h1625 #define ADC_AWD3TR_HT3_Pos (16U) macro
1626 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
1628 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
1629 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
1630 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
1631 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
1632 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
1633 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
1634 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
1635 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
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Dstm32wba52xx.h2105 #define ADC_AWD3TR_HT3_Pos (16U) macro
2106 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
2108 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
2109 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
2110 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
2111 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
2112 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
2113 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
2114 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
2115 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
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Dstm32wba54xx.h2221 #define ADC_AWD3TR_HT3_Pos (16U) macro
2222 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
2224 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
2225 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
2226 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
2227 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
2228 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
2229 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
2230 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
2231 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
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Dstm32wba55xx.h2221 #define ADC_AWD3TR_HT3_Pos (16U) macro
2222 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
2224 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
2225 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
2226 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
2227 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
2228 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
2229 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
2230 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
2231 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
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/hal_stm32-3.7.0/stm32cube/stm32u5xx/soc/
Dstm32u535xx.h4330 #define ADC_AWD3TR_HT3_Pos (16U) macro
4331 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
4333 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
4334 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
4335 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
4336 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
4337 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
4338 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
4339 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
4340 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
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Dstm32u545xx.h4494 #define ADC_AWD3TR_HT3_Pos (16U) macro
4495 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */
4497 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */
4498 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */
4499 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */
4500 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */
4501 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */
4502 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */
4503 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */
4504 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */
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