1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_HAL_RCC_H 21 #define STM32U5xx_HAL_RCC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 /** @addtogroup STM32U5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup RCC 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup RCC_Exported_Types RCC Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief RCC PLL configuration structure definition 45 */ 46 typedef struct 47 { 48 uint32_t PLLState; /*!< The new state of the PLL. 49 This parameter can be a value of @ref RCC_PLL_Config */ 50 51 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 52 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 53 54 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 55 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ 56 57 uint32_t PLLMBOOST; /*!< PLLMBOOST: Prescaler for EPOD booster input clock. 58 This parameter must be a value of @ref RCC_PLLMBOOST_EPOD_Clock_Divider */ 59 60 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 61 This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ 62 63 uint32_t PLLP; /*!< PLLP: Division factor for peripheral clocks. 64 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 65 66 uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks. 67 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 68 69 uint32_t PLLR; /*!< PLLR: Division factor for system clock. 70 This parameter must be a number between Min_Data = 2 and Max_Data = 128 71 Only division by 1 and even division factors are allowed */ 72 73 uint32_t PLLRGE; /*!< PLLRGE: PLL1 clock Input range 74 This parameter must be a value of @ref RCC_PLL_VCI_Range */ 75 76 uint32_t PLLFRACN; /*!< PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for 77 PLL1 VCO It should be a value between 0 and 8191 */ 78 79 } RCC_PLLInitTypeDef; 80 81 /** 82 * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition 83 */ 84 typedef struct 85 { 86 uint32_t OscillatorType; /*!< The oscillators to be configured. 87 This parameter can be a value of @ref RCC_Oscillator_Type */ 88 89 uint32_t HSEState; /*!< The new state of the HSE. 90 This parameter can be a value of @ref RCC_HSE_Config */ 91 92 uint32_t LSEState; /*!< The new state of the LSE. 93 This parameter can be a value of @ref RCC_LSE_Config */ 94 95 uint32_t HSIState; /*!< The new state of the HSI. 96 This parameter can be a value of @ref RCC_HSI_Config */ 97 98 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 99 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F 100 on the other devices */ 101 102 uint32_t LSIState; /*!< The new state of the LSI. 103 This parameter can be a value of @ref RCC_LSI_Config */ 104 105 uint32_t LSIDiv; /*!< The division factor of the LSI. 106 This parameter can be a value of @ref RCC_LSI_Div */ 107 108 uint32_t MSIState; /*!< The new state of the MSI. 109 This parameter can be a value of @ref RCC_MSI_Config */ 110 111 uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT). 112 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 113 114 uint32_t MSIClockRange; /*!< The MSI frequency range. 115 This parameter can be a value of @ref RCC_MSI_Clock_Range */ 116 117 uint32_t MSIKClockRange; /*!< The MSIK frequency range. 118 This parameter can be a value of @ref RCC_MSIK_Clock_Range */ 119 120 uint32_t HSI48State; /*!< The new state of the HSI48. 121 This parameter can be a value of @ref RCC_HSI48_Config */ 122 123 uint32_t SHSIState; /*!< The new state of the SHSI. 124 This parameter can be a value of @ref RCC_SHSI_Config */ 125 126 uint32_t MSIKState; /*!< The new state of the MSIK. 127 This parameter can be a value of @ref RCC_MSIK_Config */ 128 129 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ 130 131 } RCC_OscInitTypeDef; 132 133 /** 134 * @brief RCC System, AHB and APB busses clock configuration structure definition 135 */ 136 typedef struct 137 { 138 uint32_t ClockType; /*!< The clock to be configured. 139 This parameter can be a value of @ref RCC_System_Clock_Type */ 140 141 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 142 This parameter can be a value of @ref RCC_System_Clock_Source */ 143 144 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock 145 (SYSCLK). 146 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 147 148 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 149 This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ 150 151 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 152 This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ 153 154 uint32_t APB3CLKDivider; /*!< The APB3 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK). 155 This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ 156 } RCC_ClkInitTypeDef; 157 158 /** 159 * @} 160 */ 161 162 /* Exported constants --------------------------------------------------------*/ 163 /** @defgroup RCC_Exported_Constants RCC Exported Constants 164 * @{ 165 */ 166 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 167 #define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 168 #define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 169 170 /* Defines used for Flags */ 171 #define CR_REG_INDEX (1U) 172 #define BDCR_REG_INDEX (2U) 173 #define CSR_REG_INDEX (3U) 174 #define CRRCR_REG_INDEX (4U) 175 176 #define RCC_FLAG_MASK (0x1FU) 177 /** 178 * @} 179 */ 180 181 /** @defgroup RCC_Reset_Flag Reset Flag 182 * @{ 183 */ 184 #define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */ 185 #define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */ 186 #define RCC_RESET_FLAG_PWR RCC_CSR_BORRSTF /*!< BOR or POR/PDR reset flag */ 187 #define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */ 188 #define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 189 #define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ 190 #define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */ 191 #define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ 192 RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \ 193 RCC_RESET_FLAG_LPWR) 194 /** 195 * @} 196 */ 197 198 /** @defgroup RCC_Timeout_Value Timeout Values 199 * @{ 200 */ 201 #define RCC_DBP_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 202 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 203 /** 204 * @} 205 */ 206 207 /** @defgroup RCC_Oscillator_Type Oscillator Type 208 * @{ 209 */ 210 #define RCC_OSCILLATORTYPE_NONE 0x0UL /*!< Oscillator configuration unchanged */ 211 #define RCC_OSCILLATORTYPE_HSE 0x1UL /*!< HSE to configure */ 212 #define RCC_OSCILLATORTYPE_HSI 0x2UL /*!< HSI to configure */ 213 #define RCC_OSCILLATORTYPE_LSE 0x4UL /*!< LSE to configure */ 214 #define RCC_OSCILLATORTYPE_LSI 0x8UL /*!< LSI to configure */ 215 #define RCC_OSCILLATORTYPE_MSI 0x10UL /*!< MSI to configure */ 216 #define RCC_OSCILLATORTYPE_HSI48 0x20UL /*!< HSI48 to configure */ 217 #define RCC_OSCILLATORTYPE_MSIK 0x040U /*!< MSIK to configure */ 218 #define RCC_OSCILLATORTYPE_SHSI 0x80UL /*!< SHSI to configure */ 219 /* Defines Oscillator Masks */ 220 #define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI | \ 221 RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_MSIK | \ 222 RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_SHSI) /*!< All Oscillator to configure */ 223 /** 224 * @} 225 */ 226 227 /** @defgroup RCC_HSE_Config HSE Config 228 * @{ 229 */ 230 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ 231 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 232 #define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ 233 #define RCC_HSE_BYPASS_DIGITAL (RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON) 234 /** 235 * @} 236 */ 237 238 /** @defgroup RCC_LSE_Config LSE Config 239 * @{ 240 */ 241 #define RCC_LSE_OFF 0U /*!< LSE clock deactivation */ 242 #define RCC_LSE_ON_RTC_ONLY RCC_BDCR_LSEON /*!< LSE clock activation for RTC only */ 243 #define RCC_LSE_ON (RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON) /*!< LSE clock activation for RCC and peripherals */ 244 #define RCC_LSE_BYPASS_RTC_ONLY (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ 245 #define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ 246 /** 247 * @} 248 */ 249 250 /** @defgroup RCC_HSI_Config HSI Config 251 * @{ 252 */ 253 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 254 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 255 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ 256 /** 257 * @} 258 */ 259 260 /** @defgroup RCC_LSI_Config LSI Config 261 * @{ 262 */ 263 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ 264 #define RCC_LSI_ON RCC_BDCR_LSION /*!< LSI clock activation */ 265 /** 266 * @} 267 */ 268 269 /** @defgroup RCC_LSI_Div LSI Div 270 * @{ 271 */ 272 #define RCC_LSI_DIV1 0U /*!< LSI clock is not divided */ 273 #define RCC_LSI_DIV128 RCC_BDCR_LSIPREDIV /*!< LSI clock is divided by 128 */ 274 /** 275 * @} 276 */ 277 278 /** @defgroup RCC_MSI_Config MSI Config 279 * @{ 280 */ 281 #define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */ 282 #define RCC_MSI_ON RCC_CR_MSISON /*!< MSI clock activation */ 283 284 #define RCC_MSICALIBRATION_DEFAULT 0x10U /*!< Default MSI calibration trimming value */ 285 /** 286 * @} 287 */ 288 289 /** @defgroup RCC_HSI48_Config HSI48 Config 290 * @{ 291 */ 292 #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ 293 #define RCC_HSI48_ON RCC_CR_HSI48ON /*!< HSI48 clock activation */ 294 /** 295 * @} 296 */ 297 298 /** @defgroup RCC_MSIK_Config MSIK Config 299 * @{ 300 */ 301 #define RCC_MSIK_OFF 0x00000000U /*!< MSIK clock deactivation */ 302 #define RCC_MSIK_ON RCC_CR_MSIKON /*!< MSIK clock activation */ 303 /** 304 * @} 305 */ 306 307 /** @defgroup RCC_SHSI_Config SHSI Config 308 * @{ 309 */ 310 #define RCC_SHSI_OFF 0x00000000U /*!< SHSI clock deactivation */ 311 #define RCC_SHSI_ON RCC_CR_SHSION /*!< SHSI clock activation */ 312 /** 313 * @} 314 */ 315 316 /** @defgroup RCC_PLL_Config RCC PLL Config 317 * @{ 318 */ 319 #define RCC_PLL_NONE 0x00000000U 320 #define RCC_PLL_OFF 0x00000001U 321 #define RCC_PLL_ON 0x00000002U 322 /** 323 * @} 324 */ 325 326 327 328 329 /** @defgroup RCC_PLL_Clock_Output RCC PLL Clock Output 330 * @{ 331 */ 332 #define RCC_PLL1_DIVP RCC_PLL1CFGR_PLL1PEN 333 #define RCC_PLL1_DIVQ RCC_PLL1CFGR_PLL1QEN 334 #define RCC_PLL1_DIVR RCC_PLL1CFGR_PLL1REN 335 336 /** 337 * @} 338 */ 339 340 /** @defgroup RCC_PLLMBOOST_EPOD_Clock_Divider PLLMBOOST EPOD Clock Divider 341 * @{ 342 */ 343 #define RCC_PLLMBOOST_DIV1 0x00000000U 344 #define RCC_PLLMBOOST_DIV2 RCC_PLL1CFGR_PLL1MBOOST_0 345 #define RCC_PLLMBOOST_DIV4 RCC_PLL1CFGR_PLL1MBOOST_1 346 #define RCC_PLLMBOOST_DIV6 (RCC_PLL1CFGR_PLL1MBOOST_1 | RCC_PLL1CFGR_PLL1MBOOST_0) 347 #define RCC_PLLMBOOST_DIV8 RCC_PLL1CFGR_PLL1MBOOST_2 348 #define RCC_PLLMBOOST_DIV10 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_0) 349 #define RCC_PLLMBOOST_DIV12 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1) 350 #define RCC_PLLMBOOST_DIV14 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1| RCC_PLL1CFGR_PLL1MBOOST_0) 351 #define RCC_PLLMBOOST_DIV16 RCC_PLL1CFGR_PLL1MBOOST_3 352 /** 353 * @} 354 */ 355 356 /** @defgroup RCC_PLL_VCI_Range RCC PLL1 VCI Range 357 * @{ 358 */ 359 #define RCC_PLLVCIRANGE_0 0x00000000U 360 #define RCC_PLLVCIRANGE_1 (RCC_PLL1CFGR_PLL1RGE_1 | RCC_PLL1CFGR_PLL1RGE_0) 361 /** 362 * @} 363 */ 364 365 /** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source 366 * @{ 367 */ 368 #define RCC_PLLSOURCE_NONE 0x00000000U 369 #define RCC_PLLSOURCE_MSI RCC_PLL1CFGR_PLL1SRC_0 370 #define RCC_PLLSOURCE_HSI RCC_PLL1CFGR_PLL1SRC_1 371 #define RCC_PLLSOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) 372 373 /** 374 * @} 375 */ 376 377 378 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range 379 * @{ 380 */ 381 #define RCC_MSIRANGE_0 0x00000000U /*!< MSI = 48 MHz */ 382 #define RCC_MSIRANGE_1 RCC_ICSCR1_MSISRANGE_0 /*!< MSI = 24 MHz */ 383 #define RCC_MSIRANGE_2 RCC_ICSCR1_MSISRANGE_1 /*!< MSI = 16 MHz */ 384 #define RCC_MSIRANGE_3 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1) /*!< MSI = 12 MHz */ 385 #define RCC_MSIRANGE_4 RCC_ICSCR1_MSISRANGE_2 /*!< MSI = 4 MHz */ 386 #define RCC_MSIRANGE_5 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2) /*!< MSI = 2 MHz */ 387 #define RCC_MSIRANGE_6 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSI = 1.33 MHz */ 388 #define RCC_MSIRANGE_7 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSI = 1 MHz */ 389 #define RCC_MSIRANGE_8 RCC_ICSCR1_MSISRANGE_3 /*!< MSI = 3.072 MHz */ 390 #define RCC_MSIRANGE_9 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 1.536 MHz */ 391 #define RCC_MSIRANGE_10 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 1.024 MHz */ 392 #define RCC_MSIRANGE_11 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 768 KHz */ 393 #define RCC_MSIRANGE_12 (RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 400 KHz */ 394 #define RCC_MSIRANGE_13 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 200 KHz */ 395 #define RCC_MSIRANGE_14 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 133 KHz */ 396 #define RCC_MSIRANGE_15 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1| RCC_ICSCR1_MSISRANGE_2 |\ 397 RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 100 KHz */ 398 /** 399 * @} 400 */ 401 402 /** @defgroup RCC_MSIK_Clock_Range MSIK Clock Range 403 * @{ 404 */ 405 #define RCC_MSIKRANGE_0 0x00000000U /*!< MSIK = 48 MHz */ 406 #define RCC_MSIKRANGE_1 RCC_ICSCR1_MSIKRANGE_0 /*!< MSIK = 24 MHz */ 407 #define RCC_MSIKRANGE_2 RCC_ICSCR1_MSIKRANGE_1 /*!< MSIK = 16 MHz */ 408 #define RCC_MSIKRANGE_3 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1) /*!< MSIK = 12 MHz */ 409 #define RCC_MSIKRANGE_4 RCC_ICSCR1_MSIKRANGE_2 /*!< MSIK = 4 MHz */ 410 #define RCC_MSIKRANGE_5 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 2 MHz */ 411 #define RCC_MSIKRANGE_6 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1.33 MHz */ 412 #define RCC_MSIKRANGE_7 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1 MHz */ 413 #define RCC_MSIKRANGE_8 RCC_ICSCR1_MSIKRANGE_3 /*!< MSIK = 3.072 MHz */ 414 #define RCC_MSIKRANGE_9 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.536 MHz */ 415 #define RCC_MSIKRANGE_10 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.024 MHz */ 416 #define RCC_MSIKRANGE_11 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 768 KHz */ 417 #define RCC_MSIKRANGE_12 (RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 400 KHz */ 418 #define RCC_MSIKRANGE_13 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 200 KHz */ 419 #define RCC_MSIKRANGE_14 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 133 KHz */ 420 #define RCC_MSIKRANGE_15 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 |\ 421 RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 100 KHz */ 422 /** 423 * @} 424 */ 425 426 /** @defgroup RCC_System_Clock_Type System Clock Type 427 * @{ 428 */ 429 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 430 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 431 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 432 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ 433 #define RCC_CLOCKTYPE_PCLK3 0x00000010U /*!< PCLK3 to configure */ 434 /** 435 * @} 436 */ 437 438 /** @defgroup RCC_System_Clock_Source System Clock Source 439 * @{ 440 */ 441 #define RCC_SYSCLKSOURCE_MSI 0x00000000U /*!< MSI selection as system clock */ 442 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR1_SW_0 /*!< HSI selection as system clock */ 443 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE selection as system clock */ 444 #define RCC_SYSCLKSOURCE_PLLCLK (RCC_CFGR1_SW_0 | RCC_CFGR1_SW_1) /*!< PLL1 selection as system clock */ 445 /** 446 * @} 447 */ 448 449 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 450 * @{ 451 */ 452 #define RCC_SYSCLKSOURCE_STATUS_MSI 0x00000000U /*!< MSI used as system clock */ 453 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR1_SWS_0 /*!< HSI used as system clock */ 454 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE used as system clock */ 455 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK (RCC_CFGR1_SWS_0 | RCC_CFGR1_SWS_1) /*!< PLL1 used as system clock */ 456 /** 457 * @} 458 */ 459 460 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 461 * @{ 462 */ 463 #define RCC_SYSCLK_DIV1 0x00000000U /*!< SYSCLK not divided */ 464 #define RCC_SYSCLK_DIV2 RCC_CFGR2_HPRE_3 /*!< SYSCLK divided by 2 */ 465 #define RCC_SYSCLK_DIV4 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 4 */ 466 #define RCC_SYSCLK_DIV8 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 8 */ 467 #define RCC_SYSCLK_DIV16 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 16 */ 468 #define RCC_SYSCLK_DIV64 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 64 */ 469 #define RCC_SYSCLK_DIV128 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 128 */ 470 #define RCC_SYSCLK_DIV256 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 256 */ 471 #define RCC_SYSCLK_DIV512 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 512 */ 472 /** 473 * @} 474 */ 475 476 /** @defgroup RCC_APB1_APB2_APB3_Clock_Source APB1 APB2 APB3 Clock Source 477 * @{ 478 */ 479 #define RCC_HCLK_DIV1 (0x00000000U) /*!< HCLK not divided */ 480 #define RCC_HCLK_DIV2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */ 481 #define RCC_HCLK_DIV4 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 4 */ 482 #define RCC_HCLK_DIV8 (RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 8 */ 483 #define RCC_HCLK_DIV16 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 16 */ 484 /** 485 * @} 486 */ 487 488 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 489 * @{ 490 */ 491 #define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock used as RTC clock */ 492 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 493 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 494 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ 495 /** 496 * @} 497 */ 498 499 /** @defgroup RCC_MCO_Index MCO Index 500 * @{ 501 */ 502 #define RCC_MCO1 0x00000000U 503 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ 504 /** 505 * @} 506 */ 507 508 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 509 * @{ 510 */ 511 #define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ 512 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR1_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ 513 #define RCC_MCO1SOURCE_MSI RCC_CFGR1_MCOSEL_1 /*!< MSI selection as MCO1 source */ 514 #define RCC_MCO1SOURCE_HSI (RCC_CFGR1_MCOSEL_0| RCC_CFGR1_MCOSEL_1) /*!< HSI selection as MCO1 source */ 515 #define RCC_MCO1SOURCE_HSE RCC_CFGR1_MCOSEL_2 /*!< HSE selection as MCO1 source */ 516 #define RCC_MCO1SOURCE_PLL1CLK (RCC_CFGR1_MCOSEL_0|RCC_CFGR1_MCOSEL_2) /*!< PLL1CLK selection as MCO1 source */ 517 #define RCC_MCO1SOURCE_LSI (RCC_CFGR1_MCOSEL_1|RCC_CFGR1_MCOSEL_2) /*!< LSI selection as MCO1 source */ 518 #define RCC_MCO1SOURCE_LSE (RCC_CFGR1_MCOSEL_0|RCC_CFGR1_MCOSEL_1|RCC_CFGR1_MCOSEL_2) /*!< LSE selection as MCO1 source */ 519 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR1_MCOSEL_3 /*!< HSI48 selection as MCO1 source */ 520 #define RCC_MCO1SOURCE_MSIK (RCC_CFGR1_MCOSEL_0| RCC_CFGR1_MCOSEL_3) /*!< MSIK selection as MCO1 source */ 521 /** 522 * @} 523 */ 524 525 /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler 526 * @{ 527 */ 528 #define RCC_MCODIV_1 0x00000000U /*!< MCO is divided by 1 */ 529 #define RCC_MCODIV_2 RCC_CFGR1_MCOPRE_0 /*!< MCO is divided by 2 */ 530 #define RCC_MCODIV_4 RCC_CFGR1_MCOPRE_1 /*!< MCO is divided by 4 */ 531 #define RCC_MCODIV_8 (RCC_CFGR1_MCOPRE_0 | RCC_CFGR1_MCOPRE_1)/*!< MCO is divided by 8 */ 532 #define RCC_MCODIV_16 RCC_CFGR1_MCOPRE_2 /*!< MCO is divided by 16 */ 533 /** 534 * @} 535 */ 536 537 /** @defgroup RCC_Interrupt Interrupts 538 * @{ 539 */ 540 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 541 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 542 #define RCC_IT_MSIRDY RCC_CIFR_MSISRDYF /*!< MSI Ready Interrupt flag */ 543 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ 544 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 545 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 546 #define RCC_IT_PLLRDY RCC_CIFR_PLL1RDYF /*!< PLL1 Ready Interrupt flag */ 547 #define RCC_IT_PLL2RDY RCC_CIFR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */ 548 #define RCC_IT_PLL3RDY RCC_CIFR_PLL3RDYF /*!< PLL3 Ready Interrupt flag */ 549 #define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ 550 #define RCC_IT_MSIKRDY RCC_CIFR_MSIKRDYF /*!< MSIK Ready Interrupt flag */ 551 #define RCC_IT_SHSIRDY RCC_CIFR_SHSIRDYF /*!< SHSI Ready Interrupt flag */ 552 /** 553 * @} 554 */ 555 556 /** @defgroup RCC_Flag Flags 557 * Elements values convention: XXXYYYYYb 558 * - YYYYY : Flag position in the register 559 * - XXX : Register index 560 * - 001: CR register 561 * - 010: BDCR register 562 * - 011: CSR register 563 * - 100: CRRCR register 564 * @{ 565 */ 566 /* Flags in the CR register */ 567 #define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_MSISRDY_Pos)) /*!< MSI Ready flag */ 568 #define RCC_FLAG_MSIKRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_MSIKRDY_Pos)) /*!< MSI Ready flag */ 569 #define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< HSI Ready flag */ 570 #define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< HSE Ready flag */ 571 #define RCC_FLAG_PLL1RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL1RDY_Pos)) /*!< PLL Ready flag */ 572 #define RCC_FLAG_PLL2RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos)) /*!< PLL2 Ready flag */ 573 #define RCC_FLAG_PLL3RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos)) /*!< PLL3 Ready flag */ 574 #define RCC_FLAG_SHSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_SHSIRDY_Pos)) /*!< SHSI Ready flag */ 575 #define RCC_FLAG_HSI48RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos)) /*!< HSI48 Ready flag */ 576 577 /* Flags in the BDCR register */ 578 #define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< LSE Ready flag */ 579 #define RCC_FLAG_LSESYSRDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSESYSRDY_Pos)) /*!< LSESYS Ready flag */ 580 #define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)) /*!< LSE Clock Security System Interrupt flag */ 581 #define RCC_FLAG_LSIRDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSIRDY_Pos)) /*!< LSI Ready flag */ 582 /* Flags in the CSR register */ 583 #define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_RMVF_Pos)) /*!< Remove reset flag */ 584 #define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)) /*!< Option Byte Loader reset flag */ 585 #define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */ 586 #define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)) /*!< BOR reset flag */ 587 #define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */ 588 #define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ 589 #define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ 590 #define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ 591 592 /** 593 * @} 594 */ 595 596 /** @defgroup RCC_LSEDrive_Config LSE Drive Config 597 * @{ 598 */ 599 #define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ 600 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ 601 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ 602 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ 603 /** 604 * @} 605 */ 606 607 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock 608 * @{ 609 */ 610 #define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */ 611 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR1_STOPWUCK /*!< HSI selection after wake-up from STOP */ 612 /** 613 * @} 614 */ 615 616 /** @defgroup RCC_Stop_KernelWakeUpClock RCC Stop KernelWakeUpClock 617 * @{ 618 */ 619 #define RCC_STOP_KERWAKEUPCLOCK_MSI 0x00000000U /*!< MSI kernel clock selection after wake-up from STOP */ 620 #define RCC_STOP_KERWAKEUPCLOCK_HSI RCC_CFGR1_STOPKERWUCK /*!< HSI kernel clock selection after wake-up from STOP */ 621 622 /** 623 * @} 624 */ 625 626 /** @defgroup RCC_items RCC items 627 * @brief RCC items to configure attributes on 628 * @{ 629 */ 630 #define RCC_HSI RCC_SECCFGR_HSISEC 631 #define RCC_HSE RCC_SECCFGR_HSESEC 632 #define RCC_MSI RCC_SECCFGR_MSISEC 633 #define RCC_LSI RCC_SECCFGR_LSISEC 634 #define RCC_LSE RCC_SECCFGR_LSESEC 635 #define RCC_SYSCLK RCC_SECCFGR_SYSCLKSEC 636 #define RCC_PRESC RCC_SECCFGR_PRESCSEC 637 #define RCC_PLL1 RCC_SECCFGR_PLL1SEC 638 #define RCC_PLL2 RCC_SECCFGR_PLL2SEC 639 #define RCC_PLL3 RCC_SECCFGR_PLL3SEC 640 #define RCC_ICLK RCC_SECCFGR_ICLKSEC 641 #define RCC_HSI48 RCC_SECCFGR_HSI48SEC 642 #define RCC_RMVF RCC_SECCFGR_RMVFSEC 643 #define RCC_ALL (RCC_HSI|RCC_HSE|RCC_MSI|RCC_LSI|RCC_LSE|RCC_HSI48| \ 644 RCC_SYSCLK|RCC_PRESC|RCC_PLL1|RCC_PLL2| \ 645 RCC_PLL3|RCC_ICLK|RCC_RMVF) 646 /** 647 * @} 648 */ 649 650 /** @defgroup RCC_attributes RCC attributes 651 * @brief RCC privilege/non-privilege and secure/non-secure attributes 652 * @{ 653 */ 654 #define RCC_NSEC_PRIV 0x00000001U /*!< Non-secure Privilege attribute item */ 655 #define RCC_NSEC_NPRIV 0x00000002U /*!< Non-secure Non-privilege attribute item */ 656 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 657 #define RCC_SEC_PRIV 0x00000010U /*!< Secure Privilege attribute item */ 658 #define RCC_SEC_NPRIV 0x00000020U /*!< Secure Non-privilege attribute item */ 659 #endif /* __ARM_FEATURE_CMSE */ 660 /** 661 * @} 662 */ 663 664 /* Exported macros -----------------------------------------------------------*/ 665 666 /** @defgroup RCC_Exported_Macros RCC Exported Macros 667 * @{ 668 */ 669 670 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 671 * @brief Enable or disable the AHB1 peripheral clock. 672 * @note After reset, the peripheral clock (used for registers read/write access) 673 * is disabled and the application software has to enable this clock before 674 * using it. 675 * @{ 676 */ 677 #define __HAL_RCC_GPDMA1_CLK_ENABLE() do { \ 678 __IO uint32_t tmpreg; \ 679 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 680 /* Delay after an RCC peripheral clock enabling */ \ 681 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 682 UNUSED(tmpreg); \ 683 } while(0) 684 #define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ 685 __IO uint32_t tmpreg; \ 686 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 687 /* Delay after an RCC peripheral clock enabling */ \ 688 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 689 UNUSED(tmpreg); \ 690 } while(0) 691 #define __HAL_RCC_FMAC_CLK_ENABLE() do { \ 692 __IO uint32_t tmpreg; \ 693 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 694 /* Delay after an RCC peripheral clock enabling */ \ 695 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 696 UNUSED(tmpreg); \ 697 } while(0) 698 #define __HAL_RCC_TSC_CLK_ENABLE() do { \ 699 __IO uint32_t tmpreg; \ 700 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 701 /* Delay after an RCC peripheral clock enabling */ \ 702 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 703 UNUSED(tmpreg); \ 704 } while(0) 705 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 706 __IO uint32_t tmpreg; \ 707 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 708 /* Delay after an RCC peripheral clock enabling */ \ 709 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 710 UNUSED(tmpreg); \ 711 } while(0) 712 713 #if defined(JPEG) 714 #define __HAL_RCC_JPEG_CLK_ENABLE() do { \ 715 __IO uint32_t tmpreg; \ 716 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN); \ 717 /* Delay after an RCC peripheral clock enabling */ \ 718 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN); \ 719 UNUSED(tmpreg); \ 720 } while(0) 721 #endif /* JPEG */ 722 723 #define __HAL_RCC_RAMCFG_CLK_ENABLE() do { \ 724 __IO uint32_t tmpreg; \ 725 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ 726 /* Delay after an RCC peripheral clock enabling */ \ 727 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ 728 UNUSED(tmpreg); \ 729 } while(0) 730 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ 731 __IO uint32_t tmpreg; \ 732 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 733 /* Delay after an RCC peripheral clock enabling */ \ 734 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 735 UNUSED(tmpreg); \ 736 } while(0) 737 738 #define __HAL_RCC_MDF1_CLK_ENABLE() do { \ 739 __IO uint32_t tmpreg; \ 740 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \ 741 /* Delay after an RCC peripheral clock enabling */ \ 742 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \ 743 UNUSED(tmpreg); \ 744 } while(0) 745 746 #if defined(DMA2D) 747 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ 748 __IO uint32_t tmpreg; \ 749 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ 750 /* Delay after an RCC peripheral clock enabling */ \ 751 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ 752 UNUSED(tmpreg); \ 753 } while(0) 754 #endif /* DMA2D */ 755 756 #if defined(GFXMMU) 757 #define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ 758 __IO uint32_t tmpreg; \ 759 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ 760 /* Delay after an RCC peripheral clock enabling */ \ 761 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ 762 UNUSED(tmpreg); \ 763 } while(0) 764 #endif /* GFXMMU */ 765 766 #if defined(GPU2D) 767 #define __HAL_RCC_GPU2D_CLK_ENABLE() do { \ 768 __IO uint32_t tmpreg; \ 769 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN); \ 770 /* Delay after an RCC peripheral clock enabling */ \ 771 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN); \ 772 UNUSED(tmpreg); \ 773 } while(0) 774 #endif /* GPU2D */ 775 776 #if defined(DCACHE2) 777 #define __HAL_RCC_DCACHE2_CLK_ENABLE() do { \ 778 __IO uint32_t tmpreg; \ 779 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN); \ 780 /* Delay after an RCC peripheral clock enabling */ \ 781 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN); \ 782 UNUSED(tmpreg); \ 783 } while(0) 784 #endif /* DCACHE2 */ 785 786 #define __HAL_RCC_GTZC1_CLK_ENABLE() do { \ 787 __IO uint32_t tmpreg; \ 788 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \ 789 /* Delay after an RCC peripheral clock enabling */ \ 790 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \ 791 UNUSED(tmpreg); \ 792 } while(0) 793 794 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ 795 __IO uint32_t tmpreg; \ 796 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); \ 797 /* Delay after an RCC peripheral clock enabling */ \ 798 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); \ 799 UNUSED(tmpreg); \ 800 } while(0) 801 802 #define __HAL_RCC_DCACHE1_CLK_ENABLE() do { \ 803 __IO uint32_t tmpreg; \ 804 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ 805 /* Delay after an RCC peripheral clock enabling */ \ 806 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ 807 UNUSED(tmpreg); \ 808 } while(0) 809 810 #define __HAL_RCC_SRAM1_CLK_ENABLE() do { \ 811 __IO uint32_t tmpreg; \ 812 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ 813 /* Delay after an RCC peripheral clock enabling */ \ 814 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ 815 UNUSED(tmpreg); \ 816 } while(0) 817 818 #define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) 819 820 #define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) 821 822 #define __HAL_RCC_FMAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) 823 824 #define __HAL_RCC_MDF1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN) 825 826 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) 827 828 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) 829 830 #if defined(JPEG) 831 #define __HAL_RCC_JPEG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN) 832 #endif /* JPEG */ 833 834 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) 835 836 #define __HAL_RCC_RAMCFG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) 837 838 #if defined(DMA2D) 839 #define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) 840 #endif /* DMA2D */ 841 842 #if defined(GFXMMU) 843 #define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) 844 #endif /* GFXMMU */ 845 846 #if defined(GPU2D) 847 #define __HAL_RCC_GPU2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN) 848 #endif /* GPU2D */ 849 850 #if defined(DCACHE2) 851 #define __HAL_RCC_DCACHE2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN) 852 #endif /* DCACHE2 */ 853 854 #define __HAL_RCC_GTZC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) 855 856 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN) 857 858 #define __HAL_RCC_DCACHE1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) 859 860 #define __HAL_RCC_SRAM1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) 861 /** 862 * @} 863 */ 864 865 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 866 * @brief Enable or disable the AHB2 peripheral clock. 867 * @note After reset, the peripheral clock (used for registers read/write access) 868 * is disabled and the application software has to enable this clock before 869 * using it. 870 * @{ 871 */ 872 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 873 __IO uint32_t tmpreg; \ 874 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN); \ 875 /* Delay after an RCC peripheral clock enabling */ \ 876 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN); \ 877 UNUSED(tmpreg); \ 878 } while(0) 879 880 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 881 __IO uint32_t tmpreg; \ 882 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN); \ 883 /* Delay after an RCC peripheral clock enabling */ \ 884 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN); \ 885 UNUSED(tmpreg); \ 886 } while(0) 887 888 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 889 __IO uint32_t tmpreg; \ 890 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN); \ 891 /* Delay after an RCC peripheral clock enabling */ \ 892 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN); \ 893 UNUSED(tmpreg); \ 894 } while(0) 895 896 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 897 __IO uint32_t tmpreg; \ 898 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN); \ 899 /* Delay after an RCC peripheral clock enabling */ \ 900 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN); \ 901 UNUSED(tmpreg); \ 902 } while(0) 903 904 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 905 __IO uint32_t tmpreg; \ 906 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN); \ 907 /* Delay after an RCC peripheral clock enabling */ \ 908 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN); \ 909 UNUSED(tmpreg); \ 910 } while(0) 911 912 #if defined(GPIOF) 913 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 914 __IO uint32_t tmpreg; \ 915 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN); \ 916 /* Delay after an RCC peripheral clock enabling */ \ 917 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN); \ 918 UNUSED(tmpreg); \ 919 } while(0) 920 #endif /* GPIOF */ 921 922 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 923 __IO uint32_t tmpreg; \ 924 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN); \ 925 /* Delay after an RCC peripheral clock enabling */ \ 926 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN); \ 927 UNUSED(tmpreg); \ 928 } while(0) 929 930 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 931 __IO uint32_t tmpreg; \ 932 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN); \ 933 /* Delay after an RCC peripheral clock enabling */ \ 934 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN); \ 935 UNUSED(tmpreg); \ 936 } while(0) 937 938 #if defined (GPIOI) 939 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 940 __IO uint32_t tmpreg; \ 941 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN); \ 942 /* Delay after an RCC peripheral clock enabling */ \ 943 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN); \ 944 UNUSED(tmpreg); \ 945 } while(0) 946 #endif /* GPIOI */ 947 948 #if defined(GPIOJ) 949 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ 950 __IO uint32_t tmpreg; \ 951 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN); \ 952 /* Delay after an RCC peripheral clock enabling */ \ 953 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN); \ 954 UNUSED(tmpreg); \ 955 } while(0) 956 957 #endif /* GPIOJ */ 958 959 #define __HAL_RCC_ADC12_CLK_ENABLE() do { \ 960 __IO uint32_t tmpreg; \ 961 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN); \ 962 /* Delay after an RCC peripheral clock enabling */ \ 963 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN); \ 964 UNUSED(tmpreg); \ 965 } while(0) 966 967 #define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \ 968 __IO uint32_t tmpreg; \ 969 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN); \ 970 /* Delay after an RCC peripheral clock enabling */ \ 971 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN); \ 972 UNUSED(tmpreg); \ 973 } while(0) 974 #if defined (USB_OTG_HS) 975 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ 976 __IO uint32_t tmpreg; \ 977 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ 978 /* Delay after an RCC peripheral clock enabling */ \ 979 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ 980 UNUSED(tmpreg); \ 981 } while(0) 982 #endif /* USB_OTG_HS */ 983 984 #if defined(USB_OTG_FS) 985 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 986 __IO uint32_t tmpreg; \ 987 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ 988 /* Delay after an RCC peripheral clock enabling */ \ 989 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ 990 UNUSED(tmpreg); \ 991 } while(0) 992 993 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE /*!< alias define for compatibility with legacy code */ 994 #endif /* defined (USB_OTG_FS) */ 995 996 #if defined(RCC_AHB2ENR1_USBPHYCEN) 997 #define __HAL_RCC_USBPHYC_CLK_ENABLE() do { \ 998 __IO uint32_t tmpreg; \ 999 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_USBPHYCEN); \ 1000 /* Delay after an RCC peripheral clock enabling */ \ 1001 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_USBPHYCEN); \ 1002 UNUSED(tmpreg); \ 1003 } while(0) 1004 #endif /* defined (RCC_AHB2ENR1_USBPHYCEN) */ 1005 1006 #if defined(AES) 1007 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 1008 __IO uint32_t tmpreg; \ 1009 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN); \ 1010 /* Delay after an RCC peripheral clock enabling */ \ 1011 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN); \ 1012 UNUSED(tmpreg); \ 1013 } while(0) 1014 #endif /* AES */ 1015 1016 #if defined(HASH) 1017 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 1018 __IO uint32_t tmpreg; \ 1019 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN); \ 1020 /* Delay after an RCC peripheral clock enabling */ \ 1021 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN); \ 1022 UNUSED(tmpreg); \ 1023 } while(0) 1024 #endif /* HASH */ 1025 1026 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 1027 __IO uint32_t tmpreg; \ 1028 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN); \ 1029 /* Delay after an RCC peripheral clock enabling */ \ 1030 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN); \ 1031 UNUSED(tmpreg); \ 1032 } while(0) 1033 1034 #if defined(PKA) 1035 #define __HAL_RCC_PKA_CLK_ENABLE() do { \ 1036 __IO uint32_t tmpreg; \ 1037 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN); \ 1038 /* Delay after an RCC peripheral clock enabling */ \ 1039 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN); \ 1040 UNUSED(tmpreg); \ 1041 } while(0) 1042 #endif /* PKA */ 1043 1044 #if defined(SAES) 1045 #define __HAL_RCC_SAES_CLK_ENABLE() do { \ 1046 __IO uint32_t tmpreg; \ 1047 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN); \ 1048 /* Delay after an RCC peripheral clock enabling */ \ 1049 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN); \ 1050 UNUSED(tmpreg); \ 1051 } while(0) 1052 #endif /* SAES */ 1053 1054 #if defined(OCTOSPIM) 1055 #define __HAL_RCC_OSPIM_CLK_ENABLE() do { \ 1056 __IO uint32_t tmpreg; \ 1057 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN); \ 1058 /* Delay after an RCC peripheral clock enabling */ \ 1059 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN); \ 1060 UNUSED(tmpreg); \ 1061 } while(0) 1062 #endif /* OCTOSPIM */ 1063 1064 #if defined(OTFDEC1) 1065 #define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \ 1066 __IO uint32_t tmpreg; \ 1067 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN); \ 1068 /* Delay after an RCC peripheral clock enabling */ \ 1069 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN); \ 1070 UNUSED(tmpreg); \ 1071 } while(0) 1072 #endif /* OTFDEC1 */ 1073 1074 #if defined(OTFDEC2) 1075 #define __HAL_RCC_OTFDEC2_CLK_ENABLE() do { \ 1076 __IO uint32_t tmpreg; \ 1077 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN); \ 1078 /* Delay after an RCC peripheral clock enabling */ \ 1079 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN); \ 1080 UNUSED(tmpreg); \ 1081 } while(0) 1082 #endif /* OTFDEC2 */ 1083 1084 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 1085 __IO uint32_t tmpreg; \ 1086 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN); \ 1087 /* Delay after an RCC peripheral clock enabling */ \ 1088 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN); \ 1089 UNUSED(tmpreg); \ 1090 } while(0) 1091 1092 #if defined(SDMMC2) 1093 #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ 1094 __IO uint32_t tmpreg; \ 1095 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN); \ 1096 /* Delay after an RCC peripheral clock enabling */ \ 1097 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN); \ 1098 UNUSED(tmpreg); \ 1099 } while(0) 1100 #endif /* SDMMC2 */ 1101 1102 #define __HAL_RCC_SRAM2_CLK_ENABLE() do { \ 1103 __IO uint32_t tmpreg; \ 1104 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN); \ 1105 /* Delay after an RCC peripheral clock enabling */ \ 1106 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN); \ 1107 UNUSED(tmpreg); \ 1108 } while(0) 1109 #if defined(SRAM3_BASE) 1110 #define __HAL_RCC_SRAM3_CLK_ENABLE() do { \ 1111 __IO uint32_t tmpreg; \ 1112 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN); \ 1113 /* Delay after an RCC peripheral clock enabling */ \ 1114 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN); \ 1115 UNUSED(tmpreg); \ 1116 } while(0) 1117 #endif /* SRAM3_BASE */ 1118 1119 #if defined(FMC_BASE) 1120 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 1121 __IO uint32_t tmpreg; \ 1122 SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN); \ 1123 /* Delay after an RCC peripheral clock enabling */ \ 1124 tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN); \ 1125 UNUSED(tmpreg); \ 1126 } while(0) 1127 #endif /* FMC_BASE */ 1128 1129 #define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ 1130 __IO uint32_t tmpreg; \ 1131 SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN); \ 1132 /* Delay after an RCC peripheral clock enabling */ \ 1133 tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN); \ 1134 UNUSED(tmpreg); \ 1135 } while(0) 1136 1137 #if defined(OCTOSPI2) 1138 #define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ 1139 __IO uint32_t tmpreg; \ 1140 SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN); \ 1141 /* Delay after an RCC peripheral clock enabling */ \ 1142 tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN); \ 1143 UNUSED(tmpreg); \ 1144 } while(0) 1145 #endif /* OCTOSPI2 */ 1146 1147 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) 1148 1149 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN) 1150 1151 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN) 1152 1153 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN) 1154 1155 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) 1156 1157 #if defined(GPIOF) 1158 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) 1159 #endif /* GPIOF */ 1160 1161 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) 1162 1163 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) 1164 1165 #if defined(GPIOI) 1166 #define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) 1167 #endif /* GPIOI */ 1168 1169 #if defined(GPIOJ) 1170 #define __HAL_RCC_GPIOJ_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN) 1171 #endif /* GPIOJ */ 1172 1173 #define __HAL_RCC_ADC12_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN) 1174 1175 #define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) 1176 1177 #if defined(USB_OTG_HS) 1178 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) 1179 #endif /* USB_OTG_HS */ 1180 1181 #if defined(USB_OTG_FS) 1182 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) 1183 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE /*!< alias define for compatibility with legacy code */ 1184 #endif /* USB_OTG_FS */ 1185 1186 #if defined(RCC_AHB2ENR1_USBPHYCEN) 1187 #define __HAL_RCC_USBPHYC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_USBPHYCEN) 1188 #endif /* defined (RCC_AHB2ENR1_USBPHYCEN) */ 1189 1190 #if defined(AES) 1191 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) 1192 #endif /* AES */ 1193 1194 #if defined(HASH) 1195 #define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN) 1196 #endif /* HASH */ 1197 1198 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) 1199 1200 #if defined(PKA) 1201 #define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) 1202 #endif /* PKA */ 1203 1204 #if defined(SAES) 1205 #define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) 1206 #endif /* SAES */ 1207 1208 #if defined(OCTOSPIM) 1209 #define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) 1210 #endif /* OCTOSPIM */ 1211 1212 #if defined(OTFDEC1) 1213 #define __HAL_RCC_OTFDEC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) 1214 #endif /* OTFDEC1 */ 1215 1216 #if defined(OTFDEC2) 1217 #define __HAL_RCC_OTFDEC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) 1218 #endif /* OTFDEC2 */ 1219 1220 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) 1221 1222 #if defined(SDMMC2) 1223 #define __HAL_RCC_SDMMC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) 1224 #endif /* SDMMC2 */ 1225 1226 #define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) 1227 1228 #if defined(SRAM3_BASE) 1229 #define __HAL_RCC_SRAM3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) 1230 #endif /* SRAM3_BASE */ 1231 1232 #if defined(HSPI1) 1233 #define __HAL_RCC_HSPI1_CLK_ENABLE() do { \ 1234 __IO uint32_t tmpreg; \ 1235 SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN); \ 1236 /* Delay after an RCC peripheral clock enabling */ \ 1237 tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN); \ 1238 UNUSED(tmpreg); \ 1239 } while(0) 1240 #endif /* HSPI1 */ 1241 1242 #if defined (SRAM6_BASE) 1243 #define __HAL_RCC_SRAM6_CLK_ENABLE() do { \ 1244 __IO uint32_t tmpreg; \ 1245 SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN); \ 1246 /* Delay after an RCC peripheral clock enabling */ \ 1247 tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN); \ 1248 UNUSED(tmpreg); \ 1249 } while(0) 1250 #endif /* SRAM6_BASE */ 1251 1252 #if defined (SRAM5_BASE) 1253 #define __HAL_RCC_SRAM5_CLK_ENABLE() do { \ 1254 __IO uint32_t tmpreg; \ 1255 SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN); \ 1256 /* Delay after an RCC peripheral clock enabling */ \ 1257 tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN); \ 1258 UNUSED(tmpreg); \ 1259 } while(0) 1260 #endif /* SRAM5_BASE */ 1261 1262 #if defined(FMC_BASE) 1263 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) 1264 #endif /* FMC_BASE */ 1265 1266 #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) 1267 1268 #if defined(OCTOSPI2) 1269 #define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) 1270 #endif /* OCTOSPI2 */ 1271 1272 #if defined(HSPI1) 1273 #define __HAL_RCC_HSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN) 1274 #endif /* HSPI1 */ 1275 1276 #if defined (SRAM6_BASE) 1277 #define __HAL_RCC_SRAM6_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN) 1278 #endif /* SRAM6_BASE */ 1279 1280 #if defined (SRAM5_BASE) 1281 #define __HAL_RCC_SRAM5_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN) 1282 #endif /* SRAM5_BASE */ 1283 /** 1284 * @} 1285 */ 1286 1287 /** @defgroup BUS AHB APB Peripheral Clock Enable Disable 1288 * @{ 1289 */ 1290 #define __HAL_RCC_AHB1_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); 1291 1292 #define __HAL_RCC_AHB2_1_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); 1293 1294 #define __HAL_RCC_AHB2_2_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); 1295 1296 #define __HAL_RCC_AHB3_CLK_DISABLE() SET_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); 1297 1298 #define __HAL_RCC_APB1_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); 1299 1300 #define __HAL_RCC_APB2_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); 1301 1302 #define __HAL_RCC_APB3_CLK_DISABLE() SET_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); 1303 1304 #define __HAL_RCC_AHB1_CLK_ENABLE() do { \ 1305 __IO uint32_t tmpreg; \ 1306 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ 1307 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ 1308 UNUSED(tmpreg); \ 1309 } while(0) 1310 1311 #define __HAL_RCC_AHB2_1_CLK_ENABLE() do { \ 1312 __IO uint32_t tmpreg; \ 1313 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \ 1314 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \ 1315 UNUSED(tmpreg); \ 1316 } while(0) 1317 1318 #define __HAL_RCC_AHB2_2_CLK_ENABLE() do { \ 1319 __IO uint32_t tmpreg; \ 1320 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \ 1321 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \ 1322 UNUSED(tmpreg); \ 1323 } while(0) 1324 1325 1326 #define __HAL_RCC_AHB3_CLK_ENABLE() do { \ 1327 __IO uint32_t tmpreg; \ 1328 CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \ 1329 tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \ 1330 UNUSED(tmpreg); \ 1331 } while(0) 1332 1333 #define __HAL_RCC_APB1_CLK_ENABLE() do { \ 1334 __IO uint32_t tmpreg; \ 1335 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ 1336 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ 1337 UNUSED(tmpreg); \ 1338 } while(0) 1339 1340 #define __HAL_RCC_APB2_CLK_ENABLE() do { \ 1341 __IO uint32_t tmpreg; \ 1342 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ 1343 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ 1344 UNUSED(tmpreg); \ 1345 } while(0) 1346 1347 #define __HAL_RCC_APB3_CLK_ENABLE() do { \ 1348 __IO uint32_t tmpreg; \ 1349 CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \ 1350 tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \ 1351 UNUSED(tmpreg); \ 1352 } while(0) 1353 1354 /** 1355 * @} 1356 */ 1357 1358 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3ENR Peripheral Clock Enable Disable 1359 * @brief Enable or disable the AHB3ENR peripheral clock. 1360 * @note After reset, the peripheral clock (used for registers read/write access) 1361 * is disabled and the application software has to enable this clock before 1362 * using it. 1363 * @{ 1364 */ 1365 1366 #define __HAL_RCC_LPGPIO1_CLK_ENABLE() do { \ 1367 __IO uint32_t tmpreg; \ 1368 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \ 1369 /* Delay after an RCC peripheral clock enabling */ \ 1370 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \ 1371 UNUSED(tmpreg); \ 1372 } while(0) 1373 1374 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 1375 __IO uint32_t tmpreg; \ 1376 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \ 1377 /* Delay after an RCC peripheral clock enabling */ \ 1378 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \ 1379 UNUSED(tmpreg); \ 1380 } while(0) 1381 1382 #define __HAL_RCC_ADC4_CLK_ENABLE() do { \ 1383 __IO uint32_t tmpreg; \ 1384 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \ 1385 /* Delay after an RCC peripheral clock enabling */ \ 1386 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \ 1387 UNUSED(tmpreg); \ 1388 } while(0) 1389 1390 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ 1391 __IO uint32_t tmpreg; \ 1392 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \ 1393 /* Delay after an RCC peripheral clock enabling */ \ 1394 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \ 1395 UNUSED(tmpreg); \ 1396 } while(0) 1397 1398 #define __HAL_RCC_LPDMA1_CLK_ENABLE() do { \ 1399 __IO uint32_t tmpreg; \ 1400 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \ 1401 /* Delay after an RCC peripheral clock enabling */ \ 1402 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \ 1403 UNUSED(tmpreg); \ 1404 } while(0) 1405 1406 #define __HAL_RCC_ADF1_CLK_ENABLE() do { \ 1407 __IO uint32_t tmpreg; \ 1408 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN); \ 1409 /* Delay after an RCC peripheral clock enabling */ \ 1410 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN); \ 1411 UNUSED(tmpreg); \ 1412 } while(0) 1413 1414 #define __HAL_RCC_GTZC2_CLK_ENABLE() do { \ 1415 __IO uint32_t tmpreg; \ 1416 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN); \ 1417 /* Delay after an RCC peripheral clock enabling */ \ 1418 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN); \ 1419 UNUSED(tmpreg); \ 1420 } while(0) 1421 1422 #define __HAL_RCC_SRAM4_CLK_ENABLE() do { \ 1423 __IO uint32_t tmpreg; \ 1424 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN); \ 1425 /* Delay after an RCC peripheral clock enabling */ \ 1426 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN); \ 1427 UNUSED(tmpreg); \ 1428 } while(0) 1429 1430 #define __HAL_RCC_LPGPIO1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN) 1431 1432 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN) 1433 1434 #define __HAL_RCC_ADC4_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN) 1435 1436 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN) 1437 1438 #define __HAL_RCC_LPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN) 1439 1440 #define __HAL_RCC_ADF1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN) 1441 1442 #define __HAL_RCC_GTZC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) 1443 1444 #define __HAL_RCC_SRAM4_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) 1445 1446 /** 1447 * @} 1448 */ 1449 1450 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 1451 * @brief Enable or disable the APB1 peripheral clock. 1452 * @note After reset, the peripheral clock (used for registers read/write access) 1453 * is disabled and the application software has to enable this clock before 1454 * using it. 1455 * @{ 1456 */ 1457 1458 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 1459 __IO uint32_t tmpreg; \ 1460 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 1461 /* Delay after an RCC peripheral clock enabling */ \ 1462 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 1463 UNUSED(tmpreg); \ 1464 } while(0) 1465 1466 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 1467 __IO uint32_t tmpreg; \ 1468 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 1469 /* Delay after an RCC peripheral clock enabling */ \ 1470 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 1471 UNUSED(tmpreg); \ 1472 } while(0) 1473 1474 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 1475 __IO uint32_t tmpreg; \ 1476 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 1477 /* Delay after an RCC peripheral clock enabling */ \ 1478 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 1479 UNUSED(tmpreg); \ 1480 } while(0) 1481 1482 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 1483 __IO uint32_t tmpreg; \ 1484 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 1485 /* Delay after an RCC peripheral clock enabling */ \ 1486 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 1487 UNUSED(tmpreg); \ 1488 } while(0) 1489 1490 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 1491 __IO uint32_t tmpreg; \ 1492 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 1493 /* Delay after an RCC peripheral clock enabling */ \ 1494 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 1495 UNUSED(tmpreg); \ 1496 } while(0) 1497 1498 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 1499 __IO uint32_t tmpreg; \ 1500 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 1501 /* Delay after an RCC peripheral clock enabling */ \ 1502 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 1503 UNUSED(tmpreg); \ 1504 } while(0) 1505 1506 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 1507 __IO uint32_t tmpreg; \ 1508 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 1509 /* Delay after an RCC peripheral clock enabling */ \ 1510 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 1511 UNUSED(tmpreg); \ 1512 } while(0) 1513 1514 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 1515 __IO uint32_t tmpreg; \ 1516 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 1517 /* Delay after an RCC peripheral clock enabling */ \ 1518 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 1519 UNUSED(tmpreg); \ 1520 } while(0) 1521 1522 #if defined(USART2) 1523 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 1524 __IO uint32_t tmpreg; \ 1525 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 1526 /* Delay after an RCC peripheral clock enabling */ \ 1527 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 1528 UNUSED(tmpreg); \ 1529 } while(0) 1530 #endif /* USART2 */ 1531 1532 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 1533 __IO uint32_t tmpreg; \ 1534 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 1535 /* Delay after an RCC peripheral clock enabling */ \ 1536 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 1537 UNUSED(tmpreg); \ 1538 } while(0) 1539 1540 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 1541 __IO uint32_t tmpreg; \ 1542 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 1543 /* Delay after an RCC peripheral clock enabling */ \ 1544 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 1545 UNUSED(tmpreg); \ 1546 } while(0) 1547 1548 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 1549 __IO uint32_t tmpreg; \ 1550 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 1551 /* Delay after an RCC peripheral clock enabling */ \ 1552 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 1553 UNUSED(tmpreg); \ 1554 } while(0) 1555 1556 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 1557 __IO uint32_t tmpreg; \ 1558 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 1559 /* Delay after an RCC peripheral clock enabling */ \ 1560 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 1561 UNUSED(tmpreg); \ 1562 } while(0) 1563 1564 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 1565 __IO uint32_t tmpreg; \ 1566 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 1567 /* Delay after an RCC peripheral clock enabling */ \ 1568 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 1569 UNUSED(tmpreg); \ 1570 } while(0) 1571 1572 #define __HAL_RCC_CRS_CLK_ENABLE() do { \ 1573 __IO uint32_t tmpreg; \ 1574 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 1575 /* Delay after an RCC peripheral clock enabling */ \ 1576 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 1577 UNUSED(tmpreg); \ 1578 } while(0) 1579 1580 1581 #if defined(USART6) 1582 #define __HAL_RCC_USART6_CLK_ENABLE() do { \ 1583 __IO uint32_t tmpreg; \ 1584 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN); \ 1585 /* Delay after an RCC peripheral clock enabling */ \ 1586 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN); \ 1587 UNUSED(tmpreg); \ 1588 } while(0) 1589 #endif /* USART6 */ 1590 1591 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ 1592 __IO uint32_t tmpreg; \ 1593 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 1594 /* Delay after an RCC peripheral clock enabling */ \ 1595 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 1596 UNUSED(tmpreg); \ 1597 } while(0) 1598 1599 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ 1600 __IO uint32_t tmpreg; \ 1601 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 1602 /* Delay after an RCC peripheral clock enabling */ \ 1603 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 1604 UNUSED(tmpreg); \ 1605 } while(0) 1606 1607 #if defined(I2C5) 1608 #define __HAL_RCC_I2C5_CLK_ENABLE() do { \ 1609 __IO uint32_t tmpreg; \ 1610 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN); \ 1611 /* Delay after an RCC peripheral clock enabling */ \ 1612 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN); \ 1613 UNUSED(tmpreg); \ 1614 } while(0) 1615 #endif /* I2C5 */ 1616 1617 #if defined(I2C6) 1618 #define __HAL_RCC_I2C6_CLK_ENABLE() do { \ 1619 __IO uint32_t tmpreg; \ 1620 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN); \ 1621 /* Delay after an RCC peripheral clock enabling */ \ 1622 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN); \ 1623 UNUSED(tmpreg); \ 1624 } while(0) 1625 #endif /* I2C6 */ 1626 1627 #define __HAL_RCC_FDCAN1_CLK_ENABLE() do { \ 1628 __IO uint32_t tmpreg; \ 1629 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ 1630 /* Delay after an RCC peripheral clock enabling */ \ 1631 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ 1632 UNUSED(tmpreg); \ 1633 } while(0) 1634 1635 #if defined(UCPD1) 1636 #define __HAL_RCC_UCPD_CLK_ENABLE() do { \ 1637 __IO uint32_t tmpreg; \ 1638 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ 1639 /* Delay after an RCC peripheral clock enabling */ \ 1640 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ 1641 UNUSED(tmpreg); \ 1642 } while(0) 1643 #endif /* UCPD1 */ 1644 1645 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) 1646 1647 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) 1648 1649 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) 1650 1651 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) 1652 1653 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) 1654 1655 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) 1656 1657 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) 1658 1659 #if defined(USART2) 1660 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) 1661 #endif /* USART2 */ 1662 1663 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) 1664 1665 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) 1666 1667 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) 1668 1669 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) 1670 1671 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) 1672 1673 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) 1674 1675 #if defined(USART6) 1676 #define __HAL_RCC_USART6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN) 1677 #endif /* USART6 */ 1678 1679 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) 1680 1681 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) 1682 1683 #if defined(I2C5) 1684 #define __HAL_RCC_I2C5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN) 1685 #endif /* I2C5 */ 1686 1687 #if defined(I2C6) 1688 #define __HAL_RCC_I2C6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN) 1689 #endif /* I2C6 */ 1690 1691 #define __HAL_RCC_FDCAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) 1692 1693 #if defined(UCPD1) 1694 #define __HAL_RCC_UCPD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) 1695 #endif /* UCPD1 */ 1696 1697 /** 1698 * @} 1699 */ 1700 1701 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1702 * @brief Enable or disable the APB2 peripheral clock. 1703 * @note After reset, the peripheral clock (used for registers read/write access) 1704 * is disabled and the application software has to enable this clock before 1705 * using it. 1706 * @{ 1707 */ 1708 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 1709 __IO uint32_t tmpreg; \ 1710 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1711 /* Delay after an RCC peripheral clock enabling */ \ 1712 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1713 UNUSED(tmpreg); \ 1714 } while(0) 1715 1716 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 1717 __IO uint32_t tmpreg; \ 1718 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1719 /* Delay after an RCC peripheral clock enabling */ \ 1720 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1721 UNUSED(tmpreg); \ 1722 } while(0) 1723 1724 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 1725 __IO uint32_t tmpreg; \ 1726 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1727 /* Delay after an RCC peripheral clock enabling */ \ 1728 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1729 UNUSED(tmpreg); \ 1730 } while(0) 1731 1732 1733 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 1734 __IO uint32_t tmpreg; \ 1735 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1736 /* Delay after an RCC peripheral clock enabling */ \ 1737 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1738 UNUSED(tmpreg); \ 1739 } while(0) 1740 1741 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 1742 __IO uint32_t tmpreg; \ 1743 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1744 /* Delay after an RCC peripheral clock enabling */ \ 1745 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1746 UNUSED(tmpreg); \ 1747 } while(0) 1748 1749 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 1750 __IO uint32_t tmpreg; \ 1751 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1752 /* Delay after an RCC peripheral clock enabling */ \ 1753 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1754 UNUSED(tmpreg); \ 1755 } while(0) 1756 1757 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 1758 __IO uint32_t tmpreg; \ 1759 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1760 /* Delay after an RCC peripheral clock enabling */ \ 1761 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1762 UNUSED(tmpreg); \ 1763 } while(0) 1764 1765 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 1766 __IO uint32_t tmpreg; \ 1767 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1768 /* Delay after an RCC peripheral clock enabling */ \ 1769 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1770 UNUSED(tmpreg); \ 1771 } while(0) 1772 1773 #if defined (SAI2) 1774 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 1775 __IO uint32_t tmpreg; \ 1776 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1777 /* Delay after an RCC peripheral clock enabling */ \ 1778 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1779 UNUSED(tmpreg); \ 1780 } while(0) 1781 #endif /* SAI2 */ 1782 1783 #if defined(USB_DRD_FS) 1784 #define __HAL_RCC_USB_FS_CLK_ENABLE() do { \ 1785 __IO uint32_t tmpreg; \ 1786 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ 1787 /* Delay after an RCC peripheral clock enabling */ \ 1788 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ 1789 UNUSED(tmpreg); \ 1790 } while(0) 1791 #endif /* USB_DRD_FS */ 1792 1793 #if defined(GFXTIM) 1794 #define __HAL_RCC_GFXTIM_CLK_ENABLE() do { \ 1795 __IO uint32_t tmpreg; \ 1796 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN); \ 1797 /* Delay after an RCC peripheral clock enabling */ \ 1798 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN); \ 1799 UNUSED(tmpreg); \ 1800 } while(0) 1801 #endif /* GFXTIM */ 1802 1803 #if defined(LTDC) 1804 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ 1805 __IO uint32_t tmpreg; \ 1806 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ 1807 /* Delay after an RCC peripheral clock enabling */ \ 1808 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ 1809 UNUSED(tmpreg); \ 1810 } while(0) 1811 #endif /* LTDC */ 1812 1813 #if defined(DSI) 1814 #define __HAL_RCC_DSI_CLK_ENABLE() do { \ 1815 __IO uint32_t tmpreg; \ 1816 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN); \ 1817 /* Delay after an RCC peripheral clock enabling */ \ 1818 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN); \ 1819 UNUSED(tmpreg); \ 1820 } while(0) 1821 #endif /* DSI */ 1822 1823 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) 1824 1825 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) 1826 1827 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) 1828 1829 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) 1830 1831 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) 1832 1833 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) 1834 1835 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) 1836 1837 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) 1838 1839 #if defined (SAI2) 1840 #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) 1841 #endif /* SAI2 */ 1842 1843 #if defined (USB_DRD_FS) 1844 #define __HAL_RCC_USB_FS_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) 1845 #endif /* USB_DRD_FS */ 1846 1847 #if defined(GFXTIM) 1848 #define __HAL_RCC_GFXTIM_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) 1849 #endif /* GFXTIM */ 1850 1851 #if defined(LTDC) 1852 #define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) 1853 #endif /* LTDC */ 1854 1855 #if defined(DSI) 1856 #define __HAL_RCC_DSI_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN) 1857 #endif /* DSI */ 1858 1859 /** 1860 * @} 1861 */ 1862 1863 /** @defgroup RCC_APB3_Clock_Enable_Disable APB3 Peripheral Clock Enable Disable 1864 * @brief Enable or disable the APB3 peripheral clock. 1865 * @note After reset, the peripheral clock (used for registers read/write access) 1866 * is disabled and the application software has to enable this clock before 1867 * using it. 1868 * @{ 1869 */ 1870 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 1871 __IO uint32_t tmpreg; \ 1872 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN); \ 1873 /* Delay after an RCC peripheral clock enabling */ \ 1874 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN); \ 1875 UNUSED(tmpreg); \ 1876 } while(0) 1877 1878 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 1879 __IO uint32_t tmpreg; \ 1880 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN); \ 1881 /* Delay after an RCC peripheral clock enabling */ \ 1882 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN); \ 1883 UNUSED(tmpreg); \ 1884 } while(0) 1885 1886 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ 1887 __IO uint32_t tmpreg; \ 1888 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ 1889 /* Delay after an RCC peripheral clock enabling */ \ 1890 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ 1891 UNUSED(tmpreg); \ 1892 } while(0) 1893 1894 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 1895 __IO uint32_t tmpreg; \ 1896 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ 1897 /* Delay after an RCC peripheral clock enabling */ \ 1898 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ 1899 UNUSED(tmpreg); \ 1900 } while(0) 1901 1902 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 1903 __IO uint32_t tmpreg; \ 1904 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ 1905 /* Delay after an RCC peripheral clock enabling */ \ 1906 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ 1907 UNUSED(tmpreg); \ 1908 } while(0) 1909 1910 #define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ 1911 __IO uint32_t tmpreg; \ 1912 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ 1913 /* Delay after an RCC peripheral clock enabling */ \ 1914 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ 1915 UNUSED(tmpreg); \ 1916 } while(0) 1917 1918 #define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \ 1919 __IO uint32_t tmpreg; \ 1920 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ 1921 /* Delay after an RCC peripheral clock enabling */ \ 1922 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ 1923 UNUSED(tmpreg); \ 1924 } while(0) 1925 1926 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ 1927 __IO uint32_t tmpreg; \ 1928 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN); \ 1929 /* Delay after an RCC peripheral clock enabling */ \ 1930 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN); \ 1931 UNUSED(tmpreg); \ 1932 } while(0) 1933 1934 #define __HAL_RCC_COMP_CLK_ENABLE() do { \ 1935 __IO uint32_t tmpreg; \ 1936 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN); \ 1937 /* Delay after an RCC peripheral clock enabling */ \ 1938 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN); \ 1939 UNUSED(tmpreg); \ 1940 } while(0) 1941 1942 #define __HAL_RCC_VREF_CLK_ENABLE() do { \ 1943 __IO uint32_t tmpreg; \ 1944 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ 1945 /* Delay after an RCC peripheral clock enabling */ \ 1946 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ 1947 UNUSED(tmpreg); \ 1948 } while(0) 1949 1950 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 1951 __IO uint32_t tmpreg; \ 1952 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ 1953 /* Delay after an RCC peripheral clock enabling */ \ 1954 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ 1955 UNUSED(tmpreg); \ 1956 } while(0) 1957 1958 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN) 1959 1960 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN) 1961 1962 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) 1963 1964 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) 1965 1966 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) 1967 1968 #define __HAL_RCC_LPTIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) 1969 1970 #define __HAL_RCC_LPTIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) 1971 1972 #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN) 1973 1974 #define __HAL_RCC_COMP_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN) 1975 1976 #define __HAL_RCC_VREF_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) 1977 1978 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) 1979 /** 1980 * @} 1981 */ 1982 1983 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 1984 * @brief Check whether the AHB1 peripheral clock is enabled or not. 1985 * @note After reset, the peripheral clock (used for registers read/write access) 1986 * is disabled and the application software has to enable this clock before 1987 * using it. 1988 * @{ 1989 */ 1990 #define __HAL_RCC_GPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) != 0U) 1991 1992 #define __HAL_RCC_CORDIC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U) 1993 1994 #define __HAL_RCC_FMAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U) 1995 1996 #define __HAL_RCC_MDF1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN) != 0U) 1997 1998 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) 1999 2000 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) 2001 2002 #if defined(JPEG) 2003 #define __HAL_RCC_JPEG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN) != 0U) 2004 #endif /* JPEG */ 2005 2006 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U) 2007 2008 #define __HAL_RCC_RAMCFG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) != 0U) 2009 2010 #if defined(DMA2D) 2011 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != 0U) 2012 #endif /* DMA2D */ 2013 2014 #if defined(GFXMMU) 2015 #define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != 0U) 2016 #endif /* GFXMMU */ 2017 2018 #if defined(GPU2D) 2019 #define __HAL_RCC_GPU2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN) != 0U) 2020 #endif /* GPU2D */ 2021 2022 #if defined(DCACHE2) 2023 #define __HAL_RCC_DCACHE2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN) != 0U) 2024 #endif /* DCACHE2 */ 2025 2026 #define __HAL_RCC_GTZC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) != 0U) 2027 2028 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN) != 0U) 2029 2030 #define __HAL_RCC_DCACHE1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) != 0U) 2031 2032 #define __HAL_RCC_SRAM1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) != 0U) 2033 2034 #define __HAL_RCC_GPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) == 0U) 2035 2036 #define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U) 2037 2038 #define __HAL_RCC_FMAC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U) 2039 2040 #define __HAL_RCC_MDF1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN) == 0U) 2041 2042 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U) 2043 2044 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) 2045 2046 #if defined(JPEG) 2047 #define __HAL_RCC_JPEG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN) == 0U) 2048 #endif /* JPEG */ 2049 2050 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U) 2051 2052 #define __HAL_RCC_RAMCFG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) == 0U) 2053 2054 #if defined (DMA2D) 2055 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == 0U) 2056 #endif /* DMA2D */ 2057 2058 #if defined(GFXMMU) 2059 #define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == 0U) 2060 #endif /* GFXMMU */ 2061 2062 #if defined(GPU2D) 2063 #define __HAL_RCC_GPU2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN) == 0U) 2064 #endif /* GPU2D */ 2065 2066 #if defined(DCACHE2) 2067 #define __HAL_RCC_DCACHE2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN) == 0U) 2068 #endif /* DCACHE2 */ 2069 2070 #define __HAL_RCC_GTZC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) == 0U) 2071 2072 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN) == 0U) 2073 2074 #define __HAL_RCC_DCACHE1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) == 0U) 2075 2076 #define __HAL_RCC_SRAM1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) == 0U) 2077 /** 2078 * @} 2079 */ 2080 2081 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 2082 * @brief Check whether the AHB2 peripheral clock is enabled or not. 2083 * @note After reset, the peripheral clock (used for registers read/write access) 2084 * is disabled and the application software has to enable this clock before 2085 * using it. 2086 * @{ 2087 */ 2088 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) != 0U) 2089 2090 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN) != 0U) 2091 2092 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN) != 0U) 2093 2094 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN) != 0U) 2095 2096 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) != 0U) 2097 2098 #if defined(GPIOF) 2099 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) != 0U) 2100 #endif /* GPIOF */ 2101 2102 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) != 0U) 2103 2104 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) != 0U) 2105 2106 #if defined(GPIOI) 2107 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) != 0U) 2108 #endif /* GPIOI */ 2109 2110 #if defined(GPIOJ) 2111 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN) != 0U) 2112 #endif /* GPIOJ */ 2113 2114 #define __HAL_RCC_ADC12_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN) != 0U) 2115 2116 #define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) != 0U) 2117 2118 #if defined(USB_OTG_HS) 2119 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) != 0U) 2120 #endif /* USB_OTG_HS */ 2121 2122 #if defined(USB_OTG_FS) 2123 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) != 0U) 2124 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED /*!< alias define for compatibility with legacy code */ 2125 #endif /* USB_OTG_FS */ 2126 2127 #if defined(AES) 2128 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) != 0U) 2129 #endif /* AES */ 2130 2131 #if defined(HASH) 2132 #define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN) != 0U) 2133 #endif /* HASH */ 2134 2135 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) != 0U) 2136 2137 #if defined(PKA) 2138 #define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) != 0U) 2139 #endif /* PKA */ 2140 2141 #if defined(SAES) 2142 #define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) != 0U) 2143 #endif /* SAES */ 2144 2145 #if defined(OCTOSPIM) 2146 #define __HAL_RCC_OSPIM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) != 0U) 2147 #endif /* OCTOSPIM */ 2148 2149 #if defined(OTFDEC1) 2150 #define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) != 0U) 2151 #endif /* OTFDEC1 */ 2152 2153 #if defined(OTFDEC2) 2154 #define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) != 0U) 2155 #endif /* OTFDEC2 */ 2156 2157 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) != 0U) 2158 2159 #if defined(SDMMC2) 2160 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) != 0U) 2161 #endif /* SDMMC2 */ 2162 2163 #define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) != 0U) 2164 2165 #if defined (SRAM3_BASE) 2166 #define __HAL_RCC_SRAM3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) != 0U) 2167 #endif /* SRAM3_BASE */ 2168 2169 #if defined(FMC_BASE) 2170 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) != 0U) 2171 #endif /* FMC_BASE */ 2172 2173 #define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) != 0U) 2174 2175 #if defined(OCTOSPI2) 2176 #define __HAL_RCC_OSPI2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) != 0U) 2177 #endif /* OCTOSPI2 */ 2178 2179 #if defined(HSPI1) 2180 #define __HAL_RCC_HSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2,RCC_AHB2ENR2_HSPI1EN) != 0U) 2181 #endif /* HSPI1 */ 2182 2183 #if defined (SRAM6_BASE) 2184 #define __HAL_RCC_SRAM6_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN) != 0U) 2185 #endif /* SRAM6_BASE */ 2186 2187 #if defined (SRAM5_BASE) 2188 #define __HAL_RCC_SRAM5_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN) != 0U) 2189 #endif /* SRAM5_BASE */ 2190 2191 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) == 0U) 2192 2193 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN) == 0U) 2194 2195 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN) == 0U) 2196 2197 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN) == 0U) 2198 2199 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) == 0U) 2200 2201 #if defined(GPIOF) 2202 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) == 0U) 2203 #endif /* GPIOF */ 2204 2205 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) == 0U) 2206 2207 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) == 0U) 2208 2209 #if defined(GPIOI) 2210 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) == 0U) 2211 #endif /* GPIOI */ 2212 2213 #if defined(GPIOJ) 2214 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN) == 0U) 2215 #endif /* GPIOJ */ 2216 2217 #define __HAL_RCC_ADC12_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN) == 0U) 2218 2219 #define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) == 0U) 2220 2221 #if defined(USB_OTG_HS) 2222 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) == 0U) 2223 #endif /* USB_OTG_HS */ 2224 2225 #if defined(USB_OTG_FS) 2226 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) == 0U) 2227 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED /*!< alias define for compatibility with legacy code */ 2228 #endif /* USB_OTG_FS */ 2229 2230 #if defined(AES) 2231 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) == 0U) 2232 #endif /* AES */ 2233 2234 #if defined(HASH) 2235 #define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN) == 0U) 2236 #endif /* HASH */ 2237 2238 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) == 0U) 2239 2240 #if defined(PKA) 2241 #define __HAL_RCC_PKA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) == 0U) 2242 #endif /* PKA */ 2243 2244 #if defined(SAES) 2245 #define __HAL_RCC_SAES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) == 0U) 2246 #endif /* SAES */ 2247 2248 #if defined(OCTOSPIM) 2249 #define __HAL_RCC_OSPIM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) == 0U) 2250 #endif /* OCTOSPIM */ 2251 2252 #if defined(OTFDEC1) 2253 #define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) == 0U) 2254 #endif /* OTFDEC1 */ 2255 2256 #if defined (OTFDEC2) 2257 #define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) == 0U) 2258 #endif /* OTFDEC2 */ 2259 2260 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) == 0U) 2261 2262 #if defined (SDMMC2) 2263 #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) == 0U) 2264 #endif /* SDMMC2 */ 2265 2266 #define __HAL_RCC_SRAM2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) == 0U) 2267 2268 #if defined (SRAM3_BASE) 2269 #define __HAL_RCC_SRAM3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) == 0U) 2270 #endif /* SRAM3_BASE */ 2271 2272 #if defined(FMC_BASE) 2273 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) == 0U) 2274 #endif /* FMC_BASE */ 2275 2276 #define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) == 0U) 2277 2278 #if defined (OCTOSPI2) 2279 #define __HAL_RCC_OSPI2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) == 0U) 2280 #endif /* OCTOSPI2 */ 2281 2282 #if defined(HSPI1) 2283 #define __HAL_RCC_HSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN) == 0U) 2284 #endif /* HSPI1 */ 2285 2286 #if defined (SRAM6_BASE) 2287 #define __HAL_RCC_SRAM6_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN) == 0U) 2288 #endif /* SRAM6_BASE */ 2289 2290 #if defined (SRAM5_BASE) 2291 #define __HAL_RCC_SRAM5_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN) == 0U) 2292 #endif /* SRAM5_BASE */ 2293 /** 2294 * @} 2295 */ 2296 2297 /** @defgroup RCC_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status 2298 * @brief Check whether the AHB3 peripheral clock is enabled or not. 2299 * @note After reset, the peripheral clock (used for registers read/write access) 2300 * is disabled and the application software has to enable this clock before 2301 * using it. 2302 * @{ 2303 */ 2304 #define __HAL_RCC_LPGPIO1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN) != 0U) 2305 2306 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN) != 0U) 2307 2308 #define __HAL_RCC_ADC4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN) != 0U) 2309 2310 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN) != 0U) 2311 2312 #define __HAL_RCC_LPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN) != 0U) 2313 2314 #define __HAL_RCC_ADF1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN) != 0U) 2315 2316 #define __HAL_RCC_GTZC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) != 0U) 2317 2318 #define __HAL_RCC_SRAM4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) != 0U) 2319 2320 #define __HAL_RCC_LPGPIO1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN) == 0U) 2321 2322 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN) == 0U) 2323 2324 #define __HAL_RCC_ADC4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN) == 0U) 2325 2326 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN) == 0U) 2327 2328 #define __HAL_RCC_LPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN) == 0U) 2329 2330 #define __HAL_RCC_ADF1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN) == 0U) 2331 2332 #define __HAL_RCC_GTZC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) == 0U) 2333 2334 #define __HAL_RCC_SRAM4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) == 0U) 2335 2336 /** 2337 * @} 2338 */ 2339 2340 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 2341 * @brief Check whether the APB1 peripheral clock is enabled or not. 2342 * @note After reset, the peripheral clock (used for registers read/write access) 2343 * is disabled and the application software has to enable this clock before 2344 * using it. 2345 * @{ 2346 */ 2347 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) 2348 2349 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) 2350 2351 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U) 2352 2353 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U) 2354 2355 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U) 2356 2357 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U) 2358 2359 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) 2360 2361 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U) 2362 2363 #if defined(USART2) 2364 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) 2365 #endif /* USART2 */ 2366 2367 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U) 2368 2369 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U) 2370 2371 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U) 2372 2373 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U) 2374 2375 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U) 2376 2377 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U) 2378 2379 #if defined(USART6) 2380 #define __HAL_RCC_USART6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN) != 0U) 2381 #endif /* USART6 */ 2382 2383 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U) 2384 2385 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U) 2386 2387 #if defined(I2C5) 2388 #define __HAL_RCC_I2C5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN) != 0U) 2389 #endif /* I2C5 */ 2390 2391 #if defined(I2C6) 2392 #define __HAL_RCC_I2C6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN) != 0U) 2393 #endif /* I2C6 */ 2394 2395 #define __HAL_RCC_FDCAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) != 0U) 2396 2397 #if defined (UCPD1) 2398 #define __HAL_RCC_UCPD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U) 2399 #endif /* UCPD1 */ 2400 2401 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U) 2402 2403 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U) 2404 2405 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U) 2406 2407 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U) 2408 2409 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U) 2410 2411 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U) 2412 2413 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U) 2414 2415 #if defined(USART2) 2416 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U) 2417 #endif /* USART2 */ 2418 2419 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U) 2420 2421 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U) 2422 2423 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U) 2424 2425 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U) 2426 2427 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U) 2428 2429 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U) 2430 2431 #if defined(USART6) 2432 #define __HAL_RCC_USART6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN) == 0U) 2433 #endif /* USART6 */ 2434 2435 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U) 2436 2437 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U) 2438 2439 #if defined(I2C5) 2440 #define __HAL_RCC_I2C5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN) == 0U) 2441 #endif /* I2C5 */ 2442 2443 #if defined(I2C6) 2444 #define __HAL_RCC_I2C6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN) == 0U) 2445 #endif /* I2C6 */ 2446 2447 #define __HAL_RCC_FDCAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) == 0U) 2448 2449 #if defined(UCPD1) 2450 #define __HAL_RCC_UCPD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U) 2451 #endif /* UCPD1 */ 2452 2453 /** 2454 * @} 2455 */ 2456 2457 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 2458 * @brief Check whether the APB2 peripheral clock is enabled or not. 2459 * @note After reset, the peripheral clock (used for registers read/write access) 2460 * is disabled and the application software has to enable this clock before 2461 * using it. 2462 * @{ 2463 */ 2464 2465 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) 2466 2467 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) 2468 2469 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U) 2470 2471 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) 2472 2473 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) 2474 2475 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) 2476 2477 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) 2478 2479 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) 2480 2481 #if defined (SAI2) 2482 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U) 2483 #endif /* SAI2 */ 2484 2485 #if defined (USB_DRD_FS) 2486 #define __HAL_RCC_USB_FS_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) != 0U) 2487 #endif /* USB_DRD_FS */ 2488 2489 #if defined(GFXTIM) 2490 #define __HAL_RCC_GFXTIM_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) != 0U) 2491 #endif /* GFXTIM */ 2492 2493 #if defined(LTDC) 2494 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != 0U) 2495 #endif /* LTDC */ 2496 2497 #if defined(DSI) 2498 #define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN) != 0U) 2499 #endif /* DSI */ 2500 2501 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) 2502 2503 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) 2504 2505 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) 2506 2507 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) 2508 2509 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) 2510 2511 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) 2512 2513 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) 2514 2515 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) 2516 2517 #if defined (SAI2) 2518 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U) 2519 #endif /* SAI2 */ 2520 2521 #if defined (USB_DRD_FS) 2522 #define __HAL_RCC_USB_FS_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) == 0U) 2523 #endif /* USB_DRD_FS */ 2524 2525 #if defined(GFXTIM) 2526 #define __HAL_RCC_GFXTIM_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) == 0U) 2527 #endif /* GFXTIM */ 2528 2529 #if defined(LTDC) 2530 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == 0U) 2531 #endif /* LTDC */ 2532 2533 #if defined(DSI) 2534 #define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN) == 0U) 2535 #endif /* DSI */ 2536 2537 /** 2538 * @} 2539 */ 2540 2541 /** @defgroup RCC_APB3_Peripheral_Clock_Enable_Disable_Status APB3 Peripheral Clock Enabled or Disabled Status 2542 * @brief Check whether the APB3 peripheral clock is enabled or not. 2543 * @note After reset, the peripheral clock (used for registers read/write access) 2544 * is disabled and the application software has to enable this clock before 2545 * using it. 2546 * @{ 2547 */ 2548 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN) != 0U) 2549 2550 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN) != 0U) 2551 2552 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) != 0U) 2553 2554 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) != 0U) 2555 2556 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) != 0U) 2557 2558 #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) != 0U) 2559 2560 #define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) != 0U) 2561 2562 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN) != 0U) 2563 2564 #define __HAL_RCC_COMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN) != 0U) 2565 2566 #define __HAL_RCC_VREF_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) != 0U) 2567 2568 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) != 0U) 2569 2570 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN) == 0U) 2571 2572 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN) == 0U) 2573 2574 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) == 0U) 2575 2576 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) == 0U) 2577 2578 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) == 0U) 2579 2580 #define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) == 0U) 2581 2582 #define __HAL_RCC_LPTIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) == 0U) 2583 2584 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN) == 0U) 2585 2586 #define __HAL_RCC_COMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN) == 0U) 2587 2588 #define __HAL_RCC_VREF_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) == 0U) 2589 2590 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) == 0U) 2591 /** 2592 * @} 2593 */ 2594 2595 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset 2596 * @brief Force or release AHB1 peripheral reset. 2597 * @{ 2598 */ 2599 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x0007100FU) 2600 2601 #define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) 2602 2603 #define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) 2604 2605 #define __HAL_RCC_FMAC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) 2606 2607 #define __HAL_RCC_MDF1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_MDF1RST) 2608 2609 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 2610 2611 #if defined(JPEG) 2612 #define __HAL_RCC_JPEG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_JPEGRST) 2613 #endif /* JPEG */ 2614 2615 #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 2616 2617 #define __HAL_RCC_RAMCFG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) 2618 2619 #if defined(DMA2D) 2620 #define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) 2621 #endif /* DMA2D */ 2622 2623 #if defined(GFXMMU) 2624 #define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) 2625 #endif /* GFXMMU */ 2626 2627 #if defined(GPU2D) 2628 #define __HAL_RCC_GPU2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPU2DRST) 2629 #endif /* GPU2D */ 2630 2631 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) 2632 2633 #define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) 2634 2635 #define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) 2636 2637 #define __HAL_RCC_FMAC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) 2638 2639 #define __HAL_RCC_MDF1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_MDF1RST) 2640 2641 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 2642 2643 #if defined(JPEG) 2644 #define __HAL_RCC_JPEG_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_JPEGRST) 2645 #endif /* JPEG */ 2646 2647 #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 2648 2649 #define __HAL_RCC_RAMCFG_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) 2650 2651 #if defined(DMA2D) 2652 #define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) 2653 #endif /* DMA2D */ 2654 2655 #if defined(GFXMMU) 2656 #define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) 2657 #endif /* GFXMMU */ 2658 2659 #if defined(GPU2D) 2660 #define __HAL_RCC_GPU2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPU2DRST) 2661 #endif /* GPU2D */ 2662 2663 /** 2664 * @} 2665 */ 2666 2667 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset 2668 * @brief Force or release AHB2 peripheral reset. 2669 * @{ 2670 */ 2671 #define __HAL_RCC_AHB2_FORCE_RESET() do{\ 2672 WRITE_REG(RCC->AHB2RSTR1, 0x19BF55FFU);\ 2673 WRITE_REG(RCC->AHB2RSTR2, 0x00000111U);\ 2674 }while(0) 2675 2676 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST) 2677 2678 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST) 2679 2680 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST) 2681 2682 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST) 2683 2684 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST) 2685 2686 #if defined(GPIOF) 2687 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST) 2688 #endif /* GPIOF */ 2689 2690 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST) 2691 2692 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST) 2693 2694 #if defined(GPIOI) 2695 #define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST) 2696 #endif /* GPIOI */ 2697 2698 #if defined(GPIOJ) 2699 #define __HAL_RCC_GPIOJ_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOJRST) 2700 #endif /* GPIOJ */ 2701 2702 #define __HAL_RCC_ADC12_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC12RST) 2703 2704 #define __HAL_RCC_DCMI_PSSI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST) 2705 2706 #if defined(USB_OTG_HS) 2707 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) 2708 #endif /* USB_OTG_HS */ 2709 2710 #if defined(USB_OTG_FS) 2711 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) 2712 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_FORCE_RESET /*!< alias define for compatibility with legacy code */ 2713 #endif /* USB_OTG_FS */ 2714 2715 #if defined(AES) 2716 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST) 2717 #endif /* AES */ 2718 2719 #define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST) 2720 2721 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST) 2722 2723 #if defined(PKA) 2724 #define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST) 2725 #endif /* PKA */ 2726 2727 #if defined(SAES) 2728 #define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST) 2729 #endif /* SAES */ 2730 2731 #if defined(OCTOSPIM) 2732 #define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST) 2733 #endif /* OCTOSPIM */ 2734 2735 #if defined(OTFDEC1) 2736 #define __HAL_RCC_OTFDEC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST) 2737 #endif /* OTFDEC1 */ 2738 2739 #if defined(OTFDEC2) 2740 #define __HAL_RCC_OTFDEC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST) 2741 #endif /* OTFDEC2 */ 2742 2743 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST) 2744 2745 #if defined(SDMMC2) 2746 #define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST) 2747 #endif /* SDMMC2 */ 2748 2749 #if defined(FMC_BASE) 2750 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST) 2751 #endif /* FMC_BASE */ 2752 2753 #define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST) 2754 2755 #if defined (OCTOSPI2) 2756 #define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST) 2757 #endif /* OCTOSPI2 */ 2758 2759 #if defined(HSPI1) 2760 #define __HAL_RCC_HSPI1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_HSPI1RST) 2761 #endif /* HSPI1 */ 2762 2763 #define __HAL_RCC_AHB2_RELEASE_RESET() do{\ 2764 WRITE_REG(RCC->AHB2RSTR1, 0x00000000U);\ 2765 WRITE_REG(RCC->AHB2RSTR2, 0x00000000U);\ 2766 }while(0) 2767 2768 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST) 2769 2770 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST) 2771 2772 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST) 2773 2774 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST) 2775 2776 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST) 2777 2778 #if defined(GPIOF) 2779 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST) 2780 #endif /* GPIOF */ 2781 2782 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST) 2783 2784 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST) 2785 2786 #if defined(GPIOI) 2787 #define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST) 2788 #endif /* GPIOI */ 2789 2790 #if defined(GPIOJ) 2791 #define __HAL_RCC_GPIOJ_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOJRST) 2792 #endif /* GPIOJ */ 2793 2794 #define __HAL_RCC_ADC12_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC12RST) 2795 2796 #define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST) 2797 2798 #if defined(USB_OTG_HS) 2799 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) 2800 #endif /* USB_OTG_HS */ 2801 2802 #if defined(USB_OTG_FS) 2803 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) 2804 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET /*!< alias define for compatibility with legacy code */ 2805 #endif /* USB_OTG_FS */ 2806 2807 #if defined(AES) 2808 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST) 2809 #endif /* AES */ 2810 2811 #define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST) 2812 2813 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST) 2814 2815 #if defined(PKA) 2816 #define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST) 2817 #endif /* PKA */ 2818 2819 #if defined(SAES) 2820 #define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST) 2821 #endif /* SAES */ 2822 2823 #if defined(OCTOSPIM) 2824 #define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST) 2825 #endif /* OCTOSPIM */ 2826 2827 #if defined(OTFDEC1) 2828 #define __HAL_RCC_OTFDEC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST) 2829 #endif /* OTFDEC1 */ 2830 2831 #if defined(OTFDEC2) 2832 #define __HAL_RCC_OTFDEC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST) 2833 #endif /* OTFDEC2 */ 2834 2835 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST) 2836 2837 #if defined(SDMMC2) 2838 #define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST) 2839 #endif /* SDMMC2 */ 2840 2841 #if defined(FMC_BASE) 2842 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST) 2843 #endif /* FMC_BASE */ 2844 2845 #define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST) 2846 2847 #if defined(OCTOSPI2) 2848 #define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST) 2849 #endif /* OCTOSPI2 */ 2850 2851 #if defined(HSPI1) 2852 #define __HAL_RCC_HSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_HSPI1RST) 2853 #endif /* HSPI1 */ 2854 2855 /** 2856 * @} 2857 */ 2858 2859 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset 2860 * @brief Force or release AHB3 peripheral reset. 2861 * @{ 2862 */ 2863 #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000661U) 2864 2865 #define __HAL_RCC_LPGPIO1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPGPIO1RST) 2866 2867 #define __HAL_RCC_ADC4_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADC4RST) 2868 2869 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_DAC1RST) 2870 2871 #define __HAL_RCC_LPDMA1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPDMA1RST) 2872 2873 #define __HAL_RCC_ADF1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADF1RST) 2874 2875 #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U) 2876 2877 #define __HAL_RCC_LPGPIO1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPGPIO1RST) 2878 2879 #define __HAL_RCC_ADC4_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADC4RST) 2880 2881 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_DAC1RST) 2882 2883 #define __HAL_RCC_LPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPDMA1RST) 2884 2885 #define __HAL_RCC_ADF1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADF1RST) 2886 2887 /** 2888 * @} 2889 */ 2890 2891 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 2892 * @brief Force or release APB1 peripheral reset. 2893 * @{ 2894 */ 2895 2896 #define __HAL_RCC_APB1_FORCE_RESET() do { \ 2897 WRITE_REG(RCC->APB1RSTR1, 0x027E403FU); \ 2898 WRITE_REG(RCC->APB1RSTR2, 0x00800222U); \ 2899 } while(0) 2900 2901 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 2902 2903 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 2904 2905 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 2906 2907 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 2908 2909 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 2910 2911 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 2912 2913 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 2914 2915 #if defined (USART2) 2916 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 2917 #endif /* USART2 */ 2918 2919 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 2920 2921 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 2922 2923 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 2924 2925 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 2926 2927 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 2928 2929 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 2930 2931 #if defined(USART6) 2932 #define __HAL_RCC_USART6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART6RST) 2933 #endif /* USART6 */ 2934 2935 #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 2936 2937 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 2938 2939 #if defined(I2C5) 2940 #define __HAL_RCC_I2C5_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C5RST) 2941 #endif /* I2C5 */ 2942 2943 #if defined(I2C6) 2944 #define __HAL_RCC_I2C6_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C6RST) 2945 #endif /* I2C6 */ 2946 2947 #define __HAL_RCC_FDCAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST) 2948 2949 #if defined(UCPD1) 2950 #define __HAL_RCC_UCPD_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) 2951 #endif /* UCPD1 */ 2952 2953 #define __HAL_RCC_APB1_RELEASE_RESET() do { \ 2954 WRITE_REG(RCC->APB1RSTR1, 0x00000000U); \ 2955 WRITE_REG(RCC->APB1RSTR2, 0x00000000U); \ 2956 } while(0) 2957 2958 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 2959 2960 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 2961 2962 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 2963 2964 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 2965 2966 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 2967 2968 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 2969 2970 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 2971 2972 #if defined(USART2) 2973 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 2974 #endif /* USART2 */ 2975 2976 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 2977 2978 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 2979 2980 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 2981 2982 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 2983 2984 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 2985 2986 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 2987 2988 #if defined(USART6) 2989 #define __HAL_RCC_USART6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART6RST) 2990 #endif /* USART6 */ 2991 2992 #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 2993 2994 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 2995 2996 #if defined(I2C5) 2997 #define __HAL_RCC_I2C5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C5RST) 2998 #endif /* I2C5 */ 2999 3000 #if defined(I2C6) 3001 #define __HAL_RCC_I2C6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C6RST) 3002 #endif /* I2C6 */ 3003 3004 #define __HAL_RCC_FDCAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST) 3005 3006 #if defined(UCPD1) 3007 #define __HAL_RCC_UCPD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) 3008 #endif /* UCPD1 */ 3009 3010 /** 3011 * @} 3012 */ 3013 3014 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 3015 * @brief Force or release APB2 peripheral reset. 3016 * @{ 3017 */ 3018 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00677800U) 3019 3020 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 3021 3022 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 3023 3024 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 3025 3026 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 3027 3028 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 3029 3030 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 3031 3032 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 3033 3034 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 3035 3036 #if defined(SAI2) 3037 #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 3038 #endif /* SAI2 */ 3039 3040 #if defined(USB_DRD_FS) 3041 #define __HAL_RCC_USB_FS_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) 3042 #endif /* USB_DRD_FS */ 3043 3044 #if defined(GFXTIM) 3045 #define __HAL_RCC_GFXTIM_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_GFXTIMRST) 3046 #endif /* GFXTIM */ 3047 3048 #if defined(LTDC) 3049 #define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) 3050 #endif /* LTDC */ 3051 3052 #if defined(DSI) 3053 #define __HAL_RCC_DSI_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIHOSTRST) 3054 #endif /* DSI */ 3055 3056 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) 3057 3058 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 3059 3060 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 3061 3062 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 3063 3064 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 3065 3066 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 3067 3068 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 3069 3070 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 3071 3072 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 3073 3074 #if defined(SAI2) 3075 #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 3076 #endif /* SAI2 */ 3077 3078 #if defined(USB_DRD_FS) 3079 #define __HAL_RCC_USB_FS_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) 3080 #endif /* USB_DRD_FS */ 3081 3082 #if defined(GFXTIM) 3083 #define __HAL_RCC_GFXTIM_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_GFXTIMRST) 3084 #endif /* GFXTIM */ 3085 3086 #if defined(LTDC) 3087 #define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) 3088 #endif /* LTDC */ 3089 3090 #if defined(DSI) 3091 #define __HAL_RCC_DSI_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIHOSTRST) 3092 #endif /* DSI */ 3093 3094 /** 3095 * @} 3096 */ 3097 3098 /** @defgroup RCC_APB3_Force_Release_Reset APB3 Peripheral Force Release Reset 3099 * @brief Force or release APB3 peripheral reset. 3100 * @{ 3101 */ 3102 #define __HAL_RCC_APB3_FORCE_RESET() WRITE_REG(RCC->APB3RSTR, 0x0010F8E2U) 3103 3104 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SYSCFGRST) 3105 3106 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI3RST) 3107 3108 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST) 3109 3110 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST) 3111 3112 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST) 3113 3114 #define __HAL_RCC_LPTIM3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST) 3115 3116 #define __HAL_RCC_LPTIM4_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST) 3117 3118 #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_OPAMPRST) 3119 3120 #define __HAL_RCC_COMP_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_COMPRST) 3121 3122 #define __HAL_RCC_VREF_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) 3123 3124 #define __HAL_RCC_APB3_RELEASE_RESET() WRITE_REG(RCC->APB3RSTR, 0x00000000U) 3125 3126 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SYSCFGRST) 3127 3128 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI3RST) 3129 3130 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST) 3131 3132 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST) 3133 3134 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST) 3135 3136 #define __HAL_RCC_LPTIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST) 3137 3138 #define __HAL_RCC_LPTIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST) 3139 3140 #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_OPAMPRST) 3141 3142 #define __HAL_RCC_COMP_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_COMPRST) 3143 3144 #define __HAL_RCC_VREF_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) 3145 3146 /** 3147 * @} 3148 */ 3149 3150 /** @defgroup RCC_AHB1_Peripheral_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable 3151 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep and Stop) mode. 3152 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 3153 * power consumption. 3154 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 3155 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 3156 * is enabled only when a peripheral requests AHB clock. 3157 * @{ 3158 */ 3159 #define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) 3160 3161 #define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) 3162 3163 #define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) 3164 3165 #define __HAL_RCC_MDF1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_MDF1SMEN) 3166 3167 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 3168 3169 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 3170 3171 #if defined(JPEG) 3172 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_JPEGSMEN) 3173 #endif /* JPEG */ 3174 3175 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 3176 3177 #define __HAL_RCC_RAMCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) 3178 3179 #if defined(DMA2D) 3180 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) 3181 #endif /* DMA2D */ 3182 3183 #if defined(GFXMMU) 3184 #define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) 3185 #endif /* GFXMMU */ 3186 3187 #if defined(GPU2D) 3188 #define __HAL_RCC_GPU2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPU2DSMEN) 3189 #endif /* GPU2D */ 3190 3191 #if defined(DCACHE2) 3192 #define __HAL_RCC_DCACHE2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE2SMEN) 3193 #endif /* DCACHE2 */ 3194 3195 #define __HAL_RCC_GTZC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) 3196 3197 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_BKPSRAMSMEN) 3198 3199 #define __HAL_RCC_ICACHE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) 3200 3201 #define __HAL_RCC_DCACHE1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE1SMEN) 3202 3203 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 3204 3205 #define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) 3206 3207 #define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) 3208 3209 #define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) 3210 3211 #define __HAL_RCC_MDF1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_MDF1SMEN) 3212 3213 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 3214 3215 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 3216 3217 #if defined(JPEG) 3218 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_JPEGSMEN) 3219 #endif /* JPEG */ 3220 3221 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 3222 3223 #define __HAL_RCC_RAMCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) 3224 3225 #if defined(DMA2D) 3226 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) 3227 #endif /* DMA2D */ 3228 3229 #if defined(GFXMMU) 3230 #define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) 3231 #endif /* GFXMMU */ 3232 3233 #if defined(GPU2D) 3234 #define __HAL_RCC_GPU2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPU2DSMEN) 3235 #endif /* GPU2D */ 3236 3237 #if defined(DCACHE2) 3238 #define __HAL_RCC_DCACHE2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE2SMEN) 3239 #endif /* DCACHE2 */ 3240 3241 #define __HAL_RCC_GTZC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) 3242 3243 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_BKPSRAMSMEN) 3244 3245 #define __HAL_RCC_ICACHE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) 3246 3247 #define __HAL_RCC_DCACHE1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE1SMEN) 3248 3249 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 3250 3251 /** 3252 * @} 3253 */ 3254 3255 /** @defgroup RCC_AHB2_Peripheral_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable 3256 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep and Stop) mode. 3257 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 3258 * power consumption. 3259 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 3260 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 3261 * is enabled only when a peripheral requests AHB clock. 3262 * @{ 3263 */ 3264 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOASMEN) 3265 3266 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOBSMEN) 3267 3268 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOCSMEN) 3269 3270 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIODSMEN) 3271 3272 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOESMEN) 3273 3274 #if defined(GPIOF) 3275 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOFSMEN) 3276 #endif /* GPIOF */ 3277 3278 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOGSMEN) 3279 3280 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOHSMEN) 3281 3282 #if defined(GPIOI) 3283 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOISMEN) 3284 #endif /* GPIOI */ 3285 3286 #if defined(GPIOJ) 3287 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOJSMEN) 3288 #endif /* GPIOJ */ 3289 3290 #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC12SMEN) 3291 3292 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_DCMI_PSSISMEN) 3293 3294 #if defined(USB_OTG_HS) 3295 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) 3296 #endif /* USB_OTG_HS */ 3297 3298 #if defined(USB_OTG_FS) 3299 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) 3300 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE /*!< alias define for compatibility with legacy code */ 3301 #endif /* USB_OTG_FS */ 3302 3303 #if defined(RCC_AHB2SMENR1_USBPHYCSMEN) 3304 #define __HAL_RCC_USBPHYCCLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_USBPHYCSMEN) 3305 #endif /* RCC_AHB2SMENR1_USBPHYCSMEN */ 3306 3307 #if defined(AES) 3308 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN) 3309 #endif /* AES */ 3310 3311 #if defined(HASH) 3312 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_HASHSMEN) 3313 #endif /* HASH */ 3314 3315 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_RNGSMEN) 3316 3317 #if defined(PKA) 3318 #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_PKASMEN) 3319 #endif /* PKA */ 3320 3321 #if defined(SAES) 3322 #define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SAESSMEN) 3323 #endif /* SAES */ 3324 3325 #if defined(OCTOSPIM) 3326 #define __HAL_RCC_OCTOSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OCTOSPIMSMEN) 3327 #endif /* OCTOSPIM */ 3328 3329 #if defined(OTFDEC1) 3330 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC1SMEN) 3331 #endif /* OTFDEC1 */ 3332 3333 #if defined(OTFDEC2) 3334 #define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC2SMEN) 3335 #endif /* OTFDEC2 */ 3336 3337 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC1SMEN) 3338 3339 #if defined(SDMMC2) 3340 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC2SMEN) 3341 #endif /* SDMMC2 */ 3342 3343 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM2SMEN) 3344 3345 #if defined(SRAM3_BASE) 3346 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM3SMEN) 3347 #endif /* SRAM3_BASE */ 3348 3349 #if defined(FMC_BASE) 3350 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_FSMCSMEN) 3351 #endif /* FMC_BASE */ 3352 3353 #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI1SMEN) 3354 3355 #if defined(OCTOSPI2) 3356 #define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI2SMEN) 3357 #endif /* OCTOSPI2 */ 3358 3359 #if defined(HSPI1) 3360 #define __HAL_RCC_HSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_HSPI1SMEN) 3361 #endif /* HSPI1 */ 3362 3363 #if defined(SRAM6_BASE) 3364 #define __HAL_RCC_SRAM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM6SMEN) 3365 #endif /* SRAM6_BASE */ 3366 3367 #if defined(SRAM5_BASE) 3368 #define __HAL_RCC_SRAM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM5SMEN) 3369 #endif /* SRAM5_BASE */ 3370 3371 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOASMEN) 3372 3373 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOBSMEN) 3374 3375 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOCSMEN) 3376 3377 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIODSMEN) 3378 3379 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOESMEN) 3380 3381 #if defined(GPIOF) 3382 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOFSMEN) 3383 #endif /* GPIOF */ 3384 3385 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOGSMEN) 3386 3387 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOHSMEN) 3388 3389 #if defined(GPIOI) 3390 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOISMEN) 3391 #endif /* GPIOI */ 3392 3393 #if defined(GPIOJ) 3394 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOJSMEN) 3395 #endif /* GPIOJ */ 3396 3397 #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC12SMEN) 3398 3399 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_DCMI_PSSISMEN) 3400 3401 #if defined(USB_OTG_HS) 3402 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) 3403 #endif /* USB_OTG_HS */ 3404 3405 #if defined(USB_OTG_FS) 3406 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) 3407 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE /*!< alias define for compatibility with legacy code */ 3408 #endif /* USB_OTG_FS */ 3409 3410 #if defined(RCC_AHB2SMENR1_USBPHYCSMEN) 3411 #define __HAL_RCC_USBPHYCCLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_USBPHYCSMEN) 3412 #endif /* RCC_AHB2SMENR1_USBPHYCSMEN */ 3413 3414 #if defined(AES) 3415 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN) 3416 #endif /* AES */ 3417 3418 #if defined(HASH) 3419 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_HASHSMEN) 3420 #endif /* HASH */ 3421 3422 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_RNGSMEN) 3423 3424 #if defined(PKA) 3425 #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_PKASMEN) 3426 #endif /* PKA */ 3427 3428 #if defined(SAES) 3429 #define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SAESSMEN) 3430 #endif /* SAES */ 3431 3432 #if defined(OCTOSPIM) 3433 #define __HAL_RCC_OCTOSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OCTOSPIMSMEN) 3434 #endif /* OCTOSPIM */ 3435 3436 #if defined(OTFDEC1) 3437 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC1SMEN) 3438 #endif /* OTFDEC1 */ 3439 3440 #if defined(OTFDEC2) 3441 #define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC2SMEN) 3442 #endif /* OTFDEC2 */ 3443 3444 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC1SMEN) 3445 3446 #if defined(SDMMC2) 3447 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC2SMEN) 3448 #endif /* SDMMC2 */ 3449 3450 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM2SMEN) 3451 3452 #if defined(SRAM3_BASE) 3453 #define __HAL_RCC_SRAM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM3SMEN) 3454 #endif /* SRAM3_BASE */ 3455 3456 #if defined(FMC_BASE) 3457 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_FSMCSMEN) 3458 #endif /* FMC_BASE */ 3459 3460 #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI1SMEN) 3461 3462 #if defined(OCTOSPI2) 3463 #define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI2SMEN) 3464 #endif /* OCTOSPI2 */ 3465 3466 #if defined(HSPI1) 3467 #define __HAL_RCC_HSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_HSPI1SMEN) 3468 #endif /* HSPI1 */ 3469 3470 #if defined(SRAM6_BASE) 3471 #define __HAL_RCC_SRAM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM6SMEN) 3472 #endif /* SRAM6_BASE */ 3473 3474 #if defined(SRAM5_BASE) 3475 #define __HAL_RCC_SRAM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM5SMEN) 3476 #endif /* SRAM5_BASE */ 3477 3478 /** 3479 * @} 3480 */ 3481 3482 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3SMENR Peripheral Clock Sleep Enable Disable 3483 * @brief Enable or disable the AHB3SMENR peripheral clock during Low Power (Sleep and STOP ) mode. 3484 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 3485 * power consumption. 3486 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 3487 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 3488 * is enabled only when a peripheral requests AHB clock. 3489 * @{ 3490 */ 3491 #define __HAL_RCC_LPGPIO1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN) 3492 3493 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PWRSMEN) 3494 3495 #define __HAL_RCC_ADC4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADC4SMEN) 3496 3497 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_DAC1SMEN) 3498 3499 #define __HAL_RCC_LPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN) 3500 3501 #define __HAL_RCC_ADF1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADF1SMEN) 3502 3503 #define __HAL_RCC_GTZC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_GTZC2SMEN) 3504 3505 #define __HAL_RCC_SRAM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM4SMEN) 3506 3507 #define __HAL_RCC_LPGPIO1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN) 3508 3509 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PWRSMEN) 3510 3511 #define __HAL_RCC_ADC4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADC4SMEN) 3512 3513 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_DAC1SMEN) 3514 3515 #define __HAL_RCC_LPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN) 3516 3517 #define __HAL_RCC_ADF1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADF1SMEN) 3518 3519 #define __HAL_RCC_GTZC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_GTZC2SMEN) 3520 3521 #define __HAL_RCC_SRAM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM4SMEN) 3522 3523 /** 3524 * @} 3525 */ 3526 3527 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 3528 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep and Stop) mode. 3529 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 3530 * power consumption. 3531 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 3532 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 3533 * is enabled only when a peripheral requests APB clock. 3534 * @{ 3535 */ 3536 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 3537 3538 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 3539 3540 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 3541 3542 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 3543 3544 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 3545 3546 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 3547 3548 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 3549 3550 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 3551 3552 #if defined(USART2) 3553 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 3554 #endif /* USART2 */ 3555 3556 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 3557 3558 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 3559 3560 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 3561 3562 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 3563 3564 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 3565 3566 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 3567 3568 #if defined(USART6) 3569 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART6SMEN) 3570 #endif /* USART6 */ 3571 3572 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 3573 3574 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 3575 3576 #if defined(I2C5) 3577 #define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C5SMEN) 3578 #endif /* I2C5 */ 3579 3580 #if defined(I2C6) 3581 #define __HAL_RCC_I2C6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C6SMEN) 3582 #endif /* I2C6 */ 3583 3584 #define __HAL_RCC_FDCAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN) 3585 3586 #if defined(UCPD1) 3587 #define __HAL_RCC_UCPD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) 3588 #endif /* UCPD1 */ 3589 3590 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 3591 3592 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 3593 3594 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 3595 3596 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 3597 3598 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 3599 3600 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 3601 3602 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 3603 3604 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 3605 3606 #if defined(USART2) 3607 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 3608 #endif /* USART2 */ 3609 3610 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 3611 3612 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 3613 3614 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 3615 3616 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 3617 3618 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 3619 3620 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 3621 3622 #if defined(USART6) 3623 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART6SMEN) 3624 #endif /* USART6 */ 3625 3626 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 3627 3628 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 3629 3630 #if defined(I2C5) 3631 #define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C5SMEN) 3632 #endif /* I2C5 */ 3633 3634 #if defined(I2C6) 3635 #define __HAL_RCC_I2C6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C6SMEN) 3636 #endif /* I2C6 */ 3637 3638 #define __HAL_RCC_FDCAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN) 3639 3640 #if defined(UCPD1) 3641 #define __HAL_RCC_UCPD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) 3642 #endif /* UCPD1 */ 3643 3644 /** 3645 * @} 3646 */ 3647 3648 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 3649 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep and Stop) mode. 3650 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 3651 * power consumption. 3652 * @note After wakeup from SLEEP or STOP mode, the pseripheral clock is enabled again. 3653 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 3654 * is enabled only when a peripheral requests APB clock. 3655 * @{ 3656 */ 3657 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 3658 3659 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 3660 3661 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 3662 3663 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 3664 3665 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 3666 3667 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 3668 3669 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 3670 3671 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 3672 3673 #if defined(SAI2) 3674 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 3675 #endif /* SAI2 */ 3676 3677 #if defined(USB_DRD_FS) 3678 #define __HAL_RCC_USB_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USBSMEN) 3679 #endif /* USB_DRD_FS */ 3680 3681 #if defined(GFXTIM) 3682 #define __HAL_RCC_GFXTIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_GFXTIMSMEN) 3683 #endif /* GFXTIM */ 3684 3685 #if defined(LTDC) 3686 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) 3687 #endif /* LTDC */ 3688 3689 #if defined(DSI) 3690 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSIHOSTSMEN) 3691 #endif /* DSI */ 3692 3693 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 3694 3695 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 3696 3697 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 3698 3699 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 3700 3701 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 3702 3703 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 3704 3705 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 3706 3707 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 3708 3709 #if defined(SAI2) 3710 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 3711 #endif /* SAI2 */ 3712 3713 #if defined(USB_DRD_FS) 3714 #define __HAL_RCC_USB_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USBSMEN) 3715 #endif /* USB_DRD_FS */ 3716 3717 #if defined(GFXTIM) 3718 #define __HAL_RCC_GFXTIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_GFXTIMSMEN) 3719 #endif /* GFXTIM */ 3720 3721 #if defined(LTDC) 3722 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) 3723 #endif /* LTDC */ 3724 3725 #if defined(DSI) 3726 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSIHOSTSMEN) 3727 #endif /* DSI */ 3728 3729 /** 3730 * @} 3731 */ 3732 3733 /** @defgroup RCC_APB3_Clock_Sleep_Enable_Disable APB3 Peripheral Clock Sleep Enable Disable 3734 * @brief Enable or disable the APB3 peripheral clock during Low Power (Sleep and Stop) mode. 3735 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 3736 * power consumption. 3737 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 3738 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 3739 * is enabled only when a peripheral requests APB clock. 3740 * @{ 3741 */ 3742 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SYSCFGSMEN) 3743 3744 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SPI3SMEN) 3745 3746 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPUART1SMEN) 3747 3748 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_I2C3SMEN) 3749 3750 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM1SMEN) 3751 3752 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM3SMEN) 3753 3754 #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM4SMEN) 3755 3756 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_OPAMPSMEN) 3757 3758 #define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_COMPSMEN) 3759 3760 #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_VREFSMEN) 3761 3762 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_RTCAPBSMEN) 3763 3764 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SYSCFGSMEN) 3765 3766 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SPI3SMEN) 3767 3768 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPUART1SMEN) 3769 3770 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_I2C3SMEN) 3771 3772 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM1SMEN) 3773 3774 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM3SMEN) 3775 3776 #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM4SMEN) 3777 3778 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_OPAMPSMEN) 3779 3780 #define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_COMPSMEN) 3781 3782 #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_VREFSMEN) 3783 3784 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_RTCAPBSMEN) 3785 3786 /** 3787 * @} 3788 */ 3789 3790 /** @brief Enable or disable peripheral bus clock when SRD domain is in DRUN 3791 * @note After reset, peripheral clock is disabled when CPUs are in CSTOP 3792 * @{ 3793 */ 3794 #define __HAL_RCC_SPI3_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_SPI3AMEN) 3795 3796 #define __HAL_RCC_LPUART1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPUART1AMEN) 3797 3798 #define __HAL_RCC_I2C3_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_I2C3AMEN) 3799 3800 #define __HAL_RCC_LPTIM1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM1AMEN) 3801 3802 #define __HAL_RCC_LPTIM3_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM3AMEN) 3803 3804 #define __HAL_RCC_LPTIM4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM4AMEN) 3805 3806 #define __HAL_RCC_OPAMP_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_OPAMPAMEN) 3807 3808 #define __HAL_RCC_COMP12_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_COMPAMEN) 3809 3810 #define __HAL_RCC_ADC4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_ADC4AMEN) 3811 3812 #define __HAL_RCC_VREF_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_VREFAMEN) 3813 3814 #define __HAL_RCC_RTCAPB_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_RTCAPBAMEN) 3815 3816 #define __HAL_RCC_LPGPIO1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPGPIO1AMEN) 3817 3818 #define __HAL_RCC_DAC1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_DAC1AMEN) 3819 3820 #define __HAL_RCC_LPDMA1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPDMA1AMEN) 3821 3822 #define __HAL_RCC_ADF1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_ADF1AMEN) 3823 3824 #define __HAL_RCC_SRAM4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_SRAM4AMEN) 3825 3826 #define __HAL_RCC_SPI3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_SPI3AMEN) 3827 3828 #define __HAL_RCC_LPUART1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPUART1AMEN) 3829 3830 #define __HAL_RCC_I2C3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_I2C3AMEN) 3831 3832 #define __HAL_RCC_LPTIM1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM1AMEN) 3833 3834 #define __HAL_RCC_LPTIM3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM3AMEN) 3835 3836 #define __HAL_RCC_LPTIM4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM4AMEN) 3837 3838 #define __HAL_RCC_OPAMP_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_OPAMPAMEN) 3839 3840 #define __HAL_RCC_COMP12_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_COMPAMEN) 3841 3842 #define __HAL_RCC_ADC4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_ADC4AMEN) 3843 3844 #define __HAL_RCC_VREF_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_VREFAMEN) 3845 3846 #define __HAL_RCC_RTCAPB_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_RTCAPBAMEN) 3847 3848 #define __HAL_RCC_LPGPIO1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPGPIO1AMEN) 3849 3850 #define __HAL_RCC_DAC1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_DAC1AMEN) 3851 3852 #define __HAL_RCC_LPDMA1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPDMA1AMEN) 3853 3854 #define __HAL_RCC_ADF1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_ADF1AMEN) 3855 3856 #define __HAL_RCC_SRAM4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_SRAM4AMEN) 3857 3858 /** 3859 * @} 3860 */ 3861 3862 3863 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset 3864 * @{ 3865 */ 3866 3867 /** @brief Macros to force or release the Backup domain reset. 3868 * @note This function resets the RTC peripheral (including the backup registers) 3869 * and the RTC clock source selection in RCC_CSR register. 3870 * @note The BKPSRAM is not affected by this reset. 3871 * @retval None 3872 */ 3873 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) 3874 3875 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) 3876 3877 /** 3878 * @} 3879 */ 3880 3881 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 3882 * @{ 3883 */ 3884 3885 /** @brief Macros to enable or disable the RTC clock. 3886 * @note As the RTC is in the Backup domain and write access is denied to 3887 * this domain after reset, you have to enable write access using 3888 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC 3889 * (to be done once after reset). 3890 * @note These macros must be used after the RTC clock source was selected. 3891 * @retval None 3892 */ 3893 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 3894 3895 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 3896 3897 /** 3898 * @} 3899 */ 3900 3901 /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). 3902 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 3903 * It is used (enabled by hardware) as system clock source after startup 3904 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 3905 * of the HSE used directly or indirectly as system clock (if the Clock 3906 * Security System CSS is enabled). 3907 * @note HSI can not be stopped if it is used as system clock source. In this case, 3908 * you have to select another source of the system clock then stop the HSI. 3909 * @note After enabling the HSI, the application software should wait on HSIRDY 3910 * flag to be set indicating that HSI clock is stable and can be used as 3911 * system clock source. 3912 * This parameter can be: ENABLE or DISABLE. 3913 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 3914 * clock cycles. 3915 * @retval None 3916 */ 3917 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 3918 3919 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 3920 3921 /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. 3922 * @note The calibration is used to compensate for the variations in voltage 3923 * and temperature that influence the frequency of the internal HSI RC. 3924 * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value 3925 * (default is RCC_HSICALIBRATION_DEFAULT). 3926 * This parameter must be a number between 0 and 0x20. 3927 * @retval None 3928 */ 3929 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 3930 MODIFY_REG(RCC->ICSCR3, RCC_ICSCR3_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR3_HSITRIM_Pos) 3931 3932 /** 3933 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 3934 * in STOP mode to be quickly available as kernel clock for USARTs, LPUART and I2Cs. 3935 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 3936 * speed because of the HSI startup time. 3937 * @note The enable of this function has not effect on the HSION bit. 3938 * This parameter can be: ENABLE or DISABLE. 3939 * @retval None 3940 */ 3941 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 3942 3943 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 3944 3945 /** 3946 * @brief Macros to enable or disable the force of the Internal Multi Speed kernel oscillator (MSIK) 3947 * in STOP mode to be quickly available as kernel clock for USARTs, LPUART and I2Cs. 3948 * @note Keeping the MSIK ON in STOP mode allows to avoid slowing down the communication 3949 * speed because of the MSIK startup time. 3950 * @note The enable of this function has not effect on the MSIKON bit. 3951 * @note The MSIKERON must be configured at 0 before entreing stop 3 mode. 3952 * This parameter can be: ENABLE or DISABLE. 3953 * @retval None 3954 */ 3955 #define __HAL_RCC_MSIKSTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSIKERON) 3956 3957 #define __HAL_RCC_MSIKSTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSIKERON) 3958 3959 /** 3960 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). 3961 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. 3962 * It is used (enabled by hardware) as system clock source after 3963 * startup from Reset, wakeup from STOP and STANDBY mode, or in case 3964 * of failure of the HSE used directly or indirectly as system clock 3965 * (if the Clock Security System CSS is enabled). 3966 * @note MSI can not be stopped if it is used as system clock source. 3967 * In this case, you have to select another source of the system 3968 * clock then stop the MSI. 3969 * @note After enabling the MSI, the application software should wait on 3970 * MSIRDY flag to be set indicating that MSI clock is stable and can 3971 * be used as system clock source. 3972 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator 3973 * clock cycles. 3974 * @retval None 3975 */ 3976 #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSISON) 3977 3978 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSISON) 3979 3980 /** 3981 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode 3982 * @note After restart from Reset , the MSI clock is around 4 MHz. 3983 * After stop the startup clock can be MSI (at any of its possible 3984 * frequencies, the one that was used before entering stop mode) or HSI. 3985 * After Standby its frequency can be selected between 4 possible values 3986 * (1, 3.072, 4 or 8 MHz). 3987 * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready 3988 * (MSIRDY=1). 3989 * @note The MSI clock range after reset can be modified on the fly. 3990 * @param __MSIRANGEVALUE__: specifies the MSI clock range. 3991 * This parameter must be one of the following values: 3992 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 48 MHz 3993 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 24 KHz 3994 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 16 MHz 3995 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 12 MHz 3996 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset) 3997 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 3998 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz 3999 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz 4000 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz 4001 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 1.536 MHz 4002 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 1.024 MHz 4003 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 768 KHz 4004 * @arg @ref RCC_MSIRANGE_12 MSI clock is around 400 KHz 4005 * @arg @ref RCC_MSIRANGE_13 MSI clock is around 200 KHz 4006 * @arg @ref RCC_MSIRANGE_14 MSI clock is around 133 KHz 4007 * @arg @ref RCC_MSIRANGE_15 MSI clock is around 100 KHz 4008 * @retval None 4009 */ 4010 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \ 4011 do { \ 4012 SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ 4013 MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE, (__MSIRANGEVALUE__)); \ 4014 } while(0) 4015 4016 /** 4017 * @brief Macro configures the Internal Multi Speed kernel oscillator (MSIK) clock range in run mode 4018 * @note After restart from Reset , the MSIK clock is around 4 MHz. 4019 * After stop the startup clock can be MSIK (at any of its possible 4020 * frequencies, the one that was used before entering stop mode) or HSI. 4021 * After Standby its frequency can be selected between 4 possible values 4022 * (1, 3.072, 4 or 8 MHz). 4023 * @note MSIKRANGE can be modified when MSIK is OFF (MSIKON=0) or when MSIK is ready 4024 * (MSIKRDY=1). 4025 * @note The MSI clock range after reset can be modified on the fly. 4026 * @param __MSIKRANGEVALUE__: specifies the MSI clock range. 4027 * @arg @ref RCC_MSIKRANGE_0 MSIK clock is around 48 MHz 4028 * @arg @ref RCC_MSIKRANGE_1 MSIK clock is around 24 KHz 4029 * @arg @ref RCC_MSIKRANGE_2 MSIK clock is around 16 MHz 4030 * @arg @ref RCC_MSIKRANGE_3 MSIK clock is around 12 MHz 4031 * @arg @ref RCC_MSIKRANGE_4 MSIK clock is around 4 MHz (default after Reset) 4032 * @arg @ref RCC_MSIKRANGE_5 MSIK clock is around 2 MHz 4033 * @arg @ref RCC_MSIKRANGE_6 MSIK clock is around 1.33 MHz 4034 * @arg @ref RCC_MSIKRANGE_7 MSIK clock is around 1 MHz 4035 * @arg @ref RCC_MSIKRANGE_8 MSIK clock is around 3.072 MHz 4036 * @arg @ref RCC_MSIKRANGE_9 MSIK clock is around 1.536 MHz 4037 * @arg @ref RCC_MSIKRANGE_10 MSIK clock is around 1.024 MHz 4038 * @arg @ref RCC_MSIKRANGE_11 MSIK clock is around 768 KHz 4039 * @arg @ref RCC_MSIKRANGE_12 MSIK clock is around 400 KHz 4040 * @arg @ref RCC_MSIKRANGE_13 MSIK clock is around 200 KHz 4041 * @arg @ref RCC_MSIKRANGE_14 MSIK clock is around 133 KHz 4042 * @arg @ref RCC_MSIKRANGE_15 MSIK clock is around 100 KHz 4043 * @retval None 4044 */ 4045 #define __HAL_RCC_MSIK_RANGE_CONFIG(__MSIKRANGEVALUE__) \ 4046 do { \ 4047 SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ 4048 MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE, (__MSIKRANGEVALUE__)); \ 4049 } while(0) 4050 4051 /** @brief Macros to enable or disable the MSI bias mode selection. 4052 * @note By default the MSI bias is in continuous mode in order to maintain 4053 * the output clocks accuracy. 4054 * @note Setting this bit reduces the MSI consumption under range 4 but decrease its accuracy. 4055 * @retval None 4056 */ 4057 #define __HAL_RCC_MSIBIAS_SELECTION_ENABLE() SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS) 4058 4059 #define __HAL_RCC_MSIBIAS_SELECTION_DISABLE() CLEAR_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS) 4060 4061 /** @brief Macros to enable or disable LSE clock glitch filter . 4062 * @note The glitches on LSE can be filtred by setting the LSEGFON. 4063 * @note LSEGFON must be written when the LSE is disabled (LSEON = 0 and LSERDY = 0). 4064 * @retval None 4065 */ 4066 4067 #define __HAL_RCC_LSE_GLITCHFILTER_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_LSEGFON ) 4068 4069 #define __HAL_RCC_LSE_GLITCHFILTER_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEGFON ) 4070 4071 /** 4072 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode 4073 * After Standby its frequency can be selected between 5 possible values (4, 2, 1.33, 1, or 3.072 MHz). 4074 * @param __MSIRANGEVALUE__: specifies the MSI clock range. 4075 * This parameter must be one of the following values: 4076 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset) 4077 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 4078 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz 4079 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz 4080 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz 4081 * @retval None 4082 */ 4083 #define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) do {SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL);\ 4084 MODIFY_REG(RCC->CSR, RCC_CSR_MSISSRANGE,\ 4085 (__MSIRANGEVALUE__) >> (RCC_ICSCR1_MSISRANGE_Pos -\ 4086 RCC_CSR_MSISSRANGE_Pos));\ 4087 } while(0) 4088 /** 4089 * @brief Macro configures the Internal Multi Speed oscillator (MSIK) clock range after Standby mode 4090 * After Standby its frequency can be selected between 5 possible values (4, 2, 1.33, 1, or 3.072 MHz). 4091 * @param __MSIKRANGEVALUE__: specifies the MSIK clock range. 4092 * This parameter must be one of the following values: 4093 * @arg @ref RCC_MSIKRANGE_4 MSIK clock is around 4 MHz (default after Reset) 4094 * @arg @ref RCC_MSIKRANGE_5 MSIK clock is around 2 MHz 4095 * @arg @ref RCC_MSIKRANGE_6 MSIK clock is around 1.33 MHz 4096 * @arg @ref RCC_MSIKRANGE_7 MSIK clock is around 1 MHz 4097 * @arg @ref RCC_MSIKRANGE_8 MSIK clock is around 3.072 MHz 4098 * @retval None 4099 */ 4100 #define __HAL_RCC_MSIK_STANDBY_RANGE_CONFIG(__MSIKRANGEVALUE__) \ 4101 do { \ 4102 SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ 4103 MODIFY_REG(RCC->CSR, RCC_CSR_MSIKSRANGE, \ 4104 (__MSIKRANGEVALUE__) >> (RCC_ICSCR1_MSIKRANGE_Pos - RCC_CSR_MSIKSRANGE_Pos)); \ 4105 } while(0) 4106 4107 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode 4108 * @retval MSI clock range. 4109 * This parameter must be one of the following values: 4110 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 48 MHz 4111 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 24 KHz 4112 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 16 MHz 4113 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 12 MHz 4114 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz 4115 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 4116 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz 4117 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz 4118 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz 4119 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 1.536 MHz 4120 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 1.024 MHz 4121 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 768 KHz 4122 * @arg @ref RCC_MSIRANGE_12 MSI clock is around 400 KHz 4123 * @arg @ref RCC_MSIRANGE_13 MSI clock is around 200 KHz 4124 * @arg @ref RCC_MSIRANGE_14 MSI clock is around 133 KHz 4125 * @arg @ref RCC_MSIRANGE_15 MSI clock is around 100 KHz 4126 */ 4127 #define __HAL_RCC_GET_MSI_RANGE() ((READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) != 0U) ? \ 4128 (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE)) : \ 4129 (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISSRANGE) << \ 4130 (RCC_ICSCR1_MSISRANGE_Pos - RCC_CSR_MSISSRANGE_Pos))) 4131 4132 /** @brief Macro to get the Internal Multi Speed kernel oscillator (MSIK) clock range in run mode 4133 * @retval MSIK clock range. 4134 * This parameter must be one of the following values: 4135 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 48 MHz 4136 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 24 KHz 4137 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 16 MHz 4138 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 12 MHz 4139 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz 4140 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 4141 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz 4142 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz 4143 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz 4144 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 1.536 MHz 4145 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 1.024 MHz 4146 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 768 KHz 4147 * @arg @ref RCC_MSIRANGE_12 MSI clock is around 400 KHz 4148 * @arg @ref RCC_MSIRANGE_13 MSI clock is around 200 KHz 4149 * @arg @ref RCC_MSIRANGE_14 MSI clock is around 133 KHz 4150 * @arg @ref RCC_MSIRANGE_15 MSI clock is around 100 KHz 4151 */ 4152 #define __HAL_RCC_GET_MSIK_RANGE() ((READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) != 0U) ? \ 4153 (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE)) : \ 4154 (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSIKSRANGE) << \ 4155 (RCC_ICSCR1_MSIKRANGE_Pos - RCC_CSR_MSIKSRANGE_Pos))) 4156 4157 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 4158 * @note After enabling the LSI, the application software should wait on 4159 * LSIRDY flag to be set indicating that LSI clock is stable and can 4160 * be used to clock the IWDG and/or the RTC. 4161 * @note LSI can not be disabled if the IWDG is running. 4162 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 4163 * clock cycles. 4164 * @retval None 4165 */ 4166 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_LSION) 4167 4168 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSION|RCC_BDCR_LSIPREDIV) 4169 4170 /** 4171 * @brief Macro to configure the External High Speed oscillator (HSE). 4172 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 4173 * supported by this macro. User should request a transition to HSE Off 4174 * first and then HSE On or HSE Bypass. 4175 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 4176 * software should wait on HSERDY flag to be set indicating that HSE clock 4177 * is stable and can be used to clock the PLL and/or system clock. 4178 * @note HSE state can not be changed if it is used directly or through the 4179 * PLL as system clock. In this case, you have to select another source 4180 * of the system clock then change the HSE state (ex. disable it). 4181 * @note The HSE is stopped by hardware when entering STOP and STANDBY or shutdown modes. 4182 * @param __STATE__: specifies the new state of the HSE. 4183 * This parameter can be one of the following values: 4184 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 4185 * 6 HSE oscillator clock cycles. 4186 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 4187 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. 4188 * @arg @ref RCC_HSE_BYPASS_DIGITAL HSE oscillator bypassed through I/O Schmitt trigger . 4189 * @retval None 4190 */ 4191 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 4192 do { \ 4193 if((__STATE__) == RCC_HSE_ON) \ 4194 { \ 4195 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 4196 } \ 4197 else if((__STATE__) == RCC_HSE_BYPASS) \ 4198 { \ 4199 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4200 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 4201 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 4202 } \ 4203 else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL) \ 4204 { \ 4205 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4206 SET_BIT(RCC->CR, RCC_CR_HSEEXT); \ 4207 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 4208 } \ 4209 else \ 4210 { \ 4211 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 4212 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4213 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 4214 } \ 4215 } while(0) 4216 4217 /** @brief Macro to enable or disable the LSE system clock. 4218 * @note This clock can be used by any peripheral when its source clock is the LSE or at system 4219 * in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed. 4220 * @note The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by 4221 * the CSS on LSE, by a peripheral or any other source clock using LSE. 4222 * @retval None 4223 */ 4224 #define __HAL_RCC_LSESYS_ENABLE() SET_BIT(RCC->BDCR,RCC_BDCR_LSESYSEN) 4225 4226 #define __HAL_RCC_LSESYS_DISABLE() CLEAR_BIT(RCC->BDCR,RCC_BDCR_LSESYSEN) 4227 4228 /** @brief Macro to set Low-speed clock (LSI) divider. 4229 * @note This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). 4230 * The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC. 4231 * 4232 * @param __DIVIDER__ : specifies the divider value 4233 * This parameter can be one of the following values 4234 * @arg @ref RCC_LSI_DIV1 4235 * @arg @ref RCC_LSI_DIV128 4236 * @retval None 4237 */ 4238 #define __HAL_RCC_LSI_DIV_CONFIG(__DIVIDER__) \ 4239 do { \ 4240 if((__DIVIDER__) == RCC_LSI_DIV128) \ 4241 { \ 4242 SET_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV); \ 4243 } \ 4244 else \ 4245 { \ 4246 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV); \ 4247 } \ 4248 } while(0) 4249 4250 /** 4251 * @brief Macro to configure the External Low Speed oscillator (LSE). 4252 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 4253 * supported by this macro. User should request a transition to LSE Off 4254 * first and then LSE On or LSE Bypass. 4255 * @note As the LSE is in the Backup domain and write access is denied to 4256 * this domain after reset, you have to enable write access using 4257 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 4258 * (to be done once after reset). 4259 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 4260 * software should wait on LSERDY flag to be set indicating that LSE clock 4261 * is stable and can be used to clock the RTC. 4262 * @param __STATE__: specifies the new state of the LSE. 4263 * This parameter can be one of the following values: 4264 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 4265 * 6 LSE oscillator clock cycles. 4266 * @arg @ref RCC_LSE_ON_RTC_ONLY Turn ON the LSE oscillator to be used only for RTC. 4267 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator to be used by any peripheral. 4268 * @arg @ref RCC_LSE_BYPASS_RTC_ONLY LSE oscillator bypassed with external clock to be used only for RTC. 4269 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock to be used by any peripheral 4270 * @retval None 4271 */ 4272 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 4273 do { \ 4274 if((__STATE__) == RCC_LSE_ON_RTC_ONLY) \ 4275 { \ 4276 SET_BIT(RCC->BDCR,RCC_BDCR_LSEON); \ 4277 } \ 4278 else if((__STATE__) == RCC_LSE_ON) \ 4279 { \ 4280 SET_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ 4281 } \ 4282 else if((__STATE__) == RCC_LSE_BYPASS_RTC_ONLY) \ 4283 { \ 4284 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4285 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4286 } \ 4287 else if((__STATE__) == RCC_LSE_BYPASS) \ 4288 { \ 4289 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4290 SET_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ 4291 } \ 4292 else \ 4293 { \ 4294 CLEAR_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ 4295 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4296 } \ 4297 } while(0) 4298 4299 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). 4300 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 4301 * @note After enabling the HSI48, the application software should wait on HSI48RDY 4302 * flag to be set indicating that HSI48 clock is stable. 4303 * This parameter can be: ENABLE or DISABLE. 4304 * @retval None 4305 */ 4306 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON) 4307 4308 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON) 4309 4310 /** @brief Macros to enable or disable the Internal multi-speed RC oscillator clock (MSIK). 4311 * @note if the peripheral requests its kernel clock in Stop 0 or Stop 1 mode,MSIK is woken up 4312 * @note After enabling the MSIK, the application software should wait on MSIKRDY 4313 * flag to be set indicating that MSIK clock is stable. 4314 * This parameter can be: ENABLE or DISABLE. 4315 * @retval None 4316 */ 4317 #define __HAL_RCC_MSIK_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSIKON) 4318 4319 #define __HAL_RCC_MSIK_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSIKON) 4320 4321 /** @brief Macros to enable or disable the secure Internal High Speed oscillator (SHSI). 4322 * @note The SHSI is stopped by hardware when entering STOP and STANDBY modes. 4323 * @note After enabling the SHSI, the application software should wait on SHSI 4324 * flag to be set indicating that SHSI clock is stable. 4325 * This parameter can be: ENABLE or DISABLE. 4326 * @retval None 4327 */ 4328 #define __HAL_RCC_SHSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_SHSION) 4329 4330 #define __HAL_RCC_SHSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_SHSION) 4331 4332 /** @brief Macros to configure the RTC clock (RTCCLK). 4333 * @note As the RTC clock configuration bits are in the Backup domain and write 4334 * access is denied to this domain after reset, you have to enable write 4335 * access using the Power Backup Access macro before to configure 4336 * the RTC clock source (to be done once after reset). 4337 * @note Once the RTC clock is configured it cannot be changed unless the 4338 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by 4339 * a Power On Reset (POR). 4340 * 4341 * @param __RTC_CLKSOURCE__: specifies the RTC clock source. 4342 * This parameter can be one of the following values: 4343 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. 4344 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 4345 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 4346 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 4347 * 4348 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 4349 * work in STOP and STANDBY modes, and can be used as wakeup source. 4350 * However, when the HSE clock is used as RTC clock source, the RTC 4351 * cannot be used in STOP and STANDBY modes. 4352 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 4353 * RTC clock source). 4354 * @retval None 4355 */ 4356 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ 4357 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) 4358 4359 /** @brief Macro to get the RTC clock source. 4360 * @retval The returned value can be one of the following: 4361 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. 4362 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 4363 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 4364 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 4365 */ 4366 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) 4367 4368 /** @brief Macros to enable or disable the main PLL. 4369 * @note After enabling the main PLL, the application software should wait on 4370 * PLLRDY flag to be set indicating that PLL clock is stable and can 4371 * be used as system clock source. 4372 * @note The main PLL can not be disabled if it is used as system clock source 4373 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 4374 */ 4375 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON) 4376 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON) 4377 4378 /** 4379 * @brief Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK) 4380 * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL, 4381 * This is mainly used to save Power. 4382 * @param __PLL1_CLOCKOUT__: specifies the PLL clock to be outputted 4383 * This parameter can be one of the following values: 4384 * @arg RCC_PLL1_DIVP: This clock is used to generate an accurate clock to achieve, 4385 * high-quality audio performance on SAI interface. 4386 * @arg RCC_PLL1_DIVQ: This Clock is used to generate the clock for the USB FS(48 MHz), 4387 * the random analog generator (<=48 MHz) and the OCTOSPI1/2. 4388 * @arg RCC_PLL1_DIVR: This Clock is used to generate the high speed system clock (up to 160MHz) 4389 * @retval None 4390 * 4391 */ 4392 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLL1_CLOCKOUT__) SET_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 4393 4394 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLL1_CLOCKOUT__) CLEAR_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 4395 4396 /** 4397 * @brief Macro to get the PLL clock output enable status. 4398 * @param __PLL1_CLOCKOUT__ specifies the PLL1 clock to be output. 4399 * This parameter can be one of the following values: 4400 * @arg RCC_PLL1_DIVP: This clock is used to generate an accurate clock to achieve, 4401 * high-quality audio performance on SAI interface. 4402 * @arg RCC_PLL1_DIVQ: This Clock is used to generate the clock for the USB FS(48 MHz), 4403 * the random analog generator (<=48 MHz) and the OCTOSPI1/2. 4404 * @arg RCC_PLL1_DIVR: This Clock is used to generate the high speed system clock (up to 160MHz) 4405 * @retval SET / RESET 4406 */ 4407 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLL1_CLOCKOUT__) READ_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 4408 4409 /** 4410 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO 4411 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1 4412 * @retval None 4413 */ 4414 #define __HAL_RCC_PLL_FRACN_ENABLE() SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) 4415 4416 #define __HAL_RCC_PLL_FRACN_DISABLE() CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) 4417 4418 /** 4419 * @brief Macro to configure the main PLL clock source, multiplication and division factors. 4420 * @note This function must be used only when the main PLL is disabled. 4421 * 4422 * @param __PLL1SOURCE__: specifies the PLL entry clock source. 4423 * This parameter can be one of the following values: 4424 * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL clock entry 4425 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 4426 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 4427 * @note This clock source (__PLL1SOURCE__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 . 4428 * 4429 * @param __PLL1MBOOST__: specifies the division factor for the EPOD clock 4430 * This parameter must be a value of @ref RCC_PLLMBOOST_EPOD_Clock_Divider. 4431 * 4432 * @param __PLL1M__: specifies the division factor for PLL VCO input clock 4433 * This parameter must be a number between 1 and 63. 4434 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 4435 * frequency ranges from 1 to 16 MHz. 4436 * 4437 * @param __PLL1N__: specifies the multiplication factor for PLL VCO output clock 4438 * This parameter must be a number between 4 and 512. 4439 * @note You have to set the PLLN parameter correctly to ensure that the VCO 4440 * output frequency is between 128 and 544 MHz(Voltage range 1 or 2) 4441 * between 128 and 330 MHZ (Voltage range 3) and not allowed for Voltage range 4. 4442 * 4443 * @param __PLL1P__: specifies the division factor for peripheral kernel clocks. 4444 * This parameter must be a number between 1 and 128 4445 * 4446 * @param __PLL1Q__: specifies the division factor for peripheral kernel clocks. 4447 * This parameter must be a number between 1 and 128 4448 * 4449 * @param __PLL1R__: specifies the division factor for system clock. 4450 * This parameter must be a number between 1 and 128 (Only division by 1 and even division are allowed) 4451 * 4452 * @retval None 4453 */ 4454 #define __HAL_RCC_PLL_CONFIG(__PLL1SOURCE__, __PLL1MBOOST__,__PLL1M__, __PLL1N__, __PLL1P__, __PLL1Q__, __PLL1R__) \ 4455 do{ MODIFY_REG(RCC->PLL1CFGR,(RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M|\ 4456 RCC_PLL1CFGR_PLL1MBOOST), ((__PLL1SOURCE__) << RCC_PLL1CFGR_PLL1SRC_Pos) |\ 4457 (((__PLL1M__) - 1U) << RCC_PLL1CFGR_PLL1M_Pos) | (__PLL1MBOOST__));\ 4458 MODIFY_REG(RCC->PLL1DIVR ,(RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1P | RCC_PLL1DIVR_PLL1Q |\ 4459 RCC_PLL1DIVR_PLL1R), ( (((__PLL1N__) - 1U ) & RCC_PLL1DIVR_PLL1N) |\ 4460 ((((__PLL1P__) -1U ) << RCC_PLL1DIVR_PLL1P_Pos) & \ 4461 RCC_PLL1DIVR_PLL1P) | \ 4462 ((((__PLL1Q__) -1U) << RCC_PLL1DIVR_PLL1Q_Pos) & \ 4463 RCC_PLL1DIVR_PLL1Q) |\ 4464 ((((__PLL1R__)- 1U) << RCC_PLL1DIVR_PLL1R_Pos) & \ 4465 RCC_PLL1DIVR_PLL1R))); \ 4466 } while(0) 4467 4468 /** @brief Macro to configure the PLLs clock source. 4469 * @note This function must be used only when all PLLs are disabled. 4470 * @param __PLL1SOURCE__: specifies the PLLs entry clock source. 4471 * This parameter can be one of the following values: 4472 * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL clock entry 4473 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 4474 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 4475 */ 4476 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLL1SOURCE__) MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, (__PLL1SOURCE__)) 4477 4478 /** 4479 * @brief Macro to configure the main PLL clock Fractional Part Of The Multiplication Factor 4480 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO 4481 * @param __PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO 4482 * It should be a value between 0 and 8191 4483 * @note Warning: The software has to set correctly these bits to insure that the VCO 4484 * output frequency is between its valid frequency range, which is: 4485 * 192 to 836 MHz if PLL1VCOSEL = 0 4486 * 150 to 420 MHz if PLL1VCOSEL = 1. 4487 * @retval None 4488 */ 4489 #define __HAL_RCC_PLL_FRACN_CONFIG(__PLL1FRACN__) WRITE_REG(RCC->PLL1FRACR, \ 4490 (uint32_t)(__PLL1FRACN__) << \ 4491 RCC_PLL1FRACR_PLL1FRACN_Pos) 4492 4493 /** @brief Macro to select the PLL1 reference frequency range. 4494 * @param __PLL1VCIRange__: specifies the PLL1 input frequency range 4495 * This parameter can be one of the following values: 4496 * @arg RCC_PLLVCIRANGE_0: Range frequency is between 4 and 8 MHz 4497 * @arg RCC_PLLVCIRANGE_1: Range frequency is between 8 and 16 MHz 4498 * @retval None 4499 */ 4500 #define __HAL_RCC_PLL_VCIRANGE(__PLL1VCIRange__) \ 4501 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, (__PLL1VCIRange__)) 4502 4503 /** @brief Macro to get the oscillator used as PLL1 clock source. 4504 * @retval The oscillator used as PLL1 clock source. The returned value can be one 4505 * of the following: 4506 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. 4507 * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. 4508 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. 4509 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. 4510 */ 4511 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC)) 4512 4513 /** 4514 * @brief Macro to configure the system clock source. 4515 * @param __SYSCLKSOURCE__: specifies the system clock source. 4516 * This parameter can be one of the following values: 4517 * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source. 4518 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. 4519 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. 4520 * - RCC_SYSCLKSOURCE_PLL1CLK: PLL1 output is used as system clock source. 4521 * @retval None 4522 */ 4523 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 4524 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, (__SYSCLKSOURCE__)) 4525 4526 /** @brief Macro to get the clock source used as system clock. 4527 * @retval The clock source used as system clock. The returned value can be one 4528 * of the following: 4529 * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock. 4530 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. 4531 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. 4532 * - RCC_SYSCLKSOURCE_STATUS_PLL1CLK: PLL1 used as system clock. 4533 */ 4534 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR1 & RCC_CFGR1_SWS)) 4535 4536 /** 4537 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 4538 * @note As the LSE is in the Backup domain and write access is denied to 4539 * this domain after reset, you have to enable write access using 4540 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 4541 * (to be done once after reset). 4542 * @note The LSE drive can be decreased to the lower drive capability (LSEDRV = 0) 4543 * when the LSE is ON. However, once LSEDRV is selected, the drive 4544 * capability can not be increased if LSEON = 1. 4545 * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. 4546 * This parameter can be one of the following values: 4547 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 4548 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 4549 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 4550 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 4551 * @retval None 4552 */ 4553 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 4554 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) 4555 4556 /** 4557 * @brief Macro to configure the wake up from stop clock. 4558 * @note The selected clock is also used as emergency clock for the clock security system on HSE. 4559 * @param __STOPWUCLK__: specifies the clock source used after wake up from stop. 4560 * This parameter can be one of the following values: 4561 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source and CSS backup clock 4562 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source and CSS backup clock 4563 * @retval None 4564 */ 4565 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ 4566 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, (__STOPWUCLK__)) 4567 4568 /** 4569 * @brief Macro to configure the Kernel wake up from stop clock. 4570 * @param __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop 4571 * This parameter can be one of the following values: 4572 * @arg RCC_STOP_KERWAKEUPCLOCK_MSI: MSI selected as Kernel clock source 4573 * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source 4574 * @retval None 4575 */ 4576 #define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \ 4577 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK, (__RCC_STOPKERWUCLK__)) 4578 4579 /** @brief Macro to configure the MCO clock. 4580 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 4581 * This parameter can be one of the following values: 4582 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled 4583 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source 4584 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source 4585 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source 4586 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source 4587 * @arg @ref RCC_MCO1SOURCE_PLL1CLK Main PLL clock selected as MCO source 4588 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source 4589 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source 4590 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 4591 * @param __MCODIV__ specifies the MCO clock prescaler. 4592 * This parameter can be one of the following values: 4593 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 4594 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 4595 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 4596 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 4597 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 4598 */ 4599 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 4600 MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 4601 4602 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 4603 * @brief macros to manage the specified RCC Flags and interrupts. 4604 * @{ 4605 */ 4606 4607 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable 4608 * the selected interrupts). 4609 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. 4610 * This parameter can be any combination of the following values: 4611 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4612 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4613 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 4614 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4615 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4616 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 4617 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4618 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 4619 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4620 * @retval None 4621 */ 4622 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 4623 4624 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable 4625 * the selected interrupts). 4626 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. 4627 * This parameter can be any combination of the following values: 4628 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4629 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4630 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 4631 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4632 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4633 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 4634 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4635 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 4636 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4637 * @retval None 4638 */ 4639 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 4640 4641 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] 4642 * bits to clear the selected interrupt pending bits. 4643 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 4644 * This parameter can be any combination of the following values: 4645 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4646 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4647 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 4648 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4649 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4650 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 4651 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4652 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 4653 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 4654 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4655 * @arg @ref RCC_IT_MSIKRDY MSIK ready interrupt 4656 * @arg @ref RCC_IT_SHSIRDY SHSI ready interrupt 4657 * @retval None 4658 */ 4659 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) 4660 4661 /** @brief Check whether the RCC interrupt has occurred or not. 4662 * @param __INTERRUPT__: specifies the RCC interrupt source to check. 4663 * This parameter can be one of the following values: 4664 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4665 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4666 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 4667 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4668 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4669 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 4670 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4671 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 4672 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 4673 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4674 * @arg @ref RCC_IT_MSIKRDY MSIK ready interrupt 4675 * @arg @ref RCC_IT_SHSIRDY SHSI ready interrupt 4676 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 4677 */ 4678 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 4679 4680 /** @brief Set RMVF bit to clear the reset flags. 4681 * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, 4682 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 4683 * @retval None 4684 */ 4685 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) 4686 4687 /** @brief Check whether the selected RCC flag is set or not. 4688 * @param __FLAG__: specifies the flag to check. 4689 * This parameter can be one of the following values: 4690 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready 4691 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 4692 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 4693 * @arg @ref RCC_FLAG_PLL1RDY Main PLL1 clock ready 4694 * @arg @ref RCC_FLAG_PLL2RDY PLL2 clock ready 4695 * @arg @ref RCC_FLAG_PLL3RDY PLL3 clock ready 4696 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready 4697 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 4698 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 4699 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 4700 * @arg @ref RCC_FLAG_BORRST BOR reset 4701 * @arg @ref RCC_FLAG_OBLRST OBLRST reset 4702 * @arg @ref RCC_FLAG_PINRST Pin reset 4703 * @arg @ref RCC_FLAG_RMVF Remove reset Flag 4704 * @arg @ref RCC_FLAG_SFTRST Software reset 4705 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 4706 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 4707 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 4708 * @retval The new state of __FLAG__ (TRUE or FALSE). 4709 */ 4710 #define __HAL_RCC_GET_FLAG(__FLAG__) ((((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ 4711 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 4712 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ 4713 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) 4714 /** 4715 * @} 4716 */ 4717 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_MSI) || \ 4718 ((SOURCE) == RCC_PLLSOURCE_HSI) || \ 4719 ((SOURCE) == RCC_PLLSOURCE_HSE)) 4720 4721 #define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 16U)) 4722 #define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 4723 #define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4724 #define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4725 #define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4726 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) ||\ 4727 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 4728 4729 #define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_MSI) || \ 4730 ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI)) 4731 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ 4732 ((__RANGE__) == RCC_MSIRANGE_1) || \ 4733 ((__RANGE__) == RCC_MSIRANGE_2) || \ 4734 ((__RANGE__) == RCC_MSIRANGE_3) || \ 4735 ((__RANGE__) == RCC_MSIRANGE_4) || \ 4736 ((__RANGE__) == RCC_MSIRANGE_5) || \ 4737 ((__RANGE__) == RCC_MSIRANGE_6) || \ 4738 ((__RANGE__) == RCC_MSIRANGE_7) || \ 4739 ((__RANGE__) == RCC_MSIRANGE_8) || \ 4740 ((__RANGE__) == RCC_MSIRANGE_9) || \ 4741 ((__RANGE__) == RCC_MSIRANGE_10) || \ 4742 ((__RANGE__) == RCC_MSIRANGE_11) || \ 4743 ((__RANGE__) == RCC_MSIRANGE_12) || \ 4744 ((__RANGE__) == RCC_MSIRANGE_13) || \ 4745 ((__RANGE__) == RCC_MSIRANGE_14) || \ 4746 ((__RANGE__) == RCC_MSIRANGE_15)) 4747 4748 #define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \ 4749 ((__RANGE__) == RCC_MSIRANGE_5) || \ 4750 ((__RANGE__) == RCC_MSIRANGE_6) || \ 4751 ((__RANGE__) == RCC_MSIRANGE_7) || \ 4752 ((__RANGE__) == RCC_MSIRANGE_8)) 4753 4754 #define IS_RCC_MSIK_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIKRANGE_0) || \ 4755 ((__RANGE__) == RCC_MSIKRANGE_1) || \ 4756 ((__RANGE__) == RCC_MSIKRANGE_2) || \ 4757 ((__RANGE__) == RCC_MSIKRANGE_3) || \ 4758 ((__RANGE__) == RCC_MSIKRANGE_4) || \ 4759 ((__RANGE__) == RCC_MSIKRANGE_5) || \ 4760 ((__RANGE__) == RCC_MSIKRANGE_6) || \ 4761 ((__RANGE__) == RCC_MSIKRANGE_7) || \ 4762 ((__RANGE__) == RCC_MSIKRANGE_8) || \ 4763 ((__RANGE__) == RCC_MSIKRANGE_9) || \ 4764 ((__RANGE__) == RCC_MSIKRANGE_10) || \ 4765 ((__RANGE__) == RCC_MSIKRANGE_11) || \ 4766 ((__RANGE__) == RCC_MSIKRANGE_12) || \ 4767 ((__RANGE__) == RCC_MSIKRANGE_13) || \ 4768 ((__RANGE__) == RCC_MSIKRANGE_14) || \ 4769 ((__RANGE__) == RCC_MSIKRANGE_15)) 4770 4771 #define IS_RCC_MSIK_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIKRANGE_4) || \ 4772 ((__RANGE__) == RCC_MSIKRANGE_5) || \ 4773 ((__RANGE__) == RCC_MSIKRANGE_6) || \ 4774 ((__RANGE__) == RCC_MSIKRANGE_7) || \ 4775 ((__RANGE__) == RCC_MSIKRANGE_8)) 4776 4777 /** 4778 * @} 4779 */ 4780 4781 /* Include RCC HAL Extended module */ 4782 #include "stm32u5xx_hal_rcc_ex.h" 4783 4784 /* Exported functions --------------------------------------------------------*/ 4785 /** @addtogroup RCC_Exported_Functions 4786 * @{ 4787 */ 4788 4789 /** @addtogroup RCC_Exported_Functions_Group1 4790 * @{ 4791 */ 4792 4793 /* Initialization and de-initialization functions ******************************/ 4794 HAL_StatusTypeDef HAL_RCC_DeInit(void); 4795 HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pRCC_OscInitStruct); 4796 HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_ClkInitStruct, uint32_t FLatency); 4797 4798 /** 4799 * @} 4800 */ 4801 4802 /** @addtogroup RCC_Exported_Functions_Group2 4803 * @{ 4804 */ 4805 4806 /* Peripheral Control functions **********************************************/ 4807 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 4808 void HAL_RCC_EnableCSS(void); 4809 uint32_t HAL_RCC_GetSysClockFreq(void); 4810 uint32_t HAL_RCC_GetHCLKFreq(void); 4811 uint32_t HAL_RCC_GetPCLK1Freq(void); 4812 uint32_t HAL_RCC_GetPCLK2Freq(void); 4813 uint32_t HAL_RCC_GetPCLK3Freq(void); 4814 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct); 4815 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *pRCC_ClkInitStruct, uint32_t *pFLatency); 4816 uint32_t HAL_RCC_GetResetSource(void); 4817 /* CSS NMI IRQ handler */ 4818 void HAL_RCC_NMI_IRQHandler(void); 4819 /* User Callbacks in non blocking mode (IT mode) */ 4820 void HAL_RCC_CSSCallback(void); 4821 4822 /** 4823 * @} 4824 */ 4825 4826 /* Attributes management functions ********************************************/ 4827 void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes); 4828 HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 4829 4830 /** 4831 * @} 4832 */ 4833 4834 /** 4835 * @} 4836 */ 4837 /** 4838 * @} 4839 */ 4840 4841 #ifdef __cplusplus 4842 } 4843 #endif 4844 4845 #endif /* STM32U5xx_HAL_RCC_H */ 4846
