Searched refs:XSPI_DCR1_MTYP_2 (Results 1 – 17 of 17) sorted by relevance
334 #define HAL_XSPI_MEMTYPE_HYPERBUS (XSPI_DCR1_MTYP_2) /*!< Hyperbus …335 #define HAL_XSPI_MEMTYPE_APMEM_16BITS ((XSPI_DCR1_MTYP_2 | XSPI_DCR1_MTYP_1)) /*!< AP Memory…
386 #define HAL_XSPI_MEMTYPE_HYPERBUS (XSPI_DCR1_MTYP_2) /*!< Hyperbus …387 #define HAL_XSPI_MEMTYPE_APMEM_16BITS ((XSPI_DCR1_MTYP_2 | XSPI_DCR1_MTYP_1)) /*!< AP Memory…
14395 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04… macro14847 #define OCTOSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04…15261 #define HSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04…
12897 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04… macro13349 #define OCTOSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04…13763 #define HSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04…
13346 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04… macro13798 #define OCTOSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04…14212 #define HSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04…
16616 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04… macro17068 #define OCTOSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04…17482 #define HSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04…
14844 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04… macro15296 #define OCTOSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04…15710 #define HSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04…
17065 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04… macro17517 #define OCTOSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04…17931 #define HSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04…
17521 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04… macro17973 #define OCTOSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04…18387 #define HSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04…
17970 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04… macro18422 #define OCTOSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04…18836 #define HSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04…
11561 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04… macro11979 #define OCTOSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04…
11961 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04… macro12379 #define OCTOSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04…
12584 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04… macro13002 #define OCTOSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04…
13033 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04… macro13451 #define OCTOSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04…
11547 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x040… macro11959 #define OCTOSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04…
13631 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x040… macro14043 #define OCTOSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04…
14066 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x040… macro14478 #define OCTOSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 /*!< 0x04…