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Searched refs:RCC_PLL1DIVR_R1_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-3.6.0/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_rcc.c866 …((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLL… in HAL_RCC_OscConfig()
1702 …RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos)… in HAL_RCC_GetOscConfig()
/hal_stm32-3.6.0/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_rcc.h4551 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) + 1UL); in LL_RCC_PLL1_GetR()
4618 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (R - 1UL) << RCC_PLL1DIVR_R1_Pos); in LL_RCC_PLL1_SetR()
/hal_stm32-3.6.0/stm32cube/stm32h7xx/soc/
Dstm32h7b3xxq.h13501 #define RCC_PLL1DIVR_R1_Pos (24U) macro
13502 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h7b0xxq.h13494 #define RCC_PLL1DIVR_R1_Pos (24U) macro
13495 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h7b0xx.h13482 #define RCC_PLL1DIVR_R1_Pos (24U) macro
13483 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h7a3xx.h13038 #define RCC_PLL1DIVR_R1_Pos (24U) macro
13039 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h7b3xx.h13489 #define RCC_PLL1DIVR_R1_Pos (24U) macro
13490 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h7a3xxq.h13050 #define RCC_PLL1DIVR_R1_Pos (24U) macro
13051 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h730xx.h15329 #define RCC_PLL1DIVR_R1_Pos (24U) macro
15330 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h723xx.h14878 #define RCC_PLL1DIVR_R1_Pos (24U) macro
14879 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h742xx.h14224 #define RCC_PLL1DIVR_R1_Pos (24U) macro
14225 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h733xx.h15329 #define RCC_PLL1DIVR_R1_Pos (24U) macro
15330 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h730xxq.h15341 #define RCC_PLL1DIVR_R1_Pos (24U) macro
15342 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h725xx.h14890 #define RCC_PLL1DIVR_R1_Pos (24U) macro
14891 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h735xx.h15341 #define RCC_PLL1DIVR_R1_Pos (24U) macro
15342 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h755xx.h15699 #define RCC_PLL1DIVR_R1_Pos (24U) macro
15700 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h750xx.h15117 #define RCC_PLL1DIVR_R1_Pos (24U) macro
15118 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h743xx.h14854 #define RCC_PLL1DIVR_R1_Pos (24U) macro
14855 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h753xx.h15123 #define RCC_PLL1DIVR_R1_Pos (24U) macro
15124 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h745xg.h15430 #define RCC_PLL1DIVR_R1_Pos (24U) macro
15431 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h745xx.h15430 #define RCC_PLL1DIVR_R1_Pos (24U) macro
15431 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h747xx.h18587 #define RCC_PLL1DIVR_R1_Pos (24U) macro
18588 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h757xx.h18856 #define RCC_PLL1DIVR_R1_Pos (24U) macro
18857 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
Dstm32h747xg.h18587 #define RCC_PLL1DIVR_R1_Pos (24U) macro
18588 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */