/hal_stm32-3.6.0/stm32cube/stm32h7xx/drivers/src/ |
D | stm32h7xx_hal_rcc.c | 866 …((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLL… in HAL_RCC_OscConfig() 1702 …RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos)… in HAL_RCC_GetOscConfig()
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/hal_stm32-3.6.0/stm32cube/stm32h7xx/drivers/include/ |
D | stm32h7xx_ll_rcc.h | 4551 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) + 1UL); in LL_RCC_PLL1_GetR() 4618 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (R - 1UL) << RCC_PLL1DIVR_R1_Pos); in LL_RCC_PLL1_SetR()
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/hal_stm32-3.6.0/stm32cube/stm32h7xx/soc/ |
D | stm32h7b3xxq.h | 13501 #define RCC_PLL1DIVR_R1_Pos (24U) macro 13502 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
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D | stm32h7b0xxq.h | 13494 #define RCC_PLL1DIVR_R1_Pos (24U) macro 13495 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
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D | stm32h7b0xx.h | 13482 #define RCC_PLL1DIVR_R1_Pos (24U) macro 13483 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
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D | stm32h7a3xx.h | 13038 #define RCC_PLL1DIVR_R1_Pos (24U) macro 13039 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
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D | stm32h7b3xx.h | 13489 #define RCC_PLL1DIVR_R1_Pos (24U) macro 13490 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
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D | stm32h7a3xxq.h | 13050 #define RCC_PLL1DIVR_R1_Pos (24U) macro 13051 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
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D | stm32h730xx.h | 15329 #define RCC_PLL1DIVR_R1_Pos (24U) macro 15330 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
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D | stm32h723xx.h | 14878 #define RCC_PLL1DIVR_R1_Pos (24U) macro 14879 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
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D | stm32h742xx.h | 14224 #define RCC_PLL1DIVR_R1_Pos (24U) macro 14225 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
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D | stm32h733xx.h | 15329 #define RCC_PLL1DIVR_R1_Pos (24U) macro 15330 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
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D | stm32h730xxq.h | 15341 #define RCC_PLL1DIVR_R1_Pos (24U) macro 15342 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
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D | stm32h725xx.h | 14890 #define RCC_PLL1DIVR_R1_Pos (24U) macro 14891 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
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D | stm32h735xx.h | 15341 #define RCC_PLL1DIVR_R1_Pos (24U) macro 15342 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
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D | stm32h755xx.h | 15699 #define RCC_PLL1DIVR_R1_Pos (24U) macro 15700 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
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D | stm32h750xx.h | 15117 #define RCC_PLL1DIVR_R1_Pos (24U) macro 15118 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
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D | stm32h743xx.h | 14854 #define RCC_PLL1DIVR_R1_Pos (24U) macro 14855 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
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D | stm32h753xx.h | 15123 #define RCC_PLL1DIVR_R1_Pos (24U) macro 15124 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
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D | stm32h745xg.h | 15430 #define RCC_PLL1DIVR_R1_Pos (24U) macro 15431 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
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D | stm32h745xx.h | 15430 #define RCC_PLL1DIVR_R1_Pos (24U) macro 15431 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
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D | stm32h747xx.h | 18587 #define RCC_PLL1DIVR_R1_Pos (24U) macro 18588 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
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D | stm32h757xx.h | 18856 #define RCC_PLL1DIVR_R1_Pos (24U) macro 18857 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
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D | stm32h747xg.h | 18587 #define RCC_PLL1DIVR_R1_Pos (24U) macro 18588 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
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