1 /** 2 ****************************************************************************** 3 * @file stm32wlxx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2020 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WLxx_HAL_RCC_H 21 #define STM32WLxx_HAL_RCC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wlxx_hal_def.h" 29 #include "stm32wlxx_ll_rcc.h" 30 #include "stm32wlxx_ll_bus.h" 31 32 33 /** @addtogroup STM32WLxx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup RCC 38 * @{ 39 */ 40 41 /* Private constants ---------------------------------------------------------*/ 42 /** @addtogroup RCC_Private_Constants 43 * @{ 44 */ 45 /* Defines used for Flags */ 46 #define CR_REG_INDEX 1U 47 #define BDCR_REG_INDEX 2U 48 #define CSR_REG_INDEX 3U 49 #define REG_INDEX_POS 5U 50 51 #define RCC_FLAG_MASK 0x1FU 52 53 /* Defines Oscillator Masks */ 54 #define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \ 55 RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE) /*!< All Oscillator to configure */ 56 57 /** @defgroup RCC_Timeout_Value Timeout Values 58 * @{ 59 */ 60 #define RCC_DBP_TIMEOUT_VALUE 2U /*!< 2 ms (minimum Tick + 1) */ 61 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /*!< LSE timeout in ms */ 62 #define PLL_TIMEOUT_VALUE 10U /*!< 10 ms (minimum Tick + 1) */ 63 /** 64 * @} 65 */ 66 67 /** @defgroup RCC_Reset_Flag Reset Flag 68 * @{ 69 */ 70 #define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */ 71 #define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */ 72 #define RCC_RESET_FLAG_PWR RCC_CSR_BORRSTF /*!< BOR or POR/PDR reset flag */ 73 #define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */ 74 #define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 75 #define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ 76 #define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */ 77 #define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ 78 RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \ 79 RCC_RESET_FLAG_LPWR) 80 /** 81 * @} 82 */ 83 84 /** 85 * @} 86 */ 87 88 /* Private macros ------------------------------------------------------------*/ 89 /** @addtogroup RCC_Private_Macros 90 * @{ 91 */ 92 93 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 94 (((__OSCILLATOR__) & ~RCC_OSCILLATORTYPE_ALL) == 0x00U)) 95 96 97 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 98 ((__HSE__) == RCC_HSE_BYPASS_PWR)) 99 100 #define IS_RCC_HSEDIV(__HSEDIV__) (((__HSEDIV__) == RCC_HSE_DIV1) || ((__HSEDIV__) == RCC_HSE_DIV2)) 101 102 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || \ 103 ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || \ 104 ((__LSE__) == RCC_LSE_BYPASS) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY)) 105 106 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 107 108 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)127U) 109 110 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 111 112 #define IS_RCC_LSIDIV(__LSIDIV__) (((__LSIDIV__) == RCC_LSI_DIV1) || ((__LSIDIV__) == RCC_LSI_DIV128)) 113 114 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) 115 116 #define IS_RCC_MSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U) 117 118 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ 119 ((__PLL__) == RCC_PLL_ON)) 120 121 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_MSI) || \ 122 ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ 123 ((__SOURCE__) == RCC_PLLSOURCE_HSE)) 124 125 #define IS_RCC_PLLM_VALUE(__VALUE__) (((__VALUE__) == RCC_PLLM_DIV1) || \ 126 ((__VALUE__) == RCC_PLLM_DIV2) || \ 127 ((__VALUE__) == RCC_PLLM_DIV3) || \ 128 ((__VALUE__) == RCC_PLLM_DIV4) || \ 129 ((__VALUE__) == RCC_PLLM_DIV5) || \ 130 ((__VALUE__) == RCC_PLLM_DIV6) || \ 131 ((__VALUE__) == RCC_PLLM_DIV7) || \ 132 ((__VALUE__) == RCC_PLLM_DIV8)) 133 134 #define IS_RCC_PLLN_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U)) 135 136 #define IS_RCC_PLLP_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32)) 137 138 #define IS_RCC_PLLQ_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8)) 139 140 #define IS_RCC_PLLR_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8)) 141 142 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ 143 ((__RANGE__) == RCC_MSIRANGE_1) || \ 144 ((__RANGE__) == RCC_MSIRANGE_2) || \ 145 ((__RANGE__) == RCC_MSIRANGE_3) || \ 146 ((__RANGE__) == RCC_MSIRANGE_4) || \ 147 ((__RANGE__) == RCC_MSIRANGE_5) || \ 148 ((__RANGE__) == RCC_MSIRANGE_6) || \ 149 ((__RANGE__) == RCC_MSIRANGE_7) || \ 150 ((__RANGE__) == RCC_MSIRANGE_8) || \ 151 ((__RANGE__) == RCC_MSIRANGE_9) || \ 152 ((__RANGE__) == RCC_MSIRANGE_10) || \ 153 ((__RANGE__) == RCC_MSIRANGE_11)) 154 155 #if defined(DUAL_CORE) 156 #define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= (RCC_CLOCKTYPE_SYSCLK | \ 157 RCC_CLOCKTYPE_HCLK | \ 158 RCC_CLOCKTYPE_PCLK1 | \ 159 RCC_CLOCKTYPE_PCLK2 | \ 160 RCC_CLOCKTYPE_HCLK2 | \ 161 RCC_CLOCKTYPE_HCLK3))) 162 #else 163 #define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= (RCC_CLOCKTYPE_SYSCLK | \ 164 RCC_CLOCKTYPE_HCLK | \ 165 RCC_CLOCKTYPE_PCLK1 | \ 166 RCC_CLOCKTYPE_PCLK2 | \ 167 RCC_CLOCKTYPE_HCLK3))) 168 #endif /* DUAL_CORE */ 169 170 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ 171 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 172 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 173 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 174 175 #define IS_RCC_HCLKx(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 176 ((__HCLK__) == RCC_SYSCLK_DIV3) || ((__HCLK__) == RCC_SYSCLK_DIV4) || \ 177 ((__HCLK__) == RCC_SYSCLK_DIV5) || ((__HCLK__) == RCC_SYSCLK_DIV6) || \ 178 ((__HCLK__) == RCC_SYSCLK_DIV8) || ((__HCLK__) == RCC_SYSCLK_DIV10) || \ 179 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV32) || \ 180 ((__HCLK__) == RCC_SYSCLK_DIV64) || ((__HCLK__) == RCC_SYSCLK_DIV128) || \ 181 ((__HCLK__) == RCC_SYSCLK_DIV256) || ((__HCLK__) == RCC_SYSCLK_DIV512)) 182 183 #define IS_RCC_PCLKx(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 184 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 185 ((__PCLK__) == RCC_HCLK_DIV16)) 186 187 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ 188 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 189 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 190 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) 191 192 #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1_PA8) 193 194 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 195 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 196 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 197 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 198 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 199 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 200 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 201 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ 202 ((__SOURCE__) == RCC_MCO1SOURCE_PLLPCLK) || \ 203 ((__SOURCE__) == RCC_MCO1SOURCE_PLLQCLK)) 204 205 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ 206 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ 207 ((__DIV__) == RCC_MCODIV_16)) 208 209 210 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \ 211 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 212 /** 213 * @} 214 */ 215 216 /* Exported types ------------------------------------------------------------*/ 217 /** @defgroup RCC_Exported_Types RCC Exported Types 218 * @{ 219 */ 220 221 222 /** 223 * @brief RCC PLL configuration structure definition 224 */ 225 typedef struct 226 { 227 uint32_t PLLState; /*!< The new state of the PLL. 228 This parameter must be a value of @ref RCC_PLL_Config */ 229 230 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 231 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 232 233 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 234 This parameter must be a value of @ref RCC_PLLM_Clock_Divider */ 235 236 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 237 This parameter must be a number between Min_Data = 6 and Max_Data = 127 */ 238 239 uint32_t PLLP; /*!< PLLP: Division factor for ADC clock. 240 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 241 242 uint32_t PLLQ; /*!< PLLQ: Division factor for I2S2 and RNG clock. 243 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 244 245 uint32_t PLLR; /*!< PLLR: Division for the main system clock. 246 User has to set the PLLR parameter correctly to not exceed max frequency 48 MHZ. 247 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 248 249 } RCC_PLLInitTypeDef; 250 251 /** 252 * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition 253 */ 254 typedef struct 255 { 256 uint32_t OscillatorType; /*!< The oscillators to be configured. 257 This parameter can be a combination of @ref RCC_Oscillator_Type */ 258 259 uint32_t HSEState; /*!< The new state of the HSE. 260 This parameter can be a value of @ref RCC_HSE_Config */ 261 262 uint32_t HSEDiv; /*!< The division factor of the HSE. 263 This parameter can be a value of @ref RCC_HSE_Div */ 264 265 uint32_t LSEState; /*!< The new state of the LSE. 266 This parameter can be a value of @ref RCC_LSE_Config */ 267 268 uint32_t HSIState; /*!< The new state of the HSI. 269 This parameter can be a value of @ref RCC_HSI_Config */ 270 271 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is @ref RCC_HSICALIBRATION_DEFAULT). 272 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ 273 274 uint32_t LSIState; /*!< The new state of the LSI. 275 This parameter can be a value of @ref RCC_LSI_Config */ 276 277 uint32_t LSIDiv; /*!< The division factor of the LSI. 278 This parameter can be a value of @ref RCC_LSI_Div */ 279 280 uint32_t MSIState; /*!< The new state of the MSI. 281 This parameter can be a value of @ref RCC_MSI_Config */ 282 283 uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is @ref RCC_MSICALIBRATION_DEFAULT). 284 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 285 286 uint32_t MSIClockRange; /*!< The MSI frequency range. 287 This parameter can be a value of @ref RCC_MSI_Clock_Range */ 288 289 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ 290 291 } RCC_OscInitTypeDef; 292 293 /** 294 * @brief RCC System, AHB and APB buses clock configuration structure definition 295 */ 296 typedef struct 297 { 298 uint32_t ClockType; /*!< The clock to be configured. 299 This parameter can be a combination of @ref RCC_System_Clock_Type */ 300 301 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 302 This parameter can be a value of @ref RCC_System_Clock_Source */ 303 304 uint32_t AHBCLKDivider; /*!< The AHBx clock (HCLK1) divider. This clock is derived from the system clock (SYSCLK). 305 This parameter can be a value of @ref RCC_AHBx_Clock_Source */ 306 307 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 308 This parameter can be a value of @ref RCC_APBx_Clock_Source */ 309 310 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 311 This parameter can be a value of @ref RCC_APBx_Clock_Source */ 312 313 #if defined(DUAL_CORE) 314 uint32_t AHBCLK2Divider; /*!< The AHB clock (HCLK2) divider. This clock is derived from the system clock (SYSCLK). 315 This parameter can be a value of @ref RCC_AHBx_Clock_Source */ 316 317 #endif /* DUAL_CORE */ 318 uint32_t AHBCLK3Divider; /*!< The AHB shared clock (HCLK3) divider. This clock is derived from the system clock (SYSCLK). 319 This parameter can be a value of @ref RCC_AHBx_Clock_Source */ 320 321 } RCC_ClkInitTypeDef; 322 323 /** 324 * @} 325 */ 326 327 /* Exported constants --------------------------------------------------------*/ 328 /** @defgroup RCC_Exported_Constants RCC Exported Constants 329 * @{ 330 */ 331 332 /** @defgroup RCC_Oscillator_Type Oscillator Type 333 * @{ 334 */ 335 #define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ 336 #define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ 337 #define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ 338 #define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ 339 #define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ 340 #define RCC_OSCILLATORTYPE_MSI 0x00000020U /*!< MSI to configure */ 341 /** 342 * @} 343 */ 344 345 /** @defgroup RCC_HSE_Config HSE Config 346 * @{ 347 */ 348 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ 349 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 350 #define RCC_HSE_BYPASS_PWR ((uint32_t)(RCC_CR_HSEBYPPWR | RCC_CR_HSEON)) /*!< TCXO external clock source for HSE clock */ 351 /** 352 * @} 353 */ 354 355 /** @defgroup RCC_HSE_Div HSE Div 356 * @{ 357 */ 358 #define RCC_HSE_DIV1 0x00000000U /*!< HSE clock not divided */ 359 #define RCC_HSE_DIV2 RCC_CR_HSEPRE /*!< HSE clock divided by 2 */ 360 /** 361 * @} 362 */ 363 364 /** @defgroup RCC_LSE_Config LSE Config 365 * @{ 366 */ 367 #define RCC_LSE_OFF 0U /*!< LSE clock deactivation */ 368 #define RCC_LSE_ON_RTC_ONLY RCC_BDCR_LSEON /*!< LSE clock activation for RTC only */ 369 #define RCC_LSE_ON ((uint32_t)(RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON)) /*!< LSE clock activation for RTC and other peripherals */ 370 #define RCC_LSE_BYPASS_RTC_ONLY ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ 371 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ 372 373 /** 374 * @} 375 */ 376 377 /** @defgroup RCC_HSI_Config HSI Config 378 * @{ 379 */ 380 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 381 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 382 383 #define RCC_HSICALIBRATION_DEFAULT 64U /*!< Default HSI calibration trimming value */ 384 /** 385 * @} 386 */ 387 388 /** @defgroup RCC_LSI_Config LSI Config 389 * @{ 390 */ 391 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ 392 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ 393 /** 394 * @} 395 */ 396 397 /** @defgroup RCC_LSI_Div LSI Div 398 * @{ 399 */ 400 #define RCC_LSI_DIV1 LL_RCC_LSI_PREDIV_1 /*!< LSI clock not divided */ 401 #define RCC_LSI_DIV128 LL_RCC_LSI_PREDIV_128 /*!< LSI clock divided by 128 */ 402 /** 403 * @} 404 */ 405 406 /** @defgroup RCC_MSI_Config MSI Config 407 * @{ 408 */ 409 #define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */ 410 #define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ 411 412 #define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */ 413 /** 414 * @} 415 */ 416 417 418 /** @defgroup RCC_PLL_Config PLL Config 419 * @{ 420 */ 421 #define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */ 422 #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ 423 #define RCC_PLL_ON 0x00000002U /*!< PLL activation */ 424 /** 425 * @} 426 */ 427 428 /** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider 429 * @{ 430 */ 431 #define RCC_PLLM_DIV1 LL_RCC_PLLM_DIV_1 /*!< PLLM division factor = 1 */ 432 #define RCC_PLLM_DIV2 LL_RCC_PLLM_DIV_2 /*!< PLLM division factor = 2 */ 433 #define RCC_PLLM_DIV3 LL_RCC_PLLM_DIV_3 /*!< PLLM division factor = 3 */ 434 #define RCC_PLLM_DIV4 LL_RCC_PLLM_DIV_4 /*!< PLLM division factor = 4 */ 435 #define RCC_PLLM_DIV5 LL_RCC_PLLM_DIV_5 /*!< PLLM division factor = 5 */ 436 #define RCC_PLLM_DIV6 LL_RCC_PLLM_DIV_6 /*!< PLLM division factor = 6 */ 437 #define RCC_PLLM_DIV7 LL_RCC_PLLM_DIV_7 /*!< PLLM division factor = 7 */ 438 #define RCC_PLLM_DIV8 LL_RCC_PLLM_DIV_8 /*!< PLLM division factor = 8 */ 439 /** 440 * @} 441 */ 442 443 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider 444 * @{ 445 */ 446 #define RCC_PLLP_DIV2 LL_RCC_PLLP_DIV_2 /*!< PLLP division factor = 2 */ 447 #define RCC_PLLP_DIV3 LL_RCC_PLLP_DIV_3 /*!< PLLP division factor = 3 */ 448 #define RCC_PLLP_DIV4 LL_RCC_PLLP_DIV_4 /*!< PLLP division factor = 4 */ 449 #define RCC_PLLP_DIV5 LL_RCC_PLLP_DIV_5 /*!< PLLP division factor = 5 */ 450 #define RCC_PLLP_DIV6 LL_RCC_PLLP_DIV_6 /*!< PLLP division factor = 6 */ 451 #define RCC_PLLP_DIV7 LL_RCC_PLLP_DIV_7 /*!< PLLP division factor = 7 */ 452 #define RCC_PLLP_DIV8 LL_RCC_PLLP_DIV_8 /*!< PLLP division factor = 8 */ 453 #define RCC_PLLP_DIV9 LL_RCC_PLLP_DIV_9 /*!< PLLP division factor = 9 */ 454 #define RCC_PLLP_DIV10 LL_RCC_PLLP_DIV_10 /*!< PLLP division factor = 10 */ 455 #define RCC_PLLP_DIV11 LL_RCC_PLLP_DIV_11 /*!< PLLP division factor = 11 */ 456 #define RCC_PLLP_DIV12 LL_RCC_PLLP_DIV_12 /*!< PLLP division factor = 12 */ 457 #define RCC_PLLP_DIV13 LL_RCC_PLLP_DIV_13 /*!< PLLP division factor = 13 */ 458 #define RCC_PLLP_DIV14 LL_RCC_PLLP_DIV_14 /*!< PLLP division factor = 14 */ 459 #define RCC_PLLP_DIV15 LL_RCC_PLLP_DIV_15 /*!< PLLP division factor = 15 */ 460 #define RCC_PLLP_DIV16 LL_RCC_PLLP_DIV_16 /*!< PLLP division factor = 16 */ 461 #define RCC_PLLP_DIV17 LL_RCC_PLLP_DIV_17 /*!< PLLP division factor = 17 */ 462 #define RCC_PLLP_DIV18 LL_RCC_PLLP_DIV_18 /*!< PLLP division factor = 18 */ 463 #define RCC_PLLP_DIV19 LL_RCC_PLLP_DIV_19 /*!< PLLP division factor = 19 */ 464 #define RCC_PLLP_DIV20 LL_RCC_PLLP_DIV_20 /*!< PLLP division factor = 20 */ 465 #define RCC_PLLP_DIV21 LL_RCC_PLLP_DIV_21 /*!< PLLP division factor = 21 */ 466 #define RCC_PLLP_DIV22 LL_RCC_PLLP_DIV_22 /*!< PLLP division factor = 22 */ 467 #define RCC_PLLP_DIV23 LL_RCC_PLLP_DIV_23 /*!< PLLP division factor = 23 */ 468 #define RCC_PLLP_DIV24 LL_RCC_PLLP_DIV_24 /*!< PLLP division factor = 24 */ 469 #define RCC_PLLP_DIV25 LL_RCC_PLLP_DIV_25 /*!< PLLP division factor = 25 */ 470 #define RCC_PLLP_DIV26 LL_RCC_PLLP_DIV_26 /*!< PLLP division factor = 26 */ 471 #define RCC_PLLP_DIV27 LL_RCC_PLLP_DIV_27 /*!< PLLP division factor = 27 */ 472 #define RCC_PLLP_DIV28 LL_RCC_PLLP_DIV_28 /*!< PLLP division factor = 28 */ 473 #define RCC_PLLP_DIV29 LL_RCC_PLLP_DIV_29 /*!< PLLP division factor = 29 */ 474 #define RCC_PLLP_DIV30 LL_RCC_PLLP_DIV_30 /*!< PLLP division factor = 30 */ 475 #define RCC_PLLP_DIV31 LL_RCC_PLLP_DIV_31 /*!< PLLP division factor = 31 */ 476 #define RCC_PLLP_DIV32 LL_RCC_PLLP_DIV_32 /*!< PLLP division factor = 32 */ 477 /** 478 * @} 479 */ 480 481 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider 482 * @{ 483 */ 484 #define RCC_PLLQ_DIV2 LL_RCC_PLLQ_DIV_2 /*!< PLLQ division factor = 2 */ 485 #define RCC_PLLQ_DIV3 LL_RCC_PLLQ_DIV_3 /*!< PLLQ division factor = 3 */ 486 #define RCC_PLLQ_DIV4 LL_RCC_PLLQ_DIV_4 /*!< PLLQ division factor = 4 */ 487 #define RCC_PLLQ_DIV5 LL_RCC_PLLQ_DIV_5 /*!< PLLQ division factor = 5 */ 488 #define RCC_PLLQ_DIV6 LL_RCC_PLLQ_DIV_6 /*!< PLLQ division factor = 6 */ 489 #define RCC_PLLQ_DIV7 LL_RCC_PLLQ_DIV_7 /*!< PLLQ division factor = 7 */ 490 #define RCC_PLLQ_DIV8 LL_RCC_PLLQ_DIV_8 /*!< PLLQ division factor = 8 */ 491 /** 492 * @} 493 */ 494 495 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider 496 * @{ 497 */ 498 #define RCC_PLLR_DIV2 LL_RCC_PLLR_DIV_2 /*!< PLLR division factor = 2 */ 499 #define RCC_PLLR_DIV3 LL_RCC_PLLR_DIV_3 /*!< PLLR division factor = 3 */ 500 #define RCC_PLLR_DIV4 LL_RCC_PLLR_DIV_4 /*!< PLLR division factor = 4 */ 501 #define RCC_PLLR_DIV5 LL_RCC_PLLR_DIV_5 /*!< PLLR division factor = 5 */ 502 #define RCC_PLLR_DIV6 LL_RCC_PLLR_DIV_6 /*!< PLLR division factor = 6 */ 503 #define RCC_PLLR_DIV7 LL_RCC_PLLR_DIV_7 /*!< PLLR division factor = 7 */ 504 #define RCC_PLLR_DIV8 LL_RCC_PLLR_DIV_8 /*!< PLLR division factor = 8 */ 505 /** 506 * @} 507 */ 508 509 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 510 * @{ 511 */ 512 #define RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_NONE /*!< No clock selected as PLL entry clock source */ 513 #define RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_MSI /*!< MSI clock selected as PLL entry clock source */ 514 #define RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSI /*!< HSI clock selected as PLL entry clock source */ 515 #define RCC_PLLSOURCE_HSE LL_RCC_PLLSOURCE_HSE /*!< HSE clock selected as PLL entry clock source */ 516 /** 517 * @} 518 */ 519 520 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output 521 * @{ 522 */ 523 #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selected from main PLL */ 524 #define RCC_PLL_I2S2CLK RCC_PLLCFGR_PLLQEN /*!< PLLI2S2CLK selected from main PLL */ 525 #define RCC_PLL_RNGCLK RCC_PLLCFGR_PLLQEN /*!< PLLRNGCLK selected from main PLL */ 526 #define RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN /*!< PLLADCCLK selected from main PLL */ 527 /** 528 * @} 529 */ 530 531 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range 532 * @{ 533 */ 534 #define RCC_MSIRANGE_0 LL_RCC_MSIRANGE_0 /*!< MSI = 100 KHz */ 535 #define RCC_MSIRANGE_1 LL_RCC_MSIRANGE_1 /*!< MSI = 200 KHz */ 536 #define RCC_MSIRANGE_2 LL_RCC_MSIRANGE_2 /*!< MSI = 400 KHz */ 537 #define RCC_MSIRANGE_3 LL_RCC_MSIRANGE_3 /*!< MSI = 800 KHz */ 538 #define RCC_MSIRANGE_4 LL_RCC_MSIRANGE_4 /*!< MSI = 1 MHz */ 539 #define RCC_MSIRANGE_5 LL_RCC_MSIRANGE_5 /*!< MSI = 2 MHz */ 540 #define RCC_MSIRANGE_6 LL_RCC_MSIRANGE_6 /*!< MSI = 4 MHz */ 541 #define RCC_MSIRANGE_7 LL_RCC_MSIRANGE_7 /*!< MSI = 8 MHz */ 542 #define RCC_MSIRANGE_8 LL_RCC_MSIRANGE_8 /*!< MSI = 16 MHz */ 543 #define RCC_MSIRANGE_9 LL_RCC_MSIRANGE_9 /*!< MSI = 24 MHz */ 544 #define RCC_MSIRANGE_10 LL_RCC_MSIRANGE_10 /*!< MSI = 32 MHz */ 545 #define RCC_MSIRANGE_11 LL_RCC_MSIRANGE_11 /*!< MSI = 48 MHz */ 546 /** 547 * @} 548 */ 549 550 /** @defgroup RCC_System_Clock_Type System Clock Type 551 * @{ 552 */ 553 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 554 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 555 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 556 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ 557 #if defined(DUAL_CORE) 558 #define RCC_CLOCKTYPE_HCLK2 0x00000020U /*!< HCLK2 to configure */ 559 #endif /* DUAL_CORE */ 560 #define RCC_CLOCKTYPE_HCLK3 0x00000040U /*!< HCLK3 to configure */ 561 /** 562 * @} 563 */ 564 565 /** @defgroup RCC_System_Clock_Source System Clock Source 566 * @{ 567 */ 568 #define RCC_SYSCLKSOURCE_MSI LL_RCC_SYS_CLKSOURCE_MSI /*!< MSI selected as system clock */ 569 #define RCC_SYSCLKSOURCE_HSI LL_RCC_SYS_CLKSOURCE_HSI /*!< HSI selected as system clock */ 570 #define RCC_SYSCLKSOURCE_HSE LL_RCC_SYS_CLKSOURCE_HSE /*!< HSE selected as system clock */ 571 #define RCC_SYSCLKSOURCE_PLLCLK LL_RCC_SYS_CLKSOURCE_PLL /*!< PLL selected as system clock */ 572 /** 573 * @} 574 */ 575 576 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 577 * @{ 578 */ 579 #define RCC_SYSCLKSOURCE_STATUS_MSI LL_RCC_SYS_CLKSOURCE_STATUS_MSI /*!< MSI used as system clock */ 580 #define RCC_SYSCLKSOURCE_STATUS_HSI LL_RCC_SYS_CLKSOURCE_STATUS_HSI /*!< HSI used as system clock */ 581 #define RCC_SYSCLKSOURCE_STATUS_HSE LL_RCC_SYS_CLKSOURCE_STATUS_HSE /*!< HSE used as system clock */ 582 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK LL_RCC_SYS_CLKSOURCE_STATUS_PLL /*!< PLL used as system clock */ 583 /** 584 * @} 585 */ 586 587 /** @defgroup RCC_AHBx_Clock_Source AHB Clock Source 588 * @{ 589 */ 590 #define RCC_SYSCLK_DIV1 LL_RCC_SYSCLK_DIV_1 /*!< SYSCLK not divided */ 591 #define RCC_SYSCLK_DIV2 LL_RCC_SYSCLK_DIV_2 /*!< SYSCLK divided by 2 */ 592 #define RCC_SYSCLK_DIV3 LL_RCC_SYSCLK_DIV_3 /*!< SYSCLK divided by 3 */ 593 #define RCC_SYSCLK_DIV4 LL_RCC_SYSCLK_DIV_4 /*!< SYSCLK divided by 4 */ 594 #define RCC_SYSCLK_DIV5 LL_RCC_SYSCLK_DIV_5 /*!< SYSCLK divided by 5 */ 595 #define RCC_SYSCLK_DIV6 LL_RCC_SYSCLK_DIV_6 /*!< SYSCLK divided by 6 */ 596 #define RCC_SYSCLK_DIV8 LL_RCC_SYSCLK_DIV_8 /*!< SYSCLK divided by 8 */ 597 #define RCC_SYSCLK_DIV10 LL_RCC_SYSCLK_DIV_10 /*!< SYSCLK divided by 10 */ 598 #define RCC_SYSCLK_DIV16 LL_RCC_SYSCLK_DIV_16 /*!< SYSCLK divided by 16 */ 599 #define RCC_SYSCLK_DIV32 LL_RCC_SYSCLK_DIV_32 /*!< SYSCLK divided by 32 */ 600 #define RCC_SYSCLK_DIV64 LL_RCC_SYSCLK_DIV_64 /*!< SYSCLK divided by 64 */ 601 #define RCC_SYSCLK_DIV128 LL_RCC_SYSCLK_DIV_128 /*!< SYSCLK divided by 128 */ 602 #define RCC_SYSCLK_DIV256 LL_RCC_SYSCLK_DIV_256 /*!< SYSCLK divided by 256 */ 603 #define RCC_SYSCLK_DIV512 LL_RCC_SYSCLK_DIV_512 /*!< SYSCLK divided by 512 */ 604 /** 605 * @} 606 */ 607 608 /** @defgroup RCC_APBx_Clock_Source APB1 Clock Source 609 * @{ 610 */ 611 #define RCC_HCLK_DIV1 LL_RCC_APB1_DIV_1 /*!< HCLK not divided */ 612 #define RCC_HCLK_DIV2 LL_RCC_APB1_DIV_2 /*!< HCLK divided by 2 */ 613 #define RCC_HCLK_DIV4 LL_RCC_APB1_DIV_4 /*!< HCLK divided by 4 */ 614 #define RCC_HCLK_DIV8 LL_RCC_APB1_DIV_8 /*!< HCLK divided by 8 */ 615 #define RCC_HCLK_DIV16 LL_RCC_APB1_DIV_16 /*!< HCLK divided by 16 */ 616 /** 617 * @} 618 */ 619 620 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 621 * @{ 622 */ 623 #define RCC_RTCCLKSOURCE_NONE LL_RCC_RTC_CLKSOURCE_NONE /*!< No clock used as RTC clock */ 624 #define RCC_RTCCLKSOURCE_LSE LL_RCC_RTC_CLKSOURCE_LSE /*!< LSE oscillator clock used as RTC clock */ 625 #define RCC_RTCCLKSOURCE_LSI LL_RCC_RTC_CLKSOURCE_LSI /*!< LSI oscillator clock used as RTC clock */ 626 #define RCC_RTCCLKSOURCE_HSE_DIV32 LL_RCC_RTC_CLKSOURCE_HSE_DIV32 /*!< HSE oscillator clock divided by 32 used as RTC clock */ 627 /** 628 * @} 629 */ 630 631 /** @defgroup RCC_MCO_Index MCO Index 632 * @{ 633 */ 634 635 /* @cond */ 636 /* 32 28 20 16 0 637 -------------------------------- 638 | MCO | GPIO | GPIO | GPIO | 639 | Index | AF | Port | Pin | 640 -------------------------------*/ 641 642 #define RCC_MCO_GPIOPORT_POS 16U 643 #define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS) 644 #define RCC_MCO_GPIOAF_POS 20U 645 #define RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS) 646 #define RCC_MCO_INDEX_POS 28U 647 #define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS) 648 649 #define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */ 650 /* @endcond */ 651 652 #define RCC_MCO1_PA8 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \ 653 (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) 654 #define RCC_MCO1 RCC_MCO1_PA8 655 656 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 1 MCO */ 657 /** 658 * @} 659 */ 660 661 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 662 * @{ 663 */ 664 #define RCC_MCO1SOURCE_NOCLOCK LL_RCC_MCO1SOURCE_NOCLOCK /*!< MCO1 output disabled, no clock on MCO1 */ 665 #define RCC_MCO1SOURCE_SYSCLK LL_RCC_MCO1SOURCE_SYSCLK /*!< SYSCLK selected as MCO1 source */ 666 #define RCC_MCO1SOURCE_MSI LL_RCC_MCO1SOURCE_MSI /*!< MSI selected as MCO1 source */ 667 #define RCC_MCO1SOURCE_HSI LL_RCC_MCO1SOURCE_HSI /*!< HSI selected as MCO1 source */ 668 #define RCC_MCO1SOURCE_HSE LL_RCC_MCO1SOURCE_HSE /*!< HSE after stabilization selected as MCO1 source */ 669 #define RCC_MCO1SOURCE_PLLCLK LL_RCC_MCO1SOURCE_PLLCLK /*!< Main PLLRCLK selected as MCO1 source */ 670 #define RCC_MCO1SOURCE_LSI LL_RCC_MCO1SOURCE_LSI /*!< LSI selected as MCO1 source */ 671 #define RCC_MCO1SOURCE_LSE LL_RCC_MCO1SOURCE_LSE /*!< LSE selected as MCO1 source */ 672 #define RCC_MCO1SOURCE_PLLPCLK LL_RCC_MCO1SOURCE_PLLPCLK /*!< Main PLLPCLK selected as MCO1 source */ 673 #define RCC_MCO1SOURCE_PLLQCLK LL_RCC_MCO1SOURCE_PLLQCLK /*!< Main PLLQCLK selected as MCO1 source */ 674 /** 675 * @} 676 */ 677 678 /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler 679 * @{ 680 */ 681 #define RCC_MCODIV_1 LL_RCC_MCO1_DIV_1 /*!< MCO not divided */ 682 #define RCC_MCODIV_2 LL_RCC_MCO1_DIV_2 /*!< MCO divided by 2 */ 683 #define RCC_MCODIV_4 LL_RCC_MCO1_DIV_4 /*!< MCO divided by 4 */ 684 #define RCC_MCODIV_8 LL_RCC_MCO1_DIV_8 /*!< MCO divided by 8 */ 685 #define RCC_MCODIV_16 LL_RCC_MCO1_DIV_16 /*!< MCO divided by 16 */ 686 /** 687 * @} 688 */ 689 690 691 /** @defgroup RCC_Interrupt Interrupts 692 * @{ 693 */ 694 #define RCC_IT_LSIRDY LL_RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 695 #define RCC_IT_LSERDY LL_RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 696 #define RCC_IT_MSIRDY LL_RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ 697 #define RCC_IT_HSIRDY LL_RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ 698 #define RCC_IT_HSERDY LL_RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 699 #define RCC_IT_PLLRDY LL_RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ 700 #define RCC_IT_HSECSS LL_RCC_CIFR_CSSF /*!< HSE Clock Security System Interrupt flag */ 701 #define RCC_IT_LSECSS LL_RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ 702 /** 703 * @} 704 */ 705 706 707 /** @defgroup RCC_Flag Flags 708 * Elements values convention: XXXYYYYYb 709 * - YYYYY : Flag position in the register 710 * - XXX : Register index 711 * - 001: CR register 712 * - 010: BDCR register 713 * - 011: CSR register 714 * @{ 715 */ 716 /* Flags in the CR register */ 717 #define RCC_FLAG_MSIRDY ((CR_REG_INDEX << REG_INDEX_POS) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */ 718 #define RCC_FLAG_HSIRDY ((CR_REG_INDEX << REG_INDEX_POS) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ 719 #define RCC_FLAG_HSIKERDY ((CR_REG_INDEX << REG_INDEX_POS) | RCC_CR_HSIKERDY_Pos) /*!< HSI Ready flag */ 720 #define RCC_FLAG_HSERDY ((CR_REG_INDEX << REG_INDEX_POS) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ 721 #define RCC_FLAG_PLLRDY ((CR_REG_INDEX << REG_INDEX_POS) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ 722 723 /* Flags in the BDCR register */ 724 #define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << REG_INDEX_POS) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ 725 #define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << REG_INDEX_POS) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System failure detection flag */ 726 #define RCC_FLAG_LSESYSRDY ((BDCR_REG_INDEX << REG_INDEX_POS) | RCC_BDCR_LSESYSRDY_Pos) /*!< LSE system clock ready flag */ 727 728 /* Flags in the CSR register */ 729 #define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ 730 #define RCC_FLAG_RFRST ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_RFRSTF_Pos) /*!< Sub-GHz radio reset flag */ 731 #define RCC_FLAG_RFILARSTF ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_RFILARSTF_Pos) /*!< Sub-GHz radio illegal command flag */ 732 #define RCC_FLAG_OBLRST ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ 733 #define RCC_FLAG_PINRST ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_PINRSTF_Pos) /*!< Pin reset flag (NRST pin) */ 734 #define RCC_FLAG_BORRST ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ 735 #define RCC_FLAG_SFTRST ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ 736 #define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_IWDGRSTF_Pos) /*!< Watchdog reset flag */ 737 #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ 738 #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ 739 /** 740 * @} 741 */ 742 743 /** @defgroup RCC_LSEDrive_Config LSE Drive Configuration 744 * @{ 745 */ 746 #define RCC_LSEDRIVE_LOW LL_RCC_LSEDRIVE_LOW /*!< LSE low drive capability */ 747 #define RCC_LSEDRIVE_MEDIUMLOW LL_RCC_LSEDRIVE_MEDIUMLOW /*!< LSE medium low drive capability */ 748 #define RCC_LSEDRIVE_MEDIUMHIGH LL_RCC_LSEDRIVE_MEDIUMHIGH /*!< LSE medium high drive capability */ 749 #define RCC_LSEDRIVE_HIGH LL_RCC_LSEDRIVE_HIGH /*!< LSE high drive capability */ 750 /** 751 * @} 752 */ 753 754 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock 755 * @{ 756 */ 757 #define RCC_STOP_WAKEUPCLOCK_MSI LL_RCC_STOP_WAKEUPCLOCK_MSI /*!< MSI selected after wake-up from STOP */ 758 #define RCC_STOP_WAKEUPCLOCK_HSI LL_RCC_STOP_WAKEUPCLOCK_HSI /*!< HSI selected after wake-up from STOP */ 759 /** 760 * @} 761 */ 762 763 /** 764 * @} 765 */ 766 767 /* Exported macros -----------------------------------------------------------*/ 768 769 /** @defgroup RCC_Exported_Macros RCC Exported Macros 770 * @{ 771 */ 772 773 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 774 * @brief Enable or disable the AHB1 peripheral clock. 775 * @note After reset, the peripheral clock (used for registers read/write access) 776 * is disabled and the application software has to enable this clock before 777 * using it. 778 * @{ 779 */ 780 #if defined(CORE_CM0PLUS) 781 #define __HAL_RCC_DMA1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1) 782 #define __HAL_RCC_DMA2_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA2) 783 #define __HAL_RCC_DMAMUX1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) 784 #define __HAL_RCC_CRC_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_CRC) 785 786 #define __HAL_RCC_DMA1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1) 787 #define __HAL_RCC_DMA2_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA2) 788 #define __HAL_RCC_DMAMUX1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) 789 #define __HAL_RCC_CRC_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_CRC) 790 #else 791 #define __HAL_RCC_DMA1_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1) 792 #define __HAL_RCC_DMA2_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2) 793 #define __HAL_RCC_DMAMUX1_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1) 794 #define __HAL_RCC_CRC_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC) 795 796 #define __HAL_RCC_DMA1_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA1) 797 #define __HAL_RCC_DMA2_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA2) 798 #define __HAL_RCC_DMAMUX1_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1) 799 #define __HAL_RCC_CRC_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_CRC) 800 #endif /* CORE_CM0PLUS */ 801 /** 802 * @} 803 */ 804 805 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 806 * @brief Enable or disable the AHB2 peripheral clock. 807 * @note After reset, the peripheral clock (used for registers read/write access) 808 * is disabled and the application software has to enable this clock before 809 * using it. 810 * @{ 811 */ 812 #if defined(CORE_CM0PLUS) 813 #define __HAL_RCC_GPIOA_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA) 814 #define __HAL_RCC_GPIOB_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB) 815 #define __HAL_RCC_GPIOC_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC) 816 #define __HAL_RCC_GPIOH_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH) 817 818 #define __HAL_RCC_GPIOA_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA) 819 #define __HAL_RCC_GPIOB_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB) 820 #define __HAL_RCC_GPIOC_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC) 821 #define __HAL_RCC_GPIOH_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH) 822 #else 823 #define __HAL_RCC_GPIOA_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA) 824 #define __HAL_RCC_GPIOB_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB) 825 #define __HAL_RCC_GPIOC_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC) 826 #define __HAL_RCC_GPIOH_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH) 827 828 #define __HAL_RCC_GPIOA_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOA) 829 #define __HAL_RCC_GPIOB_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOB) 830 #define __HAL_RCC_GPIOC_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOC) 831 #define __HAL_RCC_GPIOH_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOH) 832 #endif /* CORE_CM0PLUS */ 833 /** 834 * @} 835 */ 836 837 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 838 * @brief Enable or disable the AHB3 peripheral clock. 839 * @note After reset, the peripheral clock (used for registers read/write access) 840 * is disabled and the application software has to enable this clock before 841 * using it. 842 * @{ 843 */ 844 #if defined(CORE_CM0PLUS) 845 #define __HAL_RCC_PKA_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_PKA) 846 #define __HAL_RCC_AES_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_AES) 847 #define __HAL_RCC_RNG_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_RNG) 848 #define __HAL_RCC_HSEM_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_HSEM) 849 #define __HAL_RCC_IPCC_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC) 850 #define __HAL_RCC_FLASH_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_FLASH) 851 852 #define __HAL_RCC_PKA_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_PKA) 853 #define __HAL_RCC_AES_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_AES) 854 #define __HAL_RCC_RNG_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_RNG) 855 #define __HAL_RCC_HSEM_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_HSEM) 856 #define __HAL_RCC_IPCC_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC) 857 #define __HAL_RCC_FLASH_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_FLASH) 858 #else 859 #define __HAL_RCC_PKA_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PKA) 860 #define __HAL_RCC_AES_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_AES) 861 #define __HAL_RCC_RNG_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_RNG) 862 #define __HAL_RCC_HSEM_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HSEM) 863 #define __HAL_RCC_IPCC_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC) 864 #define __HAL_RCC_FLASH_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_FLASH) 865 866 #define __HAL_RCC_PKA_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_PKA) 867 #define __HAL_RCC_AES_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_AES) 868 #define __HAL_RCC_RNG_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_RNG) 869 #define __HAL_RCC_HSEM_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_HSEM) 870 #define __HAL_RCC_IPCC_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_IPCC) 871 #define __HAL_RCC_FLASH_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_FLASH) 872 #endif /* CORE_CM0PLUS */ 873 /** 874 * @} 875 */ 876 877 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 878 * @brief Enable or disable the APB1 peripheral clock. 879 * @note After reset, the peripheral clock (used for registers read/write access) 880 * is disabled and the application software has to enable this clock before 881 * using it. 882 * @{ 883 */ 884 #if defined(CORE_CM0PLUS) 885 #define __HAL_RCC_TIM2_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_TIM2) 886 #define __HAL_RCC_RTCAPB_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB) 887 #define __HAL_RCC_SPI2_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_SPI2) 888 #define __HAL_RCC_USART2_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_USART2) 889 #define __HAL_RCC_I2C1_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C1) 890 #define __HAL_RCC_I2C2_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C2) 891 #define __HAL_RCC_I2C3_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C3) 892 #define __HAL_RCC_DAC_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_DAC) 893 #define __HAL_RCC_LPTIM1_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1) 894 895 #define __HAL_RCC_LPTIM2_CLK_ENABLE() LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2) 896 #define __HAL_RCC_LPTIM3_CLK_ENABLE() LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM3) 897 #define __HAL_RCC_LPUART1_CLK_ENABLE() LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPUART1) 898 899 #define __HAL_RCC_TIM2_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_TIM2) 900 #define __HAL_RCC_RTCAPB_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB) 901 #define __HAL_RCC_SPI2_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_SPI2) 902 #define __HAL_RCC_USART2_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_USART2) 903 #define __HAL_RCC_I2C1_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C1) 904 #define __HAL_RCC_I2C2_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C2) 905 #define __HAL_RCC_I2C3_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C3) 906 #define __HAL_RCC_DAC_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_DAC) 907 #define __HAL_RCC_LPTIM1_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1) 908 909 #define __HAL_RCC_LPTIM2_CLK_DISABLE() LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2) 910 #define __HAL_RCC_LPTIM3_CLK_DISABLE() LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM3) 911 #define __HAL_RCC_LPUART1_CLK_DISABLE() LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPUART1) 912 #else 913 #define __HAL_RCC_TIM2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2) 914 #define __HAL_RCC_RTCAPB_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_RTCAPB) 915 #define __HAL_RCC_SPI2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2) 916 #define __HAL_RCC_USART2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART2) 917 #define __HAL_RCC_I2C1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1) 918 #define __HAL_RCC_I2C2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C2) 919 #define __HAL_RCC_I2C3_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C3) 920 #define __HAL_RCC_DAC_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DAC) 921 #define __HAL_RCC_LPTIM1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPTIM1) 922 923 #define __HAL_RCC_LPTIM2_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPTIM2) 924 #define __HAL_RCC_LPTIM3_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPTIM3) 925 #define __HAL_RCC_LPUART1_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPUART1) 926 927 #define __HAL_RCC_TIM2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM2) 928 #define __HAL_RCC_RTCAPB_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_RTCAPB) 929 #define __HAL_RCC_SPI2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI2) 930 #define __HAL_RCC_USART2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USART2) 931 #define __HAL_RCC_I2C1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C1) 932 #define __HAL_RCC_I2C2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C2) 933 #define __HAL_RCC_I2C3_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C3) 934 #define __HAL_RCC_DAC_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_DAC) 935 #define __HAL_RCC_LPTIM1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LPTIM1) 936 937 #define __HAL_RCC_LPTIM2_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPTIM2) 938 #define __HAL_RCC_LPTIM3_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPTIM3) 939 #define __HAL_RCC_LPUART1_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPUART1) 940 #endif /* CORE_CM0PLUS */ 941 942 #define __HAL_RCC_WWDG_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_WWDG) 943 944 #define __HAL_RCC_WWDG_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_WWDG) 945 946 /** 947 * @} 948 */ 949 950 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 951 * @brief Enable or disable the APB2 peripheral clock. 952 * @note After reset, the peripheral clock (used for registers read/write access) 953 * is disabled and the application software has to enable this clock before 954 * using it. 955 * @{ 956 */ 957 #if defined(CORE_CM0PLUS) 958 #define __HAL_RCC_ADC_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_ADC) 959 #define __HAL_RCC_TIM1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM1) 960 #define __HAL_RCC_SPI1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SPI1) 961 #define __HAL_RCC_USART1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_USART1) 962 #define __HAL_RCC_TIM16_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM16) 963 #define __HAL_RCC_TIM17_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM17) 964 965 #define __HAL_RCC_ADC_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_ADC) 966 #define __HAL_RCC_TIM1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM1) 967 #define __HAL_RCC_SPI1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_SPI1) 968 #define __HAL_RCC_USART1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_USART1) 969 #define __HAL_RCC_TIM16_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM16) 970 #define __HAL_RCC_TIM17_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM17) 971 #else 972 #define __HAL_RCC_ADC_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_ADC) 973 #define __HAL_RCC_TIM1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1) 974 #define __HAL_RCC_SPI1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1) 975 #define __HAL_RCC_USART1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1) 976 #define __HAL_RCC_TIM16_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM16) 977 #define __HAL_RCC_TIM17_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM17) 978 979 #define __HAL_RCC_ADC_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_ADC) 980 #define __HAL_RCC_TIM1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM1) 981 #define __HAL_RCC_SPI1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI1) 982 #define __HAL_RCC_USART1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART1) 983 #define __HAL_RCC_TIM16_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM16) 984 #define __HAL_RCC_TIM17_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM17) 985 #endif /* CORE_CM0PLUS */ 986 /** 987 * @} 988 */ 989 990 991 /** @defgroup RCC_APB3_Clock_Enable_Disable APB3 Peripheral Clock Enable Disable 992 * @brief Enable or disable the APB3 peripheral clock. 993 * @note After reset, the peripheral clock (used for registers read/write access) 994 * is disabled and the application software has to enable this clock before 995 * using it. 996 * @{ 997 */ 998 #if defined(CORE_CM0PLUS) 999 #define __HAL_RCC_SUBGHZSPI_CLK_ENABLE() LL_C2_APB3_GRP1_EnableClock(LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI) 1000 1001 #define __HAL_RCC_SUBGHZSPI_CLK_DISABLE() LL_C2_APB3_GRP1_DisableClock(LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI) 1002 #else 1003 #define __HAL_RCC_SUBGHZSPI_CLK_ENABLE() LL_APB3_GRP1_EnableClock(LL_APB3_GRP1_PERIPH_SUBGHZSPI) 1004 1005 #define __HAL_RCC_SUBGHZSPI_CLK_DISABLE() LL_APB3_GRP1_DisableClock(LL_APB3_GRP1_PERIPH_SUBGHZSPI) 1006 #endif /* CORE_CM0PLUS */ 1007 1008 1009 /* Aliases used by CubeMX for HAL SUBGHZ Init, MspInit and DeInit generation */ 1010 #define __HAL_RCC_SUBGHZ_CLK_ENABLE() __HAL_RCC_SUBGHZSPI_CLK_ENABLE() 1011 #define __HAL_RCC_SUBGHZ_CLK_DISABLE() __HAL_RCC_SUBGHZSPI_CLK_DISABLE() 1012 /** 1013 * @} 1014 */ 1015 1016 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 1017 * @brief Check whether the AHB1 peripheral clock is enabled or not. 1018 * @note After reset, the peripheral clock (used for registers read/write access) 1019 * is disabled and the application software has to enable this clock before 1020 * using it. 1021 * @{ 1022 */ 1023 #if defined(CORE_CM0PLUS) 1024 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA1) 1025 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA2) 1026 #define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) 1027 #define __HAL_RCC_CRC_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_CRC) 1028 #else 1029 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA1) 1030 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA2) 1031 #define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMAMUX1) 1032 #define __HAL_RCC_CRC_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC) 1033 #endif /* CORE_CM0PLUS */ 1034 /** 1035 * @} 1036 */ 1037 1038 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 1039 * @brief Check whether the AHB2 peripheral clock is enabled or not. 1040 * @note After reset, the peripheral clock (used for registers read/write access) 1041 * is disabled and the application software has to enable this clock before 1042 * using it. 1043 * @{ 1044 */ 1045 #if defined(CORE_CM0PLUS) 1046 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA) 1047 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB) 1048 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC) 1049 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH) 1050 #else 1051 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOA) 1052 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOB) 1053 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOC) 1054 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH) 1055 #endif /* CORE_CM0PLUS */ 1056 /** 1057 * @} 1058 */ 1059 1060 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status 1061 * @brief Check whether the AHB3 peripheral clock is enabled or not. 1062 * @note After reset, the peripheral clock (used for registers read/write access) 1063 * is disabled and the application software has to enable this clock before 1064 * using it. 1065 * @{ 1066 */ 1067 #if defined(CORE_CM0PLUS) 1068 #define __HAL_RCC_PKA_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_PKA) 1069 #define __HAL_RCC_AES_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_AES) 1070 #define __HAL_RCC_RNG_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_RNG) 1071 #define __HAL_RCC_HSEM_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_HSEM) 1072 #define __HAL_RCC_IPCC_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_IPCC) 1073 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_FLASH) 1074 #else 1075 #define __HAL_RCC_PKA_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PKA) 1076 #define __HAL_RCC_AES_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_AES) 1077 #define __HAL_RCC_RNG_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RNG) 1078 #define __HAL_RCC_HSEM_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_HSEM) 1079 #define __HAL_RCC_IPCC_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_IPCC) 1080 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_FLASH) 1081 #endif /* CORE_CM0PLUS */ 1082 /** 1083 * @} 1084 */ 1085 1086 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 1087 * @brief Check whether the APB1 peripheral clock is enabled or not. 1088 * @note After reset, the peripheral clock (used for registers read/write access) 1089 * is disabled and the application software has to enable this clock before 1090 * using it. 1091 * @{ 1092 */ 1093 #if defined(CORE_CM0PLUS) 1094 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_TIM2) 1095 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB) 1096 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_SPI2) 1097 #define __HAL_RCC_USART2_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_USART2) 1098 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C1) 1099 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C2) 1100 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C3) 1101 #define __HAL_RCC_DAC_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_DAC) 1102 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1) 1103 1104 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2) 1105 #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPTIM3) 1106 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPUART1) 1107 #else 1108 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2) 1109 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_RTCAPB) 1110 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2) 1111 #define __HAL_RCC_USART2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USART2) 1112 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1) 1113 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C2) 1114 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C3) 1115 #define __HAL_RCC_DAC_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_DAC) 1116 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPTIM1) 1117 1118 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPTIM2) 1119 #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPTIM3) 1120 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPUART1) 1121 #endif /* CORE_CM0PLUS */ 1122 1123 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_WWDG) 1124 /** 1125 * @} 1126 */ 1127 1128 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 1129 * @brief Check whether the APB2 peripheral clock is enabled or not. 1130 * @note After reset, the peripheral clock (used for registers read/write access) 1131 * is disabled and the application software has to enable this clock before 1132 * using it. 1133 * @{ 1134 */ 1135 #if defined(CORE_CM0PLUS) 1136 #define __HAL_RCC_ADC_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_ADC) 1137 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1) 1138 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1) 1139 #define __HAL_RCC_USART1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1) 1140 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM16) 1141 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM17) 1142 #else 1143 #define __HAL_RCC_ADC_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_ADC) 1144 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1) 1145 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1) 1146 #define __HAL_RCC_USART1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1) 1147 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM16) 1148 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM17) 1149 #endif /* CORE_CM0PLUS */ 1150 /** 1151 * @} 1152 */ 1153 1154 /** @defgroup RCC_APB3_Clock_Enable_Disable_Status APB3 Peripheral Clock Enabled or Disabled Status 1155 * @brief Check whether the APB3 peripheral clock is enabled or not. 1156 * @note After reset, the peripheral clock (used for registers read/write access) 1157 * is disabled and the application software has to enable this clock before 1158 * using it. 1159 * @{ 1160 */ 1161 #if defined(CORE_CM0PLUS) 1162 #define __HAL_RCC_SUBGHZSPI_IS_CLK_ENABLED() LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI) 1163 #else 1164 #define __HAL_RCC_SUBGHZSPI_IS_CLK_ENABLED() LL_APB3_GRP1_IsEnabledClock(LL_APB3_GRP1_PERIPH_SUBGHZSPI) 1165 #endif /* CORE_CM0PLUS */ 1166 1167 /* Aliases used by CubeMX for HAL SUBGHZ Init, MspInit and DeInit generation */ 1168 #define __HAL_RCC_SUBGHZ_IS_CLK_ENABLED() __HAL_RCC_SUBGHZSPI_IS_CLK_ENABLED() 1169 /** 1170 * @} 1171 */ 1172 1173 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset 1174 * @brief Force or release AHB1 peripheral reset. 1175 * @{ 1176 */ 1177 #define __HAL_RCC_AHB1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ALL) 1178 #define __HAL_RCC_DMA1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1) 1179 #define __HAL_RCC_DMA2_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2) 1180 #define __HAL_RCC_DMAMUX1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMAMUX1) 1181 #define __HAL_RCC_CRC_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC) 1182 1183 #define __HAL_RCC_AHB1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ALL) 1184 #define __HAL_RCC_DMA1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1) 1185 #define __HAL_RCC_DMA2_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2) 1186 #define __HAL_RCC_DMAMUX1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMAMUX1) 1187 #define __HAL_RCC_CRC_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC) 1188 /** 1189 * @} 1190 */ 1191 1192 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset 1193 * @brief Force or release AHB2 peripheral reset. 1194 * @{ 1195 */ 1196 #define __HAL_RCC_AHB2_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ALL) 1197 #define __HAL_RCC_GPIOA_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOA) 1198 #define __HAL_RCC_GPIOB_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOB) 1199 #define __HAL_RCC_GPIOC_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOC) 1200 #define __HAL_RCC_GPIOH_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH) 1201 1202 #define __HAL_RCC_AHB2_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ALL) 1203 #define __HAL_RCC_GPIOA_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOA) 1204 #define __HAL_RCC_GPIOB_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOB) 1205 #define __HAL_RCC_GPIOC_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOC) 1206 #define __HAL_RCC_GPIOH_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH) 1207 /** 1208 * @} 1209 */ 1210 1211 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset 1212 * @brief Force or release AHB3 peripheral reset. 1213 * @{ 1214 */ 1215 #if defined (DUAL_CORE) 1216 #define __HAL_RCC_IPCC_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_IPCC) 1217 #define __HAL_RCC_IPCC_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_IPCC) 1218 #endif /* DUAL_CORE */ 1219 1220 #define __HAL_RCC_AHB3_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_ALL) 1221 #define __HAL_RCC_PKA_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_PKA) 1222 #define __HAL_RCC_AES_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_AES) 1223 #define __HAL_RCC_RNG_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_RNG) 1224 #define __HAL_RCC_HSEM_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_HSEM) 1225 #define __HAL_RCC_FLASH_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_FLASH) 1226 1227 #define __HAL_RCC_AHB3_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_ALL) 1228 #define __HAL_RCC_PKA_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_PKA) 1229 #define __HAL_RCC_AES_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_AES) 1230 #define __HAL_RCC_RNG_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_RNG) 1231 #define __HAL_RCC_HSEM_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_HSEM) 1232 #define __HAL_RCC_FLASH_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_FLASH) 1233 /** 1234 * @} 1235 */ 1236 1237 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 1238 * @brief Force or release APB1 peripheral reset. 1239 * @{ 1240 */ 1241 #define __HAL_RCC_APB1L_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_ALL) 1242 #define __HAL_RCC_TIM2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2) 1243 #define __HAL_RCC_SPI2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2) 1244 #define __HAL_RCC_USART2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2) 1245 #define __HAL_RCC_I2C1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1) 1246 #define __HAL_RCC_I2C2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2) 1247 #define __HAL_RCC_I2C3_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3) 1248 #define __HAL_RCC_DAC_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC) 1249 #define __HAL_RCC_LPTIM1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1) 1250 1251 #define __HAL_RCC_APB1H_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ALL) 1252 #define __HAL_RCC_LPUART1_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPUART1) 1253 #define __HAL_RCC_LPTIM2_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2) 1254 #define __HAL_RCC_LPTIM3_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM3) 1255 1256 #define __HAL_RCC_APB1_FORCE_RESET() do { \ 1257 __HAL_RCC_APB1L_FORCE_RESET();\ 1258 __HAL_RCC_APB1H_FORCE_RESET();\ 1259 } while(0U) 1260 1261 #define __HAL_RCC_APB1L_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_ALL) 1262 #define __HAL_RCC_TIM2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2) 1263 #define __HAL_RCC_USART2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2) 1264 #define __HAL_RCC_SPI2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2) 1265 #define __HAL_RCC_I2C1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1) 1266 #define __HAL_RCC_I2C2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2) 1267 #define __HAL_RCC_I2C3_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3) 1268 #define __HAL_RCC_DAC_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC) 1269 #define __HAL_RCC_LPTIM1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1) 1270 1271 #define __HAL_RCC_APB1H_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ALL) 1272 #define __HAL_RCC_LPUART1_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPUART1) 1273 #define __HAL_RCC_LPTIM2_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2) 1274 #define __HAL_RCC_LPTIM3_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM3) 1275 1276 #define __HAL_RCC_APB1_RELEASE_RESET() do { \ 1277 __HAL_RCC_APB1L_RELEASE_RESET();\ 1278 __HAL_RCC_APB1H_RELEASE_RESET();\ 1279 } while(0U) 1280 /** 1281 * @} 1282 */ 1283 1284 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 1285 * @brief Force or release APB2 peripheral reset. 1286 * @{ 1287 */ 1288 #define __HAL_RCC_APB2_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ALL) 1289 #define __HAL_RCC_ADC_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC) 1290 #define __HAL_RCC_TIM1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1) 1291 #define __HAL_RCC_SPI1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1) 1292 #define __HAL_RCC_USART1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1) 1293 #define __HAL_RCC_TIM16_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16) 1294 #define __HAL_RCC_TIM17_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17) 1295 1296 #define __HAL_RCC_APB2_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ALL) 1297 #define __HAL_RCC_ADC_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC) 1298 #define __HAL_RCC_TIM1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1) 1299 #define __HAL_RCC_SPI1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1) 1300 #define __HAL_RCC_USART1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1) 1301 #define __HAL_RCC_TIM16_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16) 1302 #define __HAL_RCC_TIM17_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17) 1303 /** 1304 * @} 1305 */ 1306 1307 /** @defgroup RCC_APB3_Force_Release_Reset APB3 Peripheral Force Release Reset 1308 * @brief Force or release APB3 peripheral reset. 1309 * @{ 1310 */ 1311 #define __HAL_RCC_APB3_FORCE_RESET() LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_ALL) 1312 #define __HAL_RCC_SUBGHZSPI_FORCE_RESET() LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_SUBGHZSPI) 1313 1314 #define __HAL_RCC_APB3_RELEASE_RESET() LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_ALL) 1315 #define __HAL_RCC_SUBGHZSPI_RELEASE_RESET() LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_SUBGHZSPI) 1316 1317 /* Aliases used by CubeMX for HAL SUBGHZ Init, MspInit and DeInit generation */ 1318 #define __HAL_RCC_SUBGHZ_FORCE_RESET() __HAL_RCC_SUBGHZSPI_FORCE_RESET() 1319 #define __HAL_RCC_SUBGHZ_RELEASE_RESET() __HAL_RCC_SUBGHZSPI_RELEASE_RESET() 1320 /** 1321 * @} 1322 */ 1323 1324 /** @defgroup RCC_SUBGHZ_Force_Release_Reset SUBGHZ Radio Force Release Reset 1325 * @brief Force or release SUBGHZ Radio reset. 1326 * @{ 1327 */ 1328 #define __HAL_RCC_SUBGHZ_RADIO_FORCE_RESET() SET_BIT(RCC->CSR, RCC_CSR_RFRST) 1329 1330 #define __HAL_RCC_SUBGHZ_RADIO_RELEASE_RESET() CLEAR_BIT(RCC->CSR, RCC_CSR_RFRST) 1331 /** 1332 * @} 1333 */ 1334 1335 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable 1336 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 1337 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1338 * power consumption. 1339 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1340 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1341 * @{ 1342 */ 1343 #if defined(CORE_CM0PLUS) 1344 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1) 1345 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA2) 1346 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) 1347 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_CRC) 1348 1349 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1) 1350 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA2) 1351 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) 1352 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_CRC) 1353 #else 1354 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMA1) 1355 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMA2) 1356 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1) 1357 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_CRC) 1358 1359 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMA1) 1360 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMA2) 1361 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1) 1362 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_CRC) 1363 #endif /* CORE_CM0PLUS */ 1364 /** 1365 * @} 1366 */ 1367 1368 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable 1369 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 1370 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1371 * power consumption. 1372 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1373 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1374 * @{ 1375 */ 1376 #if defined(CORE_CM0PLUS) 1377 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA) 1378 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB) 1379 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC) 1380 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH) 1381 1382 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA) 1383 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB) 1384 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC) 1385 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH) 1386 #else 1387 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA) 1388 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB) 1389 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC) 1390 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH) 1391 1392 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA) 1393 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB) 1394 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC) 1395 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH) 1396 #endif /* CORE_CM0PLUS */ 1397 /** 1398 * @} 1399 */ 1400 1401 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable 1402 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 1403 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1404 * power consumption. 1405 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1406 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1407 * @{ 1408 */ 1409 #if defined(CORE_CM0PLUS) 1410 #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_PKA) 1411 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_AES) 1412 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_RNG) 1413 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM1) 1414 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM2) 1415 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_FLASH) 1416 1417 #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_PKA) 1418 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_AES) 1419 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_RNG) 1420 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM1) 1421 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM2) 1422 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_FLASH) 1423 #else 1424 #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_PKA) 1425 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_AES) 1426 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_RNG) 1427 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM1) 1428 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2) 1429 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_FLASH) 1430 1431 #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_PKA) 1432 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_AES) 1433 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_RNG) 1434 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM1) 1435 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2) 1436 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_FLASH) 1437 #endif /* CORE_CM0PLUS */ 1438 /** 1439 * @} 1440 */ 1441 1442 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 1443 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 1444 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1445 * power consumption. 1446 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1447 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1448 * @{ 1449 */ 1450 #if defined(CORE_CM0PLUS) 1451 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2) 1452 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB) 1453 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2) 1454 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_USART2) 1455 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1) 1456 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C2) 1457 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3) 1458 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_DAC) 1459 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1) 1460 1461 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1) 1462 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2) 1463 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM3) 1464 1465 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2) 1466 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB) 1467 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_USART2) 1468 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2) 1469 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1) 1470 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C2) 1471 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3) 1472 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_DAC) 1473 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1) 1474 1475 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1) 1476 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2) 1477 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM3) 1478 #else 1479 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_TIM2) 1480 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB) 1481 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_SPI2) 1482 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_USART2) 1483 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C1) 1484 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C2) 1485 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C3) 1486 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_DAC) 1487 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1) 1488 1489 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPUART1) 1490 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2) 1491 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM3) 1492 1493 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_TIM2) 1494 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB) 1495 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_USART2) 1496 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_SPI2) 1497 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C1) 1498 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C2) 1499 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C3) 1500 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_DAC) 1501 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1) 1502 1503 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPUART1) 1504 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2) 1505 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM3) 1506 #endif /* CORE_CM0PLUS */ 1507 1508 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_WWDG) 1509 1510 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_WWDG) 1511 /** 1512 * @} 1513 */ 1514 1515 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 1516 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 1517 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1518 * power consumption. 1519 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1520 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1521 * @{ 1522 */ 1523 #if defined(CORE_CM0PLUS) 1524 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_ADC) 1525 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1) 1526 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1) 1527 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1) 1528 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16) 1529 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17) 1530 1531 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_ADC) 1532 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1) 1533 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1) 1534 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1) 1535 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16) 1536 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17) 1537 #else 1538 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_ADC) 1539 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM1) 1540 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SPI1) 1541 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_USART1) 1542 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM16) 1543 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM17) 1544 1545 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_ADC) 1546 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM1) 1547 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SPI1) 1548 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_USART1) 1549 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM16) 1550 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM17) 1551 #endif /* CORE_CM0PLUS */ 1552 /** 1553 * @} 1554 */ 1555 1556 /** @defgroup RCC_APB3_Clock_Sleep_Enable_Disable APB3 Peripheral Clock Sleep Enable Disable 1557 * @brief Enable or disable the APB3 peripheral clock during Low Power (Sleep) mode. 1558 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1559 * power consumption. 1560 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1561 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1562 * @{ 1563 */ 1564 #if defined(CORE_CM0PLUS) 1565 #define __HAL_RCC_SUBGHZSPI_CLK_SLEEP_ENABLE() LL_C2_APB3_GRP1_EnableClockSleep(LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI) 1566 1567 #define __HAL_RCC_SUBGHZSPI_CLK_SLEEP_DISABLE() LL_C2_APB3_GRP1_DisableClockSleep(LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI) 1568 #else 1569 #define __HAL_RCC_SUBGHZSPI_CLK_SLEEP_ENABLE() LL_APB3_GRP1_EnableClockSleep(LL_APB3_GRP1_PERIPH_SUBGHZSPI) 1570 1571 #define __HAL_RCC_SUBGHZSPI_CLK_SLEEP_DISABLE() LL_APB3_GRP1_DisableClockSleep(LL_APB3_GRP1_PERIPH_SUBGHZSPI) 1572 #endif /* CORE_CM0PLUS */ 1573 1574 /* Aliases used by CubeMX for HAL SUBGHZ Init, MspInit and DeInit generation */ 1575 #define __HAL_RCC_SUBGHZ_CLK_SLEEP_ENABLE() __HAL_RCC_SUBGHZSPI_CLK_SLEEP_ENABLE() 1576 #define __HAL_RCC_SUBGHZ_CLK_SLEEP_DISABLE() __HAL_RCC_SUBGHZSPI_CLK_SLEEP_DISABLE() 1577 /** 1578 * @} 1579 */ 1580 1581 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status 1582 * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 1583 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1584 * power consumption. 1585 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1586 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1587 * @{ 1588 */ 1589 #if defined(CORE_CM0PLUS) 1590 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_DMA1) 1591 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_DMA2) 1592 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1) 1593 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_CRC) 1594 #else 1595 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() LL_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_DMA1) 1596 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() LL_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_DMA2) 1597 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() LL_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1) 1598 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() LL_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_CRC) 1599 #endif /* CORE_CM0PLUS */ 1600 /** 1601 * @} 1602 */ 1603 1604 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status 1605 * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 1606 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1607 * power consumption. 1608 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1609 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1610 * @{ 1611 */ 1612 #if defined(CORE_CM0PLUS) 1613 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA) 1614 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB) 1615 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC) 1616 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH) 1617 #else 1618 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() LL_AHB2_GRP1_IsEnabledClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA) 1619 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() LL_AHB2_GRP1_IsEnabledClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB) 1620 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() LL_AHB2_GRP1_IsEnabledClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC) 1621 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() LL_AHB2_GRP1_IsEnabledClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH) 1622 #endif /* CORE_CM0PLUS */ 1623 /** 1624 * @} 1625 */ 1626 1627 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status 1628 * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. 1629 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1630 * power consumption. 1631 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1632 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1633 * @{ 1634 */ 1635 #if defined(CORE_CM0PLUS) 1636 #define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_PKA) 1637 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_AES) 1638 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_RNG) 1639 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_SRAM1) 1640 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2) 1641 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_FLASH) 1642 #else 1643 #define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_PKA) 1644 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_AES) 1645 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_RNG) 1646 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_SRAM1) 1647 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2) 1648 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_FLASH) 1649 #endif /* CORE_CM0PLUS */ 1650 /** 1651 * @} 1652 */ 1653 1654 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status 1655 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 1656 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1657 * power consumption. 1658 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1659 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1660 * @{ 1661 */ 1662 #if defined(CORE_CM0PLUS) 1663 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2) 1664 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB) 1665 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_USART2) 1666 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2) 1667 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1) 1668 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C2) 1669 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3) 1670 #define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_DAC) 1671 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1) 1672 1673 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP2_IsEnabledClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1) 1674 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP2_IsEnabledClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2) 1675 #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() LL_C2_APB1_GRP2_IsEnabledClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM3) 1676 #else 1677 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_TIM2) 1678 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB) 1679 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_USART2) 1680 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_SPI2) 1681 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_I2C1) 1682 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_I2C2) 1683 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_I2C3) 1684 #define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_DAC) 1685 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1) 1686 1687 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP2_IsEnabledClockSleep(LL_APB1_GRP2_PERIPH_LPUART1) 1688 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP2_IsEnabledClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2) 1689 #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP2_IsEnabledClockSleep(LL_APB1_GRP2_PERIPH_LPTIM3) 1690 #endif /* CORE_CM0PLUS */ 1691 1692 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_WWDG) 1693 /** 1694 * @} 1695 */ 1696 1697 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status 1698 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 1699 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1700 * power consumption. 1701 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1702 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1703 * @{ 1704 */ 1705 #if defined(CORE_CM0PLUS) 1706 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() LL_C2_APB2_GRP1_IsEnabledClockSleep(LL_C2_APB2_GRP1_PERIPH_ADC) 1707 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() LL_C2_APB2_GRP1_IsEnabledClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1) 1708 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() LL_C2_APB2_GRP1_IsEnabledClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1) 1709 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() LL_C2_APB2_GRP1_IsEnabledClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1) 1710 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() LL_C2_APB2_GRP1_IsEnabledClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16) 1711 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() LL_C2_APB2_GRP1_IsEnabledClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17) 1712 #else 1713 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockSleep(LL_APB2_GRP1_PERIPH_ADC) 1714 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockSleep(LL_APB2_GRP1_PERIPH_TIM1) 1715 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockSleep(LL_APB2_GRP1_PERIPH_SPI1) 1716 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockSleep(LL_APB2_GRP1_PERIPH_USART1) 1717 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockSleep(LL_APB2_GRP1_PERIPH_TIM16) 1718 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockSleep(LL_APB2_GRP1_PERIPH_TIM17) 1719 #endif /* CORE_CM0PLUS */ 1720 /** 1721 * @} 1722 */ 1723 1724 /** @defgroup RCC_APB3_Clock_Sleep_Enable_Disable_Status APB3 Peripheral Clock Sleep Enabled or Disabled Status 1725 * @brief Check whether the APB3 peripheral clock during Low Power (Sleep) mode is enabled or not. 1726 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1727 * power consumption. 1728 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1729 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1730 * @{ 1731 */ 1732 #if defined(CORE_CM0PLUS) 1733 #define __HAL_RCC_SUBGHZSPI_IS_CLK_SLEEP_ENABLED() \ 1734 LL_C2_APB3_GRP1_IsEnabledClockSleep(LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI) 1735 #else 1736 #define __HAL_RCC_SUBGHZSPI_IS_CLK_SLEEP_ENABLED() \ 1737 LL_APB3_GRP1_IsEnabledClockSleep(LL_APB3_GRP1_PERIPH_SUBGHZSPI) 1738 #endif /* CORE_CM0PLUS */ 1739 1740 /* Aliases used by CubeMX for HAL SUBGHZ Init, MspInit and DeInit generation */ 1741 #define __HAL_RCC_SUBGHZ_IS_CLK_SLEEP_ENABLED() __HAL_RCC_SUBGHZSPI_IS_CLK_SLEEP_ENABLED() 1742 /** 1743 * @} 1744 */ 1745 1746 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset 1747 * @{ 1748 */ 1749 1750 /** @brief Macros to force or release the Backup domain reset. 1751 * @note This function resets the RTC peripheral (including the backup registers) 1752 * and the RTC clock source selection in RCC_CSR register. 1753 * @note The SRAM2 is not affected by this reset. 1754 * @retval None 1755 */ 1756 #define __HAL_RCC_BACKUPRESET_FORCE() LL_RCC_ForceBackupDomainReset() 1757 #define __HAL_RCC_BACKUPRESET_RELEASE() LL_RCC_ReleaseBackupDomainReset() 1758 /** 1759 * @} 1760 */ 1761 1762 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 1763 * @{ 1764 */ 1765 1766 /** @brief Macros to enable or disable the RTC clock. 1767 * @note As the RTC is in the Backup domain and write access is denied to 1768 * this domain after reset, you have to enable write access using 1769 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC 1770 * (to be done once after reset). 1771 * @note These macros must be used after the RTC clock source was selected. 1772 * @retval None 1773 */ 1774 #define __HAL_RCC_RTC_ENABLE() LL_RCC_EnableRTC() 1775 #define __HAL_RCC_RTC_DISABLE() LL_RCC_DisableRTC() 1776 /** 1777 * @} 1778 */ 1779 1780 /** @brief Macros to enable the Internal High Speed oscillator (HSI). 1781 * @note The HSI is stopped by hardware when entering STOP, STANDBY or SHUTDOWN modes. 1782 * It is enabled by hardware to force the HSI oscillator ON when STOPWUCK=1 1783 * or HSIASFS = 1 when leaving Stop modes, or in case of failure of the HSE 1784 * crystal oscillator and Security System CSS is enabled. 1785 * @note After enabling the HSI, the application software should wait on HSIRDY 1786 * flag to be set indicating that HSI clock is stable and can be used as 1787 * system clock source. 1788 * @retval None 1789 */ 1790 #define __HAL_RCC_HSI_ENABLE() LL_RCC_HSI_Enable() 1791 1792 /** @brief Macro to disable the Internal High Speed oscillator (HSI). 1793 * @note HSI can not be stopped if it is used as system clock source. In this case, 1794 * you have to select another source of the system clock then stop the HSI. 1795 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 1796 * clock cycles. 1797 * @retval None 1798 */ 1799 #define __HAL_RCC_HSI_DISABLE() LL_RCC_HSI_Disable() 1800 1801 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 1802 * @note The calibration is used to compensate for the variations in voltage 1803 * and temperature that influence the frequency of the internal HSI RC. 1804 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value 1805 * (default is RCC_HSICALIBRATION_DEFAULT). 1806 * This parameter must be a number between Min_data=0 and Max_Data=127. 1807 * @retval None 1808 */ 1809 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 1810 LL_RCC_HSI_SetCalibTrimming(__HSICALIBRATIONVALUE__) 1811 1812 /** 1813 * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) 1814 * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup. 1815 * @note The enable of this function has not effect on the HSION bit. 1816 * This parameter can be: ENABLE or DISABLE. 1817 * @retval None 1818 */ 1819 #define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() LL_RCC_HSI_EnableAutoFromStop() 1820 #define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() LL_RCC_HSI_DisableAutoFromStop() 1821 1822 /** 1823 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 1824 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 1825 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 1826 * speed because of the HSI startup time. 1827 * @note The enable of this function has not effect on the HSION bit. 1828 * @retval None 1829 */ 1830 #define __HAL_RCC_HSISTOP_ENABLE() LL_RCC_HSI_EnableInStopMode() 1831 #define __HAL_RCC_HSISTOP_DISABLE() LL_RCC_HSI_DisableInStopMode() 1832 1833 /** 1834 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). 1835 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. 1836 * It is used (enabled by hardware) as system clock source after 1837 * startup from Reset, wakeup from STOP and STANDBY mode, or in case 1838 * of failure of the HSE used directly or indirectly as system clock 1839 * (if the Clock Security System CSS is enabled). 1840 * @note MSI can not be stopped if it is used as system clock source. 1841 * In this case, you have to select another source of the system 1842 * clock then stop the MSI. 1843 * @note After enabling the MSI, the application software should wait on 1844 * MSIRDY flag to be set indicating that MSI clock is stable and can 1845 * be used as system clock source. 1846 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator 1847 * clock cycles. 1848 * @retval None 1849 */ 1850 #define __HAL_RCC_MSI_ENABLE() LL_RCC_MSI_Enable() 1851 #define __HAL_RCC_MSI_DISABLE() LL_RCC_MSI_Disable() 1852 1853 /** @brief Macro to adjust the Internal Multi Speed oscillator (MSI) calibration value. 1854 * @note The calibration is used to compensate for the variations in voltage 1855 * and temperature that influence the frequency of the internal MSI RC. 1856 * Refer to the Application Note AN3300 for more details on how to 1857 * calibrate the MSI. 1858 * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value 1859 * (default is @ref RCC_MSICALIBRATION_DEFAULT). 1860 * This parameter must be a number between 0 and 255. 1861 * @retval None 1862 */ 1863 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \ 1864 LL_RCC_MSI_SetCalibTrimming(__MSICALIBRATIONVALUE__) 1865 1866 /** 1867 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode 1868 * @note After restart from Reset , the MSI clock is around 4 MHz. 1869 * After stop the startup clock can be MSI (at any of its possible 1870 * frequencies, the one that was used before entering stop mode) or HSI. 1871 * After Standby its frequency can be selected between 4 possible values 1872 * (1, 2, 4 or 8 MHz). 1873 * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready 1874 * (MSIRDY=1). 1875 * @note The MSI clock range after reset can be modified on the fly. 1876 * @param __MSIRANGEVALUE__ specifies the MSI clock range. 1877 * This parameter must be one of the following values: 1878 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz 1879 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz 1880 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz 1881 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz 1882 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 1883 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 1884 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 1885 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 1886 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 1887 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 1888 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 1889 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 1890 * @retval None 1891 */ 1892 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) do { \ 1893 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \ 1894 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \ 1895 } while(0) 1896 1897 /** 1898 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode 1899 * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). 1900 * @param __MSIRANGEVALUE__ specifies the MSI clock range. 1901 * This parameter must be one of the following values: 1902 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 1903 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 1904 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 1905 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 1906 * @retval None 1907 */ 1908 #define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \ 1909 MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U) 1910 1911 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode 1912 * @retval MSI clock range. 1913 * This parameter must be one of the following values: 1914 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz 1915 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz 1916 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz 1917 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz 1918 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 1919 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 1920 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 1921 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 1922 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 1923 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 1924 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 1925 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 1926 */ 1927 #define __HAL_RCC_GET_MSI_RANGE() ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != 0U) ? \ 1928 (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) : \ 1929 (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4)) 1930 1931 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 1932 * @note After enabling the LSI, the application software should wait on 1933 * LSIRDY flag to be set indicating that LSI clock is stable and can 1934 * be used to clock the IWDG and/or the RTC. 1935 * @note LSI can not be disabled if the IWDG is running. 1936 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 1937 * clock cycles. 1938 * @retval None 1939 */ 1940 #define __HAL_RCC_LSI_ENABLE() LL_RCC_LSI_Enable() 1941 #define __HAL_RCC_LSI_DISABLE() LL_RCC_LSI_Disable() 1942 1943 /** 1944 * @brief Macro to configure the External High Speed oscillator (HSE). 1945 * @note Transition RCC_HSE_BYPASS_PWR to RCC_HSE_ON and RCC_HSE_ON to 1946 * RCC_HSE_BYPASS_PWR are not supported by this macro. User should 1947 * request a transition to RCC_HSE_OFF first and then RCC_HSE_ON or 1948 * RCC_HSE_BYPASS_PWR. 1949 * @note After enabling the HSE (RCC_HSE_ON, RCC_HSE_BYPASS_PWR), 1950 * the application software should wait on HSERDY flag to be set indicating 1951 * that HSE clock is stable and can be used to clock the PLL and/or system clock. 1952 * @note HSE state can not be changed if it is used directly or through the 1953 * PLL as system clock. In this case, you have to select another source 1954 * of the system clock then change the HSE state (ex. disable it). 1955 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 1956 * @note PB0 must be configured in analog mode prior enabling the HSE with 1957 * RCC_HSE_BYPASS_PWR. 1958 * @param __STATE__ specifies the new state of the HSE. 1959 * This parameter can be one of the following values: 1960 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag 1961 * goes low after 6 HSE oscillator clock cycles. 1962 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 1963 * @arg @ref RCC_HSE_BYPASS_PWR HSE32 driven from an external TCXO powered by the PB0-VDDTCXO pin. 1964 * @retval None 1965 */ 1966 #define __HAL_RCC_HSE_CONFIG(__STATE__) do { \ 1967 if((__STATE__) == RCC_HSE_ON) \ 1968 { \ 1969 LL_RCC_HSE_Enable(); \ 1970 } \ 1971 else if((__STATE__) == RCC_HSE_BYPASS_PWR) \ 1972 { \ 1973 LL_RCC_HSE_EnableTcxo(); \ 1974 LL_RCC_HSE_Enable(); \ 1975 } \ 1976 else \ 1977 { \ 1978 LL_RCC_HSE_Disable(); \ 1979 LL_RCC_HSE_DisableTcxo(); \ 1980 } \ 1981 } while(0U) 1982 1983 /** @brief Macros to enable or disable the HSE Prescaler 1984 * @note HSE prescaler shall be enabled when HSE is used as 1985 * system clock source and Voltage scaling range 1 1986 * (Low-power range) is selected. 1987 * @retval None 1988 */ 1989 #define __HAL_RCC_HSE_DIV2_ENABLE() LL_RCC_HSE_EnableDiv2() 1990 #define __HAL_RCC_HSE_DIV2_DISABLE() LL_RCC_HSE_DisableDiv2() 1991 1992 /** 1993 * @brief Macro to configure the External Low Speed oscillator (LSE). 1994 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 1995 * supported by this macro. User should request a transition to LSE Off 1996 * first and then LSE On or LSE Bypass. 1997 * @note As the LSE is in the Backup domain and write access is denied to 1998 * this domain after reset, you have to enable write access using 1999 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 2000 * (to be done once after reset). 2001 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 2002 * software should wait on LSERDY flag to be set indicating that LSE clock 2003 * is stable and can be used to clock the RTC. 2004 * @param __STATE__ specifies the new state of the LSE. 2005 * This parameter can be one of the following values: 2006 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 2007 * 6 LSE oscillator clock cycles. 2008 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. 2009 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 2010 * @retval None 2011 */ 2012 #define __HAL_RCC_LSE_CONFIG(__STATE__) do { \ 2013 if((__STATE__) == RCC_LSE_ON) \ 2014 { \ 2015 LL_RCC_LSE_Enable(); \ 2016 } \ 2017 else if((__STATE__) == RCC_LSE_BYPASS) \ 2018 { \ 2019 LL_RCC_LSE_EnableBypass(); \ 2020 LL_RCC_LSE_Enable(); \ 2021 } \ 2022 else \ 2023 { \ 2024 LL_RCC_LSE_Disable(); \ 2025 LL_RCC_LSE_DisableBypass(); \ 2026 } \ 2027 } while(0U) 2028 2029 /** @brief Macro to configure the RTC clock (RTCCLK). 2030 * @note As the RTC clock configuration bits are in the Backup domain and write 2031 * access is denied to this domain after reset, you have to enable write 2032 * access using the Power Backup Access macro before to configure 2033 * the RTC clock source (to be done once after reset). 2034 * @note Once the RTC clock is configured it cannot be changed unless the 2035 * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by 2036 * a Power On Reset (POR). 2037 * 2038 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 2039 * This parameter can be one of the following values:* 2040 * @arg @ref RCC_RTCCLKSOURCE_NONE none clock selected as RTC clock. 2041 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 2042 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 2043 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 2044 * 2045 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 2046 * work in STOP and STANDBY modes, and can be used as wakeup source. 2047 * However, when the HSE clock is used as RTC clock source, the RTC 2048 * cannot be used in STOP and STANDBY modes. 2049 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 2050 * RTC clock source). 2051 * @retval None 2052 */ 2053 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) LL_RCC_SetRTCClockSource(__RTC_CLKSOURCE__) 2054 2055 /** @brief Macro to get the RTC clock source. 2056 * @retval The returned value can be one of the following: 2057 * @arg @ref RCC_RTCCLKSOURCE_NONE none clock selected as RTC clock. 2058 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 2059 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 2060 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 2061 */ 2062 #define __HAL_RCC_GET_RTC_SOURCE() LL_RCC_GetRTCClockSource() 2063 2064 /** @brief Macros to enable or disable the main PLL. 2065 * @note After enabling the main PLL, the application software should wait on 2066 * PLLRDY flag to be set indicating that PLL clock is stable and can 2067 * be used as system clock source. 2068 * @note The main PLL can not be disabled if it is used as system clock source 2069 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 2070 * @retval None 2071 */ 2072 #define __HAL_RCC_PLL_ENABLE() LL_RCC_PLL_Enable() 2073 #define __HAL_RCC_PLL_DISABLE() LL_RCC_PLL_Disable() 2074 2075 /** @brief Macro to configure the PLL clock source. 2076 * @note This function must be used only when the main PLL is disabled. 2077 * @param __PLLSOURCE__ specifies the PLL entry clock source. 2078 * This parameter can be one of the following values: 2079 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 2080 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 2081 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 2082 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 2083 * @retval None 2084 * 2085 */ 2086 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ 2087 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) 2088 /** 2089 * @brief Macro to configure the main PLL clock source, multiplication and division factors. 2090 * @note This function must be used only when the main PLL is disabled. 2091 * 2092 * @param __PLLSOURCE__ specifies the PLL entry clock source. 2093 * This parameter can be one of the following values: 2094 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 2095 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 2096 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 2097 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 2098 * 2099 * @param __PLLM__ specifies the division factor for PLL VCO input clock. 2100 * This parameter must be a value of @ref RCC_PLLM_Clock_Divider. 2101 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 2102 * frequency ranges from 2.66 to 16 MHz. It is recommended to select a frequency 2103 * of 16 MHz to limit PLL jitter. 2104 * 2105 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. 2106 * This parameter must be a number between 6 and 127. 2107 * @note You have to set the PLLN parameter correctly to ensure that the VCO 2108 * output frequency is between 96 and 344 MHz. 2109 * 2110 * @param __PLLP__ specifies the division factor for ADC clock. 2111 * This parameter must be a value of @ref RCC_PLLP_Clock_Divider. 2112 * 2113 * @param __PLLQ__ specifies the division factor for I2S2 and RNG clocks. 2114 * This parameter must be a value of @ref RCC_PLLQ_Clock_Divider 2115 * 2116 * @note RNG need a frequency lower than or equal to 48 MHz to work correctly. 2117 * 2118 * @param __PLLR__ specifies the division factor for the main system clock. 2119 * This parameter must be a value of @ref RCC_PLLR_Clock_Divider 2120 * @note You have to set the PLLR parameter correctly to not exceed 48 MHZ. 2121 * @retval None 2122 */ 2123 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ 2124 MODIFY_REG(RCC->PLLCFGR, \ 2125 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ 2126 RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR), \ 2127 ((uint32_t) (__PLLSOURCE__) | \ 2128 (uint32_t) (__PLLM__) | \ 2129 (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 2130 (uint32_t) (__PLLP__) | \ 2131 (uint32_t) (__PLLQ__) | \ 2132 (uint32_t) (__PLLR__))) 2133 2134 /** @brief Macro to get the oscillator used as PLL clock source. 2135 * @retval The oscillator used as PLL clock source. The returned value can be one 2136 * of the following: 2137 * @arg @ref RCC_PLLSOURCE_NONE No oscillator is used as PLL clock source. 2138 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator is used as PLL clock source. 2139 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source. 2140 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source. 2141 */ 2142 #define __HAL_RCC_GET_PLL_OSCSOURCE() LL_RCC_PLL_GetMainSource() 2143 2144 /** 2145 * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_I2S2CLK, RCC_PLL_RNGCLK, RCC_PLL_ADCCLK) 2146 * @note Enabling/disabling clock outputs RCC_PLL_I2S2CLK, RCC_PLL_RNGCLK and RCC_PLL_ADCCLK can be done at anytime 2147 * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot 2148 * be stopped if used as System Clock. 2149 * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. 2150 * This parameter can be one or a combination of the following values: 2151 * @arg @ref RCC_PLL_ADCCLK This clock is used to generate the clock for ADC 2152 * @arg @ref RCC_PLL_I2S2CLK This Clock is used to generate the clock for the I2S 2153 * @arg @ref RCC_PLL_RNGCLK This clock is used to generate the clock for RNG 2154 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 48 MHz) 2155 * @retval None 2156 */ 2157 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 2158 2159 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 2160 2161 /** 2162 * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_I2S2CLK, RCC_PLL_RNGCLK, RCC_PLL_ADCCLK) 2163 * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. 2164 * This parameter can be one of the following values: 2165 * @arg @ref RCC_PLL_ADCCLK same 2166 * @arg @ref RCC_PLL_I2S2CLK This Clock is used to generate the clock for the I2S 2167 * @arg @ref RCC_PLL_RNGCLK This clock is used to generate the clock for RNG 2168 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 48 MHz) 2169 * @retval SET / RESET 2170 */ 2171 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 2172 2173 /** 2174 * @brief Macro to configure the system clock source. 2175 * @param __SYSCLKSOURCE__ specifies the system clock source. 2176 * This parameter can be one of the following values: 2177 * @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source. 2178 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. 2179 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. 2180 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. 2181 * @retval None 2182 */ 2183 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) LL_RCC_SetSysClkSource(__SYSCLKSOURCE__) 2184 2185 /** @brief Macro to get the clock source used as system clock. 2186 * @retval The clock source used as system clock. The returned value can be one 2187 * of the following: 2188 * @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock. 2189 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock. 2190 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock. 2191 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock. 2192 */ 2193 #define __HAL_RCC_GET_SYSCLK_SOURCE() LL_RCC_GetSysClkSource() 2194 2195 /** 2196 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 2197 * @note As the LSE is in the Backup domain and write access is denied to 2198 * this domain after reset, you have to enable write access using 2199 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 2200 * (to be done once after reset). 2201 * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. 2202 * This parameter can be one of the following values: 2203 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 2204 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 2205 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 2206 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 2207 * @retval None 2208 */ 2209 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) LL_RCC_LSE_SetDriveCapability(__LSEDRIVE__) 2210 2211 /** 2212 * @brief Macro to configure the wake up from stop clock. 2213 * @param __STOPWUCLK__ specifies the clock source used after wake up from stop. 2214 * This parameter can be one of the following values: 2215 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source 2216 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source 2217 * @retval None 2218 */ 2219 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) LL_RCC_SetClkAfterWakeFromStop(__STOPWUCLK__) 2220 2221 2222 /** @brief Macro to configure the MCO clock. 2223 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 2224 * This parameter can be one of the following values: 2225 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled 2226 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source 2227 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source 2228 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source 2229 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source 2230 * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source 2231 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source 2232 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source 2233 * @arg @ref RCC_MCO1SOURCE_PLLPCLK main PLLP clock selected as MCO source 2234 * @arg @ref RCC_MCO1SOURCE_PLLQCLK main PLLQ clock selected as MCO source 2235 * @param __MCODIV__ specifies the MCO clock prescaler. 2236 * This parameter can be one of the following values: 2237 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 2238 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 2239 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 2240 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 2241 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 2242 */ 2243 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) LL_RCC_ConfigMCO((__MCOCLKSOURCE__), (__MCODIV__)) 2244 2245 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 2246 * @brief macros to manage the specified RCC Flags and interrupts. 2247 * @{ 2248 */ 2249 2250 /** @brief Enable RCC interrupt. 2251 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. 2252 * This parameter can be any combination of the following values: 2253 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt enable 2254 * @arg @ref RCC_IT_LSERDY LSE ready interrupt enable 2255 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt enable 2256 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt enable 2257 * @arg @ref RCC_IT_HSERDY HSE ready interrupt enable 2258 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt enable 2259 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt enable 2260 * @retval None 2261 */ 2262 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 2263 2264 /** @brief Disable RCC interrupt. 2265 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. 2266 * This parameter can be any combination of the following values: 2267 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt enable 2268 * @arg @ref RCC_IT_LSERDY LSE ready interrupt enable 2269 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt enable 2270 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt enable 2271 * @arg @ref RCC_IT_HSERDY HSE ready interrupt enable 2272 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt enable 2273 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt enable 2274 * @retval None 2275 */ 2276 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 2277 2278 /** @brief Clear RCC interrupt pending bits (Perform Byte access to RCC_CICR[17:0] 2279 * bits to clear the selected interrupt pending bits. 2280 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 2281 * This parameter can be any combination of the following values: 2282 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt clear 2283 * @arg @ref RCC_IT_LSERDY LSE ready interrupt clear 2284 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt clear 2285 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt clear 2286 * @arg @ref RCC_IT_HSERDY HSE ready interrupt clear 2287 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt clear 2288 * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt clear 2289 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt clear 2290 */ 2291 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) 2292 2293 /** @brief Check whether the RCC interrupt has occurred or not. 2294 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 2295 * This parameter can be one of the following values: 2296 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt flag 2297 * @arg @ref RCC_IT_LSERDY LSE ready interrupt flag 2298 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt flag 2299 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt flag 2300 * @arg @ref RCC_IT_HSERDY HSE ready interrupt flag 2301 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt flag 2302 * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt flag 2303 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt flag 2304 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 2305 */ 2306 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 2307 2308 /** @brief Set RMVF bit to clear the reset flags. 2309 * The reset flags are: LPWRRSTF, WWDGRSTF, IWDGRSTF, SFTRSTF, 2310 BORRSTF, PINRSTF, OBLRSTF, and RFILARSTF. 2311 * @retval None 2312 */ 2313 #define __HAL_RCC_CLEAR_RESET_FLAGS() LL_RCC_ClearResetFlags() 2314 2315 /** @brief Check whether the selected RCC flag is set or not. 2316 * @param __FLAG__ specifies the flag to check. 2317 * This parameter can be one of the following values: 2318 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready 2319 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 2320 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 2321 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready 2322 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 2323 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 2324 * @arg @ref RCC_FLAG_LSESYSRDY LSE system clock ready flag 2325 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 2326 * @arg @ref RCC_FLAG_RFRST Sub-GHz radio reset flag 2327 * @arg @ref RCC_FLAG_RFILARSTF Sub-GHz radio illegal command flag 2328 * @arg @ref RCC_FLAG_BORRST BOR reset 2329 * @arg @ref RCC_FLAG_OBLRST OBLRST reset 2330 * @arg @ref RCC_FLAG_PINRST Pin reset 2331 * @arg @ref RCC_FLAG_SFTRST Software reset 2332 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 2333 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 2334 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 2335 * @retval The new state of __FLAG__ (TRUE or FALSE). 2336 */ 2337 #define __HAL_RCC_GET_FLAG(__FLAG__) \ 2338 (((((((__FLAG__) >> REG_INDEX_POS) == CR_REG_INDEX) ? RCC->CR : \ 2339 ((((__FLAG__) >> REG_INDEX_POS) == BDCR_REG_INDEX) ? RCC->BDCR : \ 2340 ((((__FLAG__) >> REG_INDEX_POS) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR))) & \ 2341 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1UL : 0UL) 2342 2343 /** 2344 * @} 2345 */ 2346 2347 /** 2348 * @} 2349 */ 2350 2351 /* Include RCC HAL Extended module */ 2352 #include "stm32wlxx_hal_rcc_ex.h" 2353 2354 /* Exported functions --------------------------------------------------------*/ 2355 /** @addtogroup RCC_Exported_Functions 2356 * @{ 2357 */ 2358 2359 2360 /** @addtogroup RCC_Exported_Functions_Group1 2361 * @{ 2362 */ 2363 2364 /* Initialization and de-initialization functions ****************************/ 2365 HAL_StatusTypeDef HAL_RCC_DeInit(void); 2366 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 2367 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 2368 2369 /** 2370 * @} 2371 */ 2372 2373 /** @addtogroup RCC_Exported_Functions_Group2 2374 * @{ 2375 */ 2376 2377 /* Peripheral Control functions **********************************************/ 2378 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 2379 void HAL_RCC_EnableCSS(void); 2380 uint32_t HAL_RCC_GetSysClockFreq(void); 2381 2382 uint32_t HAL_RCC_GetHCLKFreq(void); 2383 #if defined(DUAL_CORE) 2384 uint32_t HAL_RCC_GetHCLK2Freq(void); 2385 #endif /* DUAL_CORE */ 2386 uint32_t HAL_RCC_GetHCLK3Freq(void); 2387 2388 uint32_t HAL_RCC_GetPCLK1Freq(void); 2389 uint32_t HAL_RCC_GetPCLK2Freq(void); 2390 2391 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 2392 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 2393 /* LSE & HSE CSS NMI IRQ handler */ 2394 void HAL_RCC_NMI_IRQHandler(void); 2395 /* User Callbacks in non blocking mode (IT mode) */ 2396 void HAL_RCC_CSSCallback(void); 2397 2398 uint32_t HAL_RCC_GetResetSource(void); 2399 /** 2400 * @} 2401 */ 2402 2403 /** 2404 * @} 2405 */ 2406 2407 /** 2408 * @} 2409 */ 2410 2411 /** 2412 * @} 2413 */ 2414 2415 #ifdef __cplusplus 2416 } 2417 #endif 2418 2419 #endif /* STM32WLxx_HAL_RCC_H */ 2420
