1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL SYSTEM driver contains a set of generic APIs that can be
23 used by user:
24 (+) Some of the FLASH features need to be handled in the SYSTEM file.
25 (+) Access to DBGCMU registers
26 (+) Access to SYSCFG registers
27 (+) Access to VREFBUF registers
28 @endverbatim
29 ******************************************************************************
30 */
31
32 /* Define to prevent recursive inclusion -------------------------------------*/
33 #ifndef STM32U5xx_LL_SYSTEM_H
34 #define STM32U5xx_LL_SYSTEM_H
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /* Includes ------------------------------------------------------------------*/
41 #include "stm32u5xx.h"
42
43 /** @addtogroup STM32U5xx_LL_Driver
44 * @{
45 */
46
47 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF)
48
49 /** @defgroup SYSTEM_LL SYSTEM
50 * @{
51 */
52
53 /* Private types -------------------------------------------------------------*/
54 /* Private variables ---------------------------------------------------------*/
55
56 /* Private constants ---------------------------------------------------------*/
57 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
58 * @{
59 */
60
61 /**
62 * @brief Power-down in Run mode Flash key
63 */
64 #define LL_FLASH_PDKEY1_1 0x04152637U /*!< Flash Bank1 power down key1 */
65 #define LL_FLASH_PDKEY1_2 0xFAFBFCFDU /*!< Flash Bank1 power down key2: used with FLASH_PDKEY1
66 to unlock the RUN_PD bit in FLASH_ACR */
67
68 #define LL_FLASH_PDKEY2_1 0x40516273U /*!< Flash Bank2 power down key1 */
69 #define LL_FLASH_PDKEY2_2 0xAFBFCFDFU /*!< Flash Bank2 power down key2: used with FLASH_PDKEY2_1
70 to unlock the RUN_PD bit in FLASH_ACR */
71 /**
72 * @}
73 */
74
75 /** @defgroup SYSTEM_LL_EC_CS1 SYSCFG Vdd compensation cell Code selection
76 * @{
77 */
78 #define LL_SYSCFG_VDD_CELL_CODE 0U /*VDD I/Os code from the cell
79 (available in the SYSCFG_CCVR)*/
80 #define LL_SYSCFG_VDD_REGISTER_CODE SYSCFG_CCCSR_CS1 /*VDD I/Os code from the SYSCFG compensation
81 cell code register (SYSCFG_CCCR)*/
82 /**
83 * @}
84 */
85
86 /** @defgroup SYSTEM_LL_EC_CS2 SYSCFG VddIO2 compensation cell Code selection
87 * @{
88 */
89 #define LL_SYSCFG_VDDIO2_CELL_CODE 0U /*VDDIO2 I/Os code from the cell
90 (available in the SYSCFG_CCVR)*/
91 #define LL_SYSCFG_VDDIO2_REGISTER_CODE SYSCFG_CCCSR_CS2 /*VDDIO2 I/Os code from the SYSCFG compensation
92 cell code register (SYSCFG_CCCR)*/
93 /**
94 * @}
95 */
96
97 #if defined(SYSCFG_CCCSR_CS3)
98 /** @defgroup SYSTEM_LL_EC_CS3 SYSCFG VddHSPI compensation cell Code selection
99 * @{
100 */
101 #define LL_SYSCFG_VDDHSPI_CELL_CODE 0U /*VDD HSPI I/Os code from the cell
102 (available in the SYSCFG_CCVR)*/
103 #define LL_SYSCFG_VDDHSPI_REGISTER_CODE SYSCFG_CCCSR_CS3 /*VDD HSPI I/Os code from the SYSCFG compensation
104 cell code register (SYSCFG_CCCR)*/
105 /**
106 * @}
107 */
108 #endif /* SYSCFG_CCCSR_CS3 */
109
110 /** @defgroup SYSTEM_LL_EC_ERASE_MEMORIES_STATUS SYSCFG MEMORIES ERASE STATUS
111 * @{
112 */
113 #define LL_SYSCFG_MEMORIES_ERASE_ON_GOING 0U /*Memory erase on going*/
114 #define LL_SYSCFG_MEMORIES_ERASE_ENDED SYSCFG_MESR_MCLR /*Memory erase done */
115 /**
116 * @}
117 */
118
119 /* Private macros ------------------------------------------------------------*/
120
121 /* Exported types ------------------------------------------------------------*/
122 /* Exported constants --------------------------------------------------------*/
123 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
124 * @{
125 */
126
127 /** @defgroup SYSTEM_LL_EC_FASTMODEPLUS SYSCFG FASTMODEPLUS
128 * @{
129 */
130 #define LL_SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
131 #define LL_SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
132 #define LL_SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
133 #define LL_SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
134 /**
135 * @}
136 */
137
138 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
139 * @{
140 */
141 #define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
142 with Break Input of TIM1/8/15/16/17 */
143 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
144 with TIM1/8/15/16/17 Break Input and also the PVDE
145 and PLS bits of the Power Control Interface */
146 #define LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM ECC double error signal
147 with Break Input of TIM1/8/15/16/17 */
148 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM33
149 with Break Input of TIM1/15/16/17 */
150 /**
151 * @}
152 */
153
154 /** @defgroup SYSTEM_LL_EC_SECURE_ATTRIBUTES Secure attributes
155 * @note Only available when system implements security (TZEN=1)
156 * @{
157 */
158 #define LL_SYSCFG_CLOCK_SEC SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock configuration secure-only access */
159 #define LL_SYSCFG_CLOCK_NSEC 0U /*!< SYSCFG clock configuration secure/non-secure access */
160 #define LL_SYSCFG_CLASSB_SEC SYSCFG_SECCFGR_CLASSBSEC /*!< Class B configuration secure-only access */
161 #define LL_SYSCFG_CLASSB_NSEC 0U /*!< Class B configuration secure/non-secure access */
162 #define LL_SYSCFG_FPU_SEC SYSCFG_SECCFGR_FPUSEC /*!< FPU configuration secure-only access */
163 #define LL_SYSCFG_FPU_NSEC 0U /*!< FPU configuration secure/non-secure access */
164 /**
165 * @}
166 */
167
168 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
169 * @{
170 */
171 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
172 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
173 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
174 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
175 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
176 /**
177 * @}
178 */
179
180 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
181 * @{
182 */
183 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/
184 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/
185 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when the core is halted*/
186 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /*!< The counter clock of TIM5 is stopped when the core is halted*/
187 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /*!< The counter clock of TIM6 is stopped when the core is halted*/
188 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /*!< The counter clock of TIM7 is stopped when the core is halted*/
189 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/
190 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/
191 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/
192 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/
193 /**
194 * @}
195 */
196
197 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
198 * @{
199 */
200 #define LL_DBGMCU_APB1_GRP2_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP /*!< The I2C4 SMBus timeout is frozen*/
201 #define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/
202 #define LL_DBGMCU_APB1_GRP2_I2C5_STOP DBGMCU_APB1FZR2_DBG_I2C5_STOP /*!< The I2C5 SMBus timeout is frozen*/
203 #define LL_DBGMCU_APB1_GRP2_I2C6_STOP DBGMCU_APB1FZR2_DBG_I2C6_STOP /*!< The I2C6 SMBus timeout is frozen*/
204 /**
205 * @}
206 */
207
208 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
209 * @{
210 */
211 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted*/
212 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP /*!< The counter clock of TIM8 is stopped when the core is halted*/
213 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP /*!< The counter clock of TIM15 is stopped when the core is halted*/
214 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted*/
215 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted*/
216 /**
217 * @}
218 */
219
220 /** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP
221 * @{
222 */
223 #define LL_DBGMCU_APB3_GRP1_I2C3_STOP DBGMCU_APB3FZR_DBG_I2C3_STOP /*!< The counter clock of I2C3 is stopped when the core is halted*/
224 #define LL_DBGMCU_APB3_GRP1_LPTIM1_STOP DBGMCU_APB3FZR_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
225 #define LL_DBGMCU_APB3_GRP1_LPTIM3_STOP DBGMCU_APB3FZR_DBG_LPTIM3_STOP /*!< The counter clock of LPTIM3 is stopped when the core is halted*/
226 #define LL_DBGMCU_APB3_GRP1_LPTIM4_STOP DBGMCU_APB3FZR_DBG_LPTIM4_STOP /*!< The counter clock of LPTIM4 is stopped when the core is halted*/
227 #define LL_DBGMCU_APB3_GRP1_RTC_STOP DBGMCU_APB3FZR_DBG_RTC_STOP /*!< The counter clock of RTC is stopped when the core is halted*/
228 /**
229 * @}
230 */
231
232 /** @defgroup SYSTEM_LL_EC_AHB1_GRP1_STOP_IP DBGMCU AHB1 GRP1 STOP IP
233 * @{
234 */
235 #define LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP DBGMCU_AHB1FZR_DBG_GPDMA0_STOP /*!< The counter clock of GPDMA0 is stopped when the core is halted*/
236 #define LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_STOP /*!< The counter clock of GPDMA1 is stopped when the core is halted*/
237 #define LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP DBGMCU_AHB1FZR_DBG_GPDMA2_STOP /*!< The counter clock of GPDMA2 is stopped when the core is halted*/
238 #define LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP DBGMCU_AHB1FZR_DBG_GPDMA3_STOP /*!< The counter clock of GPDMA3 is stopped when the core is halted*/
239 #define LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP DBGMCU_AHB1FZR_DBG_GPDMA4_STOP /*!< The counter clock of GPDMA4 is stopped when the core is halted*/
240 #define LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP DBGMCU_AHB1FZR_DBG_GPDMA5_STOP /*!< The counter clock of GPDMA5 is stopped when the core is halted*/
241 #define LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP DBGMCU_AHB1FZR_DBG_GPDMA6_STOP /*!< The counter clock of GPDMA6 is stopped when the core is halted*/
242 #define LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP DBGMCU_AHB1FZR_DBG_GPDMA7_STOP /*!< The counter clock of GPDMA7 is stopped when the core is halted*/
243 #define LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP DBGMCU_AHB1FZR_DBG_GPDMA8_STOP /*!< The counter clock of GPDMA8 is stopped when the core is halted*/
244 #define LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP DBGMCU_AHB1FZR_DBG_GPDMA9_STOP /*!< The counter clock of GPDMA9 is stopped when the core is halted*/
245 #define LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP DBGMCU_AHB1FZR_DBG_GPDMA10_STOP /*!< The counter clock of GPDMA10 is stopped when the core is halted*/
246 #define LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP DBGMCU_AHB1FZR_DBG_GPDMA11_STOP /*!< The counter clock of GPDMA11 is stopped when the core is halted*/
247 #define LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP DBGMCU_AHB1FZR_DBG_GPDMA12_STOP /*!< The counter clock of GPDMA12 is stopped when the core is halted*/
248 #define LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP DBGMCU_AHB1FZR_DBG_GPDMA13_STOP /*!< The counter clock of GPDMA13 is stopped when the core is halted*/
249 #define LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP DBGMCU_AHB1FZR_DBG_GPDMA14_STOP /*!< The counter clock of GPDMA14 is stopped when the core is halted*/
250 #define LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP DBGMCU_AHB1FZR_DBG_GPDMA15_STOP /*!< The counter clock of GPDMA15 is stopped when the core is halted*/
251 /**
252 * @}
253 */
254
255 /** @defgroup SYSTEM_LL_EC_AHB3_GRP1_STOP_IP DBGMCU AHB3 GRP1 STOP IP
256 * @{
257 */
258 #define LL_DBGMCU_AHB3_GRP1_LPDMA0_STOP DBGMCU_AHB3FZR_DBG_LPDMA0_STOP /*!< The counter clock of LPDMA0 is stopped when the core is halted*/
259 #define LL_DBGMCU_AHB3_GRP1_LPDMA1_STOP DBGMCU_AHB3FZR_DBG_LPDMA1_STOP /*!< The counter clock of LPDMA1 is stopped when the core is halted*/
260 #define LL_DBGMCU_AHB3_GRP1_LPDMA2_STOP DBGMCU_AHB3FZR_DBG_LPDMA2_STOP /*!< The counter clock of LPDMA2 is stopped when the core is halted*/
261 #define LL_DBGMCU_AHB3_GRP1_LPDMA3_STOP DBGMCU_AHB3FZR_DBG_LPDMA3_STOP /*!< The counter clock of LPDMA3 is stopped when the core is halted*/
262 /**
263 * @}
264 */
265
266 #if defined(VREFBUF)
267 /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
268 * @{
269 */
270 #define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
271 #define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */
272 #define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 0 (VREF_OUT3) */
273 #define LL_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_2 /*!< Voltage reference scale 1 (VREF_OUT4) */
274 /**
275 * @}
276 */
277 #endif /* VREFBUF */
278
279 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
280 * @{
281 */
282 #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH zero wait state */
283 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH one wait state */
284 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH two wait states */
285 #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH three wait states */
286 #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH four wait states */
287 #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait states */
288 #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
289 #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */
290 #define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */
291 #define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */
292 #define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */
293 #define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */
294 #define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */
295 #define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */
296 #define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */
297 #define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */
298 /**
299 * @}
300 */
301
302 /**
303 * @}
304 */
305
306 /* Exported macro ------------------------------------------------------------*/
307
308 /* Exported functions --------------------------------------------------------*/
309 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
310 * @{
311 */
312
313 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
314 * @{
315 */
316
317 /**
318 * @brief Enable I/O analog switches supplied by VDD.
319 * @rmtoll SYSCFG_CFGR1 ANASWVDD LL_SYSCFG_EnableAnalogSwitchVdd
320 * @retval None
321 */
LL_SYSCFG_EnableAnalogSwitchVdd(void)322 __STATIC_INLINE void LL_SYSCFG_EnableAnalogSwitchVdd(void)
323 {
324 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
325 }
326
327 /**
328 * @brief Disable I/O analog switches supplied by VDD.
329 * @note I/O analog switches are supplied by VDDA or booster
330 * when booster in on.
331 * Dedicated voltage booster (supplied by VDD) is the recommended
332 * configuration with low VDDA voltage operation.
333 * @rmtoll SYSCFG_CFGR1 ANASWVDD LL_SYSCFG_DisableAnalogSwitchVdd
334 * @retval None
335 */
LL_SYSCFG_DisableAnalogSwitchVdd(void)336 __STATIC_INLINE void LL_SYSCFG_DisableAnalogSwitchVdd(void)
337 {
338 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
339 }
340
341 /**
342 * @brief Enable I/O analog switch voltage booster.
343 * @note When voltage booster is enabled, I/O analog switches are supplied
344 * by a dedicated voltage booster, from VDD power domain. This is
345 * the recommended configuration with low VDDA voltage operation.
346 * @note The I/O analog switch voltage booster is relevant for peripherals
347 * using I/O in analog input: ADC, COMP, OPAMP.
348 * However, COMP and OPAMP inputs have a high impedance and
349 * voltage booster do not impact performance significantly.
350 * Therefore, the voltage booster is mainly intended for
351 * usage with ADC.
352 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
353 * @retval None
354 */
LL_SYSCFG_EnableAnalogBooster(void)355 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
356 {
357 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
358 }
359
360 /**
361 * @brief Disable I/O analog switch voltage booster.
362 * @note When voltage booster is enabled, I/O analog switches are supplied
363 * by a dedicated voltage booster, from VDD power domain. This is
364 * the recommended configuration with low VDDA voltage operation.
365 * @note The I/O analog switch voltage booster is relevant for peripherals
366 * using I/O in analog input: ADC, COMP, OPAMP.
367 * However, COMP and OPAMP inputs have a high impedance and
368 * voltage booster do not impact performance significantly.
369 * Therefore, the voltage booster is mainly intended for
370 * usage with ADC.
371 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
372 * @retval None
373 */
LL_SYSCFG_DisableAnalogBooster(void)374 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
375 {
376 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
377 }
378
379 /**
380 * @brief Enable the fast mode plus driving capability.
381 * @rmtoll SYSCFG_CFGR1 PBx_FMP LL_SYSCFG_EnableFastModePlus
382 * @param ConfigFastModePlus This parameter can be a combination of the following values:
383 * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB6
384 * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB7
385 * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB8
386 * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB9
387 * @retval None
388 */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)389 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
390 {
391 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
392 }
393
394 /**
395 * @brief Disable the fast mode plus driving capability.
396 * @rmtoll SYSCFG_CFGR1 PBx_FMP LL_SYSCFG_DisableFastModePlus
397 * @param ConfigFastModePlus This parameter can be a combination of the following values:
398 * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB6
399 * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB7
400 * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB8
401 * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB9
402 * @retval None
403 */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)404 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
405 {
406 CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
407 }
408
409 /**
410 * @brief Enable Floating Point Unit Invalid operation Interrupt
411 * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
412 * @retval None
413 */
LL_SYSCFG_EnableIT_FPU_IOC(void)414 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
415 {
416 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0);
417 }
418
419 /**
420 * @brief Enable Floating Point Unit Divide-by-zero Interrupt
421 * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
422 * @retval None
423 */
LL_SYSCFG_EnableIT_FPU_DZC(void)424 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
425 {
426 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1);
427 }
428
429 /**
430 * @brief Enable Floating Point Unit Underflow Interrupt
431 * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
432 * @retval None
433 */
LL_SYSCFG_EnableIT_FPU_UFC(void)434 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
435 {
436 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2);
437 }
438
439 /**
440 * @brief Enable Floating Point Unit Overflow Interrupt
441 * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
442 * @retval None
443 */
LL_SYSCFG_EnableIT_FPU_OFC(void)444 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
445 {
446 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3);
447 }
448
449 /**
450 * @brief Enable Floating Point Unit Input denormal Interrupt
451 * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
452 * @retval None
453 */
LL_SYSCFG_EnableIT_FPU_IDC(void)454 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
455 {
456 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4);
457 }
458
459 /**
460 * @brief Enable Floating Point Unit Inexact Interrupt
461 * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
462 * @retval None
463 */
LL_SYSCFG_EnableIT_FPU_IXC(void)464 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
465 {
466 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5);
467 }
468
469 /**
470 * @brief Disable Floating Point Unit Invalid operation Interrupt
471 * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
472 * @retval None
473 */
LL_SYSCFG_DisableIT_FPU_IOC(void)474 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
475 {
476 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0);
477 }
478
479 /**
480 * @brief Disable Floating Point Unit Divide-by-zero Interrupt
481 * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
482 * @retval None
483 */
LL_SYSCFG_DisableIT_FPU_DZC(void)484 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
485 {
486 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1);
487 }
488
489 /**
490 * @brief Disable Floating Point Unit Underflow Interrupt
491 * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
492 * @retval None
493 */
LL_SYSCFG_DisableIT_FPU_UFC(void)494 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
495 {
496 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2);
497 }
498
499 /**
500 * @brief Disable Floating Point Unit Overflow Interrupt
501 * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
502 * @retval None
503 */
LL_SYSCFG_DisableIT_FPU_OFC(void)504 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
505 {
506 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3);
507 }
508
509 /**
510 * @brief Disable Floating Point Unit Input denormal Interrupt
511 * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
512 * @retval None
513 */
LL_SYSCFG_DisableIT_FPU_IDC(void)514 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
515 {
516 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4);
517 }
518
519 /**
520 * @brief Disable Floating Point Unit Inexact Interrupt
521 * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
522 * @retval None
523 */
LL_SYSCFG_DisableIT_FPU_IXC(void)524 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
525 {
526 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5);
527 }
528
529 /**
530 * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
531 * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
532 * @retval State of bit (1 or 0).
533 */
LL_SYSCFG_IsEnabledIT_FPU_IOC(void)534 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
535 {
536 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0) == SYSCFG_FPUIMR_FPU_IE_0) ? 1UL : 0UL);
537 }
538
539 /**
540 * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
541 * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
542 * @retval State of bit (1 or 0).
543 */
LL_SYSCFG_IsEnabledIT_FPU_DZC(void)544 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
545 {
546 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1) == SYSCFG_FPUIMR_FPU_IE_1) ? 1UL : 0UL);
547 }
548
549 /**
550 * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
551 * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
552 * @retval State of bit (1 or 0).
553 */
LL_SYSCFG_IsEnabledIT_FPU_UFC(void)554 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
555 {
556 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2) == SYSCFG_FPUIMR_FPU_IE_2) ? 1UL : 0UL);
557 }
558
559 /**
560 * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
561 * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
562 * @retval State of bit (1 or 0).
563 */
LL_SYSCFG_IsEnabledIT_FPU_OFC(void)564 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
565 {
566 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3) == SYSCFG_FPUIMR_FPU_IE_3) ? 1UL : 0UL);
567 }
568
569 /**
570 * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
571 * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
572 * @retval State of bit (1 or 0).
573 */
LL_SYSCFG_IsEnabledIT_FPU_IDC(void)574 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
575 {
576 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4) == SYSCFG_FPUIMR_FPU_IE_4) ? 1UL : 0UL);
577 }
578
579 /**
580 * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
581 * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
582 * @retval State of bit (1 or 0).
583 */
LL_SYSCFG_IsEnabledIT_FPU_IXC(void)584 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
585 {
586 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5) == SYSCFG_FPUIMR_FPU_IE_5) ? 1UL : 0UL);
587 }
588
589 /**
590 * @brief Set connections to TIM1/8/15/16/17 Break inputs
591 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
592 * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
593 * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
594 * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
595 * @param Break This parameter can be a combination of the following values:
596 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
597 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
598 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK
599 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
600 * @retval None
601 */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)602 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
603 {
604 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
605 }
606
607 /**
608 * @brief Get connections to TIM1/8/15/16/17 Break inputs
609 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
610 * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
611 * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
612 * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
613 * @retval Returned value can be can be a combination of the following values:
614 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
615 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
616 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK
617 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
618 */
LL_SYSCFG_GetTIMBreakInputs(void)619 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
620 {
621 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | \
622 SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
623 }
624
625
626
627 /** @defgroup SYSTEM_LL_EF_SYSCFG_Secure_Management Secure Management
628 * @{
629 */
630
631 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
632
633 /**
634 * @brief Configure Secure mode
635 * @note Only available from secure state when system implements security (TZEN=1)
636 * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n
637 * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n
638 * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure
639 * @param Configuration This parameter shall be the full combination
640 * of the following values:
641 * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC
642 * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC
643 * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC
644 * @retval None
645 */
LL_SYSCFG_ConfigSecure(uint32_t Configuration)646 __STATIC_INLINE void LL_SYSCFG_ConfigSecure(uint32_t Configuration)
647 {
648 WRITE_REG(SYSCFG->SECCFGR, Configuration);
649 }
650
651 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
652
653 /**
654 * @brief Get Secure mode configuration
655 * @note Only available when system implements security (TZEN=1)
656 * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n
657 * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n
658 * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure
659 * @retval Returned value is the combination of the following values:
660 * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC
661 * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC
662 * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC
663 */
LL_SYSCFG_GetConfigSecure(void)664 __STATIC_INLINE uint32_t LL_SYSCFG_GetConfigSecure(void)
665 {
666 return (uint32_t)(READ_BIT(SYSCFG->SECCFGR, 0xBU));
667 }
668
669 /**
670 * @}
671 */
672
673 /**
674 * @}
675 */
676
677 /** @defgroup SYSTEM_LL_EF_COMPENSATION SYSCFG COMPENSATION
678 * @{
679 */
680
681 /**
682 * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDD
683 * @rmtoll CCVR PCV1 LL_SYSCFG_GetPMOSVddCompensationValue
684 * @retval Returned value is the PMOS compensation cell
685 */
LL_SYSCFG_GetPMOSVddCompensationValue(void)686 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationValue(void)
687 {
688 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV1));
689 }
690
691 /**
692 * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDD
693 * @rmtoll CCVR NCV1 LL_SYSCFG_GetNMOSVddCompensationValue
694 * @retval Returned value is the NMOS compensation cell
695 */
LL_SYSCFG_GetNMOSVddCompensationValue(void)696 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationValue(void)
697 {
698 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV1));
699 }
700
701 /**
702 * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDDIO2
703 * @rmtoll CCVR PCV2 LL_SYSCFG_GetPMOSVddIO2CompensationValue
704 * @retval Returned value is the PMOS compensation cell
705 */
LL_SYSCFG_GetPMOSVddIO2CompensationValue(void)706 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationValue(void)
707 {
708 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV2));
709 }
710
711 /**
712 * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDDIO2
713 * @rmtoll CCVR NCV2 LL_SYSCFG_GetNMOSVddIO2CompensationValue
714 * @retval Returned value is the NMOS compensation cell
715 */
LL_SYSCFG_GetNMOSVddIO2CompensationValue(void)716 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationValue(void)
717 {
718 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV2));
719 }
720
721 #if defined(SYSCFG_CCVR_PCV3)
722 /**
723 * @brief Get the compensation cell value of the HSPI IO PMOS transistor supplied by VDD
724 * @rmtoll CCVR PCV3 LL_SYSCFG_GetPMOSVddHSPICompensationValue
725 * @retval Returned value is the PMOS compensation cell
726 */
LL_SYSCFG_GetPMOSVddHSPICompensationValue(void)727 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddHSPICompensationValue(void)
728 {
729 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV3));
730 }
731
732 /**
733 * @brief Get the compensation cell value of the HSPI IO NMOS transistor supplied by VDD
734 * @rmtoll CCVR NCV3 LL_SYSCFG_GetNMOSVddHSPICompensationValue
735 * @retval Returned value is the NMOS compensation cell
736 */
LL_SYSCFG_GetNMOSVddHSPICompensationValue(void)737 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddHSPICompensationValue(void)
738 {
739 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV3));
740 }
741 #endif /* SYSCFG_CCVR_PCV3 */
742
743 /**
744 * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDD
745 * @rmtoll CCCR PCC1 LL_SYSCFG_SetPMOSVddCompensationCode
746 * @param PMOSCode PMOS compensation code
747 * This code is applied to the PMOS compensation cell when the CS1 bit of the
748 * SYSCFG_CCCSR is set
749 * @retval None
750 */
LL_SYSCFG_SetPMOSVddCompensationCode(uint32_t PMOSCode)751 __STATIC_INLINE void LL_SYSCFG_SetPMOSVddCompensationCode(uint32_t PMOSCode)
752 {
753 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC1, PMOSCode << SYSCFG_CCCR_PCC1_Pos);
754 }
755
756 /**
757 * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDD
758 * @rmtoll CCCR PCC1 LL_SYSCFG_GetPMOSVddCompensationCode
759 * @retval Returned value is the PMOS compensation cell
760 */
LL_SYSCFG_GetPMOSVddCompensationCode(void)761 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationCode(void)
762 {
763 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC1));
764 }
765
766 /**
767 * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2
768 * @rmtoll CCCR PCC2 LL_SYSCFG_SetPMOSVddIO2CompensationCode
769 * @param PMOSCode PMOS compensation code
770 * This code is applied to the PMOS compensation cell when the CS2 bit of the
771 * SYSCFG_CCCSR is set
772 * @retval None
773 */
LL_SYSCFG_SetPMOSVddIO2CompensationCode(uint32_t PMOSCode)774 __STATIC_INLINE void LL_SYSCFG_SetPMOSVddIO2CompensationCode(uint32_t PMOSCode)
775 {
776 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC2, PMOSCode << SYSCFG_CCCR_PCC2_Pos);
777 }
778
779
780 /**
781 * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2
782 * @rmtoll CCCR PCC2 LL_SYSCFG_GetPMOSVddIO2CompensationCode
783 * @retval Returned value is the PMOS compensation
784 */
LL_SYSCFG_GetPMOSVddIO2CompensationCode(void)785 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationCode(void)
786 {
787 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC2));
788 }
789
790 #if defined(SYSCFG_CCCR_PCC3)
791 /**
792 * @brief Set the compensation cell code of the HSPI IO PMOS transistor supplied by VDD
793 * @rmtoll CCCR PCC3 LL_SYSCFG_SetPMOSVddHSPICompensationCode
794 * @param PMOSCode PMOS compensation code
795 * This code is applied to the PMOS compensation cell when the CS3 bit of the
796 * SYSCFG_CCCSR is set
797 * @retval None
798 */
LL_SYSCFG_SetPMOSVddHSPICompensationCode(uint32_t PMOSCode)799 __STATIC_INLINE void LL_SYSCFG_SetPMOSVddHSPICompensationCode(uint32_t PMOSCode)
800 {
801 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC3, PMOSCode << SYSCFG_CCCR_PCC3_Pos);
802 }
803
804 /**
805 * @brief Get the compensation cell code of the HSPI IO PMOS transistor supplied by VDD
806 * @rmtoll CCCR PCC3 LL_SYSCFG_GetPMOSVddHSPICompensationCode
807 * @retval Returned value is the PMOS compensation
808 */
LL_SYSCFG_GetPMOSVddHSPICompensationCode(void)809 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddHSPICompensationCode(void)
810 {
811 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC3));
812 }
813 #endif /* SYSCFG_CCCR_PCC3 */
814
815 /**
816 * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDD
817 * @rmtoll CCCR PCC2 LL_SYSCFG_SetNMOSVddCompensationCode
818 * @param NMOSCode NMOS compensation code
819 * This code is applied to the NMOS compensation cell when the CS2 bit of the
820 * SYSCFG_CMPCR is set
821 * @retval None
822 */
LL_SYSCFG_SetNMOSVddCompensationCode(uint32_t NMOSCode)823 __STATIC_INLINE void LL_SYSCFG_SetNMOSVddCompensationCode(uint32_t NMOSCode)
824 {
825 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC1, NMOSCode << SYSCFG_CCCR_NCC1_Pos);
826 }
827
828 /**
829 * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDD
830 * @rmtoll CCCR NCC1 LL_SYSCFG_GetNMOSVddCompensationCode
831 * @retval Returned value is the Vdd compensation cell code for NMOS transistors
832 */
LL_SYSCFG_GetNMOSVddCompensationCode(void)833 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationCode(void)
834 {
835 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC1));
836 }
837
838 /**
839 * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2
840 * @rmtoll CCCR NCC2 LL_SYSCFG_SetNMOSVddIO2CompensationCode
841 * @param NMOSCode NMOS compensation code
842 * This code is applied to the NMOS compensation cell when the CS2 bit of the
843 * SYSCFG_CMPCR is set
844 * Value between 0 and 15
845 * @retval None
846 */
LL_SYSCFG_SetNMOSVddIO2CompensationCode(uint32_t NMOSCode)847 __STATIC_INLINE void LL_SYSCFG_SetNMOSVddIO2CompensationCode(uint32_t NMOSCode)
848 {
849 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC2, NMOSCode << SYSCFG_CCCR_NCC2_Pos);
850 }
851
852
853 /**
854 * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2
855 * @rmtoll CCCR NCC2 LL_SYSCFG_GetNMOSVddIO2CompensationCode
856 * @retval Returned value is the NMOS compensation cell code
857 */
LL_SYSCFG_GetNMOSVddIO2CompensationCode(void)858 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationCode(void)
859 {
860 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC2));
861 }
862
863 #if defined(SYSCFG_CCCR_NCC3)
864 /**
865 * @brief Set the compensation cell code of the HSPI IO NMOS transistor supplied by VDD
866 * @rmtoll CCCR NCC3 LL_SYSCFG_SetNMOSVddHSPICompensationCode
867 * @param NMOSCode NMOS compensation code
868 * This code is applied to the NMOS compensation cell when the CS3 bit of the
869 * SYSCFG_CCCSR is set
870 * Value between 0 and 15
871 * @retval None
872 */
LL_SYSCFG_SetNMOSVddHSPICompensationCode(uint32_t NMOSCode)873 __STATIC_INLINE void LL_SYSCFG_SetNMOSVddHSPICompensationCode(uint32_t NMOSCode)
874 {
875 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC3, NMOSCode << SYSCFG_CCCR_NCC3_Pos);
876 }
877
878 /**
879 * @brief Get the compensation cell code of the HSPI IO NMOS transistor supplied by VDD
880 * @rmtoll CCCR NCC3 LL_SYSCFG_GetNMOSVddHSPICompensationCode
881 * @retval Returned value is the NMOS compensation cell code
882 */
LL_SYSCFG_GetNMOSVddHSPICompensationCode(void)883 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddHSPICompensationCode(void)
884 {
885 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC3));
886 }
887 #endif /* SYSCFG_CCCR_NCC3 */
888
889 /**
890 * @brief Enable the Compensation Cell of GPIO supplied by VDD
891 * @rmtoll CCCSR EN1 LL_SYSCFG_EnableVddCompensationCell
892 * @note The vdd compensation cell can be used only when the device supply
893 * voltage ranges from 1.71 to 3.6 V
894 * @retval None
895 */
LL_SYSCFG_EnableVddCompensationCell(void)896 __STATIC_INLINE void LL_SYSCFG_EnableVddCompensationCell(void)
897 {
898 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1);
899 }
900
901 /**
902 * @brief Enable the Compensation Cell of GPIO supplied by VDDIO2
903 * @rmtoll CCCSR EN2 LL_SYSCFG_EnableVddIO2CompensationCell
904 * @note The Vdd I/O compensation cell can be used only when the device supply
905 * voltage ranges from 1.08 to 3.6 V
906 * @retval None
907 */
LL_SYSCFG_EnableVddIO2CompensationCell(void)908 __STATIC_INLINE void LL_SYSCFG_EnableVddIO2CompensationCell(void)
909 {
910 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2);
911 }
912
913 #if defined(SYSCFG_CCCSR_EN3)
914 /**
915 * @brief Enable the Compensation Cell of HSPI IO supplied by VDD
916 * @rmtoll CCCSR EN3 LL_SYSCFG_EnableVddHSPICompensationCell
917 * @retval None
918 */
LL_SYSCFG_EnableVddHSPICompensationCell(void)919 __STATIC_INLINE void LL_SYSCFG_EnableVddHSPICompensationCell(void)
920 {
921 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3);
922 }
923 #endif /* SYSCFG_CCCSR_EN3 */
924
925 /**
926 * @brief Disable the Compensation Cell of GPIO supplied by VDD
927 * @rmtoll CCCSR EN1 LL_SYSCFG_DisableVddCompensationCell
928 * @note The Vdd compensation cell can be used only when the device supply
929 * voltage ranges from 1.71 to 3.6 V
930 * @retval None
931 */
LL_SYSCFG_DisableVddCompensationCell(void)932 __STATIC_INLINE void LL_SYSCFG_DisableVddCompensationCell(void)
933 {
934 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1);
935 }
936
937 /**
938 * @brief Disable the Compensation Cell of GPIO supplied by VDDIO2
939 * @rmtoll CCCSR EN2 LL_SYSCFG_DisableVddIO2CompensationCell
940 * @note The Vdd I/O compensation cell can be used only when the device supply
941 * voltage ranges from 1.08 to 3.6 V
942 * @retval None
943 */
LL_SYSCFG_DisableVddIO2CompensationCell(void)944 __STATIC_INLINE void LL_SYSCFG_DisableVddIO2CompensationCell(void)
945 {
946 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2);
947 }
948
949 #if defined(SYSCFG_CCCSR_EN3)
950 /**
951 * @brief Disable the Compensation Cell of HSPI IO supplied by VDD
952 * @rmtoll CCCSR EN3 LL_SYSCFG_DisableVddHSPICompensationCell
953 * @retval None
954 */
LL_SYSCFG_DisableVddHSPICompensationCell(void)955 __STATIC_INLINE void LL_SYSCFG_DisableVddHSPICompensationCell(void)
956 {
957 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3);
958 }
959 #endif /* SYSCFG_CCCSR_EN3 */
960
961 /**
962 * @brief Check if the Compensation Cell of GPIO supplied by VDD is enable
963 * @rmtoll CCCSR EN1 LL_SYSCFG_IsEnabled_VddCompensationCell
964 * @retval State of bit (1 or 0).
965 */
LL_SYSCFG_IsEnabled_VddCompensationCell(void)966 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddCompensationCell(void)
967 {
968 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1) == SYSCFG_CCCSR_EN1) ? 1UL : 0UL);
969 }
970
971 /**
972 * @brief Check if the Compensation Cell of GPIO supplied by VDDIO2 is enable
973 * @rmtoll CCCSR EN2 LL_SYSCFG_IsEnabled_VddIO2CompensationCell
974 * @retval State of bit (1 or 0).
975 */
LL_SYSCFG_IsEnabled_VddIO2CompensationCell(void)976 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddIO2CompensationCell(void)
977 {
978 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2) == SYSCFG_CCCSR_EN2) ? 1UL : 0UL);
979 }
980
981 #if defined(SYSCFG_CCCSR_EN3)
982 /**
983 * @brief Check if the Compensation Cell of HSPI IO supplied by VDD is enable
984 * @rmtoll CCCSR EN3 LL_SYSCFG_IsEnabled_VddHSPICompensationCell
985 * @retval State of bit (1 or 0).
986 */
LL_SYSCFG_IsEnabled_VddHSPICompensationCell(void)987 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddHSPICompensationCell(void)
988 {
989 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3) == SYSCFG_CCCSR_EN3) ? 1UL : 0UL);
990 }
991 #endif /* SYSCFG_CCCSR_EN3 */
992
993 /**
994 * @brief Get Compensation Cell ready Flag of GPIO supplied by VDD
995 * @rmtoll CCCSR RDY1 LL_SYSCFG_IsActiveFlag_VddCMPCR
996 * @retval State of bit (1 or 0).
997 */
LL_SYSCFG_IsActiveFlag_VddCMPCR(void)998 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddCMPCR(void)
999 {
1000 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY1) == (SYSCFG_CCCSR_RDY1)) ? 1UL : 0UL);
1001 }
1002
1003 /**
1004 * @brief Get Compensation Cell ready Flag of GPIO supplied by VDDIO2
1005 * @rmtoll CCCSR RDY2 LL_SYSCFG_IsActiveFlag_VddIO2CMPCR
1006 * @retval State of bit (1 or 0).
1007 */
LL_SYSCFG_IsActiveFlag_VddIO2CMPCR(void)1008 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddIO2CMPCR(void)
1009 {
1010 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY2) == (SYSCFG_CCCSR_RDY2)) ? 1UL : 0UL);
1011 }
1012
1013 #if defined(SYSCFG_CCCSR_RDY3)
1014 /**
1015 * @brief Get Compensation Cell ready Flag of HSPI IO supplied by VDD
1016 * @rmtoll CCCSR RDY3 LL_SYSCFG_IsActiveFlag_VddHSPICMPCR
1017 * @retval State of bit (1 or 0).
1018 */
LL_SYSCFG_IsActiveFlag_VddHSPICMPCR(void)1019 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddHSPICMPCR(void)
1020 {
1021 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY3) == (SYSCFG_CCCSR_RDY3)) ? 1UL : 0UL);
1022 }
1023 #endif /* SYSCFG_CCCSR_RDY3 */
1024
1025 /**
1026 * @brief Set the compensation cell code selection of GPIO supplied by VDD
1027 * @rmtoll CCCSR CS1 LL_SYSCFG_SetVddCellCompensationCode
1028 * @param CompCode: Selects the code to be applied for the Vdd compensation cell
1029 * This parameter can be one of the following values:
1030 * @arg LL_SYSCFG_VDD_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
1031 * @arg LL_SYSCFG_VDD_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
1032 * @retval None
1033 */
LL_SYSCFG_SetVddCellCompensationCode(uint32_t CompCode)1034 __STATIC_INLINE void LL_SYSCFG_SetVddCellCompensationCode(uint32_t CompCode)
1035 {
1036 SET_BIT(SYSCFG->CCCSR, CompCode);
1037 }
1038
1039 /**
1040 * @brief Set the compensation cell code selection of GPIO supplied by VDDIO2
1041 * @rmtoll CCCSR CS2 LL_SYSCFG_SetVddIO2CellCompensationCode
1042 * @param CompCode: Selects the code to be applied for the VddIO compensation cell
1043 * This parameter can be one of the following values:
1044 * @arg LL_SYSCFG_VDDIO2_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
1045 * @arg LL_SYSCFG_VDDIO2_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
1046 * @retval None
1047 */
LL_SYSCFG_SetVddIO2CellCompensationCode(uint32_t CompCode)1048 __STATIC_INLINE void LL_SYSCFG_SetVddIO2CellCompensationCode(uint32_t CompCode)
1049 {
1050 SET_BIT(SYSCFG->CCCSR, CompCode);
1051 }
1052
1053 #if defined(SYSCFG_CCCSR_CS3)
1054 /**
1055 * @brief Set the compensation cell code selection of HSPI IO supplied by VDD
1056 * @rmtoll CCCSR CS3 LL_SYSCFG_SetVddHSPICellCompensationCode
1057 * @param CompCode: Selects the code to be applied for the VddIO compensation cell
1058 * This parameter can be one of the following values:
1059 * @arg LL_SYSCFG_VDDHSPI_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
1060 * @arg LL_SYSCFG_VDDHSPI_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
1061 * @retval None
1062 */
LL_SYSCFG_SetVddHSPICellCompensationCode(uint32_t CompCode)1063 __STATIC_INLINE void LL_SYSCFG_SetVddHSPICellCompensationCode(uint32_t CompCode)
1064 {
1065 SET_BIT(SYSCFG->CCCSR, CompCode);
1066 }
1067 #endif /* SYSCFG_CCCSR_CS3 */
1068
1069 /**
1070 * @brief Get the compensation cell code selection of GPIO supplied by VDD
1071 * @rmtoll CCCSR CS1 LL_SYSCFG_GetVddCellCompensationCode
1072 * @retval Returned value can be one of the following values:
1073 * @arg LL_SYSCFG_VDD_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
1074 * @arg LL_SYSCFG_VDD_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
1075 */
LL_SYSCFG_GetVddCellCompensationCode(void)1076 __STATIC_INLINE uint32_t LL_SYSCFG_GetVddCellCompensationCode(void)
1077 {
1078 return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS1));
1079 }
1080
1081 /**
1082 * @brief Get the compensation cell code selection of GPIO supplied by VDDIO2
1083 * @rmtoll CCCSR CS2 LL_SYSCFG_GetVddIO2CellCompensationCode
1084 * @retval Returned value can be one of the following values:
1085 * @arg LL_SYSCFG_VDDIO2_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
1086 * @arg LL_SYSCFG_VDDIO2_REGISTER_CODE: Selected Code is from the SYSCFG compensation
1087 cell code register (SYSCFG_CCCR)
1088 */
LL_SYSCFG_GetVddIO2CellCompensationCode(void)1089 __STATIC_INLINE uint32_t LL_SYSCFG_GetVddIO2CellCompensationCode(void)
1090 {
1091 return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS2));
1092 }
1093
1094 #if defined(SYSCFG_CCCSR_CS3)
1095 /**
1096 * @brief Get the compensation cell code selection of HSPI IO supplied by VDD
1097 * @rmtoll CCCSR CS3 LL_SYSCFG_GetVddHSPICellCompensationCode
1098 * @retval Returned value can be one of the following values:
1099 * @arg LL_SYSCFG_VDDHSPI_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
1100 * @arg LL_SYSCFG_VDDHSPI_REGISTER_CODE: Selected Code is from the SYSCFG compensation
1101 cell code register (SYSCFG_CCCR)
1102 */
LL_SYSCFG_GetVddHSPICellCompensationCode(void)1103 __STATIC_INLINE uint32_t LL_SYSCFG_GetVddHSPICellCompensationCode(void)
1104 {
1105 return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS3));
1106 }
1107 #endif /* SYSCFG_CCCSR_CS3 */
1108 /**
1109 * @}
1110 */
1111
1112 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1113 * @{
1114 */
1115
1116 /**
1117 * @brief Return the device identifier
1118 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
1119 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415)
1120 */
LL_DBGMCU_GetDeviceID(void)1121 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1122 {
1123 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1124 }
1125
1126 /**
1127 * @brief Return the device revision identifier
1128 * @note This field indicates the revision of the device.
1129 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
1130 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1131 */
LL_DBGMCU_GetRevisionID(void)1132 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1133 {
1134 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1135 }
1136
1137 /**
1138 * @brief Enable the Debug Module during STOP mode
1139 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
1140 * @retval None
1141 */
LL_DBGMCU_EnableDBGStopMode(void)1142 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1143 {
1144 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1145 }
1146
1147 /**
1148 * @brief Disable the Debug Module during STOP mode
1149 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
1150 * @retval None
1151 */
LL_DBGMCU_DisableDBGStopMode(void)1152 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1153 {
1154 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1155 }
1156
1157 /**
1158 * @brief Enable the Debug Module during STANDBY mode
1159 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
1160 * @retval None
1161 */
LL_DBGMCU_EnableDBGStandbyMode(void)1162 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1163 {
1164 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1165 }
1166
1167 /**
1168 * @brief Disable the Debug Module during STANDBY mode
1169 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
1170 * @retval None
1171 */
LL_DBGMCU_DisableDBGStandbyMode(void)1172 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1173 {
1174 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1175 }
1176
1177
1178 /**
1179 * @brief Enable the Debug Clock Trace
1180 * @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_EnableTraceClock
1181 * @retval None
1182 */
LL_DBGMCU_EnableTraceClock(void)1183 __STATIC_INLINE void LL_DBGMCU_EnableTraceClock(void)
1184 {
1185 SET_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN);
1186 }
1187
1188 /**
1189 * @brief Disable the Debug Clock Trace
1190 * @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_DisableTraceClock
1191 * @retval None
1192 */
LL_DBGMCU_DisableTraceClock(void)1193 __STATIC_INLINE void LL_DBGMCU_DisableTraceClock(void)
1194 {
1195 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN);
1196 }
1197
1198
1199 /**
1200 * @brief Check if clock trace is enabled or disabled.
1201 * @rmtoll DBGMCU_CR_TRACE_CLKEN LL_DBGMCU_IsEnabledTraceClock
1202 * @retval State of bit (1 or 0).
1203 */
LL_DBGMCU_IsEnabledTraceClock(void)1204 __STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledTraceClock(void)
1205 {
1206 return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN) == DBGMCU_CR_TRACE_CLKEN) ? 1UL : 0UL);
1207 }
1208
1209 /**
1210 * @brief Set Trace pin assignment control
1211 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
1212 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
1213 * @param PinAssignment This parameter can be one of the following values:
1214 * @arg @ref LL_DBGMCU_TRACE_NONE
1215 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1216 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1217 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1218 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1219 * @retval None
1220 */
LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)1221 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
1222 {
1223 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
1224 }
1225
1226 /**
1227 * @brief Get Trace pin assignment control
1228 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
1229 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
1230 * @retval Returned value can be one of the following values:
1231 * @arg @ref LL_DBGMCU_TRACE_NONE
1232 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1233 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1234 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1235 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1236 */
LL_DBGMCU_GetTracePinAssignment(void)1237 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
1238 {
1239 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
1240 }
1241
1242 /**
1243 * @brief Freeze APB1 peripherals (group1 peripherals)
1244 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
1245 * @param Periphs This parameter can be a combination of the following values:
1246 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1247 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1248 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
1249 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
1250 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1251 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
1252 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1253 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1254 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1255 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1256 * @retval None
1257 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1258 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1259 {
1260 SET_BIT(DBGMCU->APB1FZR1, Periphs);
1261 }
1262
1263 /**
1264 * @brief Freeze APB1 peripherals (group2 peripherals)
1265 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
1266 * @param Periphs This parameter can be a combination of the following values:
1267 * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP
1268 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1269 * @arg @ref LL_DBGMCU_APB1_GRP2_I2C5_STOP (*)
1270 * @arg @ref LL_DBGMCU_APB1_GRP2_I2C6_STOP (*)
1271 * @retval None
1272 * @note (*) Availability depends on devices.
1273 */
LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)1274 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
1275 {
1276 SET_BIT(DBGMCU->APB1FZR2, Periphs);
1277 }
1278
1279 /**
1280 * @brief Unfreeze APB1 peripherals (group1 peripherals)
1281 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1282 * @param Periphs This parameter can be a combination of the following values:
1283 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1284 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1285 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
1286 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
1287 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1288 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
1289 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1290 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1291 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1292 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1293 * @retval None
1294 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1295 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1296 {
1297 CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
1298 }
1299
1300 /**
1301 * @brief Unfreeze APB1 peripherals (group2 peripherals)
1302 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
1303 * @param Periphs This parameter can be a combination of the following values:
1304 * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP
1305 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1306 * @retval None
1307 */
LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)1308 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
1309 {
1310 CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
1311 }
1312
1313 /**
1314 * @brief Freeze APB2 peripherals
1315 * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
1316 * @param Periphs This parameter can be a combination of the following values:
1317 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1318 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
1319 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1320 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1321 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1322 * @retval None
1323 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1324 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1325 {
1326 SET_BIT(DBGMCU->APB2FZR, Periphs);
1327 }
1328
1329 /**
1330 * @brief Unfreeze APB2 peripherals
1331 * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1332 * @param Periphs This parameter can be a combination of the following values:
1333 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1334 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
1335 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1336 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1337 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1338 * @retval None
1339 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1340 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1341 {
1342 CLEAR_BIT(DBGMCU->APB2FZR, Periphs);
1343 }
1344
1345 /**
1346 * @brief Freeze APB3 peripherals
1347 * @rmtoll DBGMCU_APB3FZ DBG_TIMx_STOP LL_DBGMCU_APB3_GRP1_FreezePeriph
1348 * @param Periphs This parameter can be a combination of the following values:
1349 * @arg @ref LL_DBGMCU_APB3_GRP1_I2C3_STOP
1350 * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM1_STOP
1351 * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM3_STOP
1352 * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM4_STOP
1353 * @arg @ref LL_DBGMCU_APB3_GRP1_RTC_STOP
1354 * @retval None
1355 */
LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)1356 __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)
1357 {
1358 SET_BIT(DBGMCU->APB3FZR, Periphs);
1359 }
1360
1361 /**
1362 * @brief Unfreeze APB3 peripherals
1363 * @rmtoll DBGMCU_APB3FZR DBG_TIMx_STOP LL_DBGMCU_APB3_GRP1_UnFreezePeriph
1364 * @param Periphs This parameter can be a combination of the following values:
1365 * @arg @ref LL_DBGMCU_APB3_GRP1_I2C3_STOP
1366 * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM1_STOP
1367 * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM3_STOP
1368 * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM4_STOP
1369 * @arg @ref LL_DBGMCU_APB3_GRP1_RTC_STOP
1370 * @retval None
1371 */
LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)1372 __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)
1373 {
1374 CLEAR_BIT(DBGMCU->APB3FZR, Periphs);
1375 }
1376
1377 /**
1378 * @brief Freeze AHB1 peripherals
1379 * @rmtoll DBGMCU_AHB1FZ DBG_GPDMAx_STOP LL_DBGMCU_AHB1_GRP1_FreezePeriph
1380 * @param Periphs This parameter can be a combination of the following values:
1381 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP
1382 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP
1383 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP
1384 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP
1385 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP
1386 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP
1387 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP
1388 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP
1389 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP
1390 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP
1391 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP
1392 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP
1393 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP
1394 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP
1395 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP
1396 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP
1397 * @retval None
1398 */
LL_DBGMCU_AHB1_GRP1_FreezePeriph(uint32_t Periphs)1399 __STATIC_INLINE void LL_DBGMCU_AHB1_GRP1_FreezePeriph(uint32_t Periphs)
1400 {
1401 SET_BIT(DBGMCU->AHB1FZR, Periphs);
1402 }
1403
1404 /**
1405 * @brief Unfreeze AHB1 peripherals
1406 * @rmtoll DBGMCU_AHB1FZ DBG_GPDMAx_STOP LL_DBGMCU_AHB1_GRP1_FreezePeriph
1407 * @param Periphs This parameter can be a combination of the following values:
1408 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP
1409 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP
1410 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP
1411 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP
1412 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP
1413 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP
1414 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP
1415 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP
1416 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP
1417 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP
1418 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP
1419 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP
1420 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP
1421 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP
1422 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP
1423 * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP
1424 * @retval None
1425 */
LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(uint32_t Periphs)1426 __STATIC_INLINE void LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1427 {
1428 CLEAR_BIT(DBGMCU->AHB1FZR, Periphs);
1429 }
1430
1431 /**
1432 * @brief Freeze AHB3 peripherals
1433 * @rmtoll DBGMCU_AHB3FZ DBG_LPDMAx_STOP LL_DBGMCU_AHB3_GRP1_FreezePeriph
1434 * @param Periphs This parameter can be a combination of the following values:
1435 * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA0_STOP
1436 * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA1_STOP
1437 * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA2_STOP
1438 * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA3_STOP
1439 * @retval None
1440 */
LL_DBGMCU_AHB3_GRP1_FreezePeriph(uint32_t Periphs)1441 __STATIC_INLINE void LL_DBGMCU_AHB3_GRP1_FreezePeriph(uint32_t Periphs)
1442 {
1443 SET_BIT(DBGMCU->AHB3FZR, Periphs);
1444 }
1445
1446 /**
1447 * @brief Unfreeze AHB3 peripherals
1448 * @rmtoll DBGMCU_AHB3FZ DBG_LPDMAx_STOP LL_DBGMCU_AHB3_GRP1_FreezePeriph
1449 * @param Periphs This parameter can be a combination of the following values:
1450 * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA0_STOP
1451 * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA1_STOP
1452 * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA2_STOP
1453 * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA3_STOP
1454 * @retval None
1455 */
LL_DBGMCU_AHB3_GRP1_UnFreezePeriph(uint32_t Periphs)1456 __STATIC_INLINE void LL_DBGMCU_AHB3_GRP1_UnFreezePeriph(uint32_t Periphs)
1457 {
1458 CLEAR_BIT(DBGMCU->AHB3FZR, Periphs);
1459 }
1460
1461 /**
1462 * @}
1463 */
1464
1465 #if defined(VREFBUF)
1466 /** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
1467 * @{
1468 */
1469
1470 /**
1471 * @brief Enable Internal voltage reference
1472 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable
1473 * @retval None
1474 */
LL_VREFBUF_Enable(void)1475 __STATIC_INLINE void LL_VREFBUF_Enable(void)
1476 {
1477 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1478 }
1479
1480 /**
1481 * @brief Disable Internal voltage reference
1482 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable
1483 * @retval None
1484 */
LL_VREFBUF_Disable(void)1485 __STATIC_INLINE void LL_VREFBUF_Disable(void)
1486 {
1487 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1488 }
1489
1490 /**
1491 * @brief Enable high impedance (VREF+pin is high impedance)
1492 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
1493 * @retval None
1494 */
LL_VREFBUF_EnableHIZ(void)1495 __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
1496 {
1497 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1498 }
1499
1500 /**
1501 * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
1502 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
1503 * @retval None
1504 */
LL_VREFBUF_DisableHIZ(void)1505 __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
1506 {
1507 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1508 }
1509
1510 /**
1511 * @brief Set the Voltage reference scale
1512 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
1513 * @param Scale This parameter can be one of the following values:
1514 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1515 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1516 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
1517 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE3
1518 * @retval None
1519 */
LL_VREFBUF_SetVoltageScaling(uint32_t Scale)1520 __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
1521 {
1522 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
1523 }
1524
1525 /**
1526 * @brief Get the Voltage reference scale
1527 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
1528 * @retval Returned value can be one of the following values:
1529 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1530 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1531 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
1532 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE3
1533 */
LL_VREFBUF_GetVoltageScaling(void)1534 __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
1535 {
1536 return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
1537 }
1538
1539 /**
1540 * @brief Check if Voltage reference buffer is ready
1541 * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
1542 * @retval State of bit (1 or 0).
1543 */
LL_VREFBUF_IsVREFReady(void)1544 __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
1545 {
1546 return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == VREFBUF_CSR_VRR) ? 1UL : 0UL);
1547 }
1548
1549 /**
1550 * @brief Get the trimming code for VREFBUF calibration
1551 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
1552 * @retval Between 0 and 0x3F
1553 */
LL_VREFBUF_GetTrimming(void)1554 __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
1555 {
1556 return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
1557 }
1558
1559 /**
1560 * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
1561 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
1562 * @param Value Between 0 and 0x3F
1563 * @retval None
1564 */
LL_VREFBUF_SetTrimming(uint32_t Value)1565 __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
1566 {
1567 WRITE_REG(VREFBUF->CCR, Value);
1568 }
1569
1570 /**
1571 * @}
1572 */
1573 #endif /* VREFBUF */
1574
1575 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
1576 * @{
1577 */
1578 /**
1579 * @brief Set FLASH Latency
1580 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
1581 * @param Latency This parameter can be one of the following values:
1582 * @arg @ref LL_FLASH_LATENCY_0
1583 * @arg @ref LL_FLASH_LATENCY_1
1584 * @arg @ref LL_FLASH_LATENCY_2
1585 * @arg @ref LL_FLASH_LATENCY_3
1586 * @arg @ref LL_FLASH_LATENCY_4
1587 * @arg @ref LL_FLASH_LATENCY_5
1588 * @arg @ref LL_FLASH_LATENCY_6
1589 * @arg @ref LL_FLASH_LATENCY_7
1590 * @arg @ref LL_FLASH_LATENCY_8
1591 * @arg @ref LL_FLASH_LATENCY_9
1592 * @arg @ref LL_FLASH_LATENCY_10
1593 * @arg @ref LL_FLASH_LATENCY_11
1594 * @arg @ref LL_FLASH_LATENCY_12
1595 * @arg @ref LL_FLASH_LATENCY_13
1596 * @arg @ref LL_FLASH_LATENCY_14
1597 * @arg @ref LL_FLASH_LATENCY_15
1598 * @retval None
1599 */
LL_FLASH_SetLatency(uint32_t Latency)1600 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1601 {
1602 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1603 }
1604
1605 /**
1606 * @brief Get FLASH Latency
1607 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
1608 * @retval Returned value can be one of the following values:
1609 * @arg @ref LL_FLASH_LATENCY_0
1610 * @arg @ref LL_FLASH_LATENCY_1
1611 * @arg @ref LL_FLASH_LATENCY_2
1612 * @arg @ref LL_FLASH_LATENCY_3
1613 * @arg @ref LL_FLASH_LATENCY_4
1614 * @arg @ref LL_FLASH_LATENCY_5
1615 * @arg @ref LL_FLASH_LATENCY_6
1616 * @arg @ref LL_FLASH_LATENCY_7
1617 * @arg @ref LL_FLASH_LATENCY_8
1618 * @arg @ref LL_FLASH_LATENCY_9
1619 * @arg @ref LL_FLASH_LATENCY_10
1620 * @arg @ref LL_FLASH_LATENCY_11
1621 * @arg @ref LL_FLASH_LATENCY_12
1622 * @arg @ref LL_FLASH_LATENCY_13
1623 * @arg @ref LL_FLASH_LATENCY_14
1624 * @arg @ref LL_FLASH_LATENCY_15
1625 */
LL_FLASH_GetLatency(void)1626 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1627 {
1628 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1629 }
1630
1631 /**
1632 * @brief Enable Flash Power-down mode during run mode or Low-power run mode
1633 * @note Flash memory can be put in power-down mode only when the code is executed
1634 * from RAM
1635 * @note Flash must not be accessed when power down is enabled
1636 * @note Flash must not be put in power-down while a program or an erase operation
1637 * is on-going
1638 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
1639 * FLASH_PDKEYR PDKEY1_1 LL_FLASH_EnableRunPowerDown\n
1640 * FLASH_PDKEYR PDKEY1_2 LL_FLASH_EnableRunPowerDown\n
1641 * FLASH_PDKEYR PDKEY2_1 LL_FLASH_EnableRunPowerDown\n
1642 * FLASH_PDKEYR PDKEY2_2 LL_FLASH_EnableRunPowerDown
1643 * @retval None
1644 */
LL_FLASH_EnableRunPowerDown(void)1645 __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
1646 {
1647 /* Following values must be written consecutively to unlock the RUN_PD bit in
1648 FLASH_ACR */
1649 WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_1);
1650 WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_2);
1651 WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_1);
1652 WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_2);
1653
1654 /*Request to enter flash in power mode */
1655 SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ1 | FLASH_ACR_PDREQ2);
1656 }
1657
1658 /**
1659 * @brief Enable flash Power-down mode during run mode or Low-power run mode of bank1
1660 * @note Bank 1 of flash memory can be put in power-down mode only when the code is executed
1661 * from RAM
1662 * @note Bank1 of flash must not be accessed when power down is enabled
1663 * @note Bank1 of flash must not be put in power-down while a program or an erase operation
1664 * is on-going
1665 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
1666 * FLASH_PDKEYR PDKEY1_1 LL_FLASH_EnableRunPowerDown\n
1667 * FLASH_PDKEYR PDKEY1_2 LL_FLASH_EnableRunPowerDown\n
1668 * @retval None
1669 */
LL_FLASH_EnableRunPowerDownBank1(void)1670 __STATIC_INLINE void LL_FLASH_EnableRunPowerDownBank1(void)
1671 {
1672 /* Following values must be written consecutively to unlock the RUN_PD bit in
1673 FLASH_ACR */
1674 WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_1);
1675 WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_2);
1676
1677 /*Request to enter flash in power mode */
1678 SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ1);
1679 }
1680
1681 /**
1682 * @brief Enable flash Power-down mode during run mode or Low-power run mode of Bank2
1683 * @note Bank 2 of flash memory can be put in power-down mode only when the code is executed
1684 * from RAM
1685 * @note Bank2 of flash must not be accessed when power down is enabled
1686 * @note Bank2 of flash must not be put in power-down while a program or an erase operation
1687 * is on-going
1688 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
1689 * FLASH_PDKEYR PDKEY2_1 LL_FLASH_EnableRunPowerDown\n
1690 * FLASH_PDKEYR PDKEY2_2 LL_FLASH_EnableRunPowerDown\n
1691 * @retval None
1692 */
LL_FLASH_EnableRunPowerDownBank2(void)1693 __STATIC_INLINE void LL_FLASH_EnableRunPowerDownBank2(void)
1694 {
1695 /* Following values must be written consecutively to unlock the RUN_PD bit in
1696 FLASH_ACR */
1697 WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_1);
1698 WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_2);
1699
1700 /*Request to enter flash in power mode */
1701 SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ2);
1702 }
1703
1704 /**
1705 * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode
1706 * @note Flash must not be put in power-down while a program or an erase operation
1707 * is on-going
1708 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
1709 * @retval None
1710 */
LL_FLASH_EnableSleepPowerDown(void)1711 __STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
1712 {
1713 SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
1714 }
1715
1716 /**
1717 * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode
1718 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
1719 * @retval None
1720 */
LL_FLASH_DisableSleepPowerDown(void)1721 __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
1722 {
1723 CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
1724 }
1725 /**
1726 * @}
1727 */
1728
1729
1730 /** @defgroup SYSTEM_LL_EF_ERASE_MEMORIE_STATUS ERASE MEMORIE STATUS
1731 * @{
1732 */
1733
1734 /**
1735 * @brief Clear Status of End of Erase for ICACHE and PKA RAMs
1736 * @rmtoll MESR IPMEE LL_SYSCFG_ClearEraseEndStatus
1737 * @retval None
1738 */
LL_SYSCFG_ClearEraseEndStatus(void)1739 __STATIC_INLINE void LL_SYSCFG_ClearEraseEndStatus(void)
1740 {
1741 SET_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE);
1742 }
1743
1744 /**
1745 * @brief Get Status of End of Erase for ICACHE and PKA RAMs
1746 * @rmtoll MESR IPMEE LL_SYSCFG_GetEraseEndStatus
1747 * @retval Returned value can be one of the following values:
1748 * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done
1749 * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended
1750 */
LL_SYSCFG_GetEraseEndStatus(void)1751 __STATIC_INLINE uint32_t LL_SYSCFG_GetEraseEndStatus(void)
1752 {
1753 return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE));
1754 }
1755
1756
1757 /**
1758 * @brief Clear Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams
1759 * @rmtoll MESR MCLR LL_SYSCFG_ClearEraseAfterResetStatus
1760 * @retval None
1761 */
LL_SYSCFG_ClearEraseAfterResetStatus(void)1762 __STATIC_INLINE void LL_SYSCFG_ClearEraseAfterResetStatus(void)
1763 {
1764 SET_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR);
1765 }
1766
1767 /**
1768 * @brief Get Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams
1769 * @rmtoll MESR MCLR LL_SYSCFG_GetEraseAfterResetStatus
1770 * @retval Returned value can be one of the following values:
1771 * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done
1772 * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended
1773 */
LL_SYSCFG_GetEraseAfterResetStatus(void)1774 __STATIC_INLINE uint32_t LL_SYSCFG_GetEraseAfterResetStatus(void)
1775 {
1776 return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR));
1777 }
1778 /**
1779 * @}
1780 */
1781
1782 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */
1783
1784 /**
1785 * @}
1786 */
1787
1788 /**
1789 * @}
1790 */
1791
1792 /**
1793 * @}
1794 */
1795
1796 #ifdef __cplusplus
1797 }
1798 #endif
1799
1800 #endif /* STM32u5xx_LL_SYSTEM_H */
1801
