1 /**
2 ******************************************************************************
3 * @file stm32l5xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17
18 /* Define to prevent recursive inclusion -------------------------------------*/
19 #ifndef STM32L5xx_LL_RCC_H
20 #define STM32L5xx_LL_RCC_H
21
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25
26 /* Includes ------------------------------------------------------------------*/
27 #include "stm32l5xx.h"
28
29 /** @addtogroup STM32L5xx_LL_Driver
30 * @{
31 */
32
33 #if defined(RCC)
34
35 /** @defgroup RCC_LL RCC
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /* Private constants ---------------------------------------------------------*/
42 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
43 * @{
44 */
45 /* Defines used to perform offsets*/
46 /* Offset used to access to RCC_CCIPR1 and RCC_CCIPR2 registers */
47 #define RCC_OFFSET_CCIPR1 0U
48 #define RCC_OFFSET_CCIPR2 0x14U
49
50 /* Defines used for security configuration extension */
51 #define RCC_SECURE_MASK 0x1FFFU
52 /**
53 * @}
54 */
55
56 /* Private macros ------------------------------------------------------------*/
57 /* Exported types ------------------------------------------------------------*/
58 #if defined(USE_FULL_LL_DRIVER)
59 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
60 * @{
61 */
62
63 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
64 * @{
65 */
66
67 /**
68 * @brief RCC Clocks Frequency Structure
69 */
70 typedef struct
71 {
72 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
73 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
74 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
75 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
76 } LL_RCC_ClocksTypeDef;
77
78 /**
79 * @}
80 */
81
82 /**
83 * @}
84 */
85 #endif /* USE_FULL_LL_DRIVER */
86
87 /* Exported constants --------------------------------------------------------*/
88 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
89 * @{
90 */
91
92 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
93 * @brief Defines used to adapt values of different oscillators
94 * @note These values could be modified in the user environment according to
95 * HW set-up.
96 * @{
97 */
98 #if !defined (HSE_VALUE)
99 #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
100 #endif /* HSE_VALUE */
101
102 #if !defined (HSI_VALUE)
103 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
104 #endif /* HSI_VALUE */
105
106 #if !defined (LSE_VALUE)
107 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
108 #endif /* LSE_VALUE */
109
110 #if !defined (LSI_VALUE)
111 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
112 #endif /* LSI_VALUE */
113
114 #if !defined (HSI48_VALUE)
115 #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
116 #endif /* HSI48_VALUE */
117
118 #if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
119 #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */
120 #endif /* EXTERNAL_SAI1_CLOCK_VALUE */
121
122 #if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
123 #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz */
124 #endif /* EXTERNAL_SAI2_CLOCK_VALUE */
125 /**
126 * @}
127 */
128
129 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
130 * @brief Flags defines which can be used with LL_RCC_WriteReg function
131 * @{
132 */
133 #define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */
134 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
135 #define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */
136 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
137 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
138 #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */
139 #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */
140 #define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */
141 #define LL_RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC /*!< PLLSAI2 Ready Interrupt Clear */
142 #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */
143 /**
144 * @}
145 */
146
147 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
148 * @brief Flags defines which can be used with LL_RCC_ReadReg function
149 * @{
150 */
151 #define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
152 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
153 #define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */
154 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
155 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
156 #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
157 #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
158 #define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */
159 #define LL_RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */
160 #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
161 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
162 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
163 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
164 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
165 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
166 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
167 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
168 /**
169 * @}
170 */
171
172 /** @defgroup RCC_LL_EC_IT IT Defines
173 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
174 * @{
175 */
176 #define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */
177 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
178 #define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable */
179 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
180 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
181 #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */
182 #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */
183 #define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE /*!< PLLSAI1 Ready Interrupt Enable */
184 #define LL_RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE /*!< PLLSAI2 Ready Interrupt Enable */
185 /**
186 * @}
187 */
188
189 /** @defgroup RCC_LL_EC_LSIPRE LSI prescaler
190 * @{
191 */
192 #define LL_RCC_LSI_DIV_1 0UL /*!< LSI divided by 1 */
193 #define LL_RCC_LSI_DIV_128 RCC_CSR_LSIPRE /*!< LSI divided by 128 */
194 /**
195 * @}
196 */
197
198 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
199 * @{
200 */
201 #define LL_RCC_LSEDRIVE_LOW 0UL /*!< Xtal mode lower driving capability */
202 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
203 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
204 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
205 /**
206 * @}
207 */
208
209 /** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges
210 * @{
211 */
212 #define LL_RCC_MSIRANGE_0 0UL /*!< MSI = 100 kHz */
213 #define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_0 /*!< MSI = 200 kHz */
214 #define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_1 /*!< MSI = 400 kHz */
215 #define LL_RCC_MSIRANGE_3 (RCC_CR_MSIRANGE_1 | RCC_CR_MSIRANGE_0) /*!< MSI = 800 kHz */
216 #define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_2 /*!< MSI = 1 MHz */
217 #define LL_RCC_MSIRANGE_5 (RCC_CR_MSIRANGE_2 | RCC_CR_MSIRANGE_0) /*!< MSI = 2 MHz */
218 #define LL_RCC_MSIRANGE_6 (RCC_CR_MSIRANGE_2 | RCC_CR_MSIRANGE_1) /*!< MSI = 4 MHz */
219 #define LL_RCC_MSIRANGE_7 (RCC_CR_MSIRANGE_2 | RCC_CR_MSIRANGE_1 | RCC_CR_MSIRANGE_0) /*!< MSI = 8 MHz */
220 #define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_3 /*!< MSI = 16 MHz */
221 #define LL_RCC_MSIRANGE_9 (RCC_CR_MSIRANGE_3 | RCC_CR_MSIRANGE_0) /*!< MSI = 24 MHz */
222 #define LL_RCC_MSIRANGE_10 (RCC_CR_MSIRANGE_3 | RCC_CR_MSIRANGE_1) /*!< MSI = 32 MHz */
223 #define LL_RCC_MSIRANGE_11 (RCC_CR_MSIRANGE_3 | RCC_CR_MSIRANGE_1 | RCC_CR_MSIRANGE_0) /*!< MSI = 48 MHz */
224 /**
225 * @}
226 */
227
228 /** @defgroup RCC_LL_EC_MSISRANGE MSI range after Standby mode
229 * @{
230 */
231 #define LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_2 /*!< MSI = 1 MHz */
232 #define LL_RCC_MSISRANGE_5 (RCC_CSR_MSISRANGE_2 | RCC_CSR_MSISRANGE_0) /*!< MSI = 2 MHz */
233 #define LL_RCC_MSISRANGE_6 (RCC_CSR_MSISRANGE_2 | RCC_CSR_MSISRANGE_1) /*!< MSI = 4 MHz */
234 #define LL_RCC_MSISRANGE_7 (RCC_CSR_MSISRANGE_2 | RCC_CSR_MSISRANGE_1 | RCC_CSR_MSISRANGE_0) /*!< MSI = 8 MHz */
235 /**
236 * @}
237 */
238
239 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
240 * @{
241 */
242 #define LL_RCC_LSCO_CLKSOURCE_LSI 0UL /*!< LSI selection for low speed clock */
243 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
244 /**
245 * @}
246 */
247
248 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
249 * @{
250 */
251 #define LL_RCC_SYS_CLKSOURCE_MSI 0UL /*!< MSI selection as system clock */
252 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_0 /*!< HSI selection as system clock */
253 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_1 /*!< HSE selection as system clock */
254 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW /*!< PLL selection as system clock */
255 /**
256 * @}
257 */
258
259 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
260 * @{
261 */
262 #define LL_RCC_SYS_CLKSOURCE_STATUS_MSI 0UL /*!< MSI used as system clock */
263 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_0 /*!< HSI used as system clock */
264 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_1 /*!< HSE used as system clock */
265 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS /*!< PLL used as system clock */
266 /**
267 * @}
268 */
269
270 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
271 * @{
272 */
273 #define LL_RCC_SYSCLK_DIV_1 0UL /*!< SYSCLK not divided */
274 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */
275 #define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */
276 #define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */
277 #define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */
278 #define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */
279 #define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */
280 #define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */
281 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 512 */
282 /**
283 * @}
284 */
285
286 /** @defgroup RCC_LL_EC_APB1_DIV APB1 prescaler
287 * @{
288 */
289 #define LL_RCC_APB1_DIV_1 0UL /*!< HCLK not divided */
290 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_2 /*!< HCLK divided by 2 */
291 #define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_0) /*!< HCLK divided by 4 */
292 #define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1) /*!< HCLK divided by 8 */
293 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1 /*!< HCLK divided by 16 */
294 /**
295 * @}
296 */
297
298 /** @defgroup RCC_LL_EC_APB2_DIV APB2 prescaler
299 * @{
300 */
301 #define LL_RCC_APB2_DIV_1 0UL /*!< HCLK not divided */
302 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_2 /*!< HCLK divided by 2 */
303 #define LL_RCC_APB2_DIV_4 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_0) /*!< HCLK divided by 4 */
304 #define LL_RCC_APB2_DIV_8 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1) /*!< HCLK divided by 8 */
305 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2 /*!< HCLK divided by 16 */
306 /**
307 * @}
308 */
309
310 /** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection
311 * @{
312 */
313 #define LL_RCC_STOP_WAKEUPCLOCK_MSI 0UL /*!< MSI selection after wake-up from STOP */
314 #define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */
315 /**
316 * @}
317 */
318
319 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
320 * @{
321 */
322 #define LL_RCC_MCO1SOURCE_NOCLOCK 0UL /*!< MCO output disabled, no clock on MCO */
323 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
324 #define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */
325 #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */
326 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
327 #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */
328 #define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
329 #define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
330 #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */
331 /**
332 * @}
333 */
334
335 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
336 * @{
337 */
338 #define LL_RCC_MCO1_DIV_1 0UL /*!< MCO not divided */
339 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO divided by 2 */
340 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO divided by 4 */
341 #define LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 8 */
342 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO divided by 16 */
343 /**
344 * @}
345 */
346
347 #if defined(USE_FULL_LL_DRIVER)
348 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
349 * @{
350 */
351 #define LL_RCC_PERIPH_FREQUENCY_NO 0UL /*!< No clock enabled for the peripheral */
352 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFUL /*!< Frequency cannot be provided as external clock */
353 /**
354 * @}
355 */
356 #endif /* USE_FULL_LL_DRIVER */
357
358 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
359 * @{
360 */
361 #define LL_RCC_RTC_CLKSOURCE_NONE 0UL /*!< No clock used as RTC clock */
362 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
363 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
364 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
365 /**
366 * @}
367 */
368
369 /** @defgroup RCC_LL_EC_USART_CLKSOURCE Peripheral USARTx clock source selection
370 * @{
371 */
372 #define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR1_USART1SEL << 16U) /*!< PCLK2 clock used as USART1 clock source */
373 #define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR1_USART1SEL << 16U) | RCC_CCIPR1_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
374 #define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR1_USART1SEL << 16U) | RCC_CCIPR1_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
375 #define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR1_USART1SEL << 16U) | RCC_CCIPR1_USART1SEL) /*!< LSE clock used as USART1 clock source */
376 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR1_USART2SEL << 16U) /*!< PCLK1 clock used as USART2 clock source */
377 #define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR1_USART2SEL << 16U) | RCC_CCIPR1_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
378 #define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR1_USART2SEL << 16U) | RCC_CCIPR1_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
379 #define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR1_USART2SEL << 16U) | RCC_CCIPR1_USART2SEL) /*!< LSE clock used as USART2 clock source */
380 #define LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR1_USART3SEL << 16U) /*!< PCLK1 clock used as USART3 clock source */
381 #define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR1_USART3SEL << 16U) | RCC_CCIPR1_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
382 #define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR1_USART3SEL << 16U) | RCC_CCIPR1_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
383 #define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR1_USART3SEL << 16U) | RCC_CCIPR1_USART3SEL) /*!< LSE clock used as USART3 clock source */
384 /**
385 * @}
386 */
387
388 /** @defgroup RCC_LL_EC_UART_CLKSOURCE Peripheral UARTx clock source selection
389 * @{
390 */
391 #define LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR1_UART4SEL << 16U) /*!< PCLK1 clock used as UART4 clock source */
392 #define LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR1_UART4SEL << 16U) | RCC_CCIPR1_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */
393 #define LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR1_UART4SEL << 16U) | RCC_CCIPR1_UART4SEL_1) /*!< HSI clock used as UART4 clock source */
394 #define LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR1_UART4SEL << 16U) | RCC_CCIPR1_UART4SEL) /*!< LSE clock used as UART4 clock source */
395 #define LL_RCC_UART5_CLKSOURCE_PCLK1 (RCC_CCIPR1_UART5SEL << 16U) /*!< PCLK1 clock used as UART5 clock source */
396 #define LL_RCC_UART5_CLKSOURCE_SYSCLK ((RCC_CCIPR1_UART5SEL << 16U) | RCC_CCIPR1_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */
397 #define LL_RCC_UART5_CLKSOURCE_HSI ((RCC_CCIPR1_UART5SEL << 16U) | RCC_CCIPR1_UART5SEL_1) /*!< HSI clock used as UART5 clock source */
398 #define LL_RCC_UART5_CLKSOURCE_LSE ((RCC_CCIPR1_UART5SEL << 16U) | RCC_CCIPR1_UART5SEL) /*!< LSE clock used as UART5 clock source */
399 /**
400 * @}
401 */
402
403 /** @defgroup RCC_LL_EC_LPUART_CLKSOURCE Peripheral LPUARTx clock source selection
404 * @{
405 */
406 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0UL /*!< PCLK1 clock used as LPUART1 clock source */
407 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR1_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */
408 #define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR1_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */
409 #define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR1_LPUART1SEL /*!< LSE clock used as LPUART1 clock source */
410 /**
411 * @}
412 */
413
414 /** @defgroup RCC_LL_EC_I2C_CLKSOURCE Peripheral I2Cx clock source selection
415 * @{
416 */
417 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */
418 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL_0 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */
419 #define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL_1 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */
420 #define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */
421 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | (RCC_CCIPR1_I2C2SEL_0 >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */
422 #define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | (RCC_CCIPR1_I2C2SEL_1 >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */
423 #define LL_RCC_I2C3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C3SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C3 clock source */
424 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C3SEL_Pos << 16U) | (RCC_CCIPR1_I2C3SEL_0 >> RCC_CCIPR1_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */
425 #define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C3SEL_Pos << 16U) | (RCC_CCIPR1_I2C3SEL_1 >> RCC_CCIPR1_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */
426 #define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */
427 #define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */
428 #define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */
429 /**
430 * @}
431 */
432
433 /** @defgroup RCC_LL_EC_LPTIM_CLKSOURCE Peripheral LPTIMx clock source selection
434 * @{
435 */
436 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 RCC_CCIPR1_LPTIM1SEL /*!< PCLK1 clock used as LPTIM1 clock source */
437 #define LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR1_LPTIM1SEL | (RCC_CCIPR1_LPTIM1SEL_0 >> 16U)) /*!< LSI clock used as LPTIM1 clock source */
438 #define LL_RCC_LPTIM1_CLKSOURCE_HSI (RCC_CCIPR1_LPTIM1SEL | (RCC_CCIPR1_LPTIM1SEL_1 >> 16U)) /*!< HSI clock used as LPTIM1 clock source */
439 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR1_LPTIM1SEL | (RCC_CCIPR1_LPTIM1SEL >> 16U)) /*!< LSE clock used as LPTIM1 clock source */
440 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 RCC_CCIPR1_LPTIM2SEL /*!< PCLK1 clock used as LPTIM2 clock source */
441 #define LL_RCC_LPTIM2_CLKSOURCE_LSI (RCC_CCIPR1_LPTIM2SEL | (RCC_CCIPR1_LPTIM2SEL_0 >> 16U)) /*!< LSI clock used as LPTIM2 clock source */
442 #define LL_RCC_LPTIM2_CLKSOURCE_HSI (RCC_CCIPR1_LPTIM2SEL | (RCC_CCIPR1_LPTIM2SEL_1 >> 16U)) /*!< HSI clock used as LPTIM2 clock source */
443 #define LL_RCC_LPTIM2_CLKSOURCE_LSE (RCC_CCIPR1_LPTIM2SEL | (RCC_CCIPR1_LPTIM2SEL >> 16U)) /*!< LSE clock used as LPTIM2 clock source */
444 #define LL_RCC_LPTIM3_CLKSOURCE_PCLK1 RCC_CCIPR1_LPTIM3SEL /*!< PCLK1 clock used as LPTIM3 clock source */
445 #define LL_RCC_LPTIM3_CLKSOURCE_LSI (RCC_CCIPR1_LPTIM3SEL | (RCC_CCIPR1_LPTIM3SEL_0 >> 16U)) /*!< LSI clock used as LPTIM3 clock source */
446 #define LL_RCC_LPTIM3_CLKSOURCE_HSI (RCC_CCIPR1_LPTIM3SEL | (RCC_CCIPR1_LPTIM3SEL_1 >> 16U)) /*!< HSI clock used as LPTIM3 clock source */
447 #define LL_RCC_LPTIM3_CLKSOURCE_LSE (RCC_CCIPR1_LPTIM3SEL | (RCC_CCIPR1_LPTIM3SEL >> 16U)) /*!< LSE clock used as LPTIM3 clock source */
448 /**
449 * @}
450 */
451
452 /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN kernel clock source selection
453 * @{
454 */
455 #define LL_RCC_FDCAN_CLKSOURCE_HSE 0UL /*!< HSE clock used as FDCAN kernel clock source */
456 #define LL_RCC_FDCAN_CLKSOURCE_PLL RCC_CCIPR1_FDCANSEL_0 /*!< PLL clock used as FDCAN kernel clock source */
457 #define LL_RCC_FDCAN_CLKSOURCE_PLLSAI1 RCC_CCIPR1_FDCANSEL_1 /*!< PLLSAI1 clock used as FDCAN kernel clock source */
458 /**
459 * @}
460 */
461
462 /** @defgroup RCC_LL_EC_SAI_CLKSOURCE Peripheral SAIx clock source selection
463 * @{
464 */
465 #define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR2_SAI1SEL << 16U) /*!< PLL clock used as SAI1 clock source */
466 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0) /*!< PLLSAI1 clock used as SAI1 clock source */
467 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< PLLSAI2 clock used as SAI1 clock source */
468 #define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */
469 #define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0)) /*!< External input clock used as SAI1 clock source */
470 #define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR2_SAI2SEL << 16U) /*!< PLL clock used as SAI2 clock source */
471 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_0) /*!< PLLSAI1 clock used as SAI2 clock source */
472 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_1) /*!< PLLSAI2 clock used as SAI2 clock source */
473 #define LL_RCC_SAI2_CLKSOURCE_HSI ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_2) /*!< HSI clock used as SAI2 clock source */
474 #define LL_RCC_SAI2_CLKSOURCE_PIN ((RCC_CCIPR2_SAI2SEL << 16U) | (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0)) /*!< External input clock used as SAI2 clock source */
475 /**
476 * @}
477 */
478
479 /** @defgroup RCC_LL_EC_SDMMC1_KERNELCLKSOURCE Peripheral SDMMC kernel clock source selection
480 * @{
481 */
482 #define LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK 0UL /*!< 48MHz clock from internal multiplexor used as SDMMC1 clock source */
483 #define LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLLP clock (PLLSAI3CLK) used as SDMMC1 clock source */
484 /**
485 * @}
486 */
487
488 /** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE Peripheral SDMMC clock source selection
489 * @{
490 */
491 #define LL_RCC_SDMMC1_CLKSOURCE_HSI48 0UL /*!< HSI48 clock used as SDMMC1 clock source in internal multiplexor */
492 #define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 RCC_CCIPR1_CLK48MSEL_0 /*!< PLLSAI1 clock used as SDMMC1 clock source in internal multiplexor */
493 #define LL_RCC_SDMMC1_CLKSOURCE_PLL RCC_CCIPR1_CLK48MSEL_1 /*!< PLLQ clock used as SDMMC1 clock source in internal multiplexor */
494 #define LL_RCC_SDMMC1_CLKSOURCE_MSI RCC_CCIPR1_CLK48MSEL /*!< MSI clock used as SDMMC1 clock source in internal multiplexor */
495 /**
496 * @}
497 */
498
499 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
500 * @{
501 */
502 #define LL_RCC_RNG_CLKSOURCE_HSI48 0UL /*!< HSI48 clock used as RNG clock source */
503 #define LL_RCC_RNG_CLKSOURCE_PLLSAI1 RCC_CCIPR1_CLK48MSEL_0 /*!< PLLSAI1 clock used as RNG clock source */
504 #define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR1_CLK48MSEL_1 /*!< PLL clock used as RNG clock source */
505 #define LL_RCC_RNG_CLKSOURCE_MSI RCC_CCIPR1_CLK48MSEL /*!< MSI clock used as RNG clock source */
506 /**
507 * @}
508 */
509
510 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
511 * @{
512 */
513 #define LL_RCC_USB_CLKSOURCE_HSI48 0UL /*!< HSI48 clock used as USB clock source */
514 #define LL_RCC_USB_CLKSOURCE_PLLSAI1 RCC_CCIPR1_CLK48MSEL_0 /*!< PLLSAI1 clock used as USB clock source */
515 #define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR1_CLK48MSEL_1 /*!< PLL clock used as USB clock source */
516 #define LL_RCC_USB_CLKSOURCE_MSI RCC_CCIPR1_CLK48MSEL /*!< MSI clock used as USB clock source */
517 /**
518 * @}
519 */
520
521 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADCx clock source selection
522 * @{
523 */
524 #define LL_RCC_ADC_CLKSOURCE_NONE 0UL /*!< No clock used as ADC clock source */
525 #define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR1_ADCSEL_0 /*!< PLLSAI1 clock used as ADC clock source */
526 #define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR1_ADCSEL /*!< SYSCLK clock used as ADC clock source */
527 /**
528 * @}
529 */
530
531 /** @defgroup RCC_LL_EC_DFSDM_AUDIO_CLKSOURCE Peripheral DFSDMx Audio clock source selection
532 * @{
533 */
534 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0UL /*!< SAI1 clock used as DFSDM1 Audio clock */
535 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI RCC_CCIPR2_ADFSDMSEL_0 /*!< HSI clock used as DFSDM1 Audio clock */
536 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI RCC_CCIPR2_ADFSDMSEL_1 /*!< MSI clock used as DFSDM1 Audio clock */
537 /**
538 * @}
539 */
540
541 /** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM1 clock source selection
542 * @{
543 */
544 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0UL /*!< PCLK2 clock used as DFSDM1 clock source */
545 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDMSEL /*!< SYSCLK clock used as DFSDM1 clock source */
546 /**
547 * @}
548 */
549
550 /** @defgroup RCC_LL_EC_OCTOSPI_CLKSOURCE Peripheral OCTOSPI kernel clock source selection
551 * @{
552 */
553 #define LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 0UL /*!< SYSCLK clock used as OctoSPI kernel clock source */
554 #define LL_RCC_OCTOSPI_CLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 /*!< MSI clock used as OctoSPI kernel clock source */
555 #define LL_RCC_OCTOSPI_CLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 /*!< PLL clock used as OctoSPI kernel clock source */
556 /**
557 * @}
558 */
559
560 /** @defgroup RCC_LL_EC_USART Peripheral USARTx get clock source
561 * @{
562 */
563 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR1_USART1SEL /*!< USART1 Clock source selection */
564 #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR1_USART2SEL /*!< USART2 Clock source selection */
565 #define LL_RCC_USART3_CLKSOURCE RCC_CCIPR1_USART3SEL /*!< USART3 Clock source selection */
566 /**
567 * @}
568 */
569
570 /** @defgroup RCC_LL_EC_UART Peripheral UARTx get clock source
571 * @{
572 */
573 #define LL_RCC_UART4_CLKSOURCE RCC_CCIPR1_UART4SEL /*!< UART4 Clock source selection */
574 #define LL_RCC_UART5_CLKSOURCE RCC_CCIPR1_UART5SEL /*!< UART5 Clock source selection */
575 /**
576 * @}
577 */
578
579 /** @defgroup RCC_LL_EC_LPUART Peripheral LPUARTx get clock source
580 * @{
581 */
582 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR1_LPUART1SEL /*!< LPUART1 Clock source selection */
583 /**
584 * @}
585 */
586
587 /** @defgroup RCC_LL_EC_I2C Peripheral I2Cx get clock source
588 * @{
589 */
590 #define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
591 #define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | (RCC_CCIPR1_I2C2SEL >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */
592 #define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C3SEL_Pos << 16U) | (RCC_CCIPR1_I2C3SEL >> RCC_CCIPR1_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
593 #define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */
594 /**
595 * @}
596 */
597
598 /** @defgroup RCC_LL_EC_LPTIM Peripheral LPTIMx get clock source
599 * @{
600 */
601 #define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR1_LPTIM1SEL /*!< LPTIM1 Clock source selection */
602 #define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR1_LPTIM2SEL /*!< LPTIM2 Clock source selection */
603 #define LL_RCC_LPTIM3_CLKSOURCE RCC_CCIPR1_LPTIM3SEL /*!< LPTIM3 Clock source selection */
604 /**
605 * @}
606 */
607
608 /** @defgroup RCC_LL_EC_SAI Peripheral SAIx get clock source
609 * @{
610 */
611 #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL /*!< SAI1 Clock source selection */
612 #define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR2_SAI2SEL /*!< SAI2 Clock source selection */
613 /**
614 * @}
615 */
616
617 /** @defgroup RCC_LL_EC_SDMMC_KERNEL Peripheral SDMMC get kernel clock source
618 * @{
619 */
620 #define LL_RCC_SDMMC1_KERNELCLKSOURCE RCC_CCIPR2_SDMMCSEL /*!< SDMMC1 Kernel Clock source selection */
621 /**
622 * @}
623 */
624
625 /** @defgroup RCC_LL_EC_SDMMC Peripheral SDMMC get clock source
626 * @{
627 */
628 #define LL_RCC_SDMMC1_CLKSOURCE RCC_CCIPR1_CLK48MSEL /*!< SDMMC1 Clock source selection */
629 /**
630 * @}
631 */
632
633 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
634 * @{
635 */
636 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR1_CLK48MSEL /*!< RNG Clock source selection */
637 /**
638 * @}
639 */
640
641 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
642 * @{
643 */
644 #define LL_RCC_USB_CLKSOURCE RCC_CCIPR1_CLK48MSEL /*!< USB Clock source selection */
645 /**
646 * @}
647 */
648
649 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
650 * @{
651 */
652 #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR1_ADCSEL /*!< ADCs Clock source selection */
653 /**
654 * @}
655 */
656
657 /** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM1 Audio get clock source
658 * @{
659 */
660 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_CCIPR2_ADFSDMSEL /* DFSDM1 Audio Clock source selection */
661 /**
662 * @}
663 */
664
665 /** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM1 get kernel clock source
666 * @{
667 */
668 #define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR2_DFSDMSEL /*!< DFSDM1 Clock source selection */
669 /**
670 * @}
671 */
672
673 /** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get kernel clock source
674 * @{
675 */
676 #define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR1_FDCANSEL /*!< FDCAN Kernel Clock source selection */
677 /**
678 * @}
679 */
680
681 /** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source
682 * @{
683 */
684 #define LL_RCC_OCTOSPI_CLKSOURCE RCC_CCIPR2_OSPISEL /*!< OctoSPI Clock source selection */
685 /**
686 * @}
687 */
688
689 /** @defgroup RCC_LL_EC_PLLSOURCE PLL entry clock source
690 * @{
691 */
692 #define LL_RCC_PLLSOURCE_NONE 0UL /*!< No clock selected as main PLL entry clock source */
693 #define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_0 /*!< MSI clock selected as main PLL entry clock source */
694 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_1 /*!< HSI16 clock selected as main PLL entry clock source */
695 #define LL_RCC_PLLSOURCE_HSE (RCC_PLLCFGR_PLLSRC_1 | RCC_PLLCFGR_PLLSRC_0) /*!< HSE clock selected as main PLL entry clock source */
696 /**
697 * @}
698 */
699
700 /** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor
701 * @{
702 */
703 #define LL_RCC_PLLM_DIV_1 0UL /*!< Main PLL division factor for PLLM input by 1 */
704 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 2 */
705 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 3 */
706 #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 4 */
707 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< Main PLL division factor for PLLM input by 5 */
708 #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 6 */
709 #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 7 */
710 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 8 */
711 #define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3) /*!< Main PLL division factor for PLLM input by 9 */
712 #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 10 */
713 #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 11 */
714 #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 12 */
715 #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< Main PLL division factor for PLLM input by 13 */
716 #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 14 */
717 #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 15 */
718 #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 16 */
719 /**
720 * @}
721 */
722
723 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
724 * @{
725 */
726 #define LL_RCC_PLLR_DIV_2 0UL /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
727 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
728 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
729 #define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
730 /**
731 * @}
732 */
733
734 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
735 * @{
736 */
737 #define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 2 */
738 #define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 3 */
739 #define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 4 */
740 #define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 5 */
741 #define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 6 */
742 #define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 7 */
743 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 8 */
744 #define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 9 */
745 #define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 10 */
746 #define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 11 */
747 #define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 12 */
748 #define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 13 */
749 #define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 14 */
750 #define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 15 */
751 #define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 16 */
752 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 17 */
753 #define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 18 */
754 #define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 19 */
755 #define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 20 */
756 #define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 21 */
757 #define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 22 */
758 #define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 23 */
759 #define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 24 */
760 #define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 25 */
761 #define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 26 */
762 #define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 27 */
763 #define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 28 */
764 #define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 29 */
765 #define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 30 */
766 #define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 31 */
767 /**
768 * @}
769 */
770
771 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
772 * @{
773 */
774 #define LL_RCC_PLLQ_DIV_2 0UL /*!< Main PLL division factor for PLLQ output by 2 */
775 #define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */
776 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
777 #define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */
778 /**
779 * @}
780 */
781
782 /** @defgroup RCC_LL_EC_PLLSAI1SOURCE PLLSAI1 entry clock source
783 * @{
784 */
785 #define LL_RCC_PLLSAI1SOURCE_NONE 0UL /*!< No clock selected as PLLSAI1 entry clock source */
786 #define LL_RCC_PLLSAI1SOURCE_MSI RCC_PLLSAI1CFGR_PLLSAI1SRC_0 /*!< MSI clock selected as PLLSAI1 entry clock source */
787 #define LL_RCC_PLLSAI1SOURCE_HSI RCC_PLLSAI1CFGR_PLLSAI1SRC_1 /*!< HSI16 clock selected as PLLSAI1 entry clock source */
788 #define LL_RCC_PLLSAI1SOURCE_HSE (RCC_PLLSAI1CFGR_PLLSAI1SRC_1 | RCC_PLLSAI1CFGR_PLLSAI1SRC_0) /*!< HSE clock selected as PLLSAI1 entry clock source */
789 /**
790 * @}
791 */
792
793 /** @defgroup RCC_LL_EC_PLLSAI1M PLLSAI1 division factor (PLLSAI1M)
794 * @{
795 */
796 #define LL_RCC_PLLSAI1M_DIV_1 0UL /*!< PLLSAI1 division factor for PLLSAI1M input by 1 */
797 #define LL_RCC_PLLSAI1M_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 2 */
798 #define LL_RCC_PLLSAI1M_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 3 */
799 #define LL_RCC_PLLSAI1M_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 4 */
800 #define LL_RCC_PLLSAI1M_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1M_2) /*!< PLLSAI1 division factor for PLLSAI1M input by 5 */
801 #define LL_RCC_PLLSAI1M_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 6 */
802 #define LL_RCC_PLLSAI1M_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 7 */
803 #define LL_RCC_PLLSAI1M_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 8 */
804 #define LL_RCC_PLLSAI1M_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1M_3) /*!< PLLSAI1 division factor for PLLSAI1M input by 9 */
805 #define LL_RCC_PLLSAI1M_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 10 */
806 #define LL_RCC_PLLSAI1M_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 11 */
807 #define LL_RCC_PLLSAI1M_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 12 */
808 #define LL_RCC_PLLSAI1M_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2) /*!< PLLSAI1 division factor for PLLSAI1M input by 13 */
809 #define LL_RCC_PLLSAI1M_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 14 */
810 #define LL_RCC_PLLSAI1M_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 15 */
811 #define LL_RCC_PLLSAI1M_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 16 */
812 /**
813 * @}
814 */
815
816 /** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLSAI1Q)
817 * @{
818 */
819 #define LL_RCC_PLLSAI1Q_DIV_2 0UL /*!< PLLSAI1 division factor for PLLSAI1Q output by 2 */
820 #define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1Q_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 4 */
821 #define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1Q_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 6 */
822 #define LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1Q) /*!< PLLSAI1 division factor for PLLSAI1Q output by 8 */
823 /**
824 * @}
825 */
826
827 /** @defgroup RCC_LL_EC_PLLSAI1P PLLSAI1 division factor (PLLSAI1P)
828 * @{
829 */
830 #define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 2 */
831 #define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 3 */
832 #define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 4 */
833 #define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 5 */
834 #define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 6 */
835 #define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */
836 #define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 8 */
837 #define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 9 */
838 #define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 10 */
839 #define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 1 */
840 #define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 12 */
841 #define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 13 */
842 #define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 14 */
843 #define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 15 */
844 #define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 16 */
845 #define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */
846 #define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 18 */
847 #define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 19 */
848 #define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 20 */
849 #define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division fctor for PLLSAI1P output by 21 */
850 #define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 22 */
851 #define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 23 */
852 #define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 24 */
853 #define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 25 */
854 #define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 26 */
855 #define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 27 */
856 #define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 28 */
857 #define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 29 */
858 #define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 30 */
859 #define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */
860 /**
861 * @}
862 */
863
864 /** @defgroup RCC_LL_EC_PLLSAI1R PLLSAI1 division factor (PLLSAI1R)
865 * @{
866 */
867 #define LL_RCC_PLLSAI1R_DIV_2 0UL /*!< PLLSAI1 division factor for PLLSAI1R output by 2 */
868 #define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1R_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 4 */
869 #define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1R_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 6 */
870 #define LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1R) /*!< PLLSAI1 division factor for PLLSAI1R output by 8 */
871 /**
872 * @}
873 */
874
875 /** @defgroup RCC_LL_EC_PLLSAI2SOURCE PLLSAI2 entry clock source
876 * @{
877 */
878 #define LL_RCC_PLLSAI2SOURCE_NONE 0UL /*!< No clock selected as PLLSAI2 entry clock source */
879 #define LL_RCC_PLLSAI2SOURCE_MSI RCC_PLLSAI2CFGR_PLLSAI2SRC_0 /*!< MSI clock selected as PLLSAI2 entry clock source */
880 #define LL_RCC_PLLSAI2SOURCE_HSI RCC_PLLSAI2CFGR_PLLSAI2SRC_1 /*!< HSI16 clock selected as PLLSAI2 entry clock source */
881 #define LL_RCC_PLLSAI2SOURCE_HSE (RCC_PLLSAI2CFGR_PLLSAI2SRC_1 | RCC_PLLSAI2CFGR_PLLSAI2SRC_0) /*!< HSE clock selected as PLLSAI2 entry clock source */
882 /**
883 * @}
884 */
885
886 /** @defgroup RCC_LL_EC_PLLSAI2M PLLSAI2 division factor (PLLSAI2M)
887 * @{
888 */
889 #define LL_RCC_PLLSAI2M_DIV_1 0UL /*!< PLLSAI2 division factor for PLLSAI2M input by 1 */
890 #define LL_RCC_PLLSAI2M_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 2 */
891 #define LL_RCC_PLLSAI2M_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 3 */
892 #define LL_RCC_PLLSAI2M_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 4 */
893 #define LL_RCC_PLLSAI2M_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2M_2) /*!< PLLSAI2 division factor for PLLSAI2M input by 5 */
894 #define LL_RCC_PLLSAI2M_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 6 */
895 #define LL_RCC_PLLSAI2M_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 7 */
896 #define LL_RCC_PLLSAI2M_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 8 */
897 #define LL_RCC_PLLSAI2M_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2M_3) /*!< PLLSAI2 division factor for PLLSAI2M input by 9 */
898 #define LL_RCC_PLLSAI2M_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 10 */
899 #define LL_RCC_PLLSAI2M_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 11 */
900 #define LL_RCC_PLLSAI2M_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 12 */
901 #define LL_RCC_PLLSAI2M_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2) /*!< PLLSAI2 division factor for PLLSAI2M input by 13 */
902 #define LL_RCC_PLLSAI2M_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 14 */
903 #define LL_RCC_PLLSAI2M_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 15 */
904 #define LL_RCC_PLLSAI2M_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 16 */
905 /**
906 * @}
907 */
908
909 /** @defgroup RCC_LL_EC_PLLSAI2P PLLSAI2 division factor (PLLSAI2P)
910 * @{
911 */
912 #define LL_RCC_PLLSAI2P_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 2 */
913 #define LL_RCC_PLLSAI2P_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 3 */
914 #define LL_RCC_PLLSAI2P_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 4 */
915 #define LL_RCC_PLLSAI2P_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 5 */
916 #define LL_RCC_PLLSAI2P_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 6 */
917 #define LL_RCC_PLLSAI2P_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */
918 #define LL_RCC_PLLSAI2P_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /*!< PLLSAI2 division factor for PLLSAI2P output by 8 */
919 #define LL_RCC_PLLSAI2P_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 9 */
920 #define LL_RCC_PLLSAI2P_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 10 */
921 #define LL_RCC_PLLSAI2P_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 1 */
922 #define LL_RCC_PLLSAI2P_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 12 */
923 #define LL_RCC_PLLSAI2P_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 13 */
924 #define LL_RCC_PLLSAI2P_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 14 */
925 #define LL_RCC_PLLSAI2P_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 15 */
926 #define LL_RCC_PLLSAI2P_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4) /*!< PLLSAI2 division factor for PLLSAI2P output by 16 */
927 #define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */
928 #define LL_RCC_PLLSAI2P_DIV_18 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 18 */
929 #define LL_RCC_PLLSAI2P_DIV_19 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 19 */
930 #define LL_RCC_PLLSAI2P_DIV_20 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 20 */
931 #define LL_RCC_PLLSAI2P_DIV_21 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division fctor for PLLSAI2P output by 21 */
932 #define LL_RCC_PLLSAI2P_DIV_22 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 22 */
933 #define LL_RCC_PLLSAI2P_DIV_23 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 23 */
934 #define LL_RCC_PLLSAI2P_DIV_24 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /*!< PLLSAI2 division factor for PLLSAI2P output by 24 */
935 #define LL_RCC_PLLSAI2P_DIV_25 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 25 */
936 #define LL_RCC_PLLSAI2P_DIV_26 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 26 */
937 #define LL_RCC_PLLSAI2P_DIV_27 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 27 */
938 #define LL_RCC_PLLSAI2P_DIV_28 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 28 */
939 #define LL_RCC_PLLSAI2P_DIV_29 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 29 */
940 #define LL_RCC_PLLSAI2P_DIV_30 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 30 */
941 #define LL_RCC_PLLSAI2P_DIV_31 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 31 */
942 /**
943 * @}
944 */
945
946 /** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection
947 * @{
948 */
949 #define LL_RCC_MSIRANGESEL_STANDBY 0U /*!< MSI Range is provided by MSISRANGE */
950 #define LL_RCC_MSIRANGESEL_RUN 1U /*!< MSI Range is provided by MSIRANGE */
951 /**
952 * @}
953 */
954
955 /** @defgroup RCC_LL_EC_SECURE_ATTRIBUTES Secure attributes
956 * @note Only available when system implements security (TZEN=1)
957 * @{
958 */
959 #define LL_RCC_ALL_SEC RCC_SECURE_MASK /*!< Security on all RCC resources */
960 #define LL_RCC_ALL_NSEC 0U /*!< No security on RCC resources (default) */
961
962 #define LL_RCC_HSI_SEC RCC_SECCFGR_HSISEC /*!< HSI clock configuration secure-only access */
963 #define LL_RCC_HSI_NSEC 0U /*!< HSI clock configuration secure/non-secure access */
964 #define LL_RCC_HSE_SEC RCC_SECCFGR_HSESEC /*!< HSE clock configuration secure-only access */
965 #define LL_RCC_HSE_NSEC 0U /*!< HSE clock configuration secure/non-secure access */
966 #define LL_RCC_MSI_SEC RCC_SECCFGR_MSISEC /*!< MSI clock configuration secure-only access */
967 #define LL_RCC_MSI_NSEC 0U /*!< MSI clock configuration secure/non-secure access */
968 #define LL_RCC_LSI_SEC RCC_SECCFGR_LSISEC /*!< LSI clock configuration secure-only access */
969 #define LL_RCC_LSI_NSEC 0U /*!< LSI clock configuration secure/non-secure access */
970 #define LL_RCC_LSE_SEC RCC_SECCFGR_LSESEC /*!< LSE clock configuration secure-only access */
971 #define LL_RCC_LSE_NSEC 0U /*!< LSE clock configuration secure/non-secure access */
972 #define LL_RCC_SYSCLK_SEC RCC_SECCFGR_SYSCLKSEC /*!< SYSCLK clock; STOPWUCK and MCO output configuration secure-only access */
973 #define LL_RCC_SYSCLK_NSEC 0U /*!< SYSCLK clock; STOPWUCK and MCO output configuration secure/non-secure access */
974 #define LL_RCC_PRESCALERS_SEC RCC_SECCFGR_PRESCSEC /*!< AHBx/APBx prescaler configuration secure-only access */
975 #define LL_RCC_PRESCALERS_NSEC 0U /*!< AHBx/APBx prescaler configuration secure/non-secure access */
976 #define LL_RCC_PLL_SEC RCC_SECCFGR_PLLSEC /*!< main PLL clock configuration secure-only access */
977 #define LL_RCC_PLL_NSEC 0U /*!< main PLL clock configuration secure/non-secure access */
978 #define LL_RCC_PLLSAI1_SEC RCC_SECCFGR_PLLSAI1SEC /*!< PLLSAI1 clock configuration secure-only access */
979 #define LL_RCC_PLLSAI1_NSEC 0U /*!< PLLSAI1 clock configuration secure/non-secure access */
980 #define LL_RCC_PLLSAI2_SEC RCC_SECCFGR_PLLSAI2SEC /*!< PLLSAI2 clock configuration secure-only access */
981 #define LL_RCC_PLLSAI2_NSEC 0U /*!< PLLSAI2 clock configuration secure/non-secure access */
982 #define LL_RCC_CLK48M_SEC RCC_SECCFGR_CLK48MSEC /*!< 48MHz clock source selection secure-only access */
983 #define LL_RCC_CLK48M_NSEC 0U /*!< 48MHz clock source selection secure/non-secure access */
984 #define LL_RCC_HSI48_SEC RCC_SECCFGR_HSI48SEC /*!< HSI48 clock configuration secure-only access */
985 #define LL_RCC_HSI48_NSEC 0U /*!< HSI48 clock configuration secure/non-secure access */
986 #define LL_RCC_RESET_FLAGS_SEC RCC_SECCFGR_RMVFSEC /*!< Remove reset flag secure-ony access */
987 #define LL_RCC_RESET_FLAGS_NSEC 0U /*!< Remove reset flag secure/non-secure access */
988 /**
989 * @}
990 */
991
992 /**
993 * @}
994 */
995
996 /* Exported macro ------------------------------------------------------------*/
997 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
998 * @{
999 */
1000
1001 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
1002 * @{
1003 */
1004
1005 /**
1006 * @brief Write a value in RCC register
1007 * @param __REG__ Register to be written
1008 * @param __VALUE__ Value to be written in the register
1009 * @retval None
1010 */
1011 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1012
1013 /**
1014 * @brief Read a value in RCC register
1015 * @param __REG__ Register to be read
1016 * @retval Register value
1017 */
1018 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1019 /**
1020 * @}
1021 */
1022
1023 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
1024 * @{
1025 */
1026
1027 /**
1028 * @brief Helper macro to calculate the PLLCLK frequency on system domain
1029 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1030 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1031 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1032 * @param __PLLM__ This parameter can be one of the following values:
1033 * @arg @ref LL_RCC_PLLM_DIV_1
1034 * @arg @ref LL_RCC_PLLM_DIV_2
1035 * @arg @ref LL_RCC_PLLM_DIV_3
1036 * @arg @ref LL_RCC_PLLM_DIV_4
1037 * @arg @ref LL_RCC_PLLM_DIV_5
1038 * @arg @ref LL_RCC_PLLM_DIV_6
1039 * @arg @ref LL_RCC_PLLM_DIV_7
1040 * @arg @ref LL_RCC_PLLM_DIV_8
1041 * @arg @ref LL_RCC_PLLM_DIV_9
1042 * @arg @ref LL_RCC_PLLM_DIV_10
1043 * @arg @ref LL_RCC_PLLM_DIV_11
1044 * @arg @ref LL_RCC_PLLM_DIV_12
1045 * @arg @ref LL_RCC_PLLM_DIV_13
1046 * @arg @ref LL_RCC_PLLM_DIV_14
1047 * @arg @ref LL_RCC_PLLM_DIV_15
1048 * @arg @ref LL_RCC_PLLM_DIV_16
1049 * @param __PLLN__ Between 8 and 86
1050 * @param __PLLR__ This parameter can be one of the following values:
1051 * @arg @ref LL_RCC_PLLR_DIV_2
1052 * @arg @ref LL_RCC_PLLR_DIV_4
1053 * @arg @ref LL_RCC_PLLR_DIV_6
1054 * @arg @ref LL_RCC_PLLR_DIV_8
1055 * @retval PLL clock frequency (in Hz)
1056 */
1057 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) \
1058 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
1059 ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))
1060
1061 /**
1062 * @brief Helper macro to calculate the PLLCLK frequency used on SAI domain
1063 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1064 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
1065 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1066 * @param __PLLM__ This parameter can be one of the following values:
1067 * @arg @ref LL_RCC_PLLM_DIV_1
1068 * @arg @ref LL_RCC_PLLM_DIV_2
1069 * @arg @ref LL_RCC_PLLM_DIV_3
1070 * @arg @ref LL_RCC_PLLM_DIV_4
1071 * @arg @ref LL_RCC_PLLM_DIV_5
1072 * @arg @ref LL_RCC_PLLM_DIV_6
1073 * @arg @ref LL_RCC_PLLM_DIV_7
1074 * @arg @ref LL_RCC_PLLM_DIV_8
1075 * @arg @ref LL_RCC_PLLM_DIV_9
1076 * @arg @ref LL_RCC_PLLM_DIV_10
1077 * @arg @ref LL_RCC_PLLM_DIV_11
1078 * @arg @ref LL_RCC_PLLM_DIV_12
1079 * @arg @ref LL_RCC_PLLM_DIV_13
1080 * @arg @ref LL_RCC_PLLM_DIV_14
1081 * @arg @ref LL_RCC_PLLM_DIV_15
1082 * @arg @ref LL_RCC_PLLM_DIV_16
1083 * @param __PLLN__ Between 8 and 86
1084 * @param __PLLP__ This parameter can be one of the following values:
1085 * @arg @ref LL_RCC_PLLP_DIV_2
1086 * @arg @ref LL_RCC_PLLP_DIV_3
1087 * @arg @ref LL_RCC_PLLP_DIV_4
1088 * @arg @ref LL_RCC_PLLP_DIV_5
1089 * @arg @ref LL_RCC_PLLP_DIV_6
1090 * @arg @ref LL_RCC_PLLP_DIV_7
1091 * @arg @ref LL_RCC_PLLP_DIV_8
1092 * @arg @ref LL_RCC_PLLP_DIV_9
1093 * @arg @ref LL_RCC_PLLP_DIV_10
1094 * @arg @ref LL_RCC_PLLP_DIV_11
1095 * @arg @ref LL_RCC_PLLP_DIV_12
1096 * @arg @ref LL_RCC_PLLP_DIV_13
1097 * @arg @ref LL_RCC_PLLP_DIV_14
1098 * @arg @ref LL_RCC_PLLP_DIV_15
1099 * @arg @ref LL_RCC_PLLP_DIV_16
1100 * @arg @ref LL_RCC_PLLP_DIV_17
1101 * @arg @ref LL_RCC_PLLP_DIV_18
1102 * @arg @ref LL_RCC_PLLP_DIV_19
1103 * @arg @ref LL_RCC_PLLP_DIV_20
1104 * @arg @ref LL_RCC_PLLP_DIV_21
1105 * @arg @ref LL_RCC_PLLP_DIV_22
1106 * @arg @ref LL_RCC_PLLP_DIV_23
1107 * @arg @ref LL_RCC_PLLP_DIV_24
1108 * @arg @ref LL_RCC_PLLP_DIV_25
1109 * @arg @ref LL_RCC_PLLP_DIV_26
1110 * @arg @ref LL_RCC_PLLP_DIV_27
1111 * @arg @ref LL_RCC_PLLP_DIV_28
1112 * @arg @ref LL_RCC_PLLP_DIV_29
1113 * @arg @ref LL_RCC_PLLP_DIV_30
1114 * @arg @ref LL_RCC_PLLP_DIV_31
1115 * @retval PLL clock frequency (in Hz)
1116 */
1117 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \
1118 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
1119 ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos))
1120
1121 /**
1122 * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
1123 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1124 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
1125 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1126 * @param __PLLM__ This parameter can be one of the following values:
1127 * @arg @ref LL_RCC_PLLM_DIV_1
1128 * @arg @ref LL_RCC_PLLM_DIV_2
1129 * @arg @ref LL_RCC_PLLM_DIV_3
1130 * @arg @ref LL_RCC_PLLM_DIV_4
1131 * @arg @ref LL_RCC_PLLM_DIV_5
1132 * @arg @ref LL_RCC_PLLM_DIV_6
1133 * @arg @ref LL_RCC_PLLM_DIV_7
1134 * @arg @ref LL_RCC_PLLM_DIV_8
1135 * @arg @ref LL_RCC_PLLM_DIV_9
1136 * @arg @ref LL_RCC_PLLM_DIV_10
1137 * @arg @ref LL_RCC_PLLM_DIV_11
1138 * @arg @ref LL_RCC_PLLM_DIV_12
1139 * @arg @ref LL_RCC_PLLM_DIV_13
1140 * @arg @ref LL_RCC_PLLM_DIV_14
1141 * @arg @ref LL_RCC_PLLM_DIV_15
1142 * @arg @ref LL_RCC_PLLM_DIV_16
1143 * @param __PLLN__ Between 8 and 86
1144 * @param __PLLQ__ This parameter can be one of the following values:
1145 * @arg @ref LL_RCC_PLLQ_DIV_2
1146 * @arg @ref LL_RCC_PLLQ_DIV_4
1147 * @arg @ref LL_RCC_PLLQ_DIV_6
1148 * @arg @ref LL_RCC_PLLQ_DIV_8
1149 * @retval PLL clock frequency (in Hz)
1150 */
1151 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \
1152 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
1153 ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))
1154
1155 /**
1156 * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
1157 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
1158 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
1159 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1160 * @param __PLLSAI1M__ This parameter can be one of the following values:
1161 * @arg @ref LL_RCC_PLLSAI1M_DIV_1
1162 * @arg @ref LL_RCC_PLLSAI1M_DIV_2
1163 * @arg @ref LL_RCC_PLLSAI1M_DIV_3
1164 * @arg @ref LL_RCC_PLLSAI1M_DIV_4
1165 * @arg @ref LL_RCC_PLLSAI1M_DIV_5
1166 * @arg @ref LL_RCC_PLLSAI1M_DIV_6
1167 * @arg @ref LL_RCC_PLLSAI1M_DIV_7
1168 * @arg @ref LL_RCC_PLLSAI1M_DIV_8
1169 * @arg @ref LL_RCC_PLLSAI1M_DIV_9
1170 * @arg @ref LL_RCC_PLLSAI1M_DIV_10
1171 * @arg @ref LL_RCC_PLLSAI1M_DIV_11
1172 * @arg @ref LL_RCC_PLLSAI1M_DIV_12
1173 * @arg @ref LL_RCC_PLLSAI1M_DIV_13
1174 * @arg @ref LL_RCC_PLLSAI1M_DIV_14
1175 * @arg @ref LL_RCC_PLLSAI1M_DIV_15
1176 * @arg @ref LL_RCC_PLLSAI1M_DIV_16
1177 * @param __PLLSAI1N__ Between 8 and 86
1178 * @param __PLLSAI1P__ This parameter can be one of the following values:
1179 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
1180 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
1181 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
1182 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
1183 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
1184 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
1185 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
1186 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
1187 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
1188 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
1189 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
1190 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
1191 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
1192 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
1193 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
1194 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
1195 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
1196 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
1197 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
1198 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
1199 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
1200 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
1201 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
1202 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
1203 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
1204 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
1205 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
1206 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
1207 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
1208 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
1209 * @retval PLLSAI1 clock frequency (in Hz)
1210 */
1211 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__) \
1212 ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
1213 ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))
1214
1215 /**
1216 * @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain
1217 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
1218 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());
1219 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1220 * @param __PLLSAI1M__ This parameter can be one of the following values:
1221 * @arg @ref LL_RCC_PLLSAI1M_DIV_1
1222 * @arg @ref LL_RCC_PLLSAI1M_DIV_2
1223 * @arg @ref LL_RCC_PLLSAI1M_DIV_3
1224 * @arg @ref LL_RCC_PLLSAI1M_DIV_4
1225 * @arg @ref LL_RCC_PLLSAI1M_DIV_5
1226 * @arg @ref LL_RCC_PLLSAI1M_DIV_6
1227 * @arg @ref LL_RCC_PLLSAI1M_DIV_7
1228 * @arg @ref LL_RCC_PLLSAI1M_DIV_8
1229 * @arg @ref LL_RCC_PLLSAI1M_DIV_9
1230 * @arg @ref LL_RCC_PLLSAI1M_DIV_10
1231 * @arg @ref LL_RCC_PLLSAI1M_DIV_11
1232 * @arg @ref LL_RCC_PLLSAI1M_DIV_12
1233 * @arg @ref LL_RCC_PLLSAI1M_DIV_13
1234 * @arg @ref LL_RCC_PLLSAI1M_DIV_14
1235 * @arg @ref LL_RCC_PLLSAI1M_DIV_15
1236 * @arg @ref LL_RCC_PLLSAI1M_DIV_16
1237 * @param __PLLSAI1N__ Between 8 and 86
1238 * @param __PLLSAI1Q__ This parameter can be one of the following values:
1239 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
1240 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
1241 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
1242 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
1243 * @retval PLLSAI1 clock frequency (in Hz)
1244 */
1245 #define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1Q__) \
1246 ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
1247 ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))
1248
1249 /**
1250 * @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain
1251 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
1252 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());
1253 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1254 * @param __PLLSAI1M__ This parameter can be one of the following values:
1255 * @arg @ref LL_RCC_PLLSAI1M_DIV_1
1256 * @arg @ref LL_RCC_PLLSAI1M_DIV_2
1257 * @arg @ref LL_RCC_PLLSAI1M_DIV_3
1258 * @arg @ref LL_RCC_PLLSAI1M_DIV_4
1259 * @arg @ref LL_RCC_PLLSAI1M_DIV_5
1260 * @arg @ref LL_RCC_PLLSAI1M_DIV_6
1261 * @arg @ref LL_RCC_PLLSAI1M_DIV_7
1262 * @arg @ref LL_RCC_PLLSAI1M_DIV_8
1263 * @arg @ref LL_RCC_PLLSAI1M_DIV_9
1264 * @arg @ref LL_RCC_PLLSAI1M_DIV_10
1265 * @arg @ref LL_RCC_PLLSAI1M_DIV_11
1266 * @arg @ref LL_RCC_PLLSAI1M_DIV_12
1267 * @arg @ref LL_RCC_PLLSAI1M_DIV_13
1268 * @arg @ref LL_RCC_PLLSAI1M_DIV_14
1269 * @arg @ref LL_RCC_PLLSAI1M_DIV_15
1270 * @arg @ref LL_RCC_PLLSAI1M_DIV_16
1271 * @param __PLLSAI1N__ Between 8 and 86
1272 * @param __PLLSAI1R__ This parameter can be one of the following values:
1273 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
1274 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
1275 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
1276 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
1277 * @retval PLLSAI1 clock frequency (in Hz)
1278 */
1279 #define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1R__) \
1280 ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
1281 ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))
1282
1283 /**
1284 * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
1285 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),
1286 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
1287 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1288 * @param __PLLSAI2M__ This parameter can be one of the following values:
1289 * @arg @ref LL_RCC_PLLSAI2M_DIV_1
1290 * @arg @ref LL_RCC_PLLSAI2M_DIV_2
1291 * @arg @ref LL_RCC_PLLSAI2M_DIV_3
1292 * @arg @ref LL_RCC_PLLSAI2M_DIV_4
1293 * @arg @ref LL_RCC_PLLSAI2M_DIV_5
1294 * @arg @ref LL_RCC_PLLSAI2M_DIV_6
1295 * @arg @ref LL_RCC_PLLSAI2M_DIV_7
1296 * @arg @ref LL_RCC_PLLSAI2M_DIV_8
1297 * @arg @ref LL_RCC_PLLSAI2M_DIV_9
1298 * @arg @ref LL_RCC_PLLSAI2M_DIV_10
1299 * @arg @ref LL_RCC_PLLSAI2M_DIV_11
1300 * @arg @ref LL_RCC_PLLSAI2M_DIV_12
1301 * @arg @ref LL_RCC_PLLSAI2M_DIV_13
1302 * @arg @ref LL_RCC_PLLSAI2M_DIV_14
1303 * @arg @ref LL_RCC_PLLSAI2M_DIV_15
1304 * @arg @ref LL_RCC_PLLSAI2M_DIV_16
1305 * @param __PLLSAI2N__ Between 8 and 86
1306 * @param __PLLSAI2P__ This parameter can be one of the following values:
1307 * @arg @ref LL_RCC_PLLSAI2P_DIV_2
1308 * @arg @ref LL_RCC_PLLSAI2P_DIV_3
1309 * @arg @ref LL_RCC_PLLSAI2P_DIV_4
1310 * @arg @ref LL_RCC_PLLSAI2P_DIV_5
1311 * @arg @ref LL_RCC_PLLSAI2P_DIV_6
1312 * @arg @ref LL_RCC_PLLSAI2P_DIV_7
1313 * @arg @ref LL_RCC_PLLSAI2P_DIV_8
1314 * @arg @ref LL_RCC_PLLSAI2P_DIV_9
1315 * @arg @ref LL_RCC_PLLSAI2P_DIV_10
1316 * @arg @ref LL_RCC_PLLSAI2P_DIV_11
1317 * @arg @ref LL_RCC_PLLSAI2P_DIV_12
1318 * @arg @ref LL_RCC_PLLSAI2P_DIV_13
1319 * @arg @ref LL_RCC_PLLSAI2P_DIV_14
1320 * @arg @ref LL_RCC_PLLSAI2P_DIV_15
1321 * @arg @ref LL_RCC_PLLSAI2P_DIV_16
1322 * @arg @ref LL_RCC_PLLSAI2P_DIV_17
1323 * @arg @ref LL_RCC_PLLSAI2P_DIV_18
1324 * @arg @ref LL_RCC_PLLSAI2P_DIV_19
1325 * @arg @ref LL_RCC_PLLSAI2P_DIV_20
1326 * @arg @ref LL_RCC_PLLSAI2P_DIV_21
1327 * @arg @ref LL_RCC_PLLSAI2P_DIV_22
1328 * @arg @ref LL_RCC_PLLSAI2P_DIV_23
1329 * @arg @ref LL_RCC_PLLSAI2P_DIV_24
1330 * @arg @ref LL_RCC_PLLSAI2P_DIV_25
1331 * @arg @ref LL_RCC_PLLSAI2P_DIV_26
1332 * @arg @ref LL_RCC_PLLSAI2P_DIV_27
1333 * @arg @ref LL_RCC_PLLSAI2P_DIV_28
1334 * @arg @ref LL_RCC_PLLSAI2P_DIV_29
1335 * @arg @ref LL_RCC_PLLSAI2P_DIV_30
1336 * @arg @ref LL_RCC_PLLSAI2P_DIV_31
1337 * @retval PLLSAI2 clock frequency (in Hz)
1338 */
1339 #define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__) \
1340 ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
1341 ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
1342
1343 /**
1344 * @brief Helper macro to calculate the HCLK frequency
1345 * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
1346 * @param __AHBPRESCALER__ This parameter can be one of the following values:
1347 * @arg @ref LL_RCC_SYSCLK_DIV_1
1348 * @arg @ref LL_RCC_SYSCLK_DIV_2
1349 * @arg @ref LL_RCC_SYSCLK_DIV_4
1350 * @arg @ref LL_RCC_SYSCLK_DIV_8
1351 * @arg @ref LL_RCC_SYSCLK_DIV_16
1352 * @arg @ref LL_RCC_SYSCLK_DIV_64
1353 * @arg @ref LL_RCC_SYSCLK_DIV_128
1354 * @arg @ref LL_RCC_SYSCLK_DIV_256
1355 * @arg @ref LL_RCC_SYSCLK_DIV_512
1356 * @retval HCLK clock frequency (in Hz)
1357 */
1358 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) \
1359 ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
1360
1361 /**
1362 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
1363 * @param __HCLKFREQ__ HCLK frequency
1364 * @param __APB1PRESCALER__ This parameter can be one of the following values:
1365 * @arg @ref LL_RCC_APB1_DIV_1
1366 * @arg @ref LL_RCC_APB1_DIV_2
1367 * @arg @ref LL_RCC_APB1_DIV_4
1368 * @arg @ref LL_RCC_APB1_DIV_8
1369 * @arg @ref LL_RCC_APB1_DIV_16
1370 * @retval PCLK1 clock frequency (in Hz)
1371 */
1372 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
1373
1374 /**
1375 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
1376 * @param __HCLKFREQ__ HCLK frequency
1377 * @param __APB2PRESCALER__ This parameter can be one of the following values:
1378 * @arg @ref LL_RCC_APB2_DIV_1
1379 * @arg @ref LL_RCC_APB2_DIV_2
1380 * @arg @ref LL_RCC_APB2_DIV_4
1381 * @arg @ref LL_RCC_APB2_DIV_8
1382 * @arg @ref LL_RCC_APB2_DIV_16
1383 * @retval PCLK2 clock frequency (in Hz)
1384 */
1385 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
1386
1387 /**
1388 * @brief Helper macro to calculate the MSI frequency (in Hz)
1389 * @note __MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect()
1390 * @note if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY,
1391 * __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby()
1392 * else by LL_RCC_MSI_GetRange()
1393 * ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1394 * (LL_RCC_MSI_IsEnabledRangeSelect()?
1395 * LL_RCC_MSI_GetRange():
1396 * LL_RCC_MSI_GetRangeAfterStandby()))
1397 * @param __MSISEL__ This parameter can be one of the following values:
1398 * @arg @ref LL_RCC_MSIRANGESEL_STANDBY
1399 * @arg @ref LL_RCC_MSIRANGESEL_RUN
1400 * @param __MSIRANGE__ This parameter can be one of the following values:
1401 * @arg @ref LL_RCC_MSIRANGE_0
1402 * @arg @ref LL_RCC_MSIRANGE_1
1403 * @arg @ref LL_RCC_MSIRANGE_2
1404 * @arg @ref LL_RCC_MSIRANGE_3
1405 * @arg @ref LL_RCC_MSIRANGE_4
1406 * @arg @ref LL_RCC_MSIRANGE_5
1407 * @arg @ref LL_RCC_MSIRANGE_6
1408 * @arg @ref LL_RCC_MSIRANGE_7
1409 * @arg @ref LL_RCC_MSIRANGE_8
1410 * @arg @ref LL_RCC_MSIRANGE_9
1411 * @arg @ref LL_RCC_MSIRANGE_10
1412 * @arg @ref LL_RCC_MSIRANGE_11
1413 * @arg @ref LL_RCC_MSISRANGE_4
1414 * @arg @ref LL_RCC_MSISRANGE_5
1415 * @arg @ref LL_RCC_MSISRANGE_6
1416 * @arg @ref LL_RCC_MSISRANGE_7
1417 * @retval MSI clock frequency (in Hz)
1418 */
1419 #define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) \
1420 (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \
1421 MSIRangeTable[((__MSIRANGE__) >> RCC_CSR_MSISRANGE_Pos) & 0x0FU] : \
1422 MSIRangeTable[((__MSIRANGE__) >> RCC_CR_MSIRANGE_Pos) & 0x0FU])
1423
1424 /**
1425 * @}
1426 */
1427
1428 /**
1429 * @}
1430 */
1431
1432 /* Exported functions --------------------------------------------------------*/
1433 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
1434 * @{
1435 */
1436
1437 /** @defgroup RCC_LL_EF_HSE HSE
1438 * @{
1439 */
1440
1441 /**
1442 * @brief Enable the Clock Security System.
1443 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
1444 * @retval None
1445 */
LL_RCC_HSE_EnableCSS(void)1446 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
1447 {
1448 SET_BIT(RCC->CR, RCC_CR_CSSON);
1449 }
1450
1451 /**
1452 * @brief Enable HSE external oscillator (HSE Bypass)
1453 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
1454 * @retval None
1455 */
LL_RCC_HSE_EnableBypass(void)1456 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
1457 {
1458 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
1459 }
1460
1461 /**
1462 * @brief Disable HSE external oscillator (HSE Bypass)
1463 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
1464 * @retval None
1465 */
LL_RCC_HSE_DisableBypass(void)1466 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
1467 {
1468 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
1469 }
1470
1471 /**
1472 * @brief Enable HSE crystal oscillator (HSE ON)
1473 * @rmtoll CR HSEON LL_RCC_HSE_Enable
1474 * @retval None
1475 */
LL_RCC_HSE_Enable(void)1476 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
1477 {
1478 SET_BIT(RCC->CR, RCC_CR_HSEON);
1479 }
1480
1481 /**
1482 * @brief Disable HSE crystal oscillator (HSE ON)
1483 * @rmtoll CR HSEON LL_RCC_HSE_Disable
1484 * @retval None
1485 */
LL_RCC_HSE_Disable(void)1486 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
1487 {
1488 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
1489 }
1490
1491 /**
1492 * @brief Check if HSE oscillator Ready
1493 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
1494 * @retval State of bit (1 or 0).
1495 */
LL_RCC_HSE_IsReady(void)1496 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
1497 {
1498 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL);
1499 }
1500
1501 /**
1502 * @}
1503 */
1504
1505 /** @defgroup RCC_LL_EF_HSI HSI
1506 * @{
1507 */
1508
1509 /**
1510 * @brief Enable HSI even in stop mode
1511 * @note HSI oscillator is forced ON even in Stop mode
1512 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
1513 * @retval None
1514 */
LL_RCC_HSI_EnableInStopMode(void)1515 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
1516 {
1517 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
1518 }
1519
1520 /**
1521 * @brief Disable HSI in stop mode
1522 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
1523 * @retval None
1524 */
LL_RCC_HSI_DisableInStopMode(void)1525 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
1526 {
1527 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
1528 }
1529
1530 /**
1531 * @brief Check if HSI is enabled in stop mode
1532 * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
1533 * @retval State of bit (1 or 0).
1534 */
LL_RCC_HSI_IsEnabledInStopMode(void)1535 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
1536 {
1537 return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == RCC_CR_HSIKERON) ? 1UL : 0UL);
1538 }
1539
1540 /**
1541 * @brief Enable HSI oscillator
1542 * @rmtoll CR HSION LL_RCC_HSI_Enable
1543 * @retval None
1544 */
LL_RCC_HSI_Enable(void)1545 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
1546 {
1547 SET_BIT(RCC->CR, RCC_CR_HSION);
1548 }
1549
1550 /**
1551 * @brief Disable HSI oscillator
1552 * @rmtoll CR HSION LL_RCC_HSI_Disable
1553 * @retval None
1554 */
LL_RCC_HSI_Disable(void)1555 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
1556 {
1557 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
1558 }
1559
1560 /**
1561 * @brief Check if HSI clock is ready
1562 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
1563 * @retval State of bit (1 or 0).
1564 */
LL_RCC_HSI_IsReady(void)1565 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
1566 {
1567 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL);
1568 }
1569
1570 /**
1571 * @brief Enable HSI Automatic from stop mode
1572 * @rmtoll CR HSIASFS LL_RCC_HSI_EnableAutoFromStop
1573 * @retval None
1574 */
LL_RCC_HSI_EnableAutoFromStop(void)1575 __STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void)
1576 {
1577 SET_BIT(RCC->CR, RCC_CR_HSIASFS);
1578 }
1579
1580 /**
1581 * @brief Disable HSI Automatic from stop mode
1582 * @rmtoll CR HSIASFS LL_RCC_HSI_DisableAutoFromStop
1583 * @retval None
1584 */
LL_RCC_HSI_DisableAutoFromStop(void)1585 __STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void)
1586 {
1587 CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS);
1588 }
1589 /**
1590 * @brief Get HSI Calibration value
1591 * @note When HSITRIM is written, HSICAL is updated with the sum of
1592 * HSITRIM and the factory trim value
1593 * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
1594 * @retval Between Min_Data = 0 and Max_Data = 127
1595 */
LL_RCC_HSI_GetCalibration(void)1596 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
1597 {
1598 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
1599 }
1600
1601 /**
1602 * @brief Set HSI Calibration trimming
1603 * @note user-programmable trimming value that is added to the HSICAL
1604 * @note Default value is 64, which, when added to the HSICAL value,
1605 * should trim the HSI to 16 MHz +/- 1 %
1606 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
1607 * @param Value Between Min_Data = 0 and Max_Data = 127
1608 * @retval None
1609 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)1610 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1611 {
1612 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
1613 }
1614
1615 /**
1616 * @brief Get HSI Calibration trimming
1617 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
1618 * @retval Between Min_Data = 0 and Max_Data = 127
1619 */
LL_RCC_HSI_GetCalibTrimming(void)1620 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1621 {
1622 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
1623 }
1624
1625 /**
1626 * @}
1627 */
1628
1629 /** @defgroup RCC_LL_EF_HSI48 HSI48
1630 * @{
1631 */
1632
1633 /**
1634 * @brief Enable HSI48
1635 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable
1636 * @retval None
1637 */
LL_RCC_HSI48_Enable(void)1638 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
1639 {
1640 SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
1641 }
1642
1643 /**
1644 * @brief Disable HSI48
1645 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable
1646 * @retval None
1647 */
LL_RCC_HSI48_Disable(void)1648 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
1649 {
1650 CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
1651 }
1652
1653 /**
1654 * @brief Check if HSI48 oscillator Ready
1655 * @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady
1656 * @retval State of bit (1 or 0).
1657 */
LL_RCC_HSI48_IsReady(void)1658 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
1659 {
1660 return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == RCC_CRRCR_HSI48RDY) ? 1UL : 0UL);
1661 }
1662
1663 /**
1664 * @brief Get HSI48 Calibration value
1665 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
1666 * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
1667 */
LL_RCC_HSI48_GetCalibration(void)1668 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
1669 {
1670 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
1671 }
1672
1673 /**
1674 * @}
1675 */
1676
1677 /** @defgroup RCC_LL_EF_LSE LSE
1678 * @{
1679 */
1680
1681 /**
1682 * @brief Enable Low Speed External (LSE) crystal.
1683 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
1684 * @retval None
1685 */
LL_RCC_LSE_Enable(void)1686 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
1687 {
1688 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1689 }
1690
1691 /**
1692 * @brief Disable Low Speed External (LSE) crystal.
1693 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
1694 * @retval None
1695 */
LL_RCC_LSE_Disable(void)1696 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
1697 {
1698 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1699 }
1700
1701 /**
1702 * @brief Enable external clock source (LSE bypass).
1703 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
1704 * @retval None
1705 */
LL_RCC_LSE_EnableBypass(void)1706 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
1707 {
1708 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1709 }
1710
1711 /**
1712 * @brief Disable external clock source (LSE bypass).
1713 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
1714 * @retval None
1715 */
LL_RCC_LSE_DisableBypass(void)1716 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
1717 {
1718 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1719 }
1720
1721 /**
1722 * @brief Set LSE oscillator drive capability
1723 * @note The oscillator is in Xtal mode when it is not in bypass mode.
1724 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
1725 * @param LSEDrive This parameter can be one of the following values:
1726 * @arg @ref LL_RCC_LSEDRIVE_LOW
1727 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1728 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1729 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1730 * @retval None
1731 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)1732 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
1733 {
1734 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
1735 }
1736
1737 /**
1738 * @brief Get LSE oscillator drive capability
1739 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
1740 * @retval Returned value can be one of the following values:
1741 * @arg @ref LL_RCC_LSEDRIVE_LOW
1742 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1743 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1744 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1745 */
LL_RCC_LSE_GetDriveCapability(void)1746 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
1747 {
1748 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
1749 }
1750
1751 /**
1752 * @brief Enable Clock security system on LSE.
1753 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
1754 * @retval None
1755 */
LL_RCC_LSE_EnableCSS(void)1756 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
1757 {
1758 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1759 }
1760
1761 /**
1762 * @brief Disable Clock security system on LSE.
1763 * @note Clock security system can be disabled only after a LSE
1764 * failure detection. In that case it MUST be disabled by software.
1765 * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
1766 * @retval None
1767 */
LL_RCC_LSE_DisableCSS(void)1768 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
1769 {
1770 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1771 }
1772
1773 /**
1774 * @brief Check if LSE oscillator Ready
1775 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
1776 * @retval State of bit (1 or 0).
1777 */
LL_RCC_LSE_IsReady(void)1778 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
1779 {
1780 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL);
1781 }
1782
1783 /**
1784 * @brief Enable LSE oscillator propagation for system clock
1785 * @rmtoll BDCR LSESYSEN LL_RCC_LSE_EnablePropagation
1786 * @retval None
1787 */
LL_RCC_LSE_EnablePropagation(void)1788 __STATIC_INLINE void LL_RCC_LSE_EnablePropagation(void)
1789 {
1790 SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
1791 }
1792
1793 /**
1794 * @brief Disable LSE oscillator propagation for system clock
1795 * @rmtoll BDCR LSESYSEN LL_RCC_LSE_DisablePropagation
1796 * @retval None
1797 */
LL_RCC_LSE_DisablePropagation(void)1798 __STATIC_INLINE void LL_RCC_LSE_DisablePropagation(void)
1799 {
1800 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
1801 }
1802
1803 /**
1804 * @brief Check if LSE oscillator propagation for system clock Ready
1805 * @rmtoll BDCR LSESYSRDY LL_RCC_LSE_IsPropagationReady
1806 * @retval State of bit (1 or 0).
1807 */
LL_RCC_LSE_IsPropagationReady(void)1808 __STATIC_INLINE uint32_t LL_RCC_LSE_IsPropagationReady(void)
1809 {
1810 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == RCC_BDCR_LSESYSRDY) ? 1UL : 0UL);
1811 }
1812
1813 /**
1814 * @brief Check if CSS on LSE failure Detection
1815 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
1816 * @retval State of bit (1 or 0).
1817 */
LL_RCC_LSE_IsCSSDetected(void)1818 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
1819 {
1820 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == RCC_BDCR_LSECSSD) ? 1UL : 0UL);
1821 }
1822
1823 /**
1824 * @}
1825 */
1826
1827 /** @defgroup RCC_LL_EF_LSI LSI
1828 * @{
1829 */
1830
1831 /**
1832 * @brief Enable LSI Oscillator
1833 * @rmtoll CSR LSION LL_RCC_LSI_Enable
1834 * @retval None
1835 */
LL_RCC_LSI_Enable(void)1836 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
1837 {
1838 SET_BIT(RCC->CSR, RCC_CSR_LSION);
1839 }
1840
1841 /**
1842 * @brief Disable LSI Oscillator
1843 * @rmtoll CSR LSION LL_RCC_LSI_Disable
1844 * @retval None
1845 */
LL_RCC_LSI_Disable(void)1846 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
1847 {
1848 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
1849 }
1850
1851 /**
1852 * @brief Check if LSI is Ready
1853 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
1854 * @retval State of bit (1 or 0).
1855 */
LL_RCC_LSI_IsReady(void)1856 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
1857 {
1858 return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) ? 1UL : 0UL);
1859 }
1860
1861 /**
1862 * @brief Set LSI prescaler
1863 * @rmtoll CSR LSIPRE LL_RCC_LSI_SetPrescaler
1864 * @param LSIPrescaler This parameter can be one of the following values:
1865 * @arg @ref LL_RCC_LSI_DIV_1
1866 * @arg @ref LL_RCC_LSI_DIV_128
1867 * @retval None
1868 */
LL_RCC_LSI_SetPrescaler(uint32_t LSIPrescaler)1869 __STATIC_INLINE void LL_RCC_LSI_SetPrescaler(uint32_t LSIPrescaler)
1870 {
1871 MODIFY_REG(RCC->CSR, RCC_CSR_LSIPRE, LSIPrescaler);
1872 }
1873
1874 /**
1875 * @brief Get LSI prescaler
1876 * @rmtoll CSR LSIPRE LL_RCC_LSI_GetPrescaler
1877 * @retval Returned value can be one of the following values:
1878 * @arg @ref LL_RCC_LSI_DIV_1
1879 * @arg @ref LL_RCC_LSI_DIV_128
1880 */
LL_RCC_LSI_GetPrescaler(void)1881 __STATIC_INLINE uint32_t LL_RCC_LSI_GetPrescaler(void)
1882 {
1883 return (READ_BIT(RCC->CSR, RCC_CSR_LSIPRE));
1884 }
1885
1886 /**
1887 * @}
1888 */
1889
1890 /** @defgroup RCC_LL_EF_MSI MSI
1891 * @{
1892 */
1893
1894 /**
1895 * @brief Enable MSI oscillator
1896 * @rmtoll CR MSION LL_RCC_MSI_Enable
1897 * @retval None
1898 */
LL_RCC_MSI_Enable(void)1899 __STATIC_INLINE void LL_RCC_MSI_Enable(void)
1900 {
1901 SET_BIT(RCC->CR, RCC_CR_MSION);
1902 }
1903
1904 /**
1905 * @brief Disable MSI oscillator
1906 * @rmtoll CR MSION LL_RCC_MSI_Disable
1907 * @retval None
1908 */
LL_RCC_MSI_Disable(void)1909 __STATIC_INLINE void LL_RCC_MSI_Disable(void)
1910 {
1911 CLEAR_BIT(RCC->CR, RCC_CR_MSION);
1912 }
1913
1914 /**
1915 * @brief Check if MSI oscillator Ready
1916 * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
1917 * @retval State of bit (1 or 0).
1918 */
LL_RCC_MSI_IsReady(void)1919 __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
1920 {
1921 return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL);
1922 }
1923
1924 /**
1925 * @brief Enable MSI PLL-mode (Hardware auto calibration with LSE)
1926 * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled)
1927 * and ready (LSERDY set by hardware)
1928 * @note hardware protection to avoid enabling MSIPLLEN if LSE is not
1929 * ready
1930 * @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
1931 * @retval None
1932 */
LL_RCC_MSI_EnablePLLMode(void)1933 __STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
1934 {
1935 SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
1936 }
1937
1938 /**
1939 * @brief Disable MSI-PLL mode
1940 * @note cleared by hardware when LSE is disabled (LSEON = 0) or when
1941 * the Clock Security System on LSE detects a LSE failure
1942 * @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode
1943 * @retval None
1944 */
LL_RCC_MSI_DisablePLLMode(void)1945 __STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
1946 {
1947 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
1948 }
1949
1950 /**
1951 * @brief Enable MSI clock range selection with MSIRANGE register
1952 * @note Write 0 has no effect. After a standby or a reset
1953 * MSIRGSEL is at 0 and the MSI range value is provided by
1954 * MSISRANGE
1955 * @rmtoll CR MSIRGSEL LL_RCC_MSI_EnableRangeSelection
1956 * @retval None
1957 */
LL_RCC_MSI_EnableRangeSelection(void)1958 __STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
1959 {
1960 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);
1961 }
1962
1963 /**
1964 * @brief Check if MSI clock range is selected with MSIRANGE register
1965 * @rmtoll CR MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect
1966 * @retval State of bit (1 or 0).
1967 */
LL_RCC_MSI_IsEnabledRangeSelect(void)1968 __STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void)
1969 {
1970 return ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RCC_CR_MSIRGSEL) ? 1UL : 0UL);
1971 }
1972
1973 /**
1974 * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
1975 * @rmtoll CR MSIRANGE LL_RCC_MSI_SetRange
1976 * @param Range This parameter can be one of the following values:
1977 * @arg @ref LL_RCC_MSIRANGE_0
1978 * @arg @ref LL_RCC_MSIRANGE_1
1979 * @arg @ref LL_RCC_MSIRANGE_2
1980 * @arg @ref LL_RCC_MSIRANGE_3
1981 * @arg @ref LL_RCC_MSIRANGE_4
1982 * @arg @ref LL_RCC_MSIRANGE_5
1983 * @arg @ref LL_RCC_MSIRANGE_6
1984 * @arg @ref LL_RCC_MSIRANGE_7
1985 * @arg @ref LL_RCC_MSIRANGE_8
1986 * @arg @ref LL_RCC_MSIRANGE_9
1987 * @arg @ref LL_RCC_MSIRANGE_10
1988 * @arg @ref LL_RCC_MSIRANGE_11
1989 * @retval None
1990 */
LL_RCC_MSI_SetRange(uint32_t Range)1991 __STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
1992 {
1993 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
1994 }
1995
1996 /**
1997 * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
1998 * @rmtoll CR MSIRANGE LL_RCC_MSI_GetRange
1999 * @retval Returned value can be one of the following values:
2000 * @arg @ref LL_RCC_MSIRANGE_0
2001 * @arg @ref LL_RCC_MSIRANGE_1
2002 * @arg @ref LL_RCC_MSIRANGE_2
2003 * @arg @ref LL_RCC_MSIRANGE_3
2004 * @arg @ref LL_RCC_MSIRANGE_4
2005 * @arg @ref LL_RCC_MSIRANGE_5
2006 * @arg @ref LL_RCC_MSIRANGE_6
2007 * @arg @ref LL_RCC_MSIRANGE_7
2008 * @arg @ref LL_RCC_MSIRANGE_8
2009 * @arg @ref LL_RCC_MSIRANGE_9
2010 * @arg @ref LL_RCC_MSIRANGE_10
2011 * @arg @ref LL_RCC_MSIRANGE_11
2012 */
LL_RCC_MSI_GetRange(void)2013 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
2014 {
2015 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE));
2016 }
2017
2018 /**
2019 * @brief Configure MSI range used after standby
2020 * @rmtoll CSR MSISRANGE LL_RCC_MSI_SetRangeAfterStandby
2021 * @param Range This parameter can be one of the following values:
2022 * @arg @ref LL_RCC_MSISRANGE_4
2023 * @arg @ref LL_RCC_MSISRANGE_5
2024 * @arg @ref LL_RCC_MSISRANGE_6
2025 * @arg @ref LL_RCC_MSISRANGE_7
2026 * @retval None
2027 */
LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)2028 __STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)
2029 {
2030 MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, Range);
2031 }
2032
2033 /**
2034 * @brief Get MSI range used after standby
2035 * @rmtoll CSR MSISRANGE LL_RCC_MSI_GetRangeAfterStandby
2036 * @retval Returned value can be one of the following values:
2037 * @arg @ref LL_RCC_MSISRANGE_4
2038 * @arg @ref LL_RCC_MSISRANGE_5
2039 * @arg @ref LL_RCC_MSISRANGE_6
2040 * @arg @ref LL_RCC_MSISRANGE_7
2041 */
LL_RCC_MSI_GetRangeAfterStandby(void)2042 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void)
2043 {
2044 return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE));
2045 }
2046
2047 /**
2048 * @brief Get MSI Calibration value
2049 * @note When MSITRIM is written, MSICAL is updated with the sum of
2050 * MSITRIM and the factory trim value
2051 * @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration
2052 * @retval Between Min_Data = 0 and Max_Data = 255
2053 */
LL_RCC_MSI_GetCalibration(void)2054 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
2055 {
2056 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos);
2057 }
2058
2059 /**
2060 * @brief Set MSI Calibration trimming
2061 * @note user-programmable trimming value that is added to the MSICAL
2062 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
2063 * @param Value Between Min_Data = 0 and Max_Data = 255
2064 * @retval None
2065 */
LL_RCC_MSI_SetCalibTrimming(uint32_t Value)2066 __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
2067 {
2068 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
2069 }
2070
2071 /**
2072 * @brief Get MSI Calibration trimming
2073 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming
2074 * @retval Between 0 and 255
2075 */
LL_RCC_MSI_GetCalibTrimming(void)2076 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
2077 {
2078 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
2079 }
2080
2081 /**
2082 * @}
2083 */
2084
2085 /** @defgroup RCC_LL_EF_LSCO LSCO
2086 * @{
2087 */
2088
2089 /**
2090 * @brief Enable Low speed clock
2091 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
2092 * @retval None
2093 */
LL_RCC_LSCO_Enable(void)2094 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
2095 {
2096 SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
2097 }
2098
2099 /**
2100 * @brief Disable Low speed clock
2101 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
2102 * @retval None
2103 */
LL_RCC_LSCO_Disable(void)2104 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
2105 {
2106 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
2107 }
2108
2109 /**
2110 * @brief Configure Low speed clock selection
2111 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
2112 * @param Source This parameter can be one of the following values:
2113 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
2114 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
2115 * @retval None
2116 */
LL_RCC_LSCO_SetSource(uint32_t Source)2117 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
2118 {
2119 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
2120 }
2121
2122 /**
2123 * @brief Get Low speed clock selection
2124 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
2125 * @retval Returned value can be one of the following values:
2126 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
2127 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
2128 */
LL_RCC_LSCO_GetSource(void)2129 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
2130 {
2131 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
2132 }
2133
2134 /**
2135 * @}
2136 */
2137
2138 /** @defgroup RCC_LL_EF_System System
2139 * @{
2140 */
2141
2142 /**
2143 * @brief Configure the system clock source
2144 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
2145 * @param Source This parameter can be one of the following values:
2146 * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
2147 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
2148 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
2149 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
2150 * @retval None
2151 */
LL_RCC_SetSysClkSource(uint32_t Source)2152 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
2153 {
2154 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
2155 }
2156
2157 /**
2158 * @brief Get the system clock source
2159 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
2160 * @retval Returned value can be one of the following values:
2161 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
2162 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
2163 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
2164 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
2165 */
LL_RCC_GetSysClkSource(void)2166 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
2167 {
2168 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
2169 }
2170
2171 /**
2172 * @brief Set AHB prescaler
2173 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
2174 * @param Prescaler This parameter can be one of the following values:
2175 * @arg @ref LL_RCC_SYSCLK_DIV_1
2176 * @arg @ref LL_RCC_SYSCLK_DIV_2
2177 * @arg @ref LL_RCC_SYSCLK_DIV_4
2178 * @arg @ref LL_RCC_SYSCLK_DIV_8
2179 * @arg @ref LL_RCC_SYSCLK_DIV_16
2180 * @arg @ref LL_RCC_SYSCLK_DIV_64
2181 * @arg @ref LL_RCC_SYSCLK_DIV_128
2182 * @arg @ref LL_RCC_SYSCLK_DIV_256
2183 * @arg @ref LL_RCC_SYSCLK_DIV_512
2184 * @retval None
2185 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)2186 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
2187 {
2188 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
2189 }
2190
2191 /**
2192 * @brief Set APB1 prescaler
2193 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
2194 * @param Prescaler This parameter can be one of the following values:
2195 * @arg @ref LL_RCC_APB1_DIV_1
2196 * @arg @ref LL_RCC_APB1_DIV_2
2197 * @arg @ref LL_RCC_APB1_DIV_4
2198 * @arg @ref LL_RCC_APB1_DIV_8
2199 * @arg @ref LL_RCC_APB1_DIV_16
2200 * @retval None
2201 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)2202 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
2203 {
2204 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
2205 }
2206
2207 /**
2208 * @brief Set APB2 prescaler
2209 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
2210 * @param Prescaler This parameter can be one of the following values:
2211 * @arg @ref LL_RCC_APB2_DIV_1
2212 * @arg @ref LL_RCC_APB2_DIV_2
2213 * @arg @ref LL_RCC_APB2_DIV_4
2214 * @arg @ref LL_RCC_APB2_DIV_8
2215 * @arg @ref LL_RCC_APB2_DIV_16
2216 * @retval None
2217 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)2218 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
2219 {
2220 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
2221 }
2222
2223 /**
2224 * @brief Get AHB prescaler
2225 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
2226 * @retval Returned value can be one of the following values:
2227 * @arg @ref LL_RCC_SYSCLK_DIV_1
2228 * @arg @ref LL_RCC_SYSCLK_DIV_2
2229 * @arg @ref LL_RCC_SYSCLK_DIV_4
2230 * @arg @ref LL_RCC_SYSCLK_DIV_8
2231 * @arg @ref LL_RCC_SYSCLK_DIV_16
2232 * @arg @ref LL_RCC_SYSCLK_DIV_64
2233 * @arg @ref LL_RCC_SYSCLK_DIV_128
2234 * @arg @ref LL_RCC_SYSCLK_DIV_256
2235 * @arg @ref LL_RCC_SYSCLK_DIV_512
2236 */
LL_RCC_GetAHBPrescaler(void)2237 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
2238 {
2239 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
2240 }
2241
2242 /**
2243 * @brief Get APB1 prescaler
2244 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
2245 * @retval Returned value can be one of the following values:
2246 * @arg @ref LL_RCC_APB1_DIV_1
2247 * @arg @ref LL_RCC_APB1_DIV_2
2248 * @arg @ref LL_RCC_APB1_DIV_4
2249 * @arg @ref LL_RCC_APB1_DIV_8
2250 * @arg @ref LL_RCC_APB1_DIV_16
2251 */
LL_RCC_GetAPB1Prescaler(void)2252 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
2253 {
2254 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
2255 }
2256
2257 /**
2258 * @brief Get APB2 prescaler
2259 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
2260 * @retval Returned value can be one of the following values:
2261 * @arg @ref LL_RCC_APB2_DIV_1
2262 * @arg @ref LL_RCC_APB2_DIV_2
2263 * @arg @ref LL_RCC_APB2_DIV_4
2264 * @arg @ref LL_RCC_APB2_DIV_8
2265 * @arg @ref LL_RCC_APB2_DIV_16
2266 */
LL_RCC_GetAPB2Prescaler(void)2267 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
2268 {
2269 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
2270 }
2271
2272 /**
2273 * @brief Set Clock After Wake-Up From Stop mode
2274 * @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop
2275 * @param Clock This parameter can be one of the following values:
2276 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
2277 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
2278 * @retval None
2279 */
LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)2280 __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
2281 {
2282 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
2283 }
2284
2285 /**
2286 * @brief Get Clock After Wake-Up From Stop mode
2287 * @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop
2288 * @retval Returned value can be one of the following values:
2289 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
2290 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
2291 */
LL_RCC_GetClkAfterWakeFromStop(void)2292 __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
2293 {
2294 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
2295 }
2296
2297 /**
2298 * @}
2299 */
2300
2301 /** @defgroup RCC_LL_EF_MCO MCO
2302 * @{
2303 */
2304
2305 /**
2306 * @brief Configure MCOx
2307 * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
2308 * CFGR MCOPRE LL_RCC_ConfigMCO
2309 * @param MCOxSource This parameter can be one of the following values:
2310 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
2311 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
2312 * @arg @ref LL_RCC_MCO1SOURCE_MSI
2313 * @arg @ref LL_RCC_MCO1SOURCE_HSI
2314 * @arg @ref LL_RCC_MCO1SOURCE_HSE
2315 * @arg @ref LL_RCC_MCO1SOURCE_HSI48
2316 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
2317 * @arg @ref LL_RCC_MCO1SOURCE_LSI
2318 * @arg @ref LL_RCC_MCO1SOURCE_LSE
2319 * @param MCOxPrescaler This parameter can be one of the following values:
2320 * @arg @ref LL_RCC_MCO1_DIV_1
2321 * @arg @ref LL_RCC_MCO1_DIV_2
2322 * @arg @ref LL_RCC_MCO1_DIV_4
2323 * @arg @ref LL_RCC_MCO1_DIV_8
2324 * @arg @ref LL_RCC_MCO1_DIV_16
2325 * @retval None
2326 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)2327 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
2328 {
2329 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
2330 }
2331
2332 /**
2333 * @}
2334 */
2335
2336 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
2337 * @{
2338 */
2339
2340 /**
2341 * @brief Configure USARTx clock source
2342 * @rmtoll CCIPR1 USART1SEL LL_RCC_SetUSARTClockSource\n
2343 * CCIPR1 USART2SEL LL_RCC_SetUSARTClockSource\n
2344 * CCIPR1 USART3SEL LL_RCC_SetUSARTClockSource
2345 * @param USARTxSource This parameter can be one of the following values:
2346 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2347 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
2348 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2349 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2350 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
2351 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
2352 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
2353 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
2354 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
2355 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
2356 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
2357 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
2358 * @retval None
2359 */
LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)2360 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
2361 {
2362 MODIFY_REG(RCC->CCIPR1, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
2363 }
2364
2365 /**
2366 * @brief Configure UARTx clock source
2367 * @rmtoll CCIPR1 UART4SEL LL_RCC_SetUARTClockSource\n
2368 * CCIPR1 UART5SEL LL_RCC_SetUARTClockSource
2369 * @param UARTxSource This parameter can be one of the following values:
2370 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
2371 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
2372 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
2373 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
2374 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
2375 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
2376 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
2377 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
2378 * @retval None
2379 */
LL_RCC_SetUARTClockSource(uint32_t UARTxSource)2380 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
2381 {
2382 MODIFY_REG(RCC->CCIPR1, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU));
2383 }
2384
2385 /**
2386 * @brief Configure LPUARTx clock source
2387 * @rmtoll CCIPR1 LPUART1SEL LL_RCC_SetLPUARTClockSource
2388 * @param LPUARTxSource This parameter can be one of the following values:
2389 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
2390 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
2391 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
2392 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
2393 * @retval None
2394 */
LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)2395 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
2396 {
2397 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPUART1SEL, LPUARTxSource);
2398 }
2399
2400 /**
2401 * @brief Configure I2Cx clock source
2402 * @rmtoll CCIPR1 I2C1SEL LL_RCC_SetI2CClockSource\n
2403 * CCIPR1 I2C2SEL LL_RCC_SetI2CClockSource\n
2404 * CCIPR1 I2C3SEL LL_RCC_SetI2CClockSource\n
2405 * CCIPR2 I2C4SEL LL_RCC_SetI2CClockSource
2406 * @param I2CxSource This parameter can be one of the following values:
2407 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2408 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
2409 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2410 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
2411 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
2412 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
2413 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
2414 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
2415 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
2416 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1
2417 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK
2418 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
2419 * @retval None
2420 */
LL_RCC_SetI2CClockSource(uint32_t I2CxSource)2421 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
2422 {
2423 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U));
2424 MODIFY_REG(*reg, 3U << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((I2CxSource & 0x000000FFU) << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU)));
2425 }
2426
2427 /**
2428 * @brief Configure LPTIMx clock source
2429 * @rmtoll CCIPR1 LPTIM1SEL LL_RCC_SetLPTIMClockSource\n
2430 * CCIPR1 LPTIM2SEL LL_RCC_SetLPTIMClockSource\n
2431 * CCIPR1 LPTIM3SEL LL_RCC_SetLPTIMClockSource
2432 * @param LPTIMxSource This parameter can be one of the following values:
2433 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2434 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2435 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2436 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2437 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
2438 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2439 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
2440 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2441 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK1
2442 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI
2443 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_HSI
2444 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE
2445 * @retval None
2446 */
LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)2447 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
2448 {
2449 MODIFY_REG(RCC->CCIPR1, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U));
2450 }
2451
2452 /**
2453 * @brief Configure FDCAN kernel clock source
2454 * @rmtoll CCIPR1 FDCANSEL LL_RCC_SetFDCANClockSource
2455 * @param FDCANxSource This parameter can be one of the following values:
2456 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
2457 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL
2458 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLLSAI1
2459 * @retval None
2460 */
LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)2461 __STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)
2462 {
2463 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL, FDCANxSource);
2464 }
2465
2466 /**
2467 * @brief Configure SAIx clock source
2468 * @rmtoll CCIPR2 SAI1SEL LL_RCC_SetSAIClockSource\n
2469 * CCIPR2 SAI2SEL LL_RCC_SetSAIClockSource
2470 * @param SAIxSource This parameter can be one of the following values:
2471 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
2472 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2
2473 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
2474 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
2475 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1
2476 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2
2477 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL
2478 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
2479 * @retval None
2480 */
LL_RCC_SetSAIClockSource(uint32_t SAIxSource)2481 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
2482 {
2483 MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU));
2484 }
2485
2486 /**
2487 * @brief Configure SDMMC1 kernel clock source
2488 * @rmtoll CCIPR2 SDMMCSEL LL_RCC_SetSDMMCKernelClockSource
2489 * @param SDMMCxSource This parameter can be one of the following values:
2490 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK
2491 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP
2492 * @retval None
2493 */
LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource)2494 __STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource)
2495 {
2496 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, SDMMCxSource);
2497 }
2498
2499 /**
2500 * @brief Configure SDMMC1 clock source
2501 * @rmtoll CCIPR1 CLK48MSEL LL_RCC_SetSDMMCClockSource
2502 * @param SDMMCxSource This parameter can be one of the following values:
2503 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48
2504 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1
2505 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
2506 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI
2507 * @retval None
2508 */
LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)2509 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
2510 {
2511 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, SDMMCxSource);
2512 }
2513
2514 /**
2515 * @brief Configure RNG clock source
2516 * @rmtoll CCIPR1 CLK48MSEL LL_RCC_SetRNGClockSource
2517 * @param RNGxSource This parameter can be one of the following values:
2518 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
2519 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1
2520 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
2521 * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
2522 * @retval None
2523 */
LL_RCC_SetRNGClockSource(uint32_t RNGxSource)2524 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
2525 {
2526 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, RNGxSource);
2527 }
2528
2529 /**
2530 * @brief Configure USB clock source
2531 * @rmtoll CCIPR1 CLK48MSEL LL_RCC_SetUSBClockSource
2532 * @param USBxSource This parameter can be one of the following values:
2533 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
2534 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
2535 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
2536 * @arg @ref LL_RCC_USB_CLKSOURCE_MSI
2537 * @retval None
2538 */
LL_RCC_SetUSBClockSource(uint32_t USBxSource)2539 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
2540 {
2541 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, USBxSource);
2542 }
2543
2544 /**
2545 * @brief Configure ADC clock source
2546 * @rmtoll CCIPR1 ADCSEL LL_RCC_SetADCClockSource
2547 * @param ADCxSource This parameter can be one of the following values:
2548 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
2549 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
2550 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
2551 * @retval None
2552 */
LL_RCC_SetADCClockSource(uint32_t ADCxSource)2553 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
2554 {
2555 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADCSEL, ADCxSource);
2556 }
2557
2558 /**
2559 * @brief Configure DFSDM Audio clock source
2560 * @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource
2561 * @param Source This parameter can be one of the following values:
2562 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
2563 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI
2564 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI
2565 * @retval None
2566 */
LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)2567 __STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
2568 {
2569 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDMSEL, Source);
2570 }
2571
2572 /**
2573 * @brief Configure DFSDM Kernel clock source
2574 * @rmtoll CCIPR2 DFSDM1SEL LL_RCC_SetDFSDMClockSource
2575 * @param DFSDMxSource This parameter can be one of the following values:
2576 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
2577 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
2578 * @retval None
2579 */
LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource)2580 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource)
2581 {
2582 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDMSEL, DFSDMxSource);
2583 }
2584
2585 /**
2586 * @brief Configure OCTOSPI kernel clock source
2587 * @rmtoll CCIPR2 OSPISEL LL_RCC_SetOCTOSPIClockSource
2588 * @param Source This parameter can be one of the following values:
2589 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK
2590 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI
2591 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL
2592 * @retval None
2593 */
LL_RCC_SetOCTOSPIClockSource(uint32_t Source)2594 __STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t Source)
2595 {
2596 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, Source);
2597 }
2598
2599 /**
2600 * @brief Get USARTx clock source
2601 * @rmtoll CCIPR1 USART1SEL LL_RCC_GetUSARTClockSource\n
2602 * CCIPR1 USART2SEL LL_RCC_GetUSARTClockSource\n
2603 * CCIPR1 USART3SEL LL_RCC_GetUSARTClockSource
2604 * @param USARTx This parameter can be one of the following values:
2605 * @arg @ref LL_RCC_USART1_CLKSOURCE
2606 * @arg @ref LL_RCC_USART2_CLKSOURCE
2607 * @arg @ref LL_RCC_USART3_CLKSOURCE
2608 * @retval Returned value can be one of the following values:
2609 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2610 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
2611 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2612 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2613 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
2614 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
2615 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
2616 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
2617 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
2618 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
2619 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
2620 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
2621 */
LL_RCC_GetUSARTClockSource(uint32_t USARTx)2622 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
2623 {
2624 return (uint32_t)(READ_BIT(RCC->CCIPR1, USARTx) | (USARTx << 16U));
2625 }
2626
2627 /**
2628 * @brief Get UARTx clock source
2629 * @rmtoll CCIPR1 UART4SEL LL_RCC_GetUARTClockSource\n
2630 * CCIPR1 UART5SEL LL_RCC_GetUARTClockSource
2631 * @param UARTx This parameter can be one of the following values:
2632 * @arg @ref LL_RCC_UART4_CLKSOURCE
2633 * @arg @ref LL_RCC_UART5_CLKSOURCE
2634 * @retval Returned value can be one of the following values:
2635 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
2636 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
2637 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
2638 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
2639 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
2640 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
2641 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
2642 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
2643 */
LL_RCC_GetUARTClockSource(uint32_t UARTx)2644 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
2645 {
2646 return (uint32_t)(READ_BIT(RCC->CCIPR1, UARTx) | (UARTx << 16U));
2647 }
2648
2649 /**
2650 * @brief Get LPUARTx clock source
2651 * @rmtoll CCIPR1 LPUART1SEL LL_RCC_GetLPUARTClockSource
2652 * @param LPUARTx This parameter can be one of the following values:
2653 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
2654 * @retval Returned value can be one of the following values:
2655 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
2656 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
2657 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
2658 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
2659 */
LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)2660 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
2661 {
2662 return (uint32_t)(READ_BIT(RCC->CCIPR1, LPUARTx));
2663 }
2664
2665 /**
2666 * @brief Get I2Cx clock source
2667 * @rmtoll CCIPR1 I2C1SEL LL_RCC_GetI2CClockSource\n
2668 * CCIPR1 I2C2SEL LL_RCC_GetI2CClockSource\n
2669 * CCIPR1 I2C3SEL LL_RCC_GetI2CClockSource\n
2670 * CCIPR2 I2C4SEL LL_RCC_GetI2CClockSource
2671 * @param I2Cx This parameter can be one of the following values:
2672 * @arg @ref LL_RCC_I2C1_CLKSOURCE
2673 * @arg @ref LL_RCC_I2C2_CLKSOURCE
2674 * @arg @ref LL_RCC_I2C3_CLKSOURCE
2675 * @arg @ref LL_RCC_I2C4_CLKSOURCE
2676 * @retval Returned value can be one of the following values:
2677 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2678 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
2679 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2680 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
2681 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
2682 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
2683 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
2684 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
2685 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
2686 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1
2687 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK
2688 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
2689 */
LL_RCC_GetI2CClockSource(uint32_t I2Cx)2690 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
2691 {
2692 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U));
2693 return (uint32_t)((READ_BIT(*reg, (3UL << (((I2Cx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> (((I2Cx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (I2Cx & 0xFFFF0000UL));
2694 }
2695
2696 /**
2697 * @brief Get LPTIMx clock source
2698 * @rmtoll CCIPR1 LPTIM1SEL LL_RCC_GetLPTIMClockSource\n
2699 * CCIPR1 LPTIM2SEL LL_RCC_GetLPTIMClockSource\n
2700 * CCIPR1 LPTIM3SEL LL_RCC_GetLPTIMClockSource
2701 * @param LPTIMx This parameter can be one of the following values:
2702 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
2703 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
2704 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE
2705 * @retval Returned value can be one of the following values:
2706 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2707 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2708 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2709 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2710 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
2711 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2712 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
2713 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2714 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK1
2715 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI
2716 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_HSI
2717 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE
2718 */
LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)2719 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
2720 {
2721 return (uint32_t)((READ_BIT(RCC->CCIPR1, LPTIMx) >> 16U) | LPTIMx);
2722 }
2723
2724 /**
2725 * @brief Get FDCAN kernel clock source
2726 * @rmtoll CCIPR1 FDCANSEL LL_RCC_GetFDCANClockSource
2727 * @param FDCANx This parameter can be one of the following values:
2728 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
2729 * @retval Returned value can be one of the following values:
2730 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
2731 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL
2732 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLLSAI1
2733 */
LL_RCC_GetFDCANClockSource(uint32_t FDCANx)2734 __STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx)
2735 {
2736 return (uint32_t)(READ_BIT(RCC->CCIPR1, FDCANx));
2737 }
2738
2739 /**
2740 * @brief Get SAIx clock source
2741 * @rmtoll CCIPR2 SAI1SEL LL_RCC_GetSAIClockSource\n
2742 * CCIPR2 SAI2SEL LL_RCC_GetSAIClockSource
2743 * @param SAIx This parameter can be one of the following values:
2744 * @arg @ref LL_RCC_SAI1_CLKSOURCE
2745 * @arg @ref LL_RCC_SAI2_CLKSOURCE
2746 * @retval Returned value can be one of the following values:
2747 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
2748 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2
2749 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
2750 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
2751 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1
2752 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2
2753 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL
2754 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
2755 */
LL_RCC_GetSAIClockSource(uint32_t SAIx)2756 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
2757 {
2758 return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) | (SAIx << 16U));
2759 }
2760
2761 /**
2762 * @brief Get SDMMCx kernel clock source
2763 * @rmtoll CCIPR2 SDMMCSEL LL_RCC_GetSDMMCKernelClockSource
2764 * @param SDMMCx This parameter can be one of the following values:
2765 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE
2766 * @retval Returned value can be one of the following values:
2767 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK
2768 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP
2769 */
LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx)2770 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx)
2771 {
2772 return (uint32_t)(READ_BIT(RCC->CCIPR2, SDMMCx));
2773 }
2774
2775 /**
2776 * @brief Get SDMMCx clock source
2777 * @rmtoll CCIPR1 CLK48MSEL LL_RCC_GetSDMMCClockSource
2778 * @param SDMMCx This parameter can be one of the following values:
2779 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
2780 * @retval Returned value can be one of the following values:
2781 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48
2782 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1
2783 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
2784 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI
2785 */
LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)2786 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
2787 {
2788 return (uint32_t)(READ_BIT(RCC->CCIPR1, SDMMCx));
2789 }
2790
2791 /**
2792 * @brief Get RNGx clock source
2793 * @rmtoll CCIPR1 CLK48MSEL LL_RCC_GetRNGClockSource
2794 * @param RNGx This parameter can be one of the following values:
2795 * @arg @ref LL_RCC_RNG_CLKSOURCE
2796 * @retval Returned value can be one of the following values:
2797 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
2798 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1
2799 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
2800 * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
2801 */
LL_RCC_GetRNGClockSource(uint32_t RNGx)2802 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
2803 {
2804 return (uint32_t)(READ_BIT(RCC->CCIPR1, RNGx));
2805 }
2806
2807 /**
2808 * @brief Get USBx clock source
2809 * @rmtoll CCIPR1 CLK48MSEL LL_RCC_GetUSBClockSource
2810 * @param USBx This parameter can be one of the following values:
2811 * @arg @ref LL_RCC_USB_CLKSOURCE
2812 * @retval Returned value can be one of the following values:
2813 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
2814 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
2815 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
2816 * @arg @ref LL_RCC_USB_CLKSOURCE_MSI
2817 */
LL_RCC_GetUSBClockSource(uint32_t USBx)2818 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
2819 {
2820 return (uint32_t)(READ_BIT(RCC->CCIPR1, USBx));
2821 }
2822
2823 /**
2824 * @brief Get ADCx clock source
2825 * @rmtoll CCIPR1 ADCSEL LL_RCC_GetADCClockSource
2826 * @param ADCx This parameter can be one of the following values:
2827 * @arg @ref LL_RCC_ADC_CLKSOURCE
2828 * @retval Returned value can be one of the following values:
2829 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
2830 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
2831 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
2832 */
LL_RCC_GetADCClockSource(uint32_t ADCx)2833 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
2834 {
2835 return (uint32_t)(READ_BIT(RCC->CCIPR1, ADCx));
2836 }
2837
2838 /**
2839 * @brief Get DFSDM Audio Clock Source
2840 * @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource
2841 * @param DFSDMx This parameter can be one of the following values:
2842 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
2843 * @retval Returned value can be one of the following values:
2844 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
2845 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI
2846 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI
2847 */
LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)2848 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
2849 {
2850 return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx));
2851 }
2852
2853 /**
2854 * @brief Get DFSDMx Kernel clock source
2855 * @rmtoll CCIPR2 DFSDM1SEL LL_RCC_GetDFSDMClockSource
2856 * @param DFSDMx This parameter can be one of the following values:
2857 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
2858 * @retval Returned value can be one of the following values:
2859 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
2860 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
2861 */
LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)2862 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
2863 {
2864 return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx));
2865 }
2866
2867 /**
2868 * @brief Get OCTOSPI clock source
2869 * @rmtoll CCIPR2 OSPISEL LL_RCC_GetOCTOSPIClockSource
2870 * @param OCTOSPIx This parameter can be one of the following values:
2871 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE
2872 * @retval Returned value can be one of the following values:
2873 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK
2874 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI
2875 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL
2876 */
LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx)2877 __STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx)
2878 {
2879 return (uint32_t)(READ_BIT(RCC->CCIPR2, OCTOSPIx));
2880 }
2881 /**
2882 * @}
2883 */
2884
2885 /** @defgroup RCC_LL_EF_RTC RTC
2886 * @{
2887 */
2888
2889 /**
2890 * @brief Set RTC Clock Source
2891 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
2892 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
2893 * set). The BDRST bit can be used to reset them.
2894 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
2895 * @param Source This parameter can be one of the following values:
2896 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2897 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2898 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2899 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2900 * @retval None
2901 */
LL_RCC_SetRTCClockSource(uint32_t Source)2902 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
2903 {
2904 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
2905 }
2906
2907 /**
2908 * @brief Get RTC Clock Source
2909 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
2910 * @retval Returned value can be one of the following values:
2911 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2912 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2913 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2914 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2915 */
LL_RCC_GetRTCClockSource(void)2916 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
2917 {
2918 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
2919 }
2920
2921 /**
2922 * @brief Enable RTC
2923 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
2924 * @retval None
2925 */
LL_RCC_EnableRTC(void)2926 __STATIC_INLINE void LL_RCC_EnableRTC(void)
2927 {
2928 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2929 }
2930
2931 /**
2932 * @brief Disable RTC
2933 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
2934 * @retval None
2935 */
LL_RCC_DisableRTC(void)2936 __STATIC_INLINE void LL_RCC_DisableRTC(void)
2937 {
2938 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2939 }
2940
2941 /**
2942 * @brief Check if RTC has been enabled or not
2943 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
2944 * @retval State of bit (1 or 0).
2945 */
LL_RCC_IsEnabledRTC(void)2946 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
2947 {
2948 return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == RCC_BDCR_RTCEN) ? 1UL : 0UL);
2949 }
2950
2951 /**
2952 * @brief Force the Backup domain reset
2953 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
2954 * @retval None
2955 */
LL_RCC_ForceBackupDomainReset(void)2956 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
2957 {
2958 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2959 }
2960
2961 /**
2962 * @brief Release the Backup domain reset
2963 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
2964 * @retval None
2965 */
LL_RCC_ReleaseBackupDomainReset(void)2966 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
2967 {
2968 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2969 }
2970
2971 /**
2972 * @}
2973 */
2974
2975
2976 /** @defgroup RCC_LL_EF_PLL PLL
2977 * @{
2978 */
2979
2980 /**
2981 * @brief Enable PLL
2982 * @rmtoll CR PLLON LL_RCC_PLL_Enable
2983 * @retval None
2984 */
LL_RCC_PLL_Enable(void)2985 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
2986 {
2987 SET_BIT(RCC->CR, RCC_CR_PLLON);
2988 }
2989
2990 /**
2991 * @brief Disable PLL
2992 * @note Cannot be disabled if the PLL clock is used as the system clock
2993 * @rmtoll CR PLLON LL_RCC_PLL_Disable
2994 * @retval None
2995 */
LL_RCC_PLL_Disable(void)2996 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
2997 {
2998 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
2999 }
3000
3001 /**
3002 * @brief Check if PLL Ready
3003 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
3004 * @retval State of bit (1 or 0).
3005 */
LL_RCC_PLL_IsReady(void)3006 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
3007 {
3008 return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL);
3009 }
3010
3011 /**
3012 * @brief Configure PLL used for SYSCLK Domain
3013 * @note PLL Source, PLLM, PLLN and PLLR can be written only when PLL is disabled.
3014 * @note PLLN/PLLR can be written only when PLL is disabled.
3015 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
3016 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
3017 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
3018 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
3019 * @param Source This parameter can be one of the following values:
3020 * @arg @ref LL_RCC_PLLSOURCE_NONE
3021 * @arg @ref LL_RCC_PLLSOURCE_MSI
3022 * @arg @ref LL_RCC_PLLSOURCE_HSI
3023 * @arg @ref LL_RCC_PLLSOURCE_HSE
3024 * @param PLLM This parameter can be one of the following values:
3025 * @arg @ref LL_RCC_PLLM_DIV_1
3026 * @arg @ref LL_RCC_PLLM_DIV_2
3027 * @arg @ref LL_RCC_PLLM_DIV_3
3028 * @arg @ref LL_RCC_PLLM_DIV_4
3029 * @arg @ref LL_RCC_PLLM_DIV_5
3030 * @arg @ref LL_RCC_PLLM_DIV_6
3031 * @arg @ref LL_RCC_PLLM_DIV_7
3032 * @arg @ref LL_RCC_PLLM_DIV_8
3033 * @arg @ref LL_RCC_PLLM_DIV_9
3034 * @arg @ref LL_RCC_PLLM_DIV_10
3035 * @arg @ref LL_RCC_PLLM_DIV_11
3036 * @arg @ref LL_RCC_PLLM_DIV_12
3037 * @arg @ref LL_RCC_PLLM_DIV_13
3038 * @arg @ref LL_RCC_PLLM_DIV_14
3039 * @arg @ref LL_RCC_PLLM_DIV_15
3040 * @arg @ref LL_RCC_PLLM_DIV_16
3041 * @param PLLN Between 8 and 86
3042 * @param PLLR This parameter can be one of the following values:
3043 * @arg @ref LL_RCC_PLLR_DIV_2
3044 * @arg @ref LL_RCC_PLLR_DIV_4
3045 * @arg @ref LL_RCC_PLLR_DIV_6
3046 * @arg @ref LL_RCC_PLLR_DIV_8
3047 * @retval None
3048 */
LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)3049 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
3050 {
3051 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
3052 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
3053 }
3054
3055 /**
3056 * @brief Configure PLL used for SAI domain clock
3057 * @note PLL Source, PLLM, PLLN and PLLPDIV can be written only when PLL is disabled.
3058 * @note This can be selected for SAI1 or SAI2
3059 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
3060 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
3061 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
3062 * PLLCFGR PLLPDIV LL_RCC_PLL_ConfigDomain_SAI
3063 * @param Source This parameter can be one of the following values:
3064 * @arg @ref LL_RCC_PLLSOURCE_NONE
3065 * @arg @ref LL_RCC_PLLSOURCE_MSI
3066 * @arg @ref LL_RCC_PLLSOURCE_HSI
3067 * @arg @ref LL_RCC_PLLSOURCE_HSE
3068 * @param PLLM This parameter can be one of the following values:
3069 * @arg @ref LL_RCC_PLLM_DIV_1
3070 * @arg @ref LL_RCC_PLLM_DIV_2
3071 * @arg @ref LL_RCC_PLLM_DIV_3
3072 * @arg @ref LL_RCC_PLLM_DIV_4
3073 * @arg @ref LL_RCC_PLLM_DIV_5
3074 * @arg @ref LL_RCC_PLLM_DIV_6
3075 * @arg @ref LL_RCC_PLLM_DIV_7
3076 * @arg @ref LL_RCC_PLLM_DIV_8
3077 * @arg @ref LL_RCC_PLLM_DIV_9
3078 * @arg @ref LL_RCC_PLLM_DIV_10
3079 * @arg @ref LL_RCC_PLLM_DIV_11
3080 * @arg @ref LL_RCC_PLLM_DIV_12
3081 * @arg @ref LL_RCC_PLLM_DIV_13
3082 * @arg @ref LL_RCC_PLLM_DIV_14
3083 * @arg @ref LL_RCC_PLLM_DIV_15
3084 * @arg @ref LL_RCC_PLLM_DIV_16
3085 * @param PLLN Between 8 and 86
3086 * @param PLLP This parameter can be one of the following values:
3087 * @arg @ref LL_RCC_PLLP_DIV_2
3088 * @arg @ref LL_RCC_PLLP_DIV_3
3089 * @arg @ref LL_RCC_PLLP_DIV_4
3090 * @arg @ref LL_RCC_PLLP_DIV_5
3091 * @arg @ref LL_RCC_PLLP_DIV_6
3092 * @arg @ref LL_RCC_PLLP_DIV_7
3093 * @arg @ref LL_RCC_PLLP_DIV_8
3094 * @arg @ref LL_RCC_PLLP_DIV_9
3095 * @arg @ref LL_RCC_PLLP_DIV_10
3096 * @arg @ref LL_RCC_PLLP_DIV_11
3097 * @arg @ref LL_RCC_PLLP_DIV_12
3098 * @arg @ref LL_RCC_PLLP_DIV_13
3099 * @arg @ref LL_RCC_PLLP_DIV_14
3100 * @arg @ref LL_RCC_PLLP_DIV_15
3101 * @arg @ref LL_RCC_PLLP_DIV_16
3102 * @arg @ref LL_RCC_PLLP_DIV_17
3103 * @arg @ref LL_RCC_PLLP_DIV_18
3104 * @arg @ref LL_RCC_PLLP_DIV_19
3105 * @arg @ref LL_RCC_PLLP_DIV_20
3106 * @arg @ref LL_RCC_PLLP_DIV_21
3107 * @arg @ref LL_RCC_PLLP_DIV_22
3108 * @arg @ref LL_RCC_PLLP_DIV_23
3109 * @arg @ref LL_RCC_PLLP_DIV_24
3110 * @arg @ref LL_RCC_PLLP_DIV_25
3111 * @arg @ref LL_RCC_PLLP_DIV_26
3112 * @arg @ref LL_RCC_PLLP_DIV_27
3113 * @arg @ref LL_RCC_PLLP_DIV_28
3114 * @arg @ref LL_RCC_PLLP_DIV_29
3115 * @arg @ref LL_RCC_PLLP_DIV_30
3116 * @arg @ref LL_RCC_PLLP_DIV_31
3117 * @retval None
3118 */
LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)3119 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
3120 {
3121 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLPDIV,
3122 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
3123 }
3124
3125 /**
3126 * @brief Configure PLL used for 48Mhz domain clock
3127 * @note PLL Source, PLLM, PLLN and PLLQ can be written only when PLL is disabled.
3128 * @note This can be selected for USB, RNG, SDMMC
3129 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
3130 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
3131 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
3132 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
3133 * @param Source This parameter can be one of the following values:
3134 * @arg @ref LL_RCC_PLLSOURCE_NONE
3135 * @arg @ref LL_RCC_PLLSOURCE_MSI
3136 * @arg @ref LL_RCC_PLLSOURCE_HSI
3137 * @arg @ref LL_RCC_PLLSOURCE_HSE
3138 * @param PLLM This parameter can be one of the following values:
3139 * @arg @ref LL_RCC_PLLM_DIV_1
3140 * @arg @ref LL_RCC_PLLM_DIV_2
3141 * @arg @ref LL_RCC_PLLM_DIV_3
3142 * @arg @ref LL_RCC_PLLM_DIV_4
3143 * @arg @ref LL_RCC_PLLM_DIV_5
3144 * @arg @ref LL_RCC_PLLM_DIV_6
3145 * @arg @ref LL_RCC_PLLM_DIV_7
3146 * @arg @ref LL_RCC_PLLM_DIV_8
3147 * @arg @ref LL_RCC_PLLM_DIV_9
3148 * @arg @ref LL_RCC_PLLM_DIV_10
3149 * @arg @ref LL_RCC_PLLM_DIV_11
3150 * @arg @ref LL_RCC_PLLM_DIV_12
3151 * @arg @ref LL_RCC_PLLM_DIV_13
3152 * @arg @ref LL_RCC_PLLM_DIV_14
3153 * @arg @ref LL_RCC_PLLM_DIV_15
3154 * @arg @ref LL_RCC_PLLM_DIV_16
3155 * @param PLLN Between 8 and 86
3156 * @param PLLQ This parameter can be one of the following values:
3157 * @arg @ref LL_RCC_PLLQ_DIV_2
3158 * @arg @ref LL_RCC_PLLQ_DIV_4
3159 * @arg @ref LL_RCC_PLLQ_DIV_6
3160 * @arg @ref LL_RCC_PLLQ_DIV_8
3161 * @retval None
3162 */
LL_RCC_PLL_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)3163 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
3164 {
3165 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
3166 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
3167 }
3168
3169 /**
3170 * @brief Configure PLL clock source
3171 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
3172 * @param PLLSource This parameter can be one of the following values:
3173 * @arg @ref LL_RCC_PLLSOURCE_NONE
3174 * @arg @ref LL_RCC_PLLSOURCE_MSI
3175 * @arg @ref LL_RCC_PLLSOURCE_HSI
3176 * @arg @ref LL_RCC_PLLSOURCE_HSE
3177 * @retval None
3178 */
LL_RCC_PLL_SetMainSource(uint32_t PLLSource)3179 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
3180 {
3181 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
3182 }
3183
3184 /**
3185 * @brief Get the oscillator used as PLL clock source.
3186 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
3187 * @retval Returned value can be one of the following values:
3188 * @arg @ref LL_RCC_PLLSOURCE_NONE
3189 * @arg @ref LL_RCC_PLLSOURCE_MSI
3190 * @arg @ref LL_RCC_PLLSOURCE_HSI
3191 * @arg @ref LL_RCC_PLLSOURCE_HSE
3192 */
LL_RCC_PLL_GetMainSource(void)3193 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
3194 {
3195 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
3196 }
3197
3198 /**
3199 * @brief Get Main PLL multiplication factor for VCO
3200 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
3201 * @retval Between 8 and 86
3202 */
LL_RCC_PLL_GetN(void)3203 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
3204 {
3205 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
3206 }
3207
3208 /**
3209 * @brief Get Main PLL division factor for PLLP
3210 * @note Used for PLLSAI3CLK (SAI1 and SAI2 clock)
3211 * @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP
3212 * @retval Returned value can be one of the following values:
3213 * @arg @ref LL_RCC_PLLP_DIV_2
3214 * @arg @ref LL_RCC_PLLP_DIV_3
3215 * @arg @ref LL_RCC_PLLP_DIV_4
3216 * @arg @ref LL_RCC_PLLP_DIV_5
3217 * @arg @ref LL_RCC_PLLP_DIV_6
3218 * @arg @ref LL_RCC_PLLP_DIV_7
3219 * @arg @ref LL_RCC_PLLP_DIV_8
3220 * @arg @ref LL_RCC_PLLP_DIV_9
3221 * @arg @ref LL_RCC_PLLP_DIV_10
3222 * @arg @ref LL_RCC_PLLP_DIV_11
3223 * @arg @ref LL_RCC_PLLP_DIV_12
3224 * @arg @ref LL_RCC_PLLP_DIV_13
3225 * @arg @ref LL_RCC_PLLP_DIV_14
3226 * @arg @ref LL_RCC_PLLP_DIV_15
3227 * @arg @ref LL_RCC_PLLP_DIV_16
3228 * @arg @ref LL_RCC_PLLP_DIV_17
3229 * @arg @ref LL_RCC_PLLP_DIV_18
3230 * @arg @ref LL_RCC_PLLP_DIV_19
3231 * @arg @ref LL_RCC_PLLP_DIV_20
3232 * @arg @ref LL_RCC_PLLP_DIV_21
3233 * @arg @ref LL_RCC_PLLP_DIV_22
3234 * @arg @ref LL_RCC_PLLP_DIV_23
3235 * @arg @ref LL_RCC_PLLP_DIV_24
3236 * @arg @ref LL_RCC_PLLP_DIV_25
3237 * @arg @ref LL_RCC_PLLP_DIV_26
3238 * @arg @ref LL_RCC_PLLP_DIV_27
3239 * @arg @ref LL_RCC_PLLP_DIV_28
3240 * @arg @ref LL_RCC_PLLP_DIV_29
3241 * @arg @ref LL_RCC_PLLP_DIV_30
3242 * @arg @ref LL_RCC_PLLP_DIV_31
3243 */
LL_RCC_PLL_GetP(void)3244 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
3245 {
3246 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV));
3247 }
3248
3249 /**
3250 * @brief Get Main PLL division factor for PLLQ
3251 * @note Used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock)
3252 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
3253 * @retval Returned value can be one of the following values:
3254 * @arg @ref LL_RCC_PLLQ_DIV_2
3255 * @arg @ref LL_RCC_PLLQ_DIV_4
3256 * @arg @ref LL_RCC_PLLQ_DIV_6
3257 * @arg @ref LL_RCC_PLLQ_DIV_8
3258 */
LL_RCC_PLL_GetQ(void)3259 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
3260 {
3261 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
3262 }
3263
3264 /**
3265 * @brief Get Main PLL division factor for PLLR
3266 * @note Used for PLLCLK (system clock)
3267 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
3268 * @retval Returned value can be one of the following values:
3269 * @arg @ref LL_RCC_PLLR_DIV_2
3270 * @arg @ref LL_RCC_PLLR_DIV_4
3271 * @arg @ref LL_RCC_PLLR_DIV_6
3272 * @arg @ref LL_RCC_PLLR_DIV_8
3273 */
LL_RCC_PLL_GetR(void)3274 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
3275 {
3276 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
3277 }
3278
3279 /**
3280 * @brief Get Division factor for the main PLL and other PLL
3281 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
3282 * @retval Returned value can be one of the following values:
3283 * @arg @ref LL_RCC_PLLM_DIV_1
3284 * @arg @ref LL_RCC_PLLM_DIV_2
3285 * @arg @ref LL_RCC_PLLM_DIV_3
3286 * @arg @ref LL_RCC_PLLM_DIV_4
3287 * @arg @ref LL_RCC_PLLM_DIV_5
3288 * @arg @ref LL_RCC_PLLM_DIV_6
3289 * @arg @ref LL_RCC_PLLM_DIV_7
3290 * @arg @ref LL_RCC_PLLM_DIV_8
3291 * @arg @ref LL_RCC_PLLM_DIV_9
3292 * @arg @ref LL_RCC_PLLM_DIV_10
3293 * @arg @ref LL_RCC_PLLM_DIV_11
3294 * @arg @ref LL_RCC_PLLM_DIV_12
3295 * @arg @ref LL_RCC_PLLM_DIV_13
3296 * @arg @ref LL_RCC_PLLM_DIV_14
3297 * @arg @ref LL_RCC_PLLM_DIV_15
3298 * @arg @ref LL_RCC_PLLM_DIV_16
3299 */
LL_RCC_PLL_GetDivider(void)3300 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
3301 {
3302 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
3303 }
3304
3305 /**
3306 * @brief Enable PLL output mapped on SAI domain clock
3307 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI
3308 * @retval None
3309 */
LL_RCC_PLL_EnableDomain_SAI(void)3310 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void)
3311 {
3312 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3313 }
3314
3315 /**
3316 * @brief Disable PLL output mapped on SAI domain clock
3317 * @note Cannot be disabled if the PLL clock is used as the system
3318 * clock
3319 * @note In order to save power, when the PLLCLK of the PLL is
3320 * not used, should be 0
3321 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_SAI
3322 * @retval None
3323 */
LL_RCC_PLL_DisableDomain_SAI(void)3324 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void)
3325 {
3326 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3327 }
3328
3329 /**
3330 * @brief Check if PLL output mapped on SAI domain clock is enabled
3331 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_SAI
3332 * @retval State of bit (1 or 0).
3333 */
LL_RCC_PLL_IsEnabledDomain_SAI(void)3334 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SAI(void)
3335 {
3336 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL);
3337 }
3338
3339 /**
3340 * @brief Enable PLL output mapped on 48MHz domain clock
3341 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M
3342 * @retval None
3343 */
LL_RCC_PLL_EnableDomain_48M(void)3344 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
3345 {
3346 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3347 }
3348
3349 /**
3350 * @brief Disable PLL output mapped on 48MHz domain clock
3351 * @note Cannot be disabled if the PLL clock is used as the system
3352 * clock
3353 * @note In order to save power, when the PLLCLK of the PLL is
3354 * not used, should be 0
3355 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
3356 * @retval None
3357 */
LL_RCC_PLL_DisableDomain_48M(void)3358 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
3359 {
3360 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3361 }
3362
3363 /**
3364 * @brief Check if PLL output mapped on 48MHz domain clock is enabled
3365 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_48M
3366 * @retval State of bit (1 or 0).
3367 */
LL_RCC_PLL_IsEnabledDomain_48M(void)3368 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_48M(void)
3369 {
3370 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
3371 }
3372
3373 /**
3374 * @brief Enable PLL output mapped on SYSCLK domain
3375 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
3376 * @retval None
3377 */
LL_RCC_PLL_EnableDomain_SYS(void)3378 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
3379 {
3380 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
3381 }
3382
3383 /**
3384 * @brief Disable PLL output mapped on SYSCLK domain
3385 * @note Cannot be disabled if the PLL clock is used as the system
3386 * clock
3387 * @note In order to save power, when the PLLCLK of the PLL is
3388 * not used, Main PLL should be 0
3389 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
3390 * @retval None
3391 */
LL_RCC_PLL_DisableDomain_SYS(void)3392 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
3393 {
3394 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
3395 }
3396
3397 /**
3398 * @brief Check if PLL output mapped on SYSCLK domain clock is enabled
3399 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_IsEnabledDomain_SYS
3400 * @retval State of bit (1 or 0).
3401 */
LL_RCC_PLL_IsEnabledDomain_SYS(void)3402 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS(void)
3403 {
3404 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN) == (RCC_PLLCFGR_PLLREN)) ? 1UL : 0UL);
3405 }
3406
3407 /**
3408 * @}
3409 */
3410
3411 /** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1
3412 * @{
3413 */
3414
3415 /**
3416 * @brief Enable PLLSAI1
3417 * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Enable
3418 * @retval None
3419 */
LL_RCC_PLLSAI1_Enable(void)3420 __STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void)
3421 {
3422 SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
3423 }
3424
3425 /**
3426 * @brief Disable PLLSAI1
3427 * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Disable
3428 * @retval None
3429 */
LL_RCC_PLLSAI1_Disable(void)3430 __STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void)
3431 {
3432 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
3433 }
3434
3435 /**
3436 * @brief Check if PLLSAI1 Ready
3437 * @rmtoll CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady
3438 * @retval State of bit (1 or 0).
3439 */
LL_RCC_PLLSAI1_IsReady(void)3440 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void)
3441 {
3442 return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RCC_CR_PLLSAI1RDY) ? 1UL : 0UL);
3443 }
3444
3445 /**
3446 * @brief Configure PLLSAI1 used for 48Mhz domain clock
3447 * @note PLLSAI1SRC/PLLSAI1M/PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled.
3448 * @note This can be selected for USB, RNG, SDMMC
3449 * @rmtoll PLLSAI1CFGR PLLSAI1SRC LL_RCC_PLLSAI1_ConfigDomain_48M\n
3450 * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_48M\n
3451 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n
3452 * PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M
3453 * @param Source This parameter can be one of the following values:
3454 * @arg @ref LL_RCC_PLLSAI1SOURCE_NONE
3455 * @arg @ref LL_RCC_PLLSAI1SOURCE_MSI
3456 * @arg @ref LL_RCC_PLLSAI1SOURCE_HSI
3457 * @arg @ref LL_RCC_PLLSAI1SOURCE_HSE
3458 * @param PLLM This parameter can be one of the following values:
3459 * @arg @ref LL_RCC_PLLSAI1M_DIV_1
3460 * @arg @ref LL_RCC_PLLSAI1M_DIV_2
3461 * @arg @ref LL_RCC_PLLSAI1M_DIV_3
3462 * @arg @ref LL_RCC_PLLSAI1M_DIV_4
3463 * @arg @ref LL_RCC_PLLSAI1M_DIV_5
3464 * @arg @ref LL_RCC_PLLSAI1M_DIV_6
3465 * @arg @ref LL_RCC_PLLSAI1M_DIV_7
3466 * @arg @ref LL_RCC_PLLSAI1M_DIV_8
3467 * @arg @ref LL_RCC_PLLSAI1M_DIV_9
3468 * @arg @ref LL_RCC_PLLSAI1M_DIV_10
3469 * @arg @ref LL_RCC_PLLSAI1M_DIV_11
3470 * @arg @ref LL_RCC_PLLSAI1M_DIV_12
3471 * @arg @ref LL_RCC_PLLSAI1M_DIV_13
3472 * @arg @ref LL_RCC_PLLSAI1M_DIV_14
3473 * @arg @ref LL_RCC_PLLSAI1M_DIV_15
3474 * @arg @ref LL_RCC_PLLSAI1M_DIV_16
3475 * @param PLLN Between 8 and 86
3476 * @param PLLQ This parameter can be one of the following values:
3477 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
3478 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
3479 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
3480 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
3481 * @retval None
3482 */
LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)3483 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
3484 {
3485 MODIFY_REG(RCC->PLLSAI1CFGR,
3486 RCC_PLLSAI1CFGR_PLLSAI1SRC | RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q,
3487 Source | PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLQ);
3488 }
3489
3490 /**
3491 * @brief Configure PLLSAI1 used for SAI domain clock
3492 * @note PLLSAI1SRC/PLLSAI1M/PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled.
3493 * @note This can be selected for SAI1 or SAI2
3494 * @rmtoll PLLSAI1CFGR PLLSAI1SRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
3495 * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_SAI\n
3496 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
3497 * PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI
3498 * @param Source This parameter can be one of the following values:
3499 * @arg @ref LL_RCC_PLLSAI1SOURCE_NONE
3500 * @arg @ref LL_RCC_PLLSAI1SOURCE_MSI
3501 * @arg @ref LL_RCC_PLLSAI1SOURCE_HSI
3502 * @arg @ref LL_RCC_PLLSAI1SOURCE_HSE
3503 * @param PLLM This parameter can be one of the following values:
3504 * @arg @ref LL_RCC_PLLSAI1M_DIV_1
3505 * @arg @ref LL_RCC_PLLSAI1M_DIV_2
3506 * @arg @ref LL_RCC_PLLSAI1M_DIV_3
3507 * @arg @ref LL_RCC_PLLSAI1M_DIV_4
3508 * @arg @ref LL_RCC_PLLSAI1M_DIV_5
3509 * @arg @ref LL_RCC_PLLSAI1M_DIV_6
3510 * @arg @ref LL_RCC_PLLSAI1M_DIV_7
3511 * @arg @ref LL_RCC_PLLSAI1M_DIV_8
3512 * @arg @ref LL_RCC_PLLSAI1M_DIV_9
3513 * @arg @ref LL_RCC_PLLSAI1M_DIV_10
3514 * @arg @ref LL_RCC_PLLSAI1M_DIV_11
3515 * @arg @ref LL_RCC_PLLSAI1M_DIV_12
3516 * @arg @ref LL_RCC_PLLSAI1M_DIV_13
3517 * @arg @ref LL_RCC_PLLSAI1M_DIV_14
3518 * @arg @ref LL_RCC_PLLSAI1M_DIV_15
3519 * @arg @ref LL_RCC_PLLSAI1M_DIV_16
3520 * @param PLLN Between 8 and 86
3521 * @param PLLP This parameter can be one of the following values:
3522 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
3523 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
3524 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
3525 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
3526 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
3527 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
3528 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
3529 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
3530 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
3531 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
3532 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
3533 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
3534 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
3535 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
3536 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
3537 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
3538 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
3539 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
3540 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
3541 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
3542 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
3543 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
3544 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
3545 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
3546 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
3547 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
3548 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
3549 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
3550 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
3551 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
3552 * @retval None
3553 */
LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)3554 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
3555 {
3556 MODIFY_REG(RCC->PLLSAI1CFGR,
3557 RCC_PLLSAI1CFGR_PLLSAI1SRC | RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
3558 Source | PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLP);
3559 }
3560
3561 /**
3562 * @brief Configure PLLSAI1 used for ADC domain clock
3563 * @note PLLSAI1SRC/PLLSAI1M/PLLSAI1N/PLLSAI1R can be written only when PLLSAI1 is disabled.
3564 * @note This can be selected for ADC
3565 * @rmtoll PLLSAI1CFGR PLLSAI1SRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n
3566 * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_ADC\n
3567 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n
3568 * PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC
3569 * @param Source This parameter can be one of the following values:
3570 * @arg @ref LL_RCC_PLLSAI1SOURCE_NONE
3571 * @arg @ref LL_RCC_PLLSAI1SOURCE_MSI
3572 * @arg @ref LL_RCC_PLLSAI1SOURCE_HSI
3573 * @arg @ref LL_RCC_PLLSAI1SOURCE_HSE
3574 * @param PLLM This parameter can be one of the following values:
3575 * @arg @ref LL_RCC_PLLSAI1M_DIV_1
3576 * @arg @ref LL_RCC_PLLSAI1M_DIV_2
3577 * @arg @ref LL_RCC_PLLSAI1M_DIV_3
3578 * @arg @ref LL_RCC_PLLSAI1M_DIV_4
3579 * @arg @ref LL_RCC_PLLSAI1M_DIV_5
3580 * @arg @ref LL_RCC_PLLSAI1M_DIV_6
3581 * @arg @ref LL_RCC_PLLSAI1M_DIV_7
3582 * @arg @ref LL_RCC_PLLSAI1M_DIV_8
3583 * @arg @ref LL_RCC_PLLSAI1M_DIV_9
3584 * @arg @ref LL_RCC_PLLSAI1M_DIV_10
3585 * @arg @ref LL_RCC_PLLSAI1M_DIV_11
3586 * @arg @ref LL_RCC_PLLSAI1M_DIV_12
3587 * @arg @ref LL_RCC_PLLSAI1M_DIV_13
3588 * @arg @ref LL_RCC_PLLSAI1M_DIV_14
3589 * @arg @ref LL_RCC_PLLSAI1M_DIV_15
3590 * @arg @ref LL_RCC_PLLSAI1M_DIV_16
3591 * @param PLLN Between 8 and 86
3592 * @param PLLR This parameter can be one of the following values:
3593 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
3594 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
3595 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
3596 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
3597 * @retval None
3598 */
LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)3599 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
3600 {
3601 MODIFY_REG(RCC->PLLSAI1CFGR,
3602 RCC_PLLSAI1CFGR_PLLSAI1SRC | RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R,
3603 Source | PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLR);
3604 }
3605
3606 /**
3607 * @brief Configure PLLSAI1 clock source
3608 * @rmtoll PLLSAI1CFGR PLLSAI1SRC LL_RCC_PLLSAI1_SetSource
3609 * @param PLLSource This parameter can be one of the following values:
3610 * @arg @ref LL_RCC_PLLSAI1SOURCE_NONE
3611 * @arg @ref LL_RCC_PLLSAI1SOURCE_MSI
3612 * @arg @ref LL_RCC_PLLSAI1SOURCE_HSI
3613 * @arg @ref LL_RCC_PLLSAI1SOURCE_HSE
3614 * @retval None
3615 */
LL_RCC_PLLSAI1_SetSource(uint32_t PLLSource)3616 __STATIC_INLINE void LL_RCC_PLLSAI1_SetSource(uint32_t PLLSource)
3617 {
3618 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1SRC, PLLSource);
3619 }
3620
3621 /**
3622 * @brief Get the oscillator used as PLLSAI1 clock source.
3623 * @rmtoll PLLSAI1CFGR PLLSAI1SRC LL_RCC_PLLSAI1_GetSource
3624 * @retval Returned value can be one of the following values:
3625 * @arg @ref LL_RCC_PLLSAI1SOURCE_NONE
3626 * @arg @ref LL_RCC_PLLSAI1SOURCE_MSI
3627 * @arg @ref LL_RCC_PLLSAI1SOURCE_HSI
3628 * @arg @ref LL_RCC_PLLSAI1SOURCE_HSE
3629 */
LL_RCC_PLLSAI1_GetSource(void)3630 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetSource(void)
3631 {
3632 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1SRC));
3633 }
3634
3635 /**
3636 * @brief Get SAI1PLL multiplication factor for VCO
3637 * @rmtoll PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_GetN
3638 * @retval Between 8 and 86
3639 */
LL_RCC_PLLSAI1_GetN(void)3640 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void)
3641 {
3642 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos);
3643 }
3644
3645 /**
3646 * @brief Get SAI1PLL division factor for PLLSAI1P
3647 * @note Used for PLLSAI1CLK (SAI1 or SAI2 clock).
3648 * @rmtoll PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_GetP
3649 * @retval Returned value can be one of the following values:
3650 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
3651 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
3652 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
3653 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
3654 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
3655 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
3656 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
3657 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
3658 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
3659 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
3660 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
3661 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
3662 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
3663 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
3664 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
3665 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
3666 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
3667 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
3668 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
3669 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
3670 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
3671 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
3672 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
3673 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
3674 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
3675 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
3676 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
3677 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
3678 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
3679 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
3680 */
LL_RCC_PLLSAI1_GetP(void)3681 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
3682 {
3683 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV));
3684 }
3685
3686 /**
3687 * @brief Get SAI1PLL division factor for PLLSAI1Q
3688 * @note Used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock)
3689 * @rmtoll PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_GetQ
3690 * @retval Returned value can be one of the following values:
3691 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
3692 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
3693 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
3694 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
3695 */
LL_RCC_PLLSAI1_GetQ(void)3696 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void)
3697 {
3698 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q));
3699 }
3700
3701 /**
3702 * @brief Get PLLSAI1 division factor for PLLSAIR
3703 * @note Used for PLLADC1CLK (ADC clock)
3704 * @rmtoll PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_GetR
3705 * @retval Returned value can be one of the following values:
3706 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
3707 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
3708 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
3709 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
3710 */
LL_RCC_PLLSAI1_GetR(void)3711 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void)
3712 {
3713 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R));
3714 }
3715
3716 /**
3717 * @brief Get Division factor for the PLLSAI1
3718 * @rmtoll PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_GetDivider
3719 * @retval Returned value can be one of the following values:
3720 * @arg @ref LL_RCC_PLLSAI1M_DIV_1
3721 * @arg @ref LL_RCC_PLLSAI1M_DIV_2
3722 * @arg @ref LL_RCC_PLLSAI1M_DIV_3
3723 * @arg @ref LL_RCC_PLLSAI1M_DIV_4
3724 * @arg @ref LL_RCC_PLLSAI1M_DIV_5
3725 * @arg @ref LL_RCC_PLLSAI1M_DIV_6
3726 * @arg @ref LL_RCC_PLLSAI1M_DIV_7
3727 * @arg @ref LL_RCC_PLLSAI1M_DIV_8
3728 * @arg @ref LL_RCC_PLLSAI1M_DIV_9
3729 * @arg @ref LL_RCC_PLLSAI1M_DIV_10
3730 * @arg @ref LL_RCC_PLLSAI1M_DIV_11
3731 * @arg @ref LL_RCC_PLLSAI1M_DIV_12
3732 * @arg @ref LL_RCC_PLLSAI1M_DIV_13
3733 * @arg @ref LL_RCC_PLLSAI1M_DIV_14
3734 * @arg @ref LL_RCC_PLLSAI1M_DIV_15
3735 * @arg @ref LL_RCC_PLLSAI1M_DIV_16
3736 */
LL_RCC_PLLSAI1_GetDivider(void)3737 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetDivider(void)
3738 {
3739 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M));
3740 }
3741
3742 /**
3743 * @brief Enable PLLSAI1 output mapped on SAI domain clock
3744 * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI
3745 * @retval None
3746 */
LL_RCC_PLLSAI1_EnableDomain_SAI(void)3747 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void)
3748 {
3749 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
3750 }
3751
3752 /**
3753 * @brief Disable PLLSAI1 output mapped on SAI domain clock
3754 * @note In order to save power, when of the PLLSAI1 is
3755 * not used, should be 0
3756 * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_DisableDomain_SAI
3757 * @retval None
3758 */
LL_RCC_PLLSAI1_DisableDomain_SAI(void)3759 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void)
3760 {
3761 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
3762 }
3763
3764 /**
3765 * @brief Check if PLLSAI1 output mapped on SAI domain clock is enabled
3766 * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_IsEnabledDomain_SAI
3767 * @retval State of bit (1 or 0).
3768 */
LL_RCC_PLLSAI1_IsEnabledDomain_SAI(void)3769 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_SAI(void)
3770 {
3771 return ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN) == (RCC_PLLSAI1CFGR_PLLSAI1PEN)) ? 1UL : 0UL);
3772 }
3773
3774 /**
3775 * @brief Enable PLLSAI1 output mapped on 48MHz domain clock
3776 * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_EnableDomain_48M
3777 * @retval None
3778 */
LL_RCC_PLLSAI1_EnableDomain_48M(void)3779 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void)
3780 {
3781 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
3782 }
3783
3784 /**
3785 * @brief Disable PLLSAI1 output mapped on 48MHz domain clock
3786 * @note In order to save power, when of the PLLSAI1 is
3787 * not used, should be 0
3788 * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_DisableDomain_48M
3789 * @retval None
3790 */
LL_RCC_PLLSAI1_DisableDomain_48M(void)3791 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void)
3792 {
3793 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
3794 }
3795
3796 /**
3797 * @brief Check if PLLSAI1 output mapped on 48MHz domain clock is enabled
3798 * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_IsEnabledDomain_48M
3799 * @retval State of bit (1 or 0).
3800 */
LL_RCC_PLLSAI1_IsEnabledDomain_48M(void)3801 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_48M(void)
3802 {
3803 return ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN) == (RCC_PLLSAI1CFGR_PLLSAI1QEN)) ? 1UL : 0UL);
3804 }
3805
3806 /**
3807 * @brief Enable PLLSAI1 output mapped on ADC domain clock
3808 * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_EnableDomain_ADC
3809 * @retval None
3810 */
LL_RCC_PLLSAI1_EnableDomain_ADC(void)3811 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void)
3812 {
3813 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
3814 }
3815
3816 /**
3817 * @brief Disable PLLSAI1 output mapped on ADC domain clock
3818 * @note In order to save power, when of the PLLSAI1 is
3819 * not used, Main PLLSAI1 should be 0
3820 * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_DisableDomain_ADC
3821 * @retval None
3822 */
LL_RCC_PLLSAI1_DisableDomain_ADC(void)3823 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void)
3824 {
3825 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
3826 }
3827
3828 /**
3829 * @brief Check if PLLSAI1 output mapped on ADC domain clock is enabled
3830 * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_IsEnabledDomain_ADC
3831 * @retval State of bit (1 or 0).
3832 */
LL_RCC_PLLSAI1_IsEnabledDomain_ADC(void)3833 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_ADC(void)
3834 {
3835 return ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN) == (RCC_PLLSAI1CFGR_PLLSAI1REN)) ? 1UL : 0UL);
3836 }
3837
3838 /**
3839 * @}
3840 */
3841
3842 /** @defgroup RCC_LL_EF_PLLSAI2 PLLSAI2
3843 * @{
3844 */
3845
3846 /**
3847 * @brief Enable PLLSAI2
3848 * @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Enable
3849 * @retval None
3850 */
LL_RCC_PLLSAI2_Enable(void)3851 __STATIC_INLINE void LL_RCC_PLLSAI2_Enable(void)
3852 {
3853 SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
3854 }
3855
3856 /**
3857 * @brief Disable PLLSAI2
3858 * @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Disable
3859 * @retval None
3860 */
LL_RCC_PLLSAI2_Disable(void)3861 __STATIC_INLINE void LL_RCC_PLLSAI2_Disable(void)
3862 {
3863 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
3864 }
3865
3866 /**
3867 * @brief Check if PLLSAI2 Ready
3868 * @rmtoll CR PLLSAI2RDY LL_RCC_PLLSAI2_IsReady
3869 * @retval State of bit (1 or 0).
3870 */
LL_RCC_PLLSAI2_IsReady(void)3871 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void)
3872 {
3873 return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RCC_CR_PLLSAI2RDY) ? 1UL : 0UL);
3874 }
3875
3876 /**
3877 * @brief Configure PLLSAI2 used for SAI domain clock
3878 * @note PLLSAI2SRC/PLLSAI2M/PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled.
3879 * @note This can be selected for SAI1 or SAI2
3880 * @rmtoll PLLSAI2CFGR PLLSAI2SRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
3881 * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_SAI\n
3882 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
3883 * PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI
3884 * @param Source This parameter can be one of the following values:
3885 * @arg @ref LL_RCC_PLLSAI2SOURCE_NONE
3886 * @arg @ref LL_RCC_PLLSAI2SOURCE_MSI
3887 * @arg @ref LL_RCC_PLLSAI2SOURCE_HSI
3888 * @arg @ref LL_RCC_PLLSAI2SOURCE_HSE
3889 * @param PLLM This parameter can be one of the following values:
3890 * @arg @ref LL_RCC_PLLSAI2M_DIV_1
3891 * @arg @ref LL_RCC_PLLSAI2M_DIV_2
3892 * @arg @ref LL_RCC_PLLSAI2M_DIV_3
3893 * @arg @ref LL_RCC_PLLSAI2M_DIV_4
3894 * @arg @ref LL_RCC_PLLSAI2M_DIV_5
3895 * @arg @ref LL_RCC_PLLSAI2M_DIV_6
3896 * @arg @ref LL_RCC_PLLSAI2M_DIV_7
3897 * @arg @ref LL_RCC_PLLSAI2M_DIV_8
3898 * @arg @ref LL_RCC_PLLSAI2M_DIV_9
3899 * @arg @ref LL_RCC_PLLSAI2M_DIV_10
3900 * @arg @ref LL_RCC_PLLSAI2M_DIV_11
3901 * @arg @ref LL_RCC_PLLSAI2M_DIV_12
3902 * @arg @ref LL_RCC_PLLSAI2M_DIV_13
3903 * @arg @ref LL_RCC_PLLSAI2M_DIV_14
3904 * @arg @ref LL_RCC_PLLSAI2M_DIV_15
3905 * @arg @ref LL_RCC_PLLSAI2M_DIV_16
3906 * @param PLLN Between 8 and 86
3907 * @param PLLP This parameter can be one of the following values:
3908 * @arg @ref LL_RCC_PLLSAI2P_DIV_2
3909 * @arg @ref LL_RCC_PLLSAI2P_DIV_3
3910 * @arg @ref LL_RCC_PLLSAI2P_DIV_4
3911 * @arg @ref LL_RCC_PLLSAI2P_DIV_5
3912 * @arg @ref LL_RCC_PLLSAI2P_DIV_6
3913 * @arg @ref LL_RCC_PLLSAI2P_DIV_7
3914 * @arg @ref LL_RCC_PLLSAI2P_DIV_8
3915 * @arg @ref LL_RCC_PLLSAI2P_DIV_9
3916 * @arg @ref LL_RCC_PLLSAI2P_DIV_10
3917 * @arg @ref LL_RCC_PLLSAI2P_DIV_11
3918 * @arg @ref LL_RCC_PLLSAI2P_DIV_12
3919 * @arg @ref LL_RCC_PLLSAI2P_DIV_13
3920 * @arg @ref LL_RCC_PLLSAI2P_DIV_14
3921 * @arg @ref LL_RCC_PLLSAI2P_DIV_15
3922 * @arg @ref LL_RCC_PLLSAI2P_DIV_16
3923 * @arg @ref LL_RCC_PLLSAI2P_DIV_17
3924 * @arg @ref LL_RCC_PLLSAI2P_DIV_18
3925 * @arg @ref LL_RCC_PLLSAI2P_DIV_19
3926 * @arg @ref LL_RCC_PLLSAI2P_DIV_20
3927 * @arg @ref LL_RCC_PLLSAI2P_DIV_21
3928 * @arg @ref LL_RCC_PLLSAI2P_DIV_22
3929 * @arg @ref LL_RCC_PLLSAI2P_DIV_23
3930 * @arg @ref LL_RCC_PLLSAI2P_DIV_24
3931 * @arg @ref LL_RCC_PLLSAI2P_DIV_25
3932 * @arg @ref LL_RCC_PLLSAI2P_DIV_26
3933 * @arg @ref LL_RCC_PLLSAI2P_DIV_27
3934 * @arg @ref LL_RCC_PLLSAI2P_DIV_28
3935 * @arg @ref LL_RCC_PLLSAI2P_DIV_29
3936 * @arg @ref LL_RCC_PLLSAI2P_DIV_30
3937 * @arg @ref LL_RCC_PLLSAI2P_DIV_31
3938 * @retval None
3939 */
LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)3940 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
3941 {
3942 MODIFY_REG(RCC->PLLSAI2CFGR,
3943 RCC_PLLSAI2CFGR_PLLSAI2SRC | RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
3944 Source | PLLM | (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLP);
3945 }
3946
3947 /**
3948 * @brief Configure PLLSAI2 clock source
3949 * @rmtoll PLLSAI2CFGR PLLSAI2SRC LL_RCC_PLLSAI2_SetSource
3950 * @param PLLSource This parameter can be one of the following values:
3951 * @arg @ref LL_RCC_PLLSAI2SOURCE_NONE
3952 * @arg @ref LL_RCC_PLLSAI2SOURCE_MSI
3953 * @arg @ref LL_RCC_PLLSAI2SOURCE_HSI
3954 * @arg @ref LL_RCC_PLLSAI2SOURCE_HSE
3955 * @retval None
3956 */
LL_RCC_PLLSAI2_SetSource(uint32_t PLLSource)3957 __STATIC_INLINE void LL_RCC_PLLSAI2_SetSource(uint32_t PLLSource)
3958 {
3959 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2SRC, PLLSource);
3960 }
3961
3962 /**
3963 * @brief Get the oscillator used as PLLSAI2 clock source.
3964 * @rmtoll PLLSAI2CFGR PLLSAI2SRC LL_RCC_PLLSAI2_GetSource
3965 * @retval Returned value can be one of the following values:
3966 * @arg @ref LL_RCC_PLLSAI2SOURCE_NONE
3967 * @arg @ref LL_RCC_PLLSAI2SOURCE_MSI
3968 * @arg @ref LL_RCC_PLLSAI2SOURCE_HSI
3969 * @arg @ref LL_RCC_PLLSAI2SOURCE_HSE
3970 */
LL_RCC_PLLSAI2_GetSource(void)3971 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetSource(void)
3972 {
3973 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2SRC));
3974 }
3975
3976 /**
3977 * @brief Get SAI2PLL multiplication factor for VCO
3978 * @rmtoll PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_GetN
3979 * @retval Between 8 and 86
3980 */
LL_RCC_PLLSAI2_GetN(void)3981 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN(void)
3982 {
3983 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos);
3984 }
3985
3986 /**
3987 * @brief Get SAI2PLL division factor for PLLSAI2P
3988 * @note Used for PLLSAI2CLK (SAI1 or SAI2 clock).
3989 * @rmtoll PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_GetP
3990 * @retval Returned value can be one of the following values:
3991 * @arg @ref LL_RCC_PLLSAI2P_DIV_2
3992 * @arg @ref LL_RCC_PLLSAI2P_DIV_3
3993 * @arg @ref LL_RCC_PLLSAI2P_DIV_4
3994 * @arg @ref LL_RCC_PLLSAI2P_DIV_5
3995 * @arg @ref LL_RCC_PLLSAI2P_DIV_6
3996 * @arg @ref LL_RCC_PLLSAI2P_DIV_7
3997 * @arg @ref LL_RCC_PLLSAI2P_DIV_8
3998 * @arg @ref LL_RCC_PLLSAI2P_DIV_9
3999 * @arg @ref LL_RCC_PLLSAI2P_DIV_10
4000 * @arg @ref LL_RCC_PLLSAI2P_DIV_11
4001 * @arg @ref LL_RCC_PLLSAI2P_DIV_12
4002 * @arg @ref LL_RCC_PLLSAI2P_DIV_13
4003 * @arg @ref LL_RCC_PLLSAI2P_DIV_14
4004 * @arg @ref LL_RCC_PLLSAI2P_DIV_15
4005 * @arg @ref LL_RCC_PLLSAI2P_DIV_16
4006 * @arg @ref LL_RCC_PLLSAI2P_DIV_17
4007 * @arg @ref LL_RCC_PLLSAI2P_DIV_18
4008 * @arg @ref LL_RCC_PLLSAI2P_DIV_19
4009 * @arg @ref LL_RCC_PLLSAI2P_DIV_20
4010 * @arg @ref LL_RCC_PLLSAI2P_DIV_21
4011 * @arg @ref LL_RCC_PLLSAI2P_DIV_22
4012 * @arg @ref LL_RCC_PLLSAI2P_DIV_23
4013 * @arg @ref LL_RCC_PLLSAI2P_DIV_24
4014 * @arg @ref LL_RCC_PLLSAI2P_DIV_25
4015 * @arg @ref LL_RCC_PLLSAI2P_DIV_26
4016 * @arg @ref LL_RCC_PLLSAI2P_DIV_27
4017 * @arg @ref LL_RCC_PLLSAI2P_DIV_28
4018 * @arg @ref LL_RCC_PLLSAI2P_DIV_29
4019 * @arg @ref LL_RCC_PLLSAI2P_DIV_30
4020 * @arg @ref LL_RCC_PLLSAI2P_DIV_31
4021 */
LL_RCC_PLLSAI2_GetP(void)4022 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
4023 {
4024 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV));
4025 }
4026
4027 /**
4028 * @brief Get Division factor for the PLLSAI2
4029 * @rmtoll PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_GetDivider
4030 * @retval Returned value can be one of the following values:
4031 * @arg @ref LL_RCC_PLLSAI2M_DIV_1
4032 * @arg @ref LL_RCC_PLLSAI2M_DIV_2
4033 * @arg @ref LL_RCC_PLLSAI2M_DIV_3
4034 * @arg @ref LL_RCC_PLLSAI2M_DIV_4
4035 * @arg @ref LL_RCC_PLLSAI2M_DIV_5
4036 * @arg @ref LL_RCC_PLLSAI2M_DIV_6
4037 * @arg @ref LL_RCC_PLLSAI2M_DIV_7
4038 * @arg @ref LL_RCC_PLLSAI2M_DIV_8
4039 * @arg @ref LL_RCC_PLLSAI2M_DIV_9
4040 * @arg @ref LL_RCC_PLLSAI2M_DIV_10
4041 * @arg @ref LL_RCC_PLLSAI2M_DIV_11
4042 * @arg @ref LL_RCC_PLLSAI2M_DIV_12
4043 * @arg @ref LL_RCC_PLLSAI2M_DIV_13
4044 * @arg @ref LL_RCC_PLLSAI2M_DIV_14
4045 * @arg @ref LL_RCC_PLLSAI2M_DIV_15
4046 * @arg @ref LL_RCC_PLLSAI2M_DIV_16
4047 */
LL_RCC_PLLSAI2_GetDivider(void)4048 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDivider(void)
4049 {
4050 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M));
4051 }
4052
4053 /**
4054 * @brief Enable PLLSAI2 output mapped on SAI domain clock
4055 * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_EnableDomain_SAI
4056 * @retval None
4057 */
LL_RCC_PLLSAI2_EnableDomain_SAI(void)4058 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI(void)
4059 {
4060 SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
4061 }
4062
4063 /**
4064 * @brief Disable PLLSAI2 output mapped on SAI domain clock
4065 * @note In order to save power, when of the PLLSAI2 is
4066 * not used, should be 0
4067 * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_DisableDomain_SAI
4068 * @retval None
4069 */
LL_RCC_PLLSAI2_DisableDomain_SAI(void)4070 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI(void)
4071 {
4072 CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
4073 }
4074
4075 /**
4076 * @brief Check if PLLSAI2 output mapped on SAI domain clock is enabled
4077 * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_IsEnabledDomain_SAI
4078 * @retval State of bit (1 or 0).
4079 */
LL_RCC_PLLSAI2_IsEnabledDomain_SAI(void)4080 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsEnabledDomain_SAI(void)
4081 {
4082 return ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN) == (RCC_PLLSAI2CFGR_PLLSAI2PEN)) ? 1UL : 0UL);
4083 }
4084
4085 /**
4086 * @}
4087 */
4088
4089
4090 /** @defgroup RCC_LL_EF_PRIV Privileged mode
4091 * @{
4092 */
4093
4094 /**
4095 * @brief Enable Privileged mode
4096 * @rmtoll CR PRIV LL_RCC_EnablePrivilege
4097 * @retval None
4098 */
LL_RCC_EnablePrivilege(void)4099 __STATIC_INLINE void LL_RCC_EnablePrivilege(void)
4100 {
4101 SET_BIT(RCC->CR, RCC_CR_PRIV);
4102 }
4103
4104 /**
4105 * @brief Disable Privileged mode
4106 * @rmtoll CR PRIV LL_RCC_DisablePrivilege
4107 * @retval None
4108 */
LL_RCC_DisablePrivilege(void)4109 __STATIC_INLINE void LL_RCC_DisablePrivilege(void)
4110 {
4111 CLEAR_BIT(RCC->CR, RCC_CR_PRIV);
4112 }
4113
4114 /**
4115 * @brief Check if Privileged mode has been enabled or not
4116 * @rmtoll CR PRIV LL_RCC_IsEnabledPrivilege
4117 * @retval State of bit (1 or 0).
4118 */
LL_RCC_IsEnabledPrivilege(void)4119 __STATIC_INLINE uint32_t LL_RCC_IsEnabledPrivilege(void)
4120 {
4121 return ((READ_BIT(RCC->CR, RCC_CR_PRIV) == RCC_CR_PRIV) ? 1UL : 0UL);
4122 }
4123
4124 /**
4125 * @}
4126 */
4127
4128
4129 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
4130 * @{
4131 */
4132
4133 /**
4134 * @brief Clear LSI ready interrupt flag
4135 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
4136 * @retval None
4137 */
LL_RCC_ClearFlag_LSIRDY(void)4138 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
4139 {
4140 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
4141 }
4142
4143 /**
4144 * @brief Clear LSE ready interrupt flag
4145 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
4146 * @retval None
4147 */
LL_RCC_ClearFlag_LSERDY(void)4148 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
4149 {
4150 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
4151 }
4152
4153 /**
4154 * @brief Clear MSI ready interrupt flag
4155 * @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY
4156 * @retval None
4157 */
LL_RCC_ClearFlag_MSIRDY(void)4158 __STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
4159 {
4160 SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
4161 }
4162
4163 /**
4164 * @brief Clear HSI ready interrupt flag
4165 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
4166 * @retval None
4167 */
LL_RCC_ClearFlag_HSIRDY(void)4168 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
4169 {
4170 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
4171 }
4172
4173 /**
4174 * @brief Clear HSE ready interrupt flag
4175 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
4176 * @retval None
4177 */
LL_RCC_ClearFlag_HSERDY(void)4178 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
4179 {
4180 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
4181 }
4182
4183 /**
4184 * @brief Clear PLL ready interrupt flag
4185 * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
4186 * @retval None
4187 */
LL_RCC_ClearFlag_PLLRDY(void)4188 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
4189 {
4190 SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
4191 }
4192
4193 /**
4194 * @brief Clear HSI48 ready interrupt flag
4195 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
4196 * @retval None
4197 */
LL_RCC_ClearFlag_HSI48RDY(void)4198 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
4199 {
4200 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
4201 }
4202
4203 /**
4204 * @brief Clear PLLSAI1 ready interrupt flag
4205 * @rmtoll CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY
4206 * @retval None
4207 */
LL_RCC_ClearFlag_PLLSAI1RDY(void)4208 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void)
4209 {
4210 SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC);
4211 }
4212
4213 /**
4214 * @brief Clear PLLSAI1 ready interrupt flag
4215 * @rmtoll CICR PLLSAI2RDYC LL_RCC_ClearFlag_PLLSAI2RDY
4216 * @retval None
4217 */
LL_RCC_ClearFlag_PLLSAI2RDY(void)4218 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI2RDY(void)
4219 {
4220 SET_BIT(RCC->CICR, RCC_CICR_PLLSAI2RDYC);
4221 }
4222
4223 /**
4224 * @brief Clear Clock security system interrupt flag
4225 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
4226 * @retval None
4227 */
LL_RCC_ClearFlag_HSECSS(void)4228 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
4229 {
4230 SET_BIT(RCC->CICR, RCC_CICR_CSSC);
4231 }
4232
4233 /**
4234 * @brief Check if LSI ready interrupt occurred or not
4235 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
4236 * @retval State of bit (1 or 0).
4237 */
LL_RCC_IsActiveFlag_LSIRDY(void)4238 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
4239 {
4240 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL);
4241 }
4242
4243 /**
4244 * @brief Check if LSE ready interrupt occurred or not
4245 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
4246 * @retval State of bit (1 or 0).
4247 */
LL_RCC_IsActiveFlag_LSERDY(void)4248 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
4249 {
4250 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL);
4251 }
4252
4253 /**
4254 * @brief Check if MSI ready interrupt occurred or not
4255 * @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
4256 * @retval State of bit (1 or 0).
4257 */
LL_RCC_IsActiveFlag_MSIRDY(void)4258 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
4259 {
4260 return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == RCC_CIFR_MSIRDYF) ? 1UL : 0UL);
4261 }
4262
4263 /**
4264 * @brief Check if HSI ready interrupt occurred or not
4265 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
4266 * @retval State of bit (1 or 0).
4267 */
LL_RCC_IsActiveFlag_HSIRDY(void)4268 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
4269 {
4270 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL);
4271 }
4272
4273 /**
4274 * @brief Check if HSE ready interrupt occurred or not
4275 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
4276 * @retval State of bit (1 or 0).
4277 */
LL_RCC_IsActiveFlag_HSERDY(void)4278 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
4279 {
4280 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL);
4281 }
4282
4283 /**
4284 * @brief Check if PLL ready interrupt occurred or not
4285 * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
4286 * @retval State of bit (1 or 0).
4287 */
LL_RCC_IsActiveFlag_PLLRDY(void)4288 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
4289 {
4290 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == RCC_CIFR_PLLRDYF) ? 1UL : 0UL);
4291 }
4292
4293 /**
4294 * @brief Check if HSI48 ready interrupt occurred or not
4295 * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
4296 * @retval State of bit (1 or 0).
4297 */
LL_RCC_IsActiveFlag_HSI48RDY(void)4298 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
4299 {
4300 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == RCC_CIFR_HSI48RDYF) ? 1UL : 0UL);
4301 }
4302
4303 /**
4304 * @brief Check if PLLSAI1 ready interrupt occurred or not
4305 * @rmtoll CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY
4306 * @retval State of bit (1 or 0).
4307 */
LL_RCC_IsActiveFlag_PLLSAI1RDY(void)4308 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void)
4309 {
4310 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF) ? 1UL : 0UL);
4311 }
4312
4313 /**
4314 * @brief Check if PLLSAI1 ready interrupt occurred or not
4315 * @rmtoll CIFR PLLSAI2RDYF LL_RCC_IsActiveFlag_PLLSAI2RDY
4316 * @retval State of bit (1 or 0).
4317 */
LL_RCC_IsActiveFlag_PLLSAI2RDY(void)4318 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void)
4319 {
4320 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF) ? 1UL : 0UL);
4321 }
4322
4323 /**
4324 * @brief Check if Clock security system interrupt occurred or not
4325 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
4326 * @retval State of bit (1 or 0).
4327 */
LL_RCC_IsActiveFlag_HSECSS(void)4328 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
4329 {
4330 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == RCC_CIFR_CSSF) ? 1UL : 0UL);
4331 }
4332
4333 /**
4334 * @brief Check if RCC flag Independent Watchdog reset is set or not.
4335 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
4336 * @retval State of bit (1 or 0).
4337 */
LL_RCC_IsActiveFlag_IWDGRST(void)4338 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
4339 {
4340 return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL);
4341 }
4342
4343 /**
4344 * @brief Check if RCC flag Low Power reset is set or not.
4345 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
4346 * @retval State of bit (1 or 0).
4347 */
LL_RCC_IsActiveFlag_LPWRRST(void)4348 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
4349 {
4350 return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL);
4351 }
4352
4353 /**
4354 * @brief Check if RCC flag is set or not.
4355 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
4356 * @retval State of bit (1 or 0).
4357 */
LL_RCC_IsActiveFlag_OBLRST(void)4358 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
4359 {
4360 return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL);
4361 }
4362
4363 /**
4364 * @brief Check if RCC flag Pin reset is set or not.
4365 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
4366 * @retval State of bit (1 or 0).
4367 */
LL_RCC_IsActiveFlag_PINRST(void)4368 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
4369 {
4370 return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL);
4371 }
4372
4373 /**
4374 * @brief Check if RCC flag Software reset is set or not.
4375 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
4376 * @retval State of bit (1 or 0).
4377 */
LL_RCC_IsActiveFlag_SFTRST(void)4378 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
4379 {
4380 return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL);
4381 }
4382
4383 /**
4384 * @brief Check if RCC flag Window Watchdog reset is set or not.
4385 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
4386 * @retval State of bit (1 or 0).
4387 */
LL_RCC_IsActiveFlag_WWDGRST(void)4388 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
4389 {
4390 return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL);
4391 }
4392
4393 /**
4394 * @brief Check if RCC flag BOR reset is set or not.
4395 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
4396 * @retval State of bit (1 or 0).
4397 */
LL_RCC_IsActiveFlag_BORRST(void)4398 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
4399 {
4400 return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == RCC_CSR_BORRSTF) ? 1UL : 0UL);
4401 }
4402
4403 /**
4404 * @brief Set RMVF bit to clear the reset flags.
4405 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
4406 * @retval None
4407 */
LL_RCC_ClearResetFlags(void)4408 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
4409 {
4410 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
4411 }
4412
4413 /**
4414 * @}
4415 */
4416
4417 /** @defgroup RCC_LL_EF_IT_Management IT Management
4418 * @{
4419 */
4420
4421 /**
4422 * @brief Enable LSI ready interrupt
4423 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
4424 * @retval None
4425 */
LL_RCC_EnableIT_LSIRDY(void)4426 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
4427 {
4428 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
4429 }
4430
4431 /**
4432 * @brief Enable LSE ready interrupt
4433 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
4434 * @retval None
4435 */
LL_RCC_EnableIT_LSERDY(void)4436 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
4437 {
4438 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
4439 }
4440
4441 /**
4442 * @brief Enable MSI ready interrupt
4443 * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY
4444 * @retval None
4445 */
LL_RCC_EnableIT_MSIRDY(void)4446 __STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
4447 {
4448 SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
4449 }
4450
4451 /**
4452 * @brief Enable HSI ready interrupt
4453 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
4454 * @retval None
4455 */
LL_RCC_EnableIT_HSIRDY(void)4456 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
4457 {
4458 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
4459 }
4460
4461 /**
4462 * @brief Enable HSE ready interrupt
4463 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
4464 * @retval None
4465 */
LL_RCC_EnableIT_HSERDY(void)4466 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
4467 {
4468 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
4469 }
4470
4471 /**
4472 * @brief Enable PLL ready interrupt
4473 * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
4474 * @retval None
4475 */
LL_RCC_EnableIT_PLLRDY(void)4476 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
4477 {
4478 SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
4479 }
4480
4481 /**
4482 * @brief Enable HSI48 ready interrupt
4483 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
4484 * @retval None
4485 */
LL_RCC_EnableIT_HSI48RDY(void)4486 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
4487 {
4488 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
4489 }
4490
4491 /**
4492 * @brief Enable PLLSAI1 ready interrupt
4493 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY
4494 * @retval None
4495 */
LL_RCC_EnableIT_PLLSAI1RDY(void)4496 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void)
4497 {
4498 SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
4499 }
4500
4501 /**
4502 * @brief Enable PLLSAI2 ready interrupt
4503 * @rmtoll CIER PLLSAI2RDYIE LL_RCC_EnableIT_PLLSAI2RDY
4504 * @retval None
4505 */
LL_RCC_EnableIT_PLLSAI2RDY(void)4506 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI2RDY(void)
4507 {
4508 SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
4509 }
4510
4511 /**
4512 * @brief Disable LSI ready interrupt
4513 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
4514 * @retval None
4515 */
LL_RCC_DisableIT_LSIRDY(void)4516 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
4517 {
4518 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
4519 }
4520
4521 /**
4522 * @brief Disable LSE ready interrupt
4523 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
4524 * @retval None
4525 */
LL_RCC_DisableIT_LSERDY(void)4526 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
4527 {
4528 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
4529 }
4530
4531 /**
4532 * @brief Disable MSI ready interrupt
4533 * @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY
4534 * @retval None
4535 */
LL_RCC_DisableIT_MSIRDY(void)4536 __STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
4537 {
4538 CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
4539 }
4540
4541 /**
4542 * @brief Disable HSI ready interrupt
4543 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
4544 * @retval None
4545 */
LL_RCC_DisableIT_HSIRDY(void)4546 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
4547 {
4548 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
4549 }
4550
4551 /**
4552 * @brief Disable HSE ready interrupt
4553 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
4554 * @retval None
4555 */
LL_RCC_DisableIT_HSERDY(void)4556 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
4557 {
4558 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
4559 }
4560
4561 /**
4562 * @brief Disable PLL ready interrupt
4563 * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
4564 * @retval None
4565 */
LL_RCC_DisableIT_PLLRDY(void)4566 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
4567 {
4568 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
4569 }
4570
4571 /**
4572 * @brief Disable HSI48 ready interrupt
4573 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
4574 * @retval None
4575 */
LL_RCC_DisableIT_HSI48RDY(void)4576 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
4577 {
4578 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
4579 }
4580
4581 /**
4582 * @brief Disable PLLSAI1 ready interrupt
4583 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY
4584 * @retval None
4585 */
LL_RCC_DisableIT_PLLSAI1RDY(void)4586 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void)
4587 {
4588 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
4589 }
4590
4591 /**
4592 * @brief Disable PLLSAI2 ready interrupt
4593 * @rmtoll CIER PLLSAI2RDYIE LL_RCC_DisableIT_PLLSAI2RDY
4594 * @retval None
4595 */
LL_RCC_DisableIT_PLLSAI2RDY(void)4596 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI2RDY(void)
4597 {
4598 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
4599 }
4600
4601 /**
4602 * @brief Checks if LSI ready interrupt source is enabled or disabled.
4603 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
4604 * @retval State of bit (1 or 0).
4605 */
LL_RCC_IsEnabledIT_LSIRDY(void)4606 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
4607 {
4608 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL);
4609 }
4610
4611 /**
4612 * @brief Checks if LSE ready interrupt source is enabled or disabled.
4613 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
4614 * @retval State of bit (1 or 0).
4615 */
LL_RCC_IsEnabledIT_LSERDY(void)4616 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
4617 {
4618 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL);
4619 }
4620
4621 /**
4622 * @brief Checks if MSI ready interrupt source is enabled or disabled.
4623 * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
4624 * @retval State of bit (1 or 0).
4625 */
LL_RCC_IsEnabledIT_MSIRDY(void)4626 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
4627 {
4628 return ((READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == RCC_CIER_MSIRDYIE) ? 1UL : 0UL);
4629 }
4630
4631 /**
4632 * @brief Checks if HSI ready interrupt source is enabled or disabled.
4633 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
4634 * @retval State of bit (1 or 0).
4635 */
LL_RCC_IsEnabledIT_HSIRDY(void)4636 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
4637 {
4638 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL);
4639 }
4640
4641 /**
4642 * @brief Checks if HSE ready interrupt source is enabled or disabled.
4643 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
4644 * @retval State of bit (1 or 0).
4645 */
LL_RCC_IsEnabledIT_HSERDY(void)4646 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
4647 {
4648 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL);
4649 }
4650
4651 /**
4652 * @brief Checks if PLL ready interrupt source is enabled or disabled.
4653 * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
4654 * @retval State of bit (1 or 0).
4655 */
LL_RCC_IsEnabledIT_PLLRDY(void)4656 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
4657 {
4658 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == RCC_CIER_PLLRDYIE) ? 1UL : 0UL);
4659 }
4660
4661 /**
4662 * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
4663 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
4664 * @retval State of bit (1 or 0).
4665 */
LL_RCC_IsEnabledIT_HSI48RDY(void)4666 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
4667 {
4668 return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL);
4669 }
4670
4671 /**
4672 * @brief Checks if PLLSAI1 ready interrupt source is enabled or disabled.
4673 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_IsEnabledIT_PLLSAI1RDY
4674 * @retval State of bit (1 or 0).
4675 */
LL_RCC_IsEnabledIT_PLLSAI1RDY(void)4676 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void)
4677 {
4678 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == RCC_CIER_PLLSAI1RDYIE) ? 1UL : 0UL);
4679 }
4680
4681 /**
4682 * @brief Checks if PLLSAI2 ready interrupt source is enabled or disabled.
4683 * @rmtoll CIER PLLSAI2RDYIE LL_RCC_IsEnabledIT_PLLSAI2RDY
4684 * @retval State of bit (1 or 0).
4685 */
LL_RCC_IsEnabledIT_PLLSAI2RDY(void)4686 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void)
4687 {
4688 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == RCC_CIER_PLLSAI2RDYIE) ? 1UL : 0UL);
4689 }
4690
4691 /**
4692 * @}
4693 */
4694
4695 /** @defgroup RCC_LL_EF_Secure_Management Secure Management
4696 * @{
4697 */
4698
4699 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
4700
4701 /**
4702 * @brief Configure Secure mode
4703 * @note Only available from secure state when system implements security (TZEN=1)
4704 * @rmtoll SECCFGR HSISEC LL_RCC_ConfigSecure\n
4705 * SECCFGR HSESEC LL_RCC_ConfigSecure\n
4706 * SECCFGR MSISEC LL_RCC_ConfigSecure\n
4707 * SECCFGR LSISEC LL_RCC_ConfigSecure\n
4708 * SECCFGR LSESEC LL_RCC_ConfigSecure\n
4709 * SECCFGR SYSCLKSEC LL_RCC_ConfigSecure\n
4710 * SECCFGR PRESCSEC LL_RCC_ConfigSecure\n
4711 * SECCFGR PLLSEC LL_RCC_ConfigSecure\n
4712 * SECCFGR PLLSAI1SEC LL_RCC_ConfigSecure\n
4713 * SECCFGR PLLSAI2SEC LL_RCC_ConfigSecure\n
4714 * SECCFGR CLK48MSEC LL_RCC_ConfigSecure\n
4715 * SECCFGR HSI48SEC LL_RCC_ConfigSecure\n
4716 * SECCFGR RMVFSEC LL_RCC_ConfigSecure
4717 * @param Configuration This parameter shall be the full combination
4718 * of the following values:
4719 * @arg @ref LL_RCC_HSI_SEC or LL_RCC_HSI_NSEC
4720 * @arg @ref LL_RCC_HSE_SEC or LL_RCC_HSE_NSEC
4721 * @arg @ref LL_RCC_MSI_SEC or LL_RCC_MSI_NSEC
4722 * @arg @ref LL_RCC_LSI_SEC or LL_RCC_LSI_NSEC
4723 * @arg @ref LL_RCC_LSE_SEC or LL_RCC_LSE_NSEC
4724 * @arg @ref LL_RCC_SYSCLK_SEC or LL_RCC_SYSCLK_NSEC
4725 * @arg @ref LL_RCC_PRESCALERS_SEC or LL_RCC_PRESCALERS_NSEC
4726 * @arg @ref LL_RCC_PLL_SEC or LL_RCC_PLL_NSEC
4727 * @arg @ref LL_RCC_PLLSAI1_SEC or LL_RCC_PLLSAI1_NSEC
4728 * @arg @ref LL_RCC_PLLSAI2_SEC or LL_RCC_PLLSAI2_NSEC
4729 * @arg @ref LL_RCC_CLK48M_SEC or LL_RCC_CLK48M_NSEC
4730 * @arg @ref LL_RCC_HSI48_SEC or LL_RCC_HSI48_NSEC
4731 * @arg @ref LL_RCC_RESET_FLAGS_SEC or LL_RCC_RESET_FLAGS_NSEC
4732 * @retval None
4733 */
LL_RCC_ConfigSecure(uint32_t Configuration)4734 __STATIC_INLINE void LL_RCC_ConfigSecure(uint32_t Configuration)
4735 {
4736 WRITE_REG(RCC->SECCFGR, Configuration);
4737 }
4738
4739 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
4740
4741 /**
4742 * @brief Get Secure mode configuration
4743 * @note Only available when system implements security (TZEN=1)
4744 * @rmtoll SECSR HSISECF LL_RCC_GetConfigSecure\n
4745 * SECSR HSESECF LL_RCC_GetConfigSecure\n
4746 * SECSR MSISECF LL_RCC_GetConfigSecure\n
4747 * SECSR LSISECF LL_RCC_GetConfigSecure\n
4748 * SECSR LSESECF LL_RCC_GetConfigSecure\n
4749 * SECSR SYSCLKSECF LL_RCC_GetConfigSecure\n
4750 * SECSR PRESCSECF LL_RCC_GetConfigSecure\n
4751 * SECSR PLLSECF LL_RCC_GetConfigSecure\n
4752 * SECSR PLLSAI1SECF LL_RCC_GetConfigSecure\n
4753 * SECSR PLLSAI2SECF LL_RCC_GetConfigSecure\n
4754 * SECSR CLK48MSECF LL_RCC_GetConfigSecure\n
4755 * SECSR HSI48SECF LL_RCC_GetConfigSecure\n
4756 * SECSR RMVFSECF LL_RCC_GetConfigSecure
4757 * @retval Returned value is the combination of the following values:
4758 * @arg @ref LL_RCC_HSI_SEC or LL_RCC_HSI_NSEC
4759 * @arg @ref LL_RCC_HSE_SEC or LL_RCC_HSE_NSEC
4760 * @arg @ref LL_RCC_MSI_SEC or LL_RCC_MSI_NSEC
4761 * @arg @ref LL_RCC_LSI_SEC or LL_RCC_LSI_NSEC
4762 * @arg @ref LL_RCC_LSE_SEC or LL_RCC_LSE_NSEC
4763 * @arg @ref LL_RCC_SYSCLK_SEC or LL_RCC_SYSCLK_NSEC
4764 * @arg @ref LL_RCC_PRESCALERS_SEC or LL_RCC_PRESCALERS_NSEC
4765 * @arg @ref LL_RCC_PLL_SEC or LL_RCC_PLL_NSEC
4766 * @arg @ref LL_RCC_PLLSAI1_SEC or LL_RCC_PLLSAI1_NSEC
4767 * @arg @ref LL_RCC_PLLSAI2_SEC or LL_RCC_PLLSAI2_NSEC
4768 * @arg @ref LL_RCC_CLK48M_SEC or LL_RCC_CLK48M_NSEC
4769 * @arg @ref LL_RCC_HSI48_SEC or LL_RCC_HSI48_NSEC
4770 * @arg @ref LL_RCC_RESET_FLAGS_SEC or LL_RCC_RESET_FLAGS_NSEC
4771 */
LL_RCC_GetConfigSecure(void)4772 __STATIC_INLINE uint32_t LL_RCC_GetConfigSecure(void)
4773 {
4774 return (uint32_t)(READ_BIT(RCC->SECSR, RCC_SECURE_MASK));
4775 }
4776
4777 /**
4778 * @}
4779 */
4780
4781 #if defined(USE_FULL_LL_DRIVER)
4782 /** @defgroup RCC_LL_EF_Init De-initialization function
4783 * @{
4784 */
4785 ErrorStatus LL_RCC_DeInit(void);
4786 /**
4787 * @}
4788 */
4789
4790 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
4791 * @{
4792 */
4793 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
4794 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
4795 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
4796 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
4797 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
4798 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
4799 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
4800 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
4801 uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource);
4802 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
4803 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
4804 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
4805 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
4806 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
4807 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
4808 uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource);
4809 /**
4810 * @}
4811 */
4812 #endif /* USE_FULL_LL_DRIVER */
4813
4814 /**
4815 * @}
4816 */
4817
4818 /**
4819 * @}
4820 */
4821
4822 #endif /* defined(RCC) */
4823
4824 /**
4825 * @}
4826 */
4827
4828 #ifdef __cplusplus
4829 }
4830 #endif
4831
4832 #endif /* STM32L5xx_LL_RCC_H */
4833
4834
