1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17
18 /* Define to prevent recursive inclusion -------------------------------------*/
19 #ifndef __STM32F4xx_LL_RCC_H
20 #define __STM32F4xx_LL_RCC_H
21
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25
26 /* Includes ------------------------------------------------------------------*/
27 #include "stm32f4xx.h"
28
29 /** @addtogroup STM32F4xx_LL_Driver
30 * @{
31 */
32
33 #if defined(RCC)
34
35 /** @defgroup RCC_LL RCC
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
42 * @{
43 */
44
45 #if defined(RCC_DCKCFGR_PLLSAIDIVR)
46 static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};
47 #endif /* RCC_DCKCFGR_PLLSAIDIVR */
48
49 /**
50 * @}
51 */
52 /* Private constants ---------------------------------------------------------*/
53 /* Private macros ------------------------------------------------------------*/
54 #if defined(USE_FULL_LL_DRIVER)
55 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
56 * @{
57 */
58 /**
59 * @}
60 */
61 #endif /*USE_FULL_LL_DRIVER*/
62 /* Exported types ------------------------------------------------------------*/
63 #if defined(USE_FULL_LL_DRIVER)
64 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
65 * @{
66 */
67
68 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
69 * @{
70 */
71
72 /**
73 * @brief RCC Clocks Frequency Structure
74 */
75 typedef struct
76 {
77 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
78 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
79 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
80 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
81 } LL_RCC_ClocksTypeDef;
82
83 /**
84 * @}
85 */
86
87 /**
88 * @}
89 */
90 #endif /* USE_FULL_LL_DRIVER */
91
92 /* Exported constants --------------------------------------------------------*/
93 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
94 * @{
95 */
96
97 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
98 * @brief Defines used to adapt values of different oscillators
99 * @note These values could be modified in the user environment according to
100 * HW set-up.
101 * @{
102 */
103 #if !defined (HSE_VALUE)
104 #define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */
105 #endif /* HSE_VALUE */
106
107 #if !defined (HSI_VALUE)
108 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
109 #endif /* HSI_VALUE */
110
111 #if !defined (LSE_VALUE)
112 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
113 #endif /* LSE_VALUE */
114
115 #if !defined (LSI_VALUE)
116 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
117 #endif /* LSI_VALUE */
118
119 #if !defined (EXTERNAL_CLOCK_VALUE)
120 #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
121 #endif /* EXTERNAL_CLOCK_VALUE */
122 /**
123 * @}
124 */
125
126 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
127 * @brief Flags defines which can be used with LL_RCC_WriteReg function
128 * @{
129 */
130 #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
131 #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
132 #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
133 #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
134 #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
135 #if defined(RCC_PLLI2S_SUPPORT)
136 #define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */
137 #endif /* RCC_PLLI2S_SUPPORT */
138 #if defined(RCC_PLLSAI_SUPPORT)
139 #define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /*!< PLLSAI Ready Interrupt Clear */
140 #endif /* RCC_PLLSAI_SUPPORT */
141 #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
142 /**
143 * @}
144 */
145
146 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
147 * @brief Flags defines which can be used with LL_RCC_ReadReg function
148 * @{
149 */
150 #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
151 #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
152 #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
153 #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
154 #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
155 #if defined(RCC_PLLI2S_SUPPORT)
156 #define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */
157 #endif /* RCC_PLLI2S_SUPPORT */
158 #if defined(RCC_PLLSAI_SUPPORT)
159 #define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /*!< PLLSAI Ready Interrupt flag */
160 #endif /* RCC_PLLSAI_SUPPORT */
161 #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
162 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
163 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
164 #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
165 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
166 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
167 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
168 #if defined(RCC_CSR_BORRSTF)
169 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
170 #endif /* RCC_CSR_BORRSTF */
171 /**
172 * @}
173 */
174
175 /** @defgroup RCC_LL_EC_IT IT Defines
176 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
177 * @{
178 */
179 #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
180 #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
181 #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
182 #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
183 #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
184 #if defined(RCC_PLLI2S_SUPPORT)
185 #define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable */
186 #endif /* RCC_PLLI2S_SUPPORT */
187 #if defined(RCC_PLLSAI_SUPPORT)
188 #define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /*!< PLLSAI Ready Interrupt Enable */
189 #endif /* RCC_PLLSAI_SUPPORT */
190 /**
191 * @}
192 */
193
194 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
195 * @{
196 */
197 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
198 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
199 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
200 #if defined(RCC_CFGR_SW_PLLR)
201 #define LL_RCC_SYS_CLKSOURCE_PLLR RCC_CFGR_SW_PLLR /*!< PLLR selection as system clock */
202 #endif /* RCC_CFGR_SW_PLLR */
203 /**
204 * @}
205 */
206
207 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
208 * @{
209 */
210 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
211 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
212 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
213 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
214 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLLR RCC_CFGR_SWS_PLLR /*!< PLLR used as system clock */
215 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
216 /**
217 * @}
218 */
219
220 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
221 * @{
222 */
223 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
224 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
225 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
226 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
227 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
228 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
229 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
230 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
231 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
232 /**
233 * @}
234 */
235
236 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
237 * @{
238 */
239 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
240 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
241 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
242 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
243 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
244 /**
245 * @}
246 */
247
248 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
249 * @{
250 */
251 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
252 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
253 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
254 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
255 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
256 /**
257 * @}
258 */
259
260 /** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
261 * @{
262 */
263 #define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) /*!< HSI selection as MCO1 source */
264 #define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) /*!< LSE selection as MCO1 source */
265 #define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) /*!< HSE selection as MCO1 source */
266 #define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U)) /*!< PLLCLK selection as MCO1 source */
267 #if defined(RCC_CFGR_MCO2)
268 #define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) /*!< SYSCLK selection as MCO2 source */
269 #define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) /*!< PLLI2S selection as MCO2 source */
270 #define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) /*!< HSE selection as MCO2 source */
271 #define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U)) /*!< PLLCLK selection as MCO2 source */
272 #endif /* RCC_CFGR_MCO2 */
273 /**
274 * @}
275 */
276
277 /** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
278 * @{
279 */
280 #define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) /*!< MCO1 not divided */
281 #define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) /*!< MCO1 divided by 2 */
282 #define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U)) /*!< MCO1 divided by 3 */
283 #define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U)) /*!< MCO1 divided by 4 */
284 #define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) /*!< MCO1 divided by 5 */
285 #if defined(RCC_CFGR_MCO2PRE)
286 #define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) /*!< MCO2 not divided */
287 #define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) /*!< MCO2 divided by 2 */
288 #define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U)) /*!< MCO2 divided by 3 */
289 #define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U)) /*!< MCO2 divided by 4 */
290 #define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) /*!< MCO2 divided by 5 */
291 #endif /* RCC_CFGR_MCO2PRE */
292 /**
293 * @}
294 */
295
296 /** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
297 * @{
298 */
299 #define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */
300 #define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */
301 #define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 3 */
302 #define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */
303 #define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 5 */
304 #define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 6 */
305 #define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 7 */
306 #define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */
307 #define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 9 */
308 #define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 10 */
309 #define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 11 */
310 #define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 12 */
311 #define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 13 */
312 #define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 14 */
313 #define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 15 */
314 #define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */
315 #define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 17 */
316 #define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 18 */
317 #define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 19 */
318 #define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 20 */
319 #define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 21 */
320 #define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 22 */
321 #define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 23 */
322 #define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE clock divided by 24 */
323 #define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 25 */
324 #define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 26 */
325 #define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 27 */
326 #define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 28 */
327 #define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 29 */
328 #define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 30 */
329 #define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 31 */
330 /**
331 * @}
332 */
333
334 #if defined(USE_FULL_LL_DRIVER)
335 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
336 * @{
337 */
338 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
339 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
340 /**
341 * @}
342 */
343 #endif /* USE_FULL_LL_DRIVER */
344
345 #if defined(FMPI2C1)
346 /** @defgroup RCC_LL_EC_FMPI2C1_CLKSOURCE Peripheral FMPI2C clock source selection
347 * @{
348 */
349 #define LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as FMPI2C1 clock source */
350 #define LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK RCC_DCKCFGR2_FMPI2C1SEL_0 /*!< SYSCLK clock used as FMPI2C1 clock source */
351 #define LL_RCC_FMPI2C1_CLKSOURCE_HSI RCC_DCKCFGR2_FMPI2C1SEL_1 /*!< HSI clock used as FMPI2C1 clock source */
352 /**
353 * @}
354 */
355 #endif /* FMPI2C1 */
356
357 #if defined(LPTIM1)
358 /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
359 * @{
360 */
361 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock */
362 #define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_0 /*!< LSI oscillator clock used as LPTIM1 clock */
363 #define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_1 /*!< HSI oscillator clock used as LPTIM1 clock */
364 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0) /*!< LSE oscillator clock used as LPTIM1 clock */
365 /**
366 * @}
367 */
368 #endif /* LPTIM1 */
369
370 #if defined(SAI1)
371 /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection
372 * @{
373 */
374 #if defined(RCC_DCKCFGR_SAI1SRC)
375 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1SRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 clock source */
376 #define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 clock source */
377 #define LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_1 >> 16)) /*!< PLL clock used as SAI1 clock source */
378 #define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC >> 16)) /*!< External pin clock used as SAI1 clock source */
379 #endif /* RCC_DCKCFGR_SAI1SRC */
380 #if defined(RCC_DCKCFGR_SAI2SRC)
381 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI2SRC | 0x00000000U) /*!< PLLSAI clock used as SAI2 clock source */
382 #define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_0 >> 16)) /*!< PLLI2S clock used as SAI2 clock source */
383 #define LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_1 >> 16)) /*!< PLL clock used as SAI2 clock source */
384 #define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC >> 16)) /*!< PLL Main clock used as SAI2 clock source */
385 #endif /* RCC_DCKCFGR_SAI2SRC */
386 #if defined(RCC_DCKCFGR_SAI1ASRC)
387 #if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)
388 #define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block A clock source */
389 #define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< External pin used as SAI1 block A clock source */
390 #define LL_RCC_SAI1_A_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< PLL clock used as SAI1 block A clock source */
391 #define LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC >> 16)) /*!< PLL Main clock used as SAI1 block A clock source */
392 #else
393 #define LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block A clock source */
394 #define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block A clock source */
395 #define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< External pin clock used as SAI1 block A clock source */
396 #endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */
397 #endif /* RCC_DCKCFGR_SAI1ASRC */
398 #if defined(RCC_DCKCFGR_SAI1BSRC)
399 #if defined(RCC_SAI1B_PLLSOURCE_SUPPORT)
400 #define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block B clock source */
401 #define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< External pin used as SAI1 block B clock source */
402 #define LL_RCC_SAI1_B_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< PLL clock used as SAI1 block B clock source */
403 #define LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC >> 16)) /*!< PLL Main clock used as SAI1 block B clock source */
404 #else
405 #define LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block B clock source */
406 #define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block B clock source */
407 #define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< External pin clock used as SAI1 block B clock source */
408 #endif /* RCC_SAI1B_PLLSOURCE_SUPPORT */
409 #endif /* RCC_DCKCFGR_SAI1BSRC */
410 /**
411 * @}
412 */
413 #endif /* SAI1 */
414
415 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
416 /** @defgroup RCC_LL_EC_SDIOx_CLKSOURCE Peripheral SDIO clock source selection
417 * @{
418 */
419 #define LL_RCC_SDIO_CLKSOURCE_PLL48CLK 0x00000000U /*!< PLL 48M domain clock used as SDIO clock */
420 #if defined(RCC_DCKCFGR_SDIOSEL)
421 #define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR_SDIOSEL /*!< System clock clock used as SDIO clock */
422 #else
423 #define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDIOSEL /*!< System clock clock used as SDIO clock */
424 #endif /* RCC_DCKCFGR_SDIOSEL */
425 /**
426 * @}
427 */
428 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
429
430 #if defined(DSI)
431 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
432 * @{
433 */
434 #define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */
435 #define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR_DSISEL /*!< PLL clock used as DSI byte lane clock source */
436 /**
437 * @}
438 */
439 #endif /* DSI */
440
441 #if defined(CEC)
442 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
443 * @{
444 */
445 #define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U /*!< HSI oscillator clock divided by 488 used as CEC clock */
446 #define LL_RCC_CEC_CLKSOURCE_LSE RCC_DCKCFGR2_CECSEL /*!< LSE oscillator clock used as CEC clock */
447 /**
448 * @}
449 */
450 #endif /* CEC */
451
452 /** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection
453 * @{
454 */
455 #if defined(RCC_CFGR_I2SSRC)
456 #define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock used as I2S1 clock */
457 #define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock used as I2S1 clock */
458 #endif /* RCC_CFGR_I2SSRC */
459 #if defined(RCC_DCKCFGR_I2SSRC)
460 #define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2SSRC | 0x00000000U) /*!< PLL clock used as I2S1 clock source */
461 #define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_0 >> 16)) /*!< External pin used as I2S1 clock source */
462 #define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_1 >> 16)) /*!< PLL Main clock used as I2S1 clock source */
463 #endif /* RCC_DCKCFGR_I2SSRC */
464 #if defined(RCC_DCKCFGR_I2S1SRC)
465 #define LL_RCC_I2S1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S1SRC | 0x00000000U) /*!< PLLI2S clock used as I2S1 clock source */
466 #define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_0 >> 16)) /*!< External pin used as I2S1 clock source */
467 #define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_1 >> 16)) /*!< PLL clock used as I2S1 clock source */
468 #define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC >> 16)) /*!< PLL Main clock used as I2S1 clock source */
469 #endif /* RCC_DCKCFGR_I2S1SRC */
470 #if defined(RCC_DCKCFGR_I2S2SRC)
471 #define LL_RCC_I2S2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S2SRC | 0x00000000U) /*!< PLLI2S clock used as I2S2 clock source */
472 #define LL_RCC_I2S2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_0 >> 16)) /*!< External pin used as I2S2 clock source */
473 #define LL_RCC_I2S2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_1 >> 16)) /*!< PLL clock used as I2S2 clock source */
474 #define LL_RCC_I2S2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC >> 16)) /*!< PLL Main clock used as I2S2 clock source */
475 #endif /* RCC_DCKCFGR_I2S2SRC */
476 /**
477 * @}
478 */
479
480 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
481 /** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection
482 * @{
483 */
484 #if defined(RCC_DCKCFGR_CK48MSEL)
485 #define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */
486 #define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */
487 #endif /* RCC_DCKCFGR_CK48MSEL */
488 #if defined(RCC_DCKCFGR2_CK48MSEL)
489 #define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */
490 #if defined(RCC_PLLSAI_SUPPORT)
491 #define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */
492 #endif /* RCC_PLLSAI_SUPPORT */
493 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
494 #define LL_RCC_CK48M_CLKSOURCE_PLLI2S RCC_DCKCFGR2_CK48MSEL /*!< PLLI2S oscillator clock used as 48Mhz domain clock */
495 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
496 #endif /* RCC_DCKCFGR2_CK48MSEL */
497 /**
498 * @}
499 */
500
501 #if defined(RNG)
502 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
503 * @{
504 */
505 #define LL_RCC_RNG_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as RNG clock source */
506 #if defined(RCC_PLLSAI_SUPPORT)
507 #define LL_RCC_RNG_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as RNG clock source */
508 #endif /* RCC_PLLSAI_SUPPORT */
509 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
510 #define LL_RCC_RNG_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as RNG clock source */
511 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
512 /**
513 * @}
514 */
515 #endif /* RNG */
516
517 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
518 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
519 * @{
520 */
521 #define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as USB clock source */
522 #if defined(RCC_PLLSAI_SUPPORT)
523 #define LL_RCC_USB_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as USB clock source */
524 #endif /* RCC_PLLSAI_SUPPORT */
525 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
526 #define LL_RCC_USB_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as USB clock source */
527 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
528 /**
529 * @}
530 */
531 #endif /* USB_OTG_FS || USB_OTG_HS */
532
533 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
534
535 #if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)
536 /** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection
537 * @{
538 */
539 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM1 Audio clock source */
540 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | (RCC_DCKCFGR_CKDFSDM1ASEL << 16)) /*!< I2S2 clock used as DFSDM1 Audio clock source */
541 #if defined(DFSDM2_Channel0)
542 #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM2 Audio clock source */
543 #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | (RCC_DCKCFGR_CKDFSDM2ASEL << 16)) /*!< I2S2 clock used as DFSDM2 Audio clock source */
544 #endif /* DFSDM2_Channel0 */
545 /**
546 * @}
547 */
548
549 /** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection
550 * @{
551 */
552 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM1 clock */
553 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM1 clock */
554 #if defined(DFSDM2_Channel0)
555 #define LL_RCC_DFSDM2_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM2 clock */
556 #define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM2 clock */
557 #endif /* DFSDM2_Channel0 */
558 /**
559 * @}
560 */
561 #endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */
562
563 #if defined(FMPI2C1)
564 /** @defgroup RCC_LL_EC_FMPI2C1 Peripheral FMPI2C get clock source
565 * @{
566 */
567 #define LL_RCC_FMPI2C1_CLKSOURCE RCC_DCKCFGR2_FMPI2C1SEL /*!< FMPI2C1 Clock source selection */
568 /**
569 * @}
570 */
571 #endif /* FMPI2C1 */
572
573 #if defined(SPDIFRX)
574 /** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE Peripheral SPDIFRX clock source selection
575 * @{
576 */
577 #define LL_RCC_SPDIFRX1_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as SPDIFRX clock source */
578 #define LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S RCC_DCKCFGR2_SPDIFRXSEL /*!< PLLI2S clock used as SPDIFRX clock source */
579 /**
580 * @}
581 */
582 #endif /* SPDIFRX */
583
584 #if defined(LPTIM1)
585 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
586 * @{
587 */
588 #define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */
589 /**
590 * @}
591 */
592 #endif /* LPTIM1 */
593
594 #if defined(SAI1)
595 /** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source
596 * @{
597 */
598 #if defined(RCC_DCKCFGR_SAI1ASRC)
599 #define LL_RCC_SAI1_A_CLKSOURCE RCC_DCKCFGR_SAI1ASRC /*!< SAI1 block A Clock source selection */
600 #endif /* RCC_DCKCFGR_SAI1ASRC */
601 #if defined(RCC_DCKCFGR_SAI1BSRC)
602 #define LL_RCC_SAI1_B_CLKSOURCE RCC_DCKCFGR_SAI1BSRC /*!< SAI1 block B Clock source selection */
603 #endif /* RCC_DCKCFGR_SAI1BSRC */
604 #if defined(RCC_DCKCFGR_SAI1SRC)
605 #define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR_SAI1SRC /*!< SAI1 Clock source selection */
606 #endif /* RCC_DCKCFGR_SAI1SRC */
607 #if defined(RCC_DCKCFGR_SAI2SRC)
608 #define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR_SAI2SRC /*!< SAI2 Clock source selection */
609 #endif /* RCC_DCKCFGR_SAI2SRC */
610 /**
611 * @}
612 */
613 #endif /* SAI1 */
614
615 #if defined(SDIO)
616 /** @defgroup RCC_LL_EC_SDIOx Peripheral SDIO get clock source
617 * @{
618 */
619 #if defined(RCC_DCKCFGR_SDIOSEL)
620 #define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR_SDIOSEL /*!< SDIO Clock source selection */
621 #elif defined(RCC_DCKCFGR2_SDIOSEL)
622 #define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR2_SDIOSEL /*!< SDIO Clock source selection */
623 #else
624 #define LL_RCC_SDIO_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< SDIO Clock source selection */
625 #endif
626 /**
627 * @}
628 */
629 #endif /* SDIO */
630
631 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
632 /** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source
633 * @{
634 */
635 #if defined(RCC_DCKCFGR_CK48MSEL)
636 #define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR_CK48MSEL /*!< CK48M Domain clock source selection */
637 #endif /* RCC_DCKCFGR_CK48MSEL */
638 #if defined(RCC_DCKCFGR2_CK48MSEL)
639 #define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */
640 #endif /* RCC_DCKCFGR_CK48MSEL */
641 /**
642 * @}
643 */
644 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
645
646 #if defined(RNG)
647 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
648 * @{
649 */
650 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
651 #define LL_RCC_RNG_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< RNG Clock source selection */
652 #else
653 #define LL_RCC_RNG_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< RNG Clock source selection */
654 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
655 /**
656 * @}
657 */
658 #endif /* RNG */
659
660 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
661 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
662 * @{
663 */
664 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
665 #define LL_RCC_USB_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< USB Clock source selection */
666 #else
667 #define LL_RCC_USB_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< USB Clock source selection */
668 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
669 /**
670 * @}
671 */
672 #endif /* USB_OTG_FS || USB_OTG_HS */
673
674 #if defined(CEC)
675 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
676 * @{
677 */
678 #define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */
679 /**
680 * @}
681 */
682 #endif /* CEC */
683
684 /** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
685 * @{
686 */
687 #if defined(RCC_CFGR_I2SSRC)
688 #define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S1 Clock source selection */
689 #endif /* RCC_CFGR_I2SSRC */
690 #if defined(RCC_DCKCFGR_I2SSRC)
691 #define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2SSRC /*!< I2S1 Clock source selection */
692 #endif /* RCC_DCKCFGR_I2SSRC */
693 #if defined(RCC_DCKCFGR_I2S1SRC)
694 #define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2S1SRC /*!< I2S1 Clock source selection */
695 #endif /* RCC_DCKCFGR_I2S1SRC */
696 #if defined(RCC_DCKCFGR_I2S2SRC)
697 #define LL_RCC_I2S2_CLKSOURCE RCC_DCKCFGR_I2S2SRC /*!< I2S2 Clock source selection */
698 #endif /* RCC_DCKCFGR_I2S2SRC */
699 /**
700 * @}
701 */
702
703 #if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)
704 /** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source
705 * @{
706 */
707 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM1ASEL /*!< DFSDM1 Audio Clock source selection */
708 #if defined(DFSDM2_Channel0)
709 #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM2ASEL /*!< DFSDM2 Audio Clock source selection */
710 #endif /* DFSDM2_Channel0 */
711 /**
712 * @}
713 */
714
715 /** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source
716 * @{
717 */
718 #define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM1 Clock source selection */
719 #if defined(DFSDM2_Channel0)
720 #define LL_RCC_DFSDM2_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM2 Clock source selection */
721 #endif /* DFSDM2_Channel0 */
722 /**
723 * @}
724 */
725 #endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */
726
727 #if defined(SPDIFRX)
728 /** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source
729 * @{
730 */
731 #define LL_RCC_SPDIFRX1_CLKSOURCE RCC_DCKCFGR2_SPDIFRXSEL /*!< SPDIFRX Clock source selection */
732 /**
733 * @}
734 */
735 #endif /* SPDIFRX */
736
737 #if defined(DSI)
738 /** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
739 * @{
740 */
741 #define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR_DSISEL /*!< DSI Clock source selection */
742 /**
743 * @}
744 */
745 #endif /* DSI */
746
747 #if defined(LTDC)
748 /** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
749 * @{
750 */
751 #define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR_PLLSAIDIVR /*!< LTDC Clock source selection */
752 /**
753 * @}
754 */
755 #endif /* LTDC */
756
757
758 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
759 * @{
760 */
761 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
762 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
763 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
764 #define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */
765 /**
766 * @}
767 */
768
769 #if defined(RCC_DCKCFGR_TIMPRE)
770 /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection
771 * @{
772 */
773 #define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /*!< Timers clock to twice PCLK */
774 #define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR_TIMPRE /*!< Timers clock to four time PCLK */
775 /**
776 * @}
777 */
778 #endif /* RCC_DCKCFGR_TIMPRE */
779
780 /** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source
781 * @{
782 */
783 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */
784 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
785 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
786 #define LL_RCC_PLLI2SSOURCE_PIN (RCC_PLLI2SCFGR_PLLI2SSRC | 0x80U) /*!< I2S External pin input clock selected as PLLI2S entry clock source */
787 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
788 /**
789 * @}
790 */
791
792 /** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor
793 * @{
794 */
795 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */
796 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */
797 #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */
798 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */
799 #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */
800 #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */
801 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */
802 #define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */
803 #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */
804 #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */
805 #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */
806 #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */
807 #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */
808 #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */
809 #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */
810 #define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */
811 #define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */
812 #define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */
813 #define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */
814 #define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */
815 #define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */
816 #define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */
817 #define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */
818 #define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */
819 #define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */
820 #define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */
821 #define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */
822 #define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */
823 #define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */
824 #define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */
825 #define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */
826 #define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */
827 #define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */
828 #define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */
829 #define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */
830 #define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */
831 #define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */
832 #define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */
833 #define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */
834 #define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */
835 #define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */
836 #define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */
837 #define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */
838 #define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */
839 #define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */
840 #define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */
841 #define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */
842 #define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */
843 #define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */
844 #define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */
845 #define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */
846 #define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */
847 #define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */
848 #define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */
849 #define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */
850 #define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */
851 #define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */
852 #define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */
853 #define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */
854 #define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */
855 #define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */
856 #define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */
857 /**
858 * @}
859 */
860
861 #if defined(RCC_PLLCFGR_PLLR)
862 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
863 * @{
864 */
865 #define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
866 #define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */
867 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
868 #define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */
869 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
870 #define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */
871 /**
872 * @}
873 */
874 #endif /* RCC_PLLCFGR_PLLR */
875
876 #if defined(RCC_DCKCFGR_PLLDIVR)
877 /** @defgroup RCC_LL_EC_PLLDIVR PLLDIVR division factor (PLLDIVR)
878 * @{
879 */
880 #define LL_RCC_PLLDIVR_DIV_1 (RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 1 */
881 #define LL_RCC_PLLDIVR_DIV_2 (RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 2 */
882 #define LL_RCC_PLLDIVR_DIV_3 (RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 3 */
883 #define LL_RCC_PLLDIVR_DIV_4 (RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 4 */
884 #define LL_RCC_PLLDIVR_DIV_5 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 5 */
885 #define LL_RCC_PLLDIVR_DIV_6 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 6 */
886 #define LL_RCC_PLLDIVR_DIV_7 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 7 */
887 #define LL_RCC_PLLDIVR_DIV_8 (RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 8 */
888 #define LL_RCC_PLLDIVR_DIV_9 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 9 */
889 #define LL_RCC_PLLDIVR_DIV_10 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 10 */
890 #define LL_RCC_PLLDIVR_DIV_11 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 11 */
891 #define LL_RCC_PLLDIVR_DIV_12 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 12 */
892 #define LL_RCC_PLLDIVR_DIV_13 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 13 */
893 #define LL_RCC_PLLDIVR_DIV_14 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 14 */
894 #define LL_RCC_PLLDIVR_DIV_15 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 15 */
895 #define LL_RCC_PLLDIVR_DIV_16 (RCC_DCKCFGR_PLLDIVR_4) /*!< PLL division factor for PLLDIVR output by 16 */
896 #define LL_RCC_PLLDIVR_DIV_17 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 17 */
897 #define LL_RCC_PLLDIVR_DIV_18 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 18 */
898 #define LL_RCC_PLLDIVR_DIV_19 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 19 */
899 #define LL_RCC_PLLDIVR_DIV_20 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 20 */
900 #define LL_RCC_PLLDIVR_DIV_21 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 21 */
901 #define LL_RCC_PLLDIVR_DIV_22 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 22 */
902 #define LL_RCC_PLLDIVR_DIV_23 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 23 */
903 #define LL_RCC_PLLDIVR_DIV_24 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 24 */
904 #define LL_RCC_PLLDIVR_DIV_25 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 25 */
905 #define LL_RCC_PLLDIVR_DIV_26 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 26 */
906 #define LL_RCC_PLLDIVR_DIV_27 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 27 */
907 #define LL_RCC_PLLDIVR_DIV_28 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 28 */
908 #define LL_RCC_PLLDIVR_DIV_29 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 29 */
909 #define LL_RCC_PLLDIVR_DIV_30 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 30 */
910 #define LL_RCC_PLLDIVR_DIV_31 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 31 */
911 /**
912 * @}
913 */
914 #endif /* RCC_DCKCFGR_PLLDIVR */
915
916 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
917 * @{
918 */
919 #define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for PLLP output by 2 */
920 #define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for PLLP output by 4 */
921 #define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for PLLP output by 6 */
922 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 8 */
923 /**
924 * @}
925 */
926
927 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
928 * @{
929 */
930 #define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL division factor for PLLQ output by 2 */
931 #define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */
932 #define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL division factor for PLLQ output by 4 */
933 #define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */
934 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
935 #define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */
936 #define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL division factor for PLLQ output by 8 */
937 #define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */
938 #define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */
939 #define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */
940 #define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */
941 #define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */
942 #define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */
943 #define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */
944 /**
945 * @}
946 */
947
948 /** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection
949 * @{
950 */
951 #define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spectrum selection */
952 #define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */
953 /**
954 * @}
955 */
956
957 #if defined(RCC_PLLI2S_SUPPORT)
958 /** @defgroup RCC_LL_EC_PLLI2SM PLLI2SM division factor (PLLI2SM)
959 * @{
960 */
961 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
962 #define LL_RCC_PLLI2SM_DIV_2 (RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 2 */
963 #define LL_RCC_PLLI2SM_DIV_3 (RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 3 */
964 #define LL_RCC_PLLI2SM_DIV_4 (RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 4 */
965 #define LL_RCC_PLLI2SM_DIV_5 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 5 */
966 #define LL_RCC_PLLI2SM_DIV_6 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 6 */
967 #define LL_RCC_PLLI2SM_DIV_7 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 7 */
968 #define LL_RCC_PLLI2SM_DIV_8 (RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 8 */
969 #define LL_RCC_PLLI2SM_DIV_9 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 9 */
970 #define LL_RCC_PLLI2SM_DIV_10 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 10 */
971 #define LL_RCC_PLLI2SM_DIV_11 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 11 */
972 #define LL_RCC_PLLI2SM_DIV_12 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 12 */
973 #define LL_RCC_PLLI2SM_DIV_13 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 13 */
974 #define LL_RCC_PLLI2SM_DIV_14 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 14 */
975 #define LL_RCC_PLLI2SM_DIV_15 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 15 */
976 #define LL_RCC_PLLI2SM_DIV_16 (RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 16 */
977 #define LL_RCC_PLLI2SM_DIV_17 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 17 */
978 #define LL_RCC_PLLI2SM_DIV_18 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 18 */
979 #define LL_RCC_PLLI2SM_DIV_19 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 19 */
980 #define LL_RCC_PLLI2SM_DIV_20 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 20 */
981 #define LL_RCC_PLLI2SM_DIV_21 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 21 */
982 #define LL_RCC_PLLI2SM_DIV_22 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 22 */
983 #define LL_RCC_PLLI2SM_DIV_23 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 23 */
984 #define LL_RCC_PLLI2SM_DIV_24 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 24 */
985 #define LL_RCC_PLLI2SM_DIV_25 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 25 */
986 #define LL_RCC_PLLI2SM_DIV_26 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 26 */
987 #define LL_RCC_PLLI2SM_DIV_27 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 27 */
988 #define LL_RCC_PLLI2SM_DIV_28 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 28 */
989 #define LL_RCC_PLLI2SM_DIV_29 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 29 */
990 #define LL_RCC_PLLI2SM_DIV_30 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 30 */
991 #define LL_RCC_PLLI2SM_DIV_31 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 31 */
992 #define LL_RCC_PLLI2SM_DIV_32 (RCC_PLLI2SCFGR_PLLI2SM_5) /*!< PLLI2S division factor for PLLI2SM output by 32 */
993 #define LL_RCC_PLLI2SM_DIV_33 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 33 */
994 #define LL_RCC_PLLI2SM_DIV_34 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 34 */
995 #define LL_RCC_PLLI2SM_DIV_35 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 35 */
996 #define LL_RCC_PLLI2SM_DIV_36 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 36 */
997 #define LL_RCC_PLLI2SM_DIV_37 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 37 */
998 #define LL_RCC_PLLI2SM_DIV_38 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 38 */
999 #define LL_RCC_PLLI2SM_DIV_39 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 39 */
1000 #define LL_RCC_PLLI2SM_DIV_40 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 40 */
1001 #define LL_RCC_PLLI2SM_DIV_41 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 41 */
1002 #define LL_RCC_PLLI2SM_DIV_42 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 42 */
1003 #define LL_RCC_PLLI2SM_DIV_43 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 43 */
1004 #define LL_RCC_PLLI2SM_DIV_44 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 44 */
1005 #define LL_RCC_PLLI2SM_DIV_45 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 45 */
1006 #define LL_RCC_PLLI2SM_DIV_46 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 46 */
1007 #define LL_RCC_PLLI2SM_DIV_47 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 47 */
1008 #define LL_RCC_PLLI2SM_DIV_48 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 48 */
1009 #define LL_RCC_PLLI2SM_DIV_49 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 49 */
1010 #define LL_RCC_PLLI2SM_DIV_50 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 50 */
1011 #define LL_RCC_PLLI2SM_DIV_51 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 51 */
1012 #define LL_RCC_PLLI2SM_DIV_52 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 52 */
1013 #define LL_RCC_PLLI2SM_DIV_53 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 53 */
1014 #define LL_RCC_PLLI2SM_DIV_54 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 54 */
1015 #define LL_RCC_PLLI2SM_DIV_55 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 55 */
1016 #define LL_RCC_PLLI2SM_DIV_56 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 56 */
1017 #define LL_RCC_PLLI2SM_DIV_57 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 57 */
1018 #define LL_RCC_PLLI2SM_DIV_58 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 58 */
1019 #define LL_RCC_PLLI2SM_DIV_59 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 59 */
1020 #define LL_RCC_PLLI2SM_DIV_60 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 60 */
1021 #define LL_RCC_PLLI2SM_DIV_61 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 61 */
1022 #define LL_RCC_PLLI2SM_DIV_62 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 62 */
1023 #define LL_RCC_PLLI2SM_DIV_63 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 63 */
1024 #else
1025 #define LL_RCC_PLLI2SM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLI2S division factor for PLLI2SM output by 2 */
1026 #define LL_RCC_PLLI2SM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLI2S division factor for PLLI2SM output by 3 */
1027 #define LL_RCC_PLLI2SM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLI2S division factor for PLLI2SM output by 4 */
1028 #define LL_RCC_PLLI2SM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLI2S division factor for PLLI2SM output by 5 */
1029 #define LL_RCC_PLLI2SM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLI2S division factor for PLLI2SM output by 6 */
1030 #define LL_RCC_PLLI2SM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLI2S division factor for PLLI2SM output by 7 */
1031 #define LL_RCC_PLLI2SM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLI2S division factor for PLLI2SM output by 8 */
1032 #define LL_RCC_PLLI2SM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLI2S division factor for PLLI2SM output by 9 */
1033 #define LL_RCC_PLLI2SM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLI2S division factor for PLLI2SM output by 10 */
1034 #define LL_RCC_PLLI2SM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLI2S division factor for PLLI2SM output by 11 */
1035 #define LL_RCC_PLLI2SM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLI2S division factor for PLLI2SM output by 12 */
1036 #define LL_RCC_PLLI2SM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLI2S division factor for PLLI2SM output by 13 */
1037 #define LL_RCC_PLLI2SM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLI2S division factor for PLLI2SM output by 14 */
1038 #define LL_RCC_PLLI2SM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLI2S division factor for PLLI2SM output by 15 */
1039 #define LL_RCC_PLLI2SM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLI2S division factor for PLLI2SM output by 16 */
1040 #define LL_RCC_PLLI2SM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLI2S division factor for PLLI2SM output by 17 */
1041 #define LL_RCC_PLLI2SM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLI2S division factor for PLLI2SM output by 18 */
1042 #define LL_RCC_PLLI2SM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLI2S division factor for PLLI2SM output by 19 */
1043 #define LL_RCC_PLLI2SM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLI2S division factor for PLLI2SM output by 20 */
1044 #define LL_RCC_PLLI2SM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLI2S division factor for PLLI2SM output by 21 */
1045 #define LL_RCC_PLLI2SM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLI2S division factor for PLLI2SM output by 22 */
1046 #define LL_RCC_PLLI2SM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLI2S division factor for PLLI2SM output by 23 */
1047 #define LL_RCC_PLLI2SM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLI2S division factor for PLLI2SM output by 24 */
1048 #define LL_RCC_PLLI2SM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLI2S division factor for PLLI2SM output by 25 */
1049 #define LL_RCC_PLLI2SM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLI2S division factor for PLLI2SM output by 26 */
1050 #define LL_RCC_PLLI2SM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLI2S division factor for PLLI2SM output by 27 */
1051 #define LL_RCC_PLLI2SM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLI2S division factor for PLLI2SM output by 28 */
1052 #define LL_RCC_PLLI2SM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLI2S division factor for PLLI2SM output by 29 */
1053 #define LL_RCC_PLLI2SM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLI2S division factor for PLLI2SM output by 30 */
1054 #define LL_RCC_PLLI2SM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLI2S division factor for PLLI2SM output by 31 */
1055 #define LL_RCC_PLLI2SM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLI2S division factor for PLLI2SM output by 32 */
1056 #define LL_RCC_PLLI2SM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLI2S division factor for PLLI2SM output by 33 */
1057 #define LL_RCC_PLLI2SM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLI2S division factor for PLLI2SM output by 34 */
1058 #define LL_RCC_PLLI2SM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLI2S division factor for PLLI2SM output by 35 */
1059 #define LL_RCC_PLLI2SM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLI2S division factor for PLLI2SM output by 36 */
1060 #define LL_RCC_PLLI2SM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLI2S division factor for PLLI2SM output by 37 */
1061 #define LL_RCC_PLLI2SM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLI2S division factor for PLLI2SM output by 38 */
1062 #define LL_RCC_PLLI2SM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLI2S division factor for PLLI2SM output by 39 */
1063 #define LL_RCC_PLLI2SM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLI2S division factor for PLLI2SM output by 40 */
1064 #define LL_RCC_PLLI2SM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLI2S division factor for PLLI2SM output by 41 */
1065 #define LL_RCC_PLLI2SM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLI2S division factor for PLLI2SM output by 42 */
1066 #define LL_RCC_PLLI2SM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLI2S division factor for PLLI2SM output by 43 */
1067 #define LL_RCC_PLLI2SM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLI2S division factor for PLLI2SM output by 44 */
1068 #define LL_RCC_PLLI2SM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLI2S division factor for PLLI2SM output by 45 */
1069 #define LL_RCC_PLLI2SM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLI2S division factor for PLLI2SM output by 46 */
1070 #define LL_RCC_PLLI2SM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLI2S division factor for PLLI2SM output by 47 */
1071 #define LL_RCC_PLLI2SM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLI2S division factor for PLLI2SM output by 48 */
1072 #define LL_RCC_PLLI2SM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLI2S division factor for PLLI2SM output by 49 */
1073 #define LL_RCC_PLLI2SM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLI2S division factor for PLLI2SM output by 50 */
1074 #define LL_RCC_PLLI2SM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLI2S division factor for PLLI2SM output by 51 */
1075 #define LL_RCC_PLLI2SM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLI2S division factor for PLLI2SM output by 52 */
1076 #define LL_RCC_PLLI2SM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLI2S division factor for PLLI2SM output by 53 */
1077 #define LL_RCC_PLLI2SM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLI2S division factor for PLLI2SM output by 54 */
1078 #define LL_RCC_PLLI2SM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLI2S division factor for PLLI2SM output by 55 */
1079 #define LL_RCC_PLLI2SM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLI2S division factor for PLLI2SM output by 56 */
1080 #define LL_RCC_PLLI2SM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLI2S division factor for PLLI2SM output by 57 */
1081 #define LL_RCC_PLLI2SM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLI2S division factor for PLLI2SM output by 58 */
1082 #define LL_RCC_PLLI2SM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLI2S division factor for PLLI2SM output by 59 */
1083 #define LL_RCC_PLLI2SM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLI2S division factor for PLLI2SM output by 60 */
1084 #define LL_RCC_PLLI2SM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLI2S division factor for PLLI2SM output by 61 */
1085 #define LL_RCC_PLLI2SM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLI2S division factor for PLLI2SM output by 62 */
1086 #define LL_RCC_PLLI2SM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLI2S division factor for PLLI2SM output by 63 */
1087 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
1088 /**
1089 * @}
1090 */
1091
1092 #if defined(RCC_PLLI2SCFGR_PLLI2SQ)
1093 /** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ)
1094 * @{
1095 */
1096 #define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /*!< PLLI2S division factor for PLLI2SQ output by 2 */
1097 #define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 3 */
1098 #define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /*!< PLLI2S division factor for PLLI2SQ output by 4 */
1099 #define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 5 */
1100 #define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 6 */
1101 #define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 7 */
1102 #define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /*!< PLLI2S division factor for PLLI2SQ output by 8 */
1103 #define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 9 */
1104 #define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 10 */
1105 #define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 11 */
1106 #define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2) /*!< PLLI2S division factor for PLLI2SQ output by 12 */
1107 #define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 13 */
1108 #define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 14 */
1109 #define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 15 */
1110 /**
1111 * @}
1112 */
1113 #endif /* RCC_PLLI2SCFGR_PLLI2SQ */
1114
1115 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
1116 /** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ)
1117 * @{
1118 */
1119 #define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */
1120 #define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR_PLLI2SDIVQ_0 /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */
1121 #define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR_PLLI2SDIVQ_1 /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */
1122 #define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */
1123 #define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR_PLLI2SDIVQ_2 /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */
1124 #define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */
1125 #define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */
1126 #define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */
1127 #define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR_PLLI2SDIVQ_3 /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */
1128 #define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */
1129 #define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */
1130 #define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */
1131 #define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */
1132 #define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */
1133 #define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */
1134 #define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */
1135 #define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR_PLLI2SDIVQ_4 /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */
1136 #define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */
1137 #define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */
1138 #define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */
1139 #define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */
1140 #define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */
1141 #define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */
1142 #define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */
1143 #define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3) /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */
1144 #define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */
1145 #define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */
1146 #define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */
1147 #define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */
1148 #define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */
1149 #define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */
1150 #define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */
1151 /**
1152 * @}
1153 */
1154 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
1155
1156 #if defined(RCC_DCKCFGR_PLLI2SDIVR)
1157 /** @defgroup RCC_LL_EC_PLLI2SDIVR PLLI2SDIVR division factor (PLLI2SDIVR)
1158 * @{
1159 */
1160 #define LL_RCC_PLLI2SDIVR_DIV_1 (RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 1 */
1161 #define LL_RCC_PLLI2SDIVR_DIV_2 (RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 2 */
1162 #define LL_RCC_PLLI2SDIVR_DIV_3 (RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 3 */
1163 #define LL_RCC_PLLI2SDIVR_DIV_4 (RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 4 */
1164 #define LL_RCC_PLLI2SDIVR_DIV_5 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 5 */
1165 #define LL_RCC_PLLI2SDIVR_DIV_6 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 6 */
1166 #define LL_RCC_PLLI2SDIVR_DIV_7 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 7 */
1167 #define LL_RCC_PLLI2SDIVR_DIV_8 (RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 8 */
1168 #define LL_RCC_PLLI2SDIVR_DIV_9 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 9 */
1169 #define LL_RCC_PLLI2SDIVR_DIV_10 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 10 */
1170 #define LL_RCC_PLLI2SDIVR_DIV_11 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 11 */
1171 #define LL_RCC_PLLI2SDIVR_DIV_12 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 12 */
1172 #define LL_RCC_PLLI2SDIVR_DIV_13 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 13 */
1173 #define LL_RCC_PLLI2SDIVR_DIV_14 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 14 */
1174 #define LL_RCC_PLLI2SDIVR_DIV_15 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 15 */
1175 #define LL_RCC_PLLI2SDIVR_DIV_16 (RCC_DCKCFGR_PLLI2SDIVR_4) /*!< PLLI2S division factor for PLLI2SDIVR output by 16 */
1176 #define LL_RCC_PLLI2SDIVR_DIV_17 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 17 */
1177 #define LL_RCC_PLLI2SDIVR_DIV_18 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 18 */
1178 #define LL_RCC_PLLI2SDIVR_DIV_19 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 19 */
1179 #define LL_RCC_PLLI2SDIVR_DIV_20 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 20 */
1180 #define LL_RCC_PLLI2SDIVR_DIV_21 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 21 */
1181 #define LL_RCC_PLLI2SDIVR_DIV_22 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 22 */
1182 #define LL_RCC_PLLI2SDIVR_DIV_23 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 23 */
1183 #define LL_RCC_PLLI2SDIVR_DIV_24 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 24 */
1184 #define LL_RCC_PLLI2SDIVR_DIV_25 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 25 */
1185 #define LL_RCC_PLLI2SDIVR_DIV_26 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 26 */
1186 #define LL_RCC_PLLI2SDIVR_DIV_27 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 27 */
1187 #define LL_RCC_PLLI2SDIVR_DIV_28 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 28 */
1188 #define LL_RCC_PLLI2SDIVR_DIV_29 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 29 */
1189 #define LL_RCC_PLLI2SDIVR_DIV_30 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 30 */
1190 #define LL_RCC_PLLI2SDIVR_DIV_31 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 31 */
1191 /**
1192 * @}
1193 */
1194 #endif /* RCC_DCKCFGR_PLLI2SDIVR */
1195
1196 /** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR)
1197 * @{
1198 */
1199 #define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /*!< PLLI2S division factor for PLLI2SR output by 2 */
1200 #define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 3 */
1201 #define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /*!< PLLI2S division factor for PLLI2SR output by 4 */
1202 #define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 5 */
1203 #define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) /*!< PLLI2S division factor for PLLI2SR output by 6 */
1204 #define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 7 */
1205 /**
1206 * @}
1207 */
1208
1209 #if defined(RCC_PLLI2SCFGR_PLLI2SP)
1210 /** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP)
1211 * @{
1212 */
1213 #define LL_RCC_PLLI2SP_DIV_2 0x00000000U /*!< PLLI2S division factor for PLLI2SP output by 2 */
1214 #define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /*!< PLLI2S division factor for PLLI2SP output by 4 */
1215 #define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /*!< PLLI2S division factor for PLLI2SP output by 6 */
1216 #define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0) /*!< PLLI2S division factor for PLLI2SP output by 8 */
1217 /**
1218 * @}
1219 */
1220 #endif /* RCC_PLLI2SCFGR_PLLI2SP */
1221 #endif /* RCC_PLLI2S_SUPPORT */
1222
1223 #if defined(RCC_PLLSAI_SUPPORT)
1224 /** @defgroup RCC_LL_EC_PLLSAIM PLLSAIM division factor (PLLSAIM or PLLM)
1225 * @{
1226 */
1227 #if defined(RCC_PLLSAICFGR_PLLSAIM)
1228 #define LL_RCC_PLLSAIM_DIV_2 (RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 2 */
1229 #define LL_RCC_PLLSAIM_DIV_3 (RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 3 */
1230 #define LL_RCC_PLLSAIM_DIV_4 (RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 4 */
1231 #define LL_RCC_PLLSAIM_DIV_5 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 5 */
1232 #define LL_RCC_PLLSAIM_DIV_6 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 6 */
1233 #define LL_RCC_PLLSAIM_DIV_7 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 7 */
1234 #define LL_RCC_PLLSAIM_DIV_8 (RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 8 */
1235 #define LL_RCC_PLLSAIM_DIV_9 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 9 */
1236 #define LL_RCC_PLLSAIM_DIV_10 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 10 */
1237 #define LL_RCC_PLLSAIM_DIV_11 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 11 */
1238 #define LL_RCC_PLLSAIM_DIV_12 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 12 */
1239 #define LL_RCC_PLLSAIM_DIV_13 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 13 */
1240 #define LL_RCC_PLLSAIM_DIV_14 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 14 */
1241 #define LL_RCC_PLLSAIM_DIV_15 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 15 */
1242 #define LL_RCC_PLLSAIM_DIV_16 (RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 16 */
1243 #define LL_RCC_PLLSAIM_DIV_17 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 17 */
1244 #define LL_RCC_PLLSAIM_DIV_18 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 18 */
1245 #define LL_RCC_PLLSAIM_DIV_19 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 19 */
1246 #define LL_RCC_PLLSAIM_DIV_20 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 20 */
1247 #define LL_RCC_PLLSAIM_DIV_21 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 21 */
1248 #define LL_RCC_PLLSAIM_DIV_22 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 22 */
1249 #define LL_RCC_PLLSAIM_DIV_23 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 23 */
1250 #define LL_RCC_PLLSAIM_DIV_24 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 24 */
1251 #define LL_RCC_PLLSAIM_DIV_25 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 25 */
1252 #define LL_RCC_PLLSAIM_DIV_26 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 26 */
1253 #define LL_RCC_PLLSAIM_DIV_27 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 27 */
1254 #define LL_RCC_PLLSAIM_DIV_28 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 28 */
1255 #define LL_RCC_PLLSAIM_DIV_29 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 29 */
1256 #define LL_RCC_PLLSAIM_DIV_30 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 30 */
1257 #define LL_RCC_PLLSAIM_DIV_31 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 31 */
1258 #define LL_RCC_PLLSAIM_DIV_32 (RCC_PLLSAICFGR_PLLSAIM_5) /*!< PLLSAI division factor for PLLSAIM output by 32 */
1259 #define LL_RCC_PLLSAIM_DIV_33 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 33 */
1260 #define LL_RCC_PLLSAIM_DIV_34 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 34 */
1261 #define LL_RCC_PLLSAIM_DIV_35 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 35 */
1262 #define LL_RCC_PLLSAIM_DIV_36 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 36 */
1263 #define LL_RCC_PLLSAIM_DIV_37 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 37 */
1264 #define LL_RCC_PLLSAIM_DIV_38 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 38 */
1265 #define LL_RCC_PLLSAIM_DIV_39 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 39 */
1266 #define LL_RCC_PLLSAIM_DIV_40 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 40 */
1267 #define LL_RCC_PLLSAIM_DIV_41 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 41 */
1268 #define LL_RCC_PLLSAIM_DIV_42 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 42 */
1269 #define LL_RCC_PLLSAIM_DIV_43 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 43 */
1270 #define LL_RCC_PLLSAIM_DIV_44 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 44 */
1271 #define LL_RCC_PLLSAIM_DIV_45 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 45 */
1272 #define LL_RCC_PLLSAIM_DIV_46 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 46 */
1273 #define LL_RCC_PLLSAIM_DIV_47 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 47 */
1274 #define LL_RCC_PLLSAIM_DIV_48 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 48 */
1275 #define LL_RCC_PLLSAIM_DIV_49 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 49 */
1276 #define LL_RCC_PLLSAIM_DIV_50 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 50 */
1277 #define LL_RCC_PLLSAIM_DIV_51 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 51 */
1278 #define LL_RCC_PLLSAIM_DIV_52 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 52 */
1279 #define LL_RCC_PLLSAIM_DIV_53 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 53 */
1280 #define LL_RCC_PLLSAIM_DIV_54 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 54 */
1281 #define LL_RCC_PLLSAIM_DIV_55 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 55 */
1282 #define LL_RCC_PLLSAIM_DIV_56 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 56 */
1283 #define LL_RCC_PLLSAIM_DIV_57 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 57 */
1284 #define LL_RCC_PLLSAIM_DIV_58 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 58 */
1285 #define LL_RCC_PLLSAIM_DIV_59 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 59 */
1286 #define LL_RCC_PLLSAIM_DIV_60 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 60 */
1287 #define LL_RCC_PLLSAIM_DIV_61 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 61 */
1288 #define LL_RCC_PLLSAIM_DIV_62 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 62 */
1289 #define LL_RCC_PLLSAIM_DIV_63 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 63 */
1290 #else
1291 #define LL_RCC_PLLSAIM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLSAI division factor for PLLSAIM output by 2 */
1292 #define LL_RCC_PLLSAIM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLSAI division factor for PLLSAIM output by 3 */
1293 #define LL_RCC_PLLSAIM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLSAI division factor for PLLSAIM output by 4 */
1294 #define LL_RCC_PLLSAIM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLSAI division factor for PLLSAIM output by 5 */
1295 #define LL_RCC_PLLSAIM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLSAI division factor for PLLSAIM output by 6 */
1296 #define LL_RCC_PLLSAIM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLSAI division factor for PLLSAIM output by 7 */
1297 #define LL_RCC_PLLSAIM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLSAI division factor for PLLSAIM output by 8 */
1298 #define LL_RCC_PLLSAIM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLSAI division factor for PLLSAIM output by 9 */
1299 #define LL_RCC_PLLSAIM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLSAI division factor for PLLSAIM output by 10 */
1300 #define LL_RCC_PLLSAIM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLSAI division factor for PLLSAIM output by 11 */
1301 #define LL_RCC_PLLSAIM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLSAI division factor for PLLSAIM output by 12 */
1302 #define LL_RCC_PLLSAIM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLSAI division factor for PLLSAIM output by 13 */
1303 #define LL_RCC_PLLSAIM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLSAI division factor for PLLSAIM output by 14 */
1304 #define LL_RCC_PLLSAIM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLSAI division factor for PLLSAIM output by 15 */
1305 #define LL_RCC_PLLSAIM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLSAI division factor for PLLSAIM output by 16 */
1306 #define LL_RCC_PLLSAIM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLSAI division factor for PLLSAIM output by 17 */
1307 #define LL_RCC_PLLSAIM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLSAI division factor for PLLSAIM output by 18 */
1308 #define LL_RCC_PLLSAIM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLSAI division factor for PLLSAIM output by 19 */
1309 #define LL_RCC_PLLSAIM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLSAI division factor for PLLSAIM output by 20 */
1310 #define LL_RCC_PLLSAIM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLSAI division factor for PLLSAIM output by 21 */
1311 #define LL_RCC_PLLSAIM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLSAI division factor for PLLSAIM output by 22 */
1312 #define LL_RCC_PLLSAIM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLSAI division factor for PLLSAIM output by 23 */
1313 #define LL_RCC_PLLSAIM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLSAI division factor for PLLSAIM output by 24 */
1314 #define LL_RCC_PLLSAIM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLSAI division factor for PLLSAIM output by 25 */
1315 #define LL_RCC_PLLSAIM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLSAI division factor for PLLSAIM output by 26 */
1316 #define LL_RCC_PLLSAIM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLSAI division factor for PLLSAIM output by 27 */
1317 #define LL_RCC_PLLSAIM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLSAI division factor for PLLSAIM output by 28 */
1318 #define LL_RCC_PLLSAIM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLSAI division factor for PLLSAIM output by 29 */
1319 #define LL_RCC_PLLSAIM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLSAI division factor for PLLSAIM output by 30 */
1320 #define LL_RCC_PLLSAIM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLSAI division factor for PLLSAIM output by 31 */
1321 #define LL_RCC_PLLSAIM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLSAI division factor for PLLSAIM output by 32 */
1322 #define LL_RCC_PLLSAIM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLSAI division factor for PLLSAIM output by 33 */
1323 #define LL_RCC_PLLSAIM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLSAI division factor for PLLSAIM output by 34 */
1324 #define LL_RCC_PLLSAIM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLSAI division factor for PLLSAIM output by 35 */
1325 #define LL_RCC_PLLSAIM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLSAI division factor for PLLSAIM output by 36 */
1326 #define LL_RCC_PLLSAIM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLSAI division factor for PLLSAIM output by 37 */
1327 #define LL_RCC_PLLSAIM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLSAI division factor for PLLSAIM output by 38 */
1328 #define LL_RCC_PLLSAIM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLSAI division factor for PLLSAIM output by 39 */
1329 #define LL_RCC_PLLSAIM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLSAI division factor for PLLSAIM output by 40 */
1330 #define LL_RCC_PLLSAIM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLSAI division factor for PLLSAIM output by 41 */
1331 #define LL_RCC_PLLSAIM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLSAI division factor for PLLSAIM output by 42 */
1332 #define LL_RCC_PLLSAIM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLSAI division factor for PLLSAIM output by 43 */
1333 #define LL_RCC_PLLSAIM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLSAI division factor for PLLSAIM output by 44 */
1334 #define LL_RCC_PLLSAIM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLSAI division factor for PLLSAIM output by 45 */
1335 #define LL_RCC_PLLSAIM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLSAI division factor for PLLSAIM output by 46 */
1336 #define LL_RCC_PLLSAIM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLSAI division factor for PLLSAIM output by 47 */
1337 #define LL_RCC_PLLSAIM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLSAI division factor for PLLSAIM output by 48 */
1338 #define LL_RCC_PLLSAIM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLSAI division factor for PLLSAIM output by 49 */
1339 #define LL_RCC_PLLSAIM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLSAI division factor for PLLSAIM output by 50 */
1340 #define LL_RCC_PLLSAIM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLSAI division factor for PLLSAIM output by 51 */
1341 #define LL_RCC_PLLSAIM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLSAI division factor for PLLSAIM output by 52 */
1342 #define LL_RCC_PLLSAIM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLSAI division factor for PLLSAIM output by 53 */
1343 #define LL_RCC_PLLSAIM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLSAI division factor for PLLSAIM output by 54 */
1344 #define LL_RCC_PLLSAIM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLSAI division factor for PLLSAIM output by 55 */
1345 #define LL_RCC_PLLSAIM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLSAI division factor for PLLSAIM output by 56 */
1346 #define LL_RCC_PLLSAIM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLSAI division factor for PLLSAIM output by 57 */
1347 #define LL_RCC_PLLSAIM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLSAI division factor for PLLSAIM output by 58 */
1348 #define LL_RCC_PLLSAIM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLSAI division factor for PLLSAIM output by 59 */
1349 #define LL_RCC_PLLSAIM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLSAI division factor for PLLSAIM output by 60 */
1350 #define LL_RCC_PLLSAIM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLSAI division factor for PLLSAIM output by 61 */
1351 #define LL_RCC_PLLSAIM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLSAI division factor for PLLSAIM output by 62 */
1352 #define LL_RCC_PLLSAIM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLSAI division factor for PLLSAIM output by 63 */
1353 #endif /* RCC_PLLSAICFGR_PLLSAIM */
1354 /**
1355 * @}
1356 */
1357
1358 /** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ)
1359 * @{
1360 */
1361 #define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /*!< PLLSAI division factor for PLLSAIQ output by 2 */
1362 #define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 3 */
1363 #define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /*!< PLLSAI division factor for PLLSAIQ output by 4 */
1364 #define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 5 */
1365 #define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 6 */
1366 #define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 7 */
1367 #define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /*!< PLLSAI division factor for PLLSAIQ output by 8 */
1368 #define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 9 */
1369 #define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 10 */
1370 #define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 11 */
1371 #define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2) /*!< PLLSAI division factor for PLLSAIQ output by 12 */
1372 #define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 13 */
1373 #define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 14 */
1374 #define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 15 */
1375 /**
1376 * @}
1377 */
1378
1379 #if defined(RCC_DCKCFGR_PLLSAIDIVQ)
1380 /** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ)
1381 * @{
1382 */
1383 #define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */
1384 #define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR_PLLSAIDIVQ_0 /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */
1385 #define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR_PLLSAIDIVQ_1 /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */
1386 #define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */
1387 #define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR_PLLSAIDIVQ_2 /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */
1388 #define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */
1389 #define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */
1390 #define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */
1391 #define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR_PLLSAIDIVQ_3 /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */
1392 #define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */
1393 #define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */
1394 #define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */
1395 #define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */
1396 #define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */
1397 #define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */
1398 #define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */
1399 #define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR_PLLSAIDIVQ_4 /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */
1400 #define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */
1401 #define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */
1402 #define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */
1403 #define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */
1404 #define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */
1405 #define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */
1406 #define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */
1407 #define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3) /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */
1408 #define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */
1409 #define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */
1410 #define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */
1411 #define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */
1412 #define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */
1413 #define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */
1414 #define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */
1415 /**
1416 * @}
1417 */
1418 #endif /* RCC_DCKCFGR_PLLSAIDIVQ */
1419
1420 #if defined(RCC_PLLSAICFGR_PLLSAIR)
1421 /** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR)
1422 * @{
1423 */
1424 #define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /*!< PLLSAI division factor for PLLSAIR output by 2 */
1425 #define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 3 */
1426 #define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /*!< PLLSAI division factor for PLLSAIR output by 4 */
1427 #define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 5 */
1428 #define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1) /*!< PLLSAI division factor for PLLSAIR output by 6 */
1429 #define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 7 */
1430 /**
1431 * @}
1432 */
1433 #endif /* RCC_PLLSAICFGR_PLLSAIR */
1434
1435 #if defined(RCC_DCKCFGR_PLLSAIDIVR)
1436 /** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR)
1437 * @{
1438 */
1439 #define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */
1440 #define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR_PLLSAIDIVR_0 /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */
1441 #define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR_PLLSAIDIVR_1 /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */
1442 #define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR_PLLSAIDIVR_1 | RCC_DCKCFGR_PLLSAIDIVR_0) /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */
1443 /**
1444 * @}
1445 */
1446 #endif /* RCC_DCKCFGR_PLLSAIDIVR */
1447
1448 #if defined(RCC_PLLSAICFGR_PLLSAIP)
1449 /** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP)
1450 * @{
1451 */
1452 #define LL_RCC_PLLSAIP_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIP output by 2 */
1453 #define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /*!< PLLSAI division factor for PLLSAIP output by 4 */
1454 #define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /*!< PLLSAI division factor for PLLSAIP output by 6 */
1455 #define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0) /*!< PLLSAI division factor for PLLSAIP output by 8 */
1456 /**
1457 * @}
1458 */
1459 #endif /* RCC_PLLSAICFGR_PLLSAIP */
1460 #endif /* RCC_PLLSAI_SUPPORT */
1461 /**
1462 * @}
1463 */
1464
1465 /* Exported macro ------------------------------------------------------------*/
1466 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
1467 * @{
1468 */
1469
1470 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
1471 * @{
1472 */
1473
1474 /**
1475 * @brief Write a value in RCC register
1476 * @param __REG__ Register to be written
1477 * @param __VALUE__ Value to be written in the register
1478 * @retval None
1479 */
1480 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1481
1482 /**
1483 * @brief Read a value in RCC register
1484 * @param __REG__ Register to be read
1485 * @retval Register value
1486 */
1487 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1488 /**
1489 * @}
1490 */
1491
1492 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
1493 * @{
1494 */
1495
1496 /**
1497 * @brief Helper macro to calculate the PLLCLK frequency on system domain
1498 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1499 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
1500 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1501 * @param __PLLM__ This parameter can be one of the following values:
1502 * @arg @ref LL_RCC_PLLM_DIV_2
1503 * @arg @ref LL_RCC_PLLM_DIV_3
1504 * @arg @ref LL_RCC_PLLM_DIV_4
1505 * @arg @ref LL_RCC_PLLM_DIV_5
1506 * @arg @ref LL_RCC_PLLM_DIV_6
1507 * @arg @ref LL_RCC_PLLM_DIV_7
1508 * @arg @ref LL_RCC_PLLM_DIV_8
1509 * @arg @ref LL_RCC_PLLM_DIV_9
1510 * @arg @ref LL_RCC_PLLM_DIV_10
1511 * @arg @ref LL_RCC_PLLM_DIV_11
1512 * @arg @ref LL_RCC_PLLM_DIV_12
1513 * @arg @ref LL_RCC_PLLM_DIV_13
1514 * @arg @ref LL_RCC_PLLM_DIV_14
1515 * @arg @ref LL_RCC_PLLM_DIV_15
1516 * @arg @ref LL_RCC_PLLM_DIV_16
1517 * @arg @ref LL_RCC_PLLM_DIV_17
1518 * @arg @ref LL_RCC_PLLM_DIV_18
1519 * @arg @ref LL_RCC_PLLM_DIV_19
1520 * @arg @ref LL_RCC_PLLM_DIV_20
1521 * @arg @ref LL_RCC_PLLM_DIV_21
1522 * @arg @ref LL_RCC_PLLM_DIV_22
1523 * @arg @ref LL_RCC_PLLM_DIV_23
1524 * @arg @ref LL_RCC_PLLM_DIV_24
1525 * @arg @ref LL_RCC_PLLM_DIV_25
1526 * @arg @ref LL_RCC_PLLM_DIV_26
1527 * @arg @ref LL_RCC_PLLM_DIV_27
1528 * @arg @ref LL_RCC_PLLM_DIV_28
1529 * @arg @ref LL_RCC_PLLM_DIV_29
1530 * @arg @ref LL_RCC_PLLM_DIV_30
1531 * @arg @ref LL_RCC_PLLM_DIV_31
1532 * @arg @ref LL_RCC_PLLM_DIV_32
1533 * @arg @ref LL_RCC_PLLM_DIV_33
1534 * @arg @ref LL_RCC_PLLM_DIV_34
1535 * @arg @ref LL_RCC_PLLM_DIV_35
1536 * @arg @ref LL_RCC_PLLM_DIV_36
1537 * @arg @ref LL_RCC_PLLM_DIV_37
1538 * @arg @ref LL_RCC_PLLM_DIV_38
1539 * @arg @ref LL_RCC_PLLM_DIV_39
1540 * @arg @ref LL_RCC_PLLM_DIV_40
1541 * @arg @ref LL_RCC_PLLM_DIV_41
1542 * @arg @ref LL_RCC_PLLM_DIV_42
1543 * @arg @ref LL_RCC_PLLM_DIV_43
1544 * @arg @ref LL_RCC_PLLM_DIV_44
1545 * @arg @ref LL_RCC_PLLM_DIV_45
1546 * @arg @ref LL_RCC_PLLM_DIV_46
1547 * @arg @ref LL_RCC_PLLM_DIV_47
1548 * @arg @ref LL_RCC_PLLM_DIV_48
1549 * @arg @ref LL_RCC_PLLM_DIV_49
1550 * @arg @ref LL_RCC_PLLM_DIV_50
1551 * @arg @ref LL_RCC_PLLM_DIV_51
1552 * @arg @ref LL_RCC_PLLM_DIV_52
1553 * @arg @ref LL_RCC_PLLM_DIV_53
1554 * @arg @ref LL_RCC_PLLM_DIV_54
1555 * @arg @ref LL_RCC_PLLM_DIV_55
1556 * @arg @ref LL_RCC_PLLM_DIV_56
1557 * @arg @ref LL_RCC_PLLM_DIV_57
1558 * @arg @ref LL_RCC_PLLM_DIV_58
1559 * @arg @ref LL_RCC_PLLM_DIV_59
1560 * @arg @ref LL_RCC_PLLM_DIV_60
1561 * @arg @ref LL_RCC_PLLM_DIV_61
1562 * @arg @ref LL_RCC_PLLM_DIV_62
1563 * @arg @ref LL_RCC_PLLM_DIV_63
1564 * @param __PLLN__ Between 50/192(*) and 432
1565 *
1566 * (*) value not defined in all devices.
1567 * @param __PLLP__ This parameter can be one of the following values:
1568 * @arg @ref LL_RCC_PLLP_DIV_2
1569 * @arg @ref LL_RCC_PLLP_DIV_4
1570 * @arg @ref LL_RCC_PLLP_DIV_6
1571 * @arg @ref LL_RCC_PLLP_DIV_8
1572 * @retval PLL clock frequency (in Hz)
1573 */
1574 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1575 ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
1576
1577 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
1578 /**
1579 * @brief Helper macro to calculate the PLLRCLK frequency on system domain
1580 * @note ex: @ref __LL_RCC_CALC_PLLRCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1581 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1582 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1583 * @param __PLLM__ This parameter can be one of the following values:
1584 * @arg @ref LL_RCC_PLLM_DIV_2
1585 * @arg @ref LL_RCC_PLLM_DIV_3
1586 * @arg @ref LL_RCC_PLLM_DIV_4
1587 * @arg @ref LL_RCC_PLLM_DIV_5
1588 * @arg @ref LL_RCC_PLLM_DIV_6
1589 * @arg @ref LL_RCC_PLLM_DIV_7
1590 * @arg @ref LL_RCC_PLLM_DIV_8
1591 * @arg @ref LL_RCC_PLLM_DIV_9
1592 * @arg @ref LL_RCC_PLLM_DIV_10
1593 * @arg @ref LL_RCC_PLLM_DIV_11
1594 * @arg @ref LL_RCC_PLLM_DIV_12
1595 * @arg @ref LL_RCC_PLLM_DIV_13
1596 * @arg @ref LL_RCC_PLLM_DIV_14
1597 * @arg @ref LL_RCC_PLLM_DIV_15
1598 * @arg @ref LL_RCC_PLLM_DIV_16
1599 * @arg @ref LL_RCC_PLLM_DIV_17
1600 * @arg @ref LL_RCC_PLLM_DIV_18
1601 * @arg @ref LL_RCC_PLLM_DIV_19
1602 * @arg @ref LL_RCC_PLLM_DIV_20
1603 * @arg @ref LL_RCC_PLLM_DIV_21
1604 * @arg @ref LL_RCC_PLLM_DIV_22
1605 * @arg @ref LL_RCC_PLLM_DIV_23
1606 * @arg @ref LL_RCC_PLLM_DIV_24
1607 * @arg @ref LL_RCC_PLLM_DIV_25
1608 * @arg @ref LL_RCC_PLLM_DIV_26
1609 * @arg @ref LL_RCC_PLLM_DIV_27
1610 * @arg @ref LL_RCC_PLLM_DIV_28
1611 * @arg @ref LL_RCC_PLLM_DIV_29
1612 * @arg @ref LL_RCC_PLLM_DIV_30
1613 * @arg @ref LL_RCC_PLLM_DIV_31
1614 * @arg @ref LL_RCC_PLLM_DIV_32
1615 * @arg @ref LL_RCC_PLLM_DIV_33
1616 * @arg @ref LL_RCC_PLLM_DIV_34
1617 * @arg @ref LL_RCC_PLLM_DIV_35
1618 * @arg @ref LL_RCC_PLLM_DIV_36
1619 * @arg @ref LL_RCC_PLLM_DIV_37
1620 * @arg @ref LL_RCC_PLLM_DIV_38
1621 * @arg @ref LL_RCC_PLLM_DIV_39
1622 * @arg @ref LL_RCC_PLLM_DIV_40
1623 * @arg @ref LL_RCC_PLLM_DIV_41
1624 * @arg @ref LL_RCC_PLLM_DIV_42
1625 * @arg @ref LL_RCC_PLLM_DIV_43
1626 * @arg @ref LL_RCC_PLLM_DIV_44
1627 * @arg @ref LL_RCC_PLLM_DIV_45
1628 * @arg @ref LL_RCC_PLLM_DIV_46
1629 * @arg @ref LL_RCC_PLLM_DIV_47
1630 * @arg @ref LL_RCC_PLLM_DIV_48
1631 * @arg @ref LL_RCC_PLLM_DIV_49
1632 * @arg @ref LL_RCC_PLLM_DIV_50
1633 * @arg @ref LL_RCC_PLLM_DIV_51
1634 * @arg @ref LL_RCC_PLLM_DIV_52
1635 * @arg @ref LL_RCC_PLLM_DIV_53
1636 * @arg @ref LL_RCC_PLLM_DIV_54
1637 * @arg @ref LL_RCC_PLLM_DIV_55
1638 * @arg @ref LL_RCC_PLLM_DIV_56
1639 * @arg @ref LL_RCC_PLLM_DIV_57
1640 * @arg @ref LL_RCC_PLLM_DIV_58
1641 * @arg @ref LL_RCC_PLLM_DIV_59
1642 * @arg @ref LL_RCC_PLLM_DIV_60
1643 * @arg @ref LL_RCC_PLLM_DIV_61
1644 * @arg @ref LL_RCC_PLLM_DIV_62
1645 * @arg @ref LL_RCC_PLLM_DIV_63
1646 * @param __PLLN__ Between 50 and 432
1647 * @param __PLLR__ This parameter can be one of the following values:
1648 * @arg @ref LL_RCC_PLLR_DIV_2
1649 * @arg @ref LL_RCC_PLLR_DIV_3
1650 * @arg @ref LL_RCC_PLLR_DIV_4
1651 * @arg @ref LL_RCC_PLLR_DIV_5
1652 * @arg @ref LL_RCC_PLLR_DIV_6
1653 * @arg @ref LL_RCC_PLLR_DIV_7
1654 * @retval PLL clock frequency (in Hz)
1655 */
1656 #define __LL_RCC_CALC_PLLRCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1657 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1658
1659 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
1660
1661 /**
1662 * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
1663 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1664 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
1665 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1666 * @param __PLLM__ This parameter can be one of the following values:
1667 * @arg @ref LL_RCC_PLLM_DIV_2
1668 * @arg @ref LL_RCC_PLLM_DIV_3
1669 * @arg @ref LL_RCC_PLLM_DIV_4
1670 * @arg @ref LL_RCC_PLLM_DIV_5
1671 * @arg @ref LL_RCC_PLLM_DIV_6
1672 * @arg @ref LL_RCC_PLLM_DIV_7
1673 * @arg @ref LL_RCC_PLLM_DIV_8
1674 * @arg @ref LL_RCC_PLLM_DIV_9
1675 * @arg @ref LL_RCC_PLLM_DIV_10
1676 * @arg @ref LL_RCC_PLLM_DIV_11
1677 * @arg @ref LL_RCC_PLLM_DIV_12
1678 * @arg @ref LL_RCC_PLLM_DIV_13
1679 * @arg @ref LL_RCC_PLLM_DIV_14
1680 * @arg @ref LL_RCC_PLLM_DIV_15
1681 * @arg @ref LL_RCC_PLLM_DIV_16
1682 * @arg @ref LL_RCC_PLLM_DIV_17
1683 * @arg @ref LL_RCC_PLLM_DIV_18
1684 * @arg @ref LL_RCC_PLLM_DIV_19
1685 * @arg @ref LL_RCC_PLLM_DIV_20
1686 * @arg @ref LL_RCC_PLLM_DIV_21
1687 * @arg @ref LL_RCC_PLLM_DIV_22
1688 * @arg @ref LL_RCC_PLLM_DIV_23
1689 * @arg @ref LL_RCC_PLLM_DIV_24
1690 * @arg @ref LL_RCC_PLLM_DIV_25
1691 * @arg @ref LL_RCC_PLLM_DIV_26
1692 * @arg @ref LL_RCC_PLLM_DIV_27
1693 * @arg @ref LL_RCC_PLLM_DIV_28
1694 * @arg @ref LL_RCC_PLLM_DIV_29
1695 * @arg @ref LL_RCC_PLLM_DIV_30
1696 * @arg @ref LL_RCC_PLLM_DIV_31
1697 * @arg @ref LL_RCC_PLLM_DIV_32
1698 * @arg @ref LL_RCC_PLLM_DIV_33
1699 * @arg @ref LL_RCC_PLLM_DIV_34
1700 * @arg @ref LL_RCC_PLLM_DIV_35
1701 * @arg @ref LL_RCC_PLLM_DIV_36
1702 * @arg @ref LL_RCC_PLLM_DIV_37
1703 * @arg @ref LL_RCC_PLLM_DIV_38
1704 * @arg @ref LL_RCC_PLLM_DIV_39
1705 * @arg @ref LL_RCC_PLLM_DIV_40
1706 * @arg @ref LL_RCC_PLLM_DIV_41
1707 * @arg @ref LL_RCC_PLLM_DIV_42
1708 * @arg @ref LL_RCC_PLLM_DIV_43
1709 * @arg @ref LL_RCC_PLLM_DIV_44
1710 * @arg @ref LL_RCC_PLLM_DIV_45
1711 * @arg @ref LL_RCC_PLLM_DIV_46
1712 * @arg @ref LL_RCC_PLLM_DIV_47
1713 * @arg @ref LL_RCC_PLLM_DIV_48
1714 * @arg @ref LL_RCC_PLLM_DIV_49
1715 * @arg @ref LL_RCC_PLLM_DIV_50
1716 * @arg @ref LL_RCC_PLLM_DIV_51
1717 * @arg @ref LL_RCC_PLLM_DIV_52
1718 * @arg @ref LL_RCC_PLLM_DIV_53
1719 * @arg @ref LL_RCC_PLLM_DIV_54
1720 * @arg @ref LL_RCC_PLLM_DIV_55
1721 * @arg @ref LL_RCC_PLLM_DIV_56
1722 * @arg @ref LL_RCC_PLLM_DIV_57
1723 * @arg @ref LL_RCC_PLLM_DIV_58
1724 * @arg @ref LL_RCC_PLLM_DIV_59
1725 * @arg @ref LL_RCC_PLLM_DIV_60
1726 * @arg @ref LL_RCC_PLLM_DIV_61
1727 * @arg @ref LL_RCC_PLLM_DIV_62
1728 * @arg @ref LL_RCC_PLLM_DIV_63
1729 * @param __PLLN__ Between 50/192(*) and 432
1730 *
1731 * (*) value not defined in all devices.
1732 * @param __PLLQ__ This parameter can be one of the following values:
1733 * @arg @ref LL_RCC_PLLQ_DIV_2
1734 * @arg @ref LL_RCC_PLLQ_DIV_3
1735 * @arg @ref LL_RCC_PLLQ_DIV_4
1736 * @arg @ref LL_RCC_PLLQ_DIV_5
1737 * @arg @ref LL_RCC_PLLQ_DIV_6
1738 * @arg @ref LL_RCC_PLLQ_DIV_7
1739 * @arg @ref LL_RCC_PLLQ_DIV_8
1740 * @arg @ref LL_RCC_PLLQ_DIV_9
1741 * @arg @ref LL_RCC_PLLQ_DIV_10
1742 * @arg @ref LL_RCC_PLLQ_DIV_11
1743 * @arg @ref LL_RCC_PLLQ_DIV_12
1744 * @arg @ref LL_RCC_PLLQ_DIV_13
1745 * @arg @ref LL_RCC_PLLQ_DIV_14
1746 * @arg @ref LL_RCC_PLLQ_DIV_15
1747 * @retval PLL clock frequency (in Hz)
1748 */
1749 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1750 ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
1751
1752 #if defined(DSI)
1753 /**
1754 * @brief Helper macro to calculate the PLLCLK frequency used on DSI
1755 * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
1756 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1757 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1758 * @param __PLLM__ This parameter can be one of the following values:
1759 * @arg @ref LL_RCC_PLLM_DIV_2
1760 * @arg @ref LL_RCC_PLLM_DIV_3
1761 * @arg @ref LL_RCC_PLLM_DIV_4
1762 * @arg @ref LL_RCC_PLLM_DIV_5
1763 * @arg @ref LL_RCC_PLLM_DIV_6
1764 * @arg @ref LL_RCC_PLLM_DIV_7
1765 * @arg @ref LL_RCC_PLLM_DIV_8
1766 * @arg @ref LL_RCC_PLLM_DIV_9
1767 * @arg @ref LL_RCC_PLLM_DIV_10
1768 * @arg @ref LL_RCC_PLLM_DIV_11
1769 * @arg @ref LL_RCC_PLLM_DIV_12
1770 * @arg @ref LL_RCC_PLLM_DIV_13
1771 * @arg @ref LL_RCC_PLLM_DIV_14
1772 * @arg @ref LL_RCC_PLLM_DIV_15
1773 * @arg @ref LL_RCC_PLLM_DIV_16
1774 * @arg @ref LL_RCC_PLLM_DIV_17
1775 * @arg @ref LL_RCC_PLLM_DIV_18
1776 * @arg @ref LL_RCC_PLLM_DIV_19
1777 * @arg @ref LL_RCC_PLLM_DIV_20
1778 * @arg @ref LL_RCC_PLLM_DIV_21
1779 * @arg @ref LL_RCC_PLLM_DIV_22
1780 * @arg @ref LL_RCC_PLLM_DIV_23
1781 * @arg @ref LL_RCC_PLLM_DIV_24
1782 * @arg @ref LL_RCC_PLLM_DIV_25
1783 * @arg @ref LL_RCC_PLLM_DIV_26
1784 * @arg @ref LL_RCC_PLLM_DIV_27
1785 * @arg @ref LL_RCC_PLLM_DIV_28
1786 * @arg @ref LL_RCC_PLLM_DIV_29
1787 * @arg @ref LL_RCC_PLLM_DIV_30
1788 * @arg @ref LL_RCC_PLLM_DIV_31
1789 * @arg @ref LL_RCC_PLLM_DIV_32
1790 * @arg @ref LL_RCC_PLLM_DIV_33
1791 * @arg @ref LL_RCC_PLLM_DIV_34
1792 * @arg @ref LL_RCC_PLLM_DIV_35
1793 * @arg @ref LL_RCC_PLLM_DIV_36
1794 * @arg @ref LL_RCC_PLLM_DIV_37
1795 * @arg @ref LL_RCC_PLLM_DIV_38
1796 * @arg @ref LL_RCC_PLLM_DIV_39
1797 * @arg @ref LL_RCC_PLLM_DIV_40
1798 * @arg @ref LL_RCC_PLLM_DIV_41
1799 * @arg @ref LL_RCC_PLLM_DIV_42
1800 * @arg @ref LL_RCC_PLLM_DIV_43
1801 * @arg @ref LL_RCC_PLLM_DIV_44
1802 * @arg @ref LL_RCC_PLLM_DIV_45
1803 * @arg @ref LL_RCC_PLLM_DIV_46
1804 * @arg @ref LL_RCC_PLLM_DIV_47
1805 * @arg @ref LL_RCC_PLLM_DIV_48
1806 * @arg @ref LL_RCC_PLLM_DIV_49
1807 * @arg @ref LL_RCC_PLLM_DIV_50
1808 * @arg @ref LL_RCC_PLLM_DIV_51
1809 * @arg @ref LL_RCC_PLLM_DIV_52
1810 * @arg @ref LL_RCC_PLLM_DIV_53
1811 * @arg @ref LL_RCC_PLLM_DIV_54
1812 * @arg @ref LL_RCC_PLLM_DIV_55
1813 * @arg @ref LL_RCC_PLLM_DIV_56
1814 * @arg @ref LL_RCC_PLLM_DIV_57
1815 * @arg @ref LL_RCC_PLLM_DIV_58
1816 * @arg @ref LL_RCC_PLLM_DIV_59
1817 * @arg @ref LL_RCC_PLLM_DIV_60
1818 * @arg @ref LL_RCC_PLLM_DIV_61
1819 * @arg @ref LL_RCC_PLLM_DIV_62
1820 * @arg @ref LL_RCC_PLLM_DIV_63
1821 * @param __PLLN__ Between 50 and 432
1822 * @param __PLLR__ This parameter can be one of the following values:
1823 * @arg @ref LL_RCC_PLLR_DIV_2
1824 * @arg @ref LL_RCC_PLLR_DIV_3
1825 * @arg @ref LL_RCC_PLLR_DIV_4
1826 * @arg @ref LL_RCC_PLLR_DIV_5
1827 * @arg @ref LL_RCC_PLLR_DIV_6
1828 * @arg @ref LL_RCC_PLLR_DIV_7
1829 * @retval PLL clock frequency (in Hz)
1830 */
1831 #define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1832 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1833 #endif /* DSI */
1834
1835 #if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
1836 /**
1837 * @brief Helper macro to calculate the PLLCLK frequency used on I2S
1838 * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
1839 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1840 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1841 * @param __PLLM__ This parameter can be one of the following values:
1842 * @arg @ref LL_RCC_PLLM_DIV_2
1843 * @arg @ref LL_RCC_PLLM_DIV_3
1844 * @arg @ref LL_RCC_PLLM_DIV_4
1845 * @arg @ref LL_RCC_PLLM_DIV_5
1846 * @arg @ref LL_RCC_PLLM_DIV_6
1847 * @arg @ref LL_RCC_PLLM_DIV_7
1848 * @arg @ref LL_RCC_PLLM_DIV_8
1849 * @arg @ref LL_RCC_PLLM_DIV_9
1850 * @arg @ref LL_RCC_PLLM_DIV_10
1851 * @arg @ref LL_RCC_PLLM_DIV_11
1852 * @arg @ref LL_RCC_PLLM_DIV_12
1853 * @arg @ref LL_RCC_PLLM_DIV_13
1854 * @arg @ref LL_RCC_PLLM_DIV_14
1855 * @arg @ref LL_RCC_PLLM_DIV_15
1856 * @arg @ref LL_RCC_PLLM_DIV_16
1857 * @arg @ref LL_RCC_PLLM_DIV_17
1858 * @arg @ref LL_RCC_PLLM_DIV_18
1859 * @arg @ref LL_RCC_PLLM_DIV_19
1860 * @arg @ref LL_RCC_PLLM_DIV_20
1861 * @arg @ref LL_RCC_PLLM_DIV_21
1862 * @arg @ref LL_RCC_PLLM_DIV_22
1863 * @arg @ref LL_RCC_PLLM_DIV_23
1864 * @arg @ref LL_RCC_PLLM_DIV_24
1865 * @arg @ref LL_RCC_PLLM_DIV_25
1866 * @arg @ref LL_RCC_PLLM_DIV_26
1867 * @arg @ref LL_RCC_PLLM_DIV_27
1868 * @arg @ref LL_RCC_PLLM_DIV_28
1869 * @arg @ref LL_RCC_PLLM_DIV_29
1870 * @arg @ref LL_RCC_PLLM_DIV_30
1871 * @arg @ref LL_RCC_PLLM_DIV_31
1872 * @arg @ref LL_RCC_PLLM_DIV_32
1873 * @arg @ref LL_RCC_PLLM_DIV_33
1874 * @arg @ref LL_RCC_PLLM_DIV_34
1875 * @arg @ref LL_RCC_PLLM_DIV_35
1876 * @arg @ref LL_RCC_PLLM_DIV_36
1877 * @arg @ref LL_RCC_PLLM_DIV_37
1878 * @arg @ref LL_RCC_PLLM_DIV_38
1879 * @arg @ref LL_RCC_PLLM_DIV_39
1880 * @arg @ref LL_RCC_PLLM_DIV_40
1881 * @arg @ref LL_RCC_PLLM_DIV_41
1882 * @arg @ref LL_RCC_PLLM_DIV_42
1883 * @arg @ref LL_RCC_PLLM_DIV_43
1884 * @arg @ref LL_RCC_PLLM_DIV_44
1885 * @arg @ref LL_RCC_PLLM_DIV_45
1886 * @arg @ref LL_RCC_PLLM_DIV_46
1887 * @arg @ref LL_RCC_PLLM_DIV_47
1888 * @arg @ref LL_RCC_PLLM_DIV_48
1889 * @arg @ref LL_RCC_PLLM_DIV_49
1890 * @arg @ref LL_RCC_PLLM_DIV_50
1891 * @arg @ref LL_RCC_PLLM_DIV_51
1892 * @arg @ref LL_RCC_PLLM_DIV_52
1893 * @arg @ref LL_RCC_PLLM_DIV_53
1894 * @arg @ref LL_RCC_PLLM_DIV_54
1895 * @arg @ref LL_RCC_PLLM_DIV_55
1896 * @arg @ref LL_RCC_PLLM_DIV_56
1897 * @arg @ref LL_RCC_PLLM_DIV_57
1898 * @arg @ref LL_RCC_PLLM_DIV_58
1899 * @arg @ref LL_RCC_PLLM_DIV_59
1900 * @arg @ref LL_RCC_PLLM_DIV_60
1901 * @arg @ref LL_RCC_PLLM_DIV_61
1902 * @arg @ref LL_RCC_PLLM_DIV_62
1903 * @arg @ref LL_RCC_PLLM_DIV_63
1904 * @param __PLLN__ Between 50 and 432
1905 * @param __PLLR__ This parameter can be one of the following values:
1906 * @arg @ref LL_RCC_PLLR_DIV_2
1907 * @arg @ref LL_RCC_PLLR_DIV_3
1908 * @arg @ref LL_RCC_PLLR_DIV_4
1909 * @arg @ref LL_RCC_PLLR_DIV_5
1910 * @arg @ref LL_RCC_PLLR_DIV_6
1911 * @arg @ref LL_RCC_PLLR_DIV_7
1912 * @retval PLL clock frequency (in Hz)
1913 */
1914 #define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1915 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1916 #endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
1917
1918 #if defined(SPDIFRX)
1919 /**
1920 * @brief Helper macro to calculate the PLLCLK frequency used on SPDIFRX
1921 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
1922 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1923 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1924 * @param __PLLM__ This parameter can be one of the following values:
1925 * @arg @ref LL_RCC_PLLM_DIV_2
1926 * @arg @ref LL_RCC_PLLM_DIV_3
1927 * @arg @ref LL_RCC_PLLM_DIV_4
1928 * @arg @ref LL_RCC_PLLM_DIV_5
1929 * @arg @ref LL_RCC_PLLM_DIV_6
1930 * @arg @ref LL_RCC_PLLM_DIV_7
1931 * @arg @ref LL_RCC_PLLM_DIV_8
1932 * @arg @ref LL_RCC_PLLM_DIV_9
1933 * @arg @ref LL_RCC_PLLM_DIV_10
1934 * @arg @ref LL_RCC_PLLM_DIV_11
1935 * @arg @ref LL_RCC_PLLM_DIV_12
1936 * @arg @ref LL_RCC_PLLM_DIV_13
1937 * @arg @ref LL_RCC_PLLM_DIV_14
1938 * @arg @ref LL_RCC_PLLM_DIV_15
1939 * @arg @ref LL_RCC_PLLM_DIV_16
1940 * @arg @ref LL_RCC_PLLM_DIV_17
1941 * @arg @ref LL_RCC_PLLM_DIV_18
1942 * @arg @ref LL_RCC_PLLM_DIV_19
1943 * @arg @ref LL_RCC_PLLM_DIV_20
1944 * @arg @ref LL_RCC_PLLM_DIV_21
1945 * @arg @ref LL_RCC_PLLM_DIV_22
1946 * @arg @ref LL_RCC_PLLM_DIV_23
1947 * @arg @ref LL_RCC_PLLM_DIV_24
1948 * @arg @ref LL_RCC_PLLM_DIV_25
1949 * @arg @ref LL_RCC_PLLM_DIV_26
1950 * @arg @ref LL_RCC_PLLM_DIV_27
1951 * @arg @ref LL_RCC_PLLM_DIV_28
1952 * @arg @ref LL_RCC_PLLM_DIV_29
1953 * @arg @ref LL_RCC_PLLM_DIV_30
1954 * @arg @ref LL_RCC_PLLM_DIV_31
1955 * @arg @ref LL_RCC_PLLM_DIV_32
1956 * @arg @ref LL_RCC_PLLM_DIV_33
1957 * @arg @ref LL_RCC_PLLM_DIV_34
1958 * @arg @ref LL_RCC_PLLM_DIV_35
1959 * @arg @ref LL_RCC_PLLM_DIV_36
1960 * @arg @ref LL_RCC_PLLM_DIV_37
1961 * @arg @ref LL_RCC_PLLM_DIV_38
1962 * @arg @ref LL_RCC_PLLM_DIV_39
1963 * @arg @ref LL_RCC_PLLM_DIV_40
1964 * @arg @ref LL_RCC_PLLM_DIV_41
1965 * @arg @ref LL_RCC_PLLM_DIV_42
1966 * @arg @ref LL_RCC_PLLM_DIV_43
1967 * @arg @ref LL_RCC_PLLM_DIV_44
1968 * @arg @ref LL_RCC_PLLM_DIV_45
1969 * @arg @ref LL_RCC_PLLM_DIV_46
1970 * @arg @ref LL_RCC_PLLM_DIV_47
1971 * @arg @ref LL_RCC_PLLM_DIV_48
1972 * @arg @ref LL_RCC_PLLM_DIV_49
1973 * @arg @ref LL_RCC_PLLM_DIV_50
1974 * @arg @ref LL_RCC_PLLM_DIV_51
1975 * @arg @ref LL_RCC_PLLM_DIV_52
1976 * @arg @ref LL_RCC_PLLM_DIV_53
1977 * @arg @ref LL_RCC_PLLM_DIV_54
1978 * @arg @ref LL_RCC_PLLM_DIV_55
1979 * @arg @ref LL_RCC_PLLM_DIV_56
1980 * @arg @ref LL_RCC_PLLM_DIV_57
1981 * @arg @ref LL_RCC_PLLM_DIV_58
1982 * @arg @ref LL_RCC_PLLM_DIV_59
1983 * @arg @ref LL_RCC_PLLM_DIV_60
1984 * @arg @ref LL_RCC_PLLM_DIV_61
1985 * @arg @ref LL_RCC_PLLM_DIV_62
1986 * @arg @ref LL_RCC_PLLM_DIV_63
1987 * @param __PLLN__ Between 50 and 432
1988 * @param __PLLR__ This parameter can be one of the following values:
1989 * @arg @ref LL_RCC_PLLR_DIV_2
1990 * @arg @ref LL_RCC_PLLR_DIV_3
1991 * @arg @ref LL_RCC_PLLR_DIV_4
1992 * @arg @ref LL_RCC_PLLR_DIV_5
1993 * @arg @ref LL_RCC_PLLR_DIV_6
1994 * @arg @ref LL_RCC_PLLR_DIV_7
1995 * @retval PLL clock frequency (in Hz)
1996 */
1997 #define __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1998 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1999 #endif /* SPDIFRX */
2000
2001 #if defined(RCC_PLLCFGR_PLLR)
2002 #if defined(SAI1)
2003 /**
2004 * @brief Helper macro to calculate the PLLCLK frequency used on SAI
2005 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
2006 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR (), @ref LL_RCC_PLL_GetDIVR ());
2007 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2008 * @param __PLLM__ This parameter can be one of the following values:
2009 * @arg @ref LL_RCC_PLLM_DIV_2
2010 * @arg @ref LL_RCC_PLLM_DIV_3
2011 * @arg @ref LL_RCC_PLLM_DIV_4
2012 * @arg @ref LL_RCC_PLLM_DIV_5
2013 * @arg @ref LL_RCC_PLLM_DIV_6
2014 * @arg @ref LL_RCC_PLLM_DIV_7
2015 * @arg @ref LL_RCC_PLLM_DIV_8
2016 * @arg @ref LL_RCC_PLLM_DIV_9
2017 * @arg @ref LL_RCC_PLLM_DIV_10
2018 * @arg @ref LL_RCC_PLLM_DIV_11
2019 * @arg @ref LL_RCC_PLLM_DIV_12
2020 * @arg @ref LL_RCC_PLLM_DIV_13
2021 * @arg @ref LL_RCC_PLLM_DIV_14
2022 * @arg @ref LL_RCC_PLLM_DIV_15
2023 * @arg @ref LL_RCC_PLLM_DIV_16
2024 * @arg @ref LL_RCC_PLLM_DIV_17
2025 * @arg @ref LL_RCC_PLLM_DIV_18
2026 * @arg @ref LL_RCC_PLLM_DIV_19
2027 * @arg @ref LL_RCC_PLLM_DIV_20
2028 * @arg @ref LL_RCC_PLLM_DIV_21
2029 * @arg @ref LL_RCC_PLLM_DIV_22
2030 * @arg @ref LL_RCC_PLLM_DIV_23
2031 * @arg @ref LL_RCC_PLLM_DIV_24
2032 * @arg @ref LL_RCC_PLLM_DIV_25
2033 * @arg @ref LL_RCC_PLLM_DIV_26
2034 * @arg @ref LL_RCC_PLLM_DIV_27
2035 * @arg @ref LL_RCC_PLLM_DIV_28
2036 * @arg @ref LL_RCC_PLLM_DIV_29
2037 * @arg @ref LL_RCC_PLLM_DIV_30
2038 * @arg @ref LL_RCC_PLLM_DIV_31
2039 * @arg @ref LL_RCC_PLLM_DIV_32
2040 * @arg @ref LL_RCC_PLLM_DIV_33
2041 * @arg @ref LL_RCC_PLLM_DIV_34
2042 * @arg @ref LL_RCC_PLLM_DIV_35
2043 * @arg @ref LL_RCC_PLLM_DIV_36
2044 * @arg @ref LL_RCC_PLLM_DIV_37
2045 * @arg @ref LL_RCC_PLLM_DIV_38
2046 * @arg @ref LL_RCC_PLLM_DIV_39
2047 * @arg @ref LL_RCC_PLLM_DIV_40
2048 * @arg @ref LL_RCC_PLLM_DIV_41
2049 * @arg @ref LL_RCC_PLLM_DIV_42
2050 * @arg @ref LL_RCC_PLLM_DIV_43
2051 * @arg @ref LL_RCC_PLLM_DIV_44
2052 * @arg @ref LL_RCC_PLLM_DIV_45
2053 * @arg @ref LL_RCC_PLLM_DIV_46
2054 * @arg @ref LL_RCC_PLLM_DIV_47
2055 * @arg @ref LL_RCC_PLLM_DIV_48
2056 * @arg @ref LL_RCC_PLLM_DIV_49
2057 * @arg @ref LL_RCC_PLLM_DIV_50
2058 * @arg @ref LL_RCC_PLLM_DIV_51
2059 * @arg @ref LL_RCC_PLLM_DIV_52
2060 * @arg @ref LL_RCC_PLLM_DIV_53
2061 * @arg @ref LL_RCC_PLLM_DIV_54
2062 * @arg @ref LL_RCC_PLLM_DIV_55
2063 * @arg @ref LL_RCC_PLLM_DIV_56
2064 * @arg @ref LL_RCC_PLLM_DIV_57
2065 * @arg @ref LL_RCC_PLLM_DIV_58
2066 * @arg @ref LL_RCC_PLLM_DIV_59
2067 * @arg @ref LL_RCC_PLLM_DIV_60
2068 * @arg @ref LL_RCC_PLLM_DIV_61
2069 * @arg @ref LL_RCC_PLLM_DIV_62
2070 * @arg @ref LL_RCC_PLLM_DIV_63
2071 * @param __PLLN__ Between 50 and 432
2072 * @param __PLLR__ This parameter can be one of the following values:
2073 * @arg @ref LL_RCC_PLLR_DIV_2
2074 * @arg @ref LL_RCC_PLLR_DIV_3
2075 * @arg @ref LL_RCC_PLLR_DIV_4
2076 * @arg @ref LL_RCC_PLLR_DIV_5
2077 * @arg @ref LL_RCC_PLLR_DIV_6
2078 * @arg @ref LL_RCC_PLLR_DIV_7
2079 * @param __PLLDIVR__ This parameter can be one of the following values:
2080 * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
2081 * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
2082 * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
2083 * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
2084 * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
2085 * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
2086 * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
2087 * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
2088 * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
2089 * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
2090 * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
2091 * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
2092 * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
2093 * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
2094 * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
2095 * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
2096 * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
2097 * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
2098 * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
2099 * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
2100 * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
2101 * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
2102 * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
2103 * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
2104 * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
2105 * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
2106 * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
2107 * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
2108 * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
2109 * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
2110 * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
2111 *
2112 * (*) value not defined in all devices.
2113 * @retval PLL clock frequency (in Hz)
2114 */
2115 #if defined(RCC_DCKCFGR_PLLDIVR)
2116 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__, __PLLDIVR__) (((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
2117 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) / ((__PLLDIVR__) >> RCC_DCKCFGR_PLLDIVR_Pos ))
2118 #else
2119 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
2120 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
2121 #endif /* RCC_DCKCFGR_PLLDIVR */
2122 #endif /* SAI1 */
2123 #endif /* RCC_PLLCFGR_PLLR */
2124
2125 #if defined(RCC_PLLSAI_SUPPORT)
2126 /**
2127 * @brief Helper macro to calculate the PLLSAI frequency used for SAI domain
2128 * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
2129 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ());
2130 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2131 * @param __PLLM__ This parameter can be one of the following values:
2132 * @arg @ref LL_RCC_PLLSAIM_DIV_2
2133 * @arg @ref LL_RCC_PLLSAIM_DIV_3
2134 * @arg @ref LL_RCC_PLLSAIM_DIV_4
2135 * @arg @ref LL_RCC_PLLSAIM_DIV_5
2136 * @arg @ref LL_RCC_PLLSAIM_DIV_6
2137 * @arg @ref LL_RCC_PLLSAIM_DIV_7
2138 * @arg @ref LL_RCC_PLLSAIM_DIV_8
2139 * @arg @ref LL_RCC_PLLSAIM_DIV_9
2140 * @arg @ref LL_RCC_PLLSAIM_DIV_10
2141 * @arg @ref LL_RCC_PLLSAIM_DIV_11
2142 * @arg @ref LL_RCC_PLLSAIM_DIV_12
2143 * @arg @ref LL_RCC_PLLSAIM_DIV_13
2144 * @arg @ref LL_RCC_PLLSAIM_DIV_14
2145 * @arg @ref LL_RCC_PLLSAIM_DIV_15
2146 * @arg @ref LL_RCC_PLLSAIM_DIV_16
2147 * @arg @ref LL_RCC_PLLSAIM_DIV_17
2148 * @arg @ref LL_RCC_PLLSAIM_DIV_18
2149 * @arg @ref LL_RCC_PLLSAIM_DIV_19
2150 * @arg @ref LL_RCC_PLLSAIM_DIV_20
2151 * @arg @ref LL_RCC_PLLSAIM_DIV_21
2152 * @arg @ref LL_RCC_PLLSAIM_DIV_22
2153 * @arg @ref LL_RCC_PLLSAIM_DIV_23
2154 * @arg @ref LL_RCC_PLLSAIM_DIV_24
2155 * @arg @ref LL_RCC_PLLSAIM_DIV_25
2156 * @arg @ref LL_RCC_PLLSAIM_DIV_26
2157 * @arg @ref LL_RCC_PLLSAIM_DIV_27
2158 * @arg @ref LL_RCC_PLLSAIM_DIV_28
2159 * @arg @ref LL_RCC_PLLSAIM_DIV_29
2160 * @arg @ref LL_RCC_PLLSAIM_DIV_30
2161 * @arg @ref LL_RCC_PLLSAIM_DIV_31
2162 * @arg @ref LL_RCC_PLLSAIM_DIV_32
2163 * @arg @ref LL_RCC_PLLSAIM_DIV_33
2164 * @arg @ref LL_RCC_PLLSAIM_DIV_34
2165 * @arg @ref LL_RCC_PLLSAIM_DIV_35
2166 * @arg @ref LL_RCC_PLLSAIM_DIV_36
2167 * @arg @ref LL_RCC_PLLSAIM_DIV_37
2168 * @arg @ref LL_RCC_PLLSAIM_DIV_38
2169 * @arg @ref LL_RCC_PLLSAIM_DIV_39
2170 * @arg @ref LL_RCC_PLLSAIM_DIV_40
2171 * @arg @ref LL_RCC_PLLSAIM_DIV_41
2172 * @arg @ref LL_RCC_PLLSAIM_DIV_42
2173 * @arg @ref LL_RCC_PLLSAIM_DIV_43
2174 * @arg @ref LL_RCC_PLLSAIM_DIV_44
2175 * @arg @ref LL_RCC_PLLSAIM_DIV_45
2176 * @arg @ref LL_RCC_PLLSAIM_DIV_46
2177 * @arg @ref LL_RCC_PLLSAIM_DIV_47
2178 * @arg @ref LL_RCC_PLLSAIM_DIV_48
2179 * @arg @ref LL_RCC_PLLSAIM_DIV_49
2180 * @arg @ref LL_RCC_PLLSAIM_DIV_50
2181 * @arg @ref LL_RCC_PLLSAIM_DIV_51
2182 * @arg @ref LL_RCC_PLLSAIM_DIV_52
2183 * @arg @ref LL_RCC_PLLSAIM_DIV_53
2184 * @arg @ref LL_RCC_PLLSAIM_DIV_54
2185 * @arg @ref LL_RCC_PLLSAIM_DIV_55
2186 * @arg @ref LL_RCC_PLLSAIM_DIV_56
2187 * @arg @ref LL_RCC_PLLSAIM_DIV_57
2188 * @arg @ref LL_RCC_PLLSAIM_DIV_58
2189 * @arg @ref LL_RCC_PLLSAIM_DIV_59
2190 * @arg @ref LL_RCC_PLLSAIM_DIV_60
2191 * @arg @ref LL_RCC_PLLSAIM_DIV_61
2192 * @arg @ref LL_RCC_PLLSAIM_DIV_62
2193 * @arg @ref LL_RCC_PLLSAIM_DIV_63
2194 * @param __PLLSAIN__ Between 49/50(*) and 432
2195 *
2196 * (*) value not defined in all devices.
2197 * @param __PLLSAIQ__ This parameter can be one of the following values:
2198 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
2199 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
2200 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
2201 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
2202 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
2203 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
2204 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
2205 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
2206 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
2207 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
2208 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
2209 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
2210 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
2211 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
2212 * @param __PLLSAIDIVQ__ This parameter can be one of the following values:
2213 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
2214 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
2215 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
2216 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
2217 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
2218 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
2219 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
2220 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
2221 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
2222 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
2223 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
2224 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
2225 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
2226 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
2227 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
2228 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
2229 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
2230 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
2231 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
2232 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
2233 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
2234 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
2235 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
2236 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
2237 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
2238 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
2239 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
2240 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
2241 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
2242 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
2243 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
2244 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
2245 * @retval PLLSAI clock frequency (in Hz)
2246 */
2247 #define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
2248 (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos) + 1U)))
2249
2250 #if defined(RCC_PLLSAICFGR_PLLSAIP)
2251 /**
2252 * @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain
2253 * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
2254 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ());
2255 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2256 * @param __PLLM__ This parameter can be one of the following values:
2257 * @arg @ref LL_RCC_PLLSAIM_DIV_2
2258 * @arg @ref LL_RCC_PLLSAIM_DIV_3
2259 * @arg @ref LL_RCC_PLLSAIM_DIV_4
2260 * @arg @ref LL_RCC_PLLSAIM_DIV_5
2261 * @arg @ref LL_RCC_PLLSAIM_DIV_6
2262 * @arg @ref LL_RCC_PLLSAIM_DIV_7
2263 * @arg @ref LL_RCC_PLLSAIM_DIV_8
2264 * @arg @ref LL_RCC_PLLSAIM_DIV_9
2265 * @arg @ref LL_RCC_PLLSAIM_DIV_10
2266 * @arg @ref LL_RCC_PLLSAIM_DIV_11
2267 * @arg @ref LL_RCC_PLLSAIM_DIV_12
2268 * @arg @ref LL_RCC_PLLSAIM_DIV_13
2269 * @arg @ref LL_RCC_PLLSAIM_DIV_14
2270 * @arg @ref LL_RCC_PLLSAIM_DIV_15
2271 * @arg @ref LL_RCC_PLLSAIM_DIV_16
2272 * @arg @ref LL_RCC_PLLSAIM_DIV_17
2273 * @arg @ref LL_RCC_PLLSAIM_DIV_18
2274 * @arg @ref LL_RCC_PLLSAIM_DIV_19
2275 * @arg @ref LL_RCC_PLLSAIM_DIV_20
2276 * @arg @ref LL_RCC_PLLSAIM_DIV_21
2277 * @arg @ref LL_RCC_PLLSAIM_DIV_22
2278 * @arg @ref LL_RCC_PLLSAIM_DIV_23
2279 * @arg @ref LL_RCC_PLLSAIM_DIV_24
2280 * @arg @ref LL_RCC_PLLSAIM_DIV_25
2281 * @arg @ref LL_RCC_PLLSAIM_DIV_26
2282 * @arg @ref LL_RCC_PLLSAIM_DIV_27
2283 * @arg @ref LL_RCC_PLLSAIM_DIV_28
2284 * @arg @ref LL_RCC_PLLSAIM_DIV_29
2285 * @arg @ref LL_RCC_PLLSAIM_DIV_30
2286 * @arg @ref LL_RCC_PLLSAIM_DIV_31
2287 * @arg @ref LL_RCC_PLLSAIM_DIV_32
2288 * @arg @ref LL_RCC_PLLSAIM_DIV_33
2289 * @arg @ref LL_RCC_PLLSAIM_DIV_34
2290 * @arg @ref LL_RCC_PLLSAIM_DIV_35
2291 * @arg @ref LL_RCC_PLLSAIM_DIV_36
2292 * @arg @ref LL_RCC_PLLSAIM_DIV_37
2293 * @arg @ref LL_RCC_PLLSAIM_DIV_38
2294 * @arg @ref LL_RCC_PLLSAIM_DIV_39
2295 * @arg @ref LL_RCC_PLLSAIM_DIV_40
2296 * @arg @ref LL_RCC_PLLSAIM_DIV_41
2297 * @arg @ref LL_RCC_PLLSAIM_DIV_42
2298 * @arg @ref LL_RCC_PLLSAIM_DIV_43
2299 * @arg @ref LL_RCC_PLLSAIM_DIV_44
2300 * @arg @ref LL_RCC_PLLSAIM_DIV_45
2301 * @arg @ref LL_RCC_PLLSAIM_DIV_46
2302 * @arg @ref LL_RCC_PLLSAIM_DIV_47
2303 * @arg @ref LL_RCC_PLLSAIM_DIV_48
2304 * @arg @ref LL_RCC_PLLSAIM_DIV_49
2305 * @arg @ref LL_RCC_PLLSAIM_DIV_50
2306 * @arg @ref LL_RCC_PLLSAIM_DIV_51
2307 * @arg @ref LL_RCC_PLLSAIM_DIV_52
2308 * @arg @ref LL_RCC_PLLSAIM_DIV_53
2309 * @arg @ref LL_RCC_PLLSAIM_DIV_54
2310 * @arg @ref LL_RCC_PLLSAIM_DIV_55
2311 * @arg @ref LL_RCC_PLLSAIM_DIV_56
2312 * @arg @ref LL_RCC_PLLSAIM_DIV_57
2313 * @arg @ref LL_RCC_PLLSAIM_DIV_58
2314 * @arg @ref LL_RCC_PLLSAIM_DIV_59
2315 * @arg @ref LL_RCC_PLLSAIM_DIV_60
2316 * @arg @ref LL_RCC_PLLSAIM_DIV_61
2317 * @arg @ref LL_RCC_PLLSAIM_DIV_62
2318 * @arg @ref LL_RCC_PLLSAIM_DIV_63
2319 * @param __PLLSAIN__ Between 50 and 432
2320 * @param __PLLSAIP__ This parameter can be one of the following values:
2321 * @arg @ref LL_RCC_PLLSAIP_DIV_2
2322 * @arg @ref LL_RCC_PLLSAIP_DIV_4
2323 * @arg @ref LL_RCC_PLLSAIP_DIV_6
2324 * @arg @ref LL_RCC_PLLSAIP_DIV_8
2325 * @retval PLLSAI clock frequency (in Hz)
2326 */
2327 #define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
2328 ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) * 2U))
2329 #endif /* RCC_PLLSAICFGR_PLLSAIP */
2330
2331 #if defined(LTDC)
2332 /**
2333 * @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain
2334 * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
2335 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ());
2336 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2337 * @param __PLLM__ This parameter can be one of the following values:
2338 * @arg @ref LL_RCC_PLLSAIM_DIV_2
2339 * @arg @ref LL_RCC_PLLSAIM_DIV_3
2340 * @arg @ref LL_RCC_PLLSAIM_DIV_4
2341 * @arg @ref LL_RCC_PLLSAIM_DIV_5
2342 * @arg @ref LL_RCC_PLLSAIM_DIV_6
2343 * @arg @ref LL_RCC_PLLSAIM_DIV_7
2344 * @arg @ref LL_RCC_PLLSAIM_DIV_8
2345 * @arg @ref LL_RCC_PLLSAIM_DIV_9
2346 * @arg @ref LL_RCC_PLLSAIM_DIV_10
2347 * @arg @ref LL_RCC_PLLSAIM_DIV_11
2348 * @arg @ref LL_RCC_PLLSAIM_DIV_12
2349 * @arg @ref LL_RCC_PLLSAIM_DIV_13
2350 * @arg @ref LL_RCC_PLLSAIM_DIV_14
2351 * @arg @ref LL_RCC_PLLSAIM_DIV_15
2352 * @arg @ref LL_RCC_PLLSAIM_DIV_16
2353 * @arg @ref LL_RCC_PLLSAIM_DIV_17
2354 * @arg @ref LL_RCC_PLLSAIM_DIV_18
2355 * @arg @ref LL_RCC_PLLSAIM_DIV_19
2356 * @arg @ref LL_RCC_PLLSAIM_DIV_20
2357 * @arg @ref LL_RCC_PLLSAIM_DIV_21
2358 * @arg @ref LL_RCC_PLLSAIM_DIV_22
2359 * @arg @ref LL_RCC_PLLSAIM_DIV_23
2360 * @arg @ref LL_RCC_PLLSAIM_DIV_24
2361 * @arg @ref LL_RCC_PLLSAIM_DIV_25
2362 * @arg @ref LL_RCC_PLLSAIM_DIV_26
2363 * @arg @ref LL_RCC_PLLSAIM_DIV_27
2364 * @arg @ref LL_RCC_PLLSAIM_DIV_28
2365 * @arg @ref LL_RCC_PLLSAIM_DIV_29
2366 * @arg @ref LL_RCC_PLLSAIM_DIV_30
2367 * @arg @ref LL_RCC_PLLSAIM_DIV_31
2368 * @arg @ref LL_RCC_PLLSAIM_DIV_32
2369 * @arg @ref LL_RCC_PLLSAIM_DIV_33
2370 * @arg @ref LL_RCC_PLLSAIM_DIV_34
2371 * @arg @ref LL_RCC_PLLSAIM_DIV_35
2372 * @arg @ref LL_RCC_PLLSAIM_DIV_36
2373 * @arg @ref LL_RCC_PLLSAIM_DIV_37
2374 * @arg @ref LL_RCC_PLLSAIM_DIV_38
2375 * @arg @ref LL_RCC_PLLSAIM_DIV_39
2376 * @arg @ref LL_RCC_PLLSAIM_DIV_40
2377 * @arg @ref LL_RCC_PLLSAIM_DIV_41
2378 * @arg @ref LL_RCC_PLLSAIM_DIV_42
2379 * @arg @ref LL_RCC_PLLSAIM_DIV_43
2380 * @arg @ref LL_RCC_PLLSAIM_DIV_44
2381 * @arg @ref LL_RCC_PLLSAIM_DIV_45
2382 * @arg @ref LL_RCC_PLLSAIM_DIV_46
2383 * @arg @ref LL_RCC_PLLSAIM_DIV_47
2384 * @arg @ref LL_RCC_PLLSAIM_DIV_48
2385 * @arg @ref LL_RCC_PLLSAIM_DIV_49
2386 * @arg @ref LL_RCC_PLLSAIM_DIV_50
2387 * @arg @ref LL_RCC_PLLSAIM_DIV_51
2388 * @arg @ref LL_RCC_PLLSAIM_DIV_52
2389 * @arg @ref LL_RCC_PLLSAIM_DIV_53
2390 * @arg @ref LL_RCC_PLLSAIM_DIV_54
2391 * @arg @ref LL_RCC_PLLSAIM_DIV_55
2392 * @arg @ref LL_RCC_PLLSAIM_DIV_56
2393 * @arg @ref LL_RCC_PLLSAIM_DIV_57
2394 * @arg @ref LL_RCC_PLLSAIM_DIV_58
2395 * @arg @ref LL_RCC_PLLSAIM_DIV_59
2396 * @arg @ref LL_RCC_PLLSAIM_DIV_60
2397 * @arg @ref LL_RCC_PLLSAIM_DIV_61
2398 * @arg @ref LL_RCC_PLLSAIM_DIV_62
2399 * @arg @ref LL_RCC_PLLSAIM_DIV_63
2400 * @param __PLLSAIN__ Between 49/50(*) and 432
2401 *
2402 * (*) value not defined in all devices.
2403 * @param __PLLSAIR__ This parameter can be one of the following values:
2404 * @arg @ref LL_RCC_PLLSAIR_DIV_2
2405 * @arg @ref LL_RCC_PLLSAIR_DIV_3
2406 * @arg @ref LL_RCC_PLLSAIR_DIV_4
2407 * @arg @ref LL_RCC_PLLSAIR_DIV_5
2408 * @arg @ref LL_RCC_PLLSAIR_DIV_6
2409 * @arg @ref LL_RCC_PLLSAIR_DIV_7
2410 * @param __PLLSAIDIVR__ This parameter can be one of the following values:
2411 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
2412 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
2413 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
2414 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
2415 * @retval PLLSAI clock frequency (in Hz)
2416 */
2417 #define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
2418 (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR_PLLSAIDIVR_Pos])))
2419 #endif /* LTDC */
2420 #endif /* RCC_PLLSAI_SUPPORT */
2421
2422 #if defined(RCC_PLLI2S_SUPPORT)
2423 #if defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR)
2424 /**
2425 * @brief Helper macro to calculate the PLLI2S frequency used for SAI domain
2426 * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
2427 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ());
2428 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2429 * @param __PLLM__ This parameter can be one of the following values:
2430 * @arg @ref LL_RCC_PLLI2SM_DIV_2
2431 * @arg @ref LL_RCC_PLLI2SM_DIV_3
2432 * @arg @ref LL_RCC_PLLI2SM_DIV_4
2433 * @arg @ref LL_RCC_PLLI2SM_DIV_5
2434 * @arg @ref LL_RCC_PLLI2SM_DIV_6
2435 * @arg @ref LL_RCC_PLLI2SM_DIV_7
2436 * @arg @ref LL_RCC_PLLI2SM_DIV_8
2437 * @arg @ref LL_RCC_PLLI2SM_DIV_9
2438 * @arg @ref LL_RCC_PLLI2SM_DIV_10
2439 * @arg @ref LL_RCC_PLLI2SM_DIV_11
2440 * @arg @ref LL_RCC_PLLI2SM_DIV_12
2441 * @arg @ref LL_RCC_PLLI2SM_DIV_13
2442 * @arg @ref LL_RCC_PLLI2SM_DIV_14
2443 * @arg @ref LL_RCC_PLLI2SM_DIV_15
2444 * @arg @ref LL_RCC_PLLI2SM_DIV_16
2445 * @arg @ref LL_RCC_PLLI2SM_DIV_17
2446 * @arg @ref LL_RCC_PLLI2SM_DIV_18
2447 * @arg @ref LL_RCC_PLLI2SM_DIV_19
2448 * @arg @ref LL_RCC_PLLI2SM_DIV_20
2449 * @arg @ref LL_RCC_PLLI2SM_DIV_21
2450 * @arg @ref LL_RCC_PLLI2SM_DIV_22
2451 * @arg @ref LL_RCC_PLLI2SM_DIV_23
2452 * @arg @ref LL_RCC_PLLI2SM_DIV_24
2453 * @arg @ref LL_RCC_PLLI2SM_DIV_25
2454 * @arg @ref LL_RCC_PLLI2SM_DIV_26
2455 * @arg @ref LL_RCC_PLLI2SM_DIV_27
2456 * @arg @ref LL_RCC_PLLI2SM_DIV_28
2457 * @arg @ref LL_RCC_PLLI2SM_DIV_29
2458 * @arg @ref LL_RCC_PLLI2SM_DIV_30
2459 * @arg @ref LL_RCC_PLLI2SM_DIV_31
2460 * @arg @ref LL_RCC_PLLI2SM_DIV_32
2461 * @arg @ref LL_RCC_PLLI2SM_DIV_33
2462 * @arg @ref LL_RCC_PLLI2SM_DIV_34
2463 * @arg @ref LL_RCC_PLLI2SM_DIV_35
2464 * @arg @ref LL_RCC_PLLI2SM_DIV_36
2465 * @arg @ref LL_RCC_PLLI2SM_DIV_37
2466 * @arg @ref LL_RCC_PLLI2SM_DIV_38
2467 * @arg @ref LL_RCC_PLLI2SM_DIV_39
2468 * @arg @ref LL_RCC_PLLI2SM_DIV_40
2469 * @arg @ref LL_RCC_PLLI2SM_DIV_41
2470 * @arg @ref LL_RCC_PLLI2SM_DIV_42
2471 * @arg @ref LL_RCC_PLLI2SM_DIV_43
2472 * @arg @ref LL_RCC_PLLI2SM_DIV_44
2473 * @arg @ref LL_RCC_PLLI2SM_DIV_45
2474 * @arg @ref LL_RCC_PLLI2SM_DIV_46
2475 * @arg @ref LL_RCC_PLLI2SM_DIV_47
2476 * @arg @ref LL_RCC_PLLI2SM_DIV_48
2477 * @arg @ref LL_RCC_PLLI2SM_DIV_49
2478 * @arg @ref LL_RCC_PLLI2SM_DIV_50
2479 * @arg @ref LL_RCC_PLLI2SM_DIV_51
2480 * @arg @ref LL_RCC_PLLI2SM_DIV_52
2481 * @arg @ref LL_RCC_PLLI2SM_DIV_53
2482 * @arg @ref LL_RCC_PLLI2SM_DIV_54
2483 * @arg @ref LL_RCC_PLLI2SM_DIV_55
2484 * @arg @ref LL_RCC_PLLI2SM_DIV_56
2485 * @arg @ref LL_RCC_PLLI2SM_DIV_57
2486 * @arg @ref LL_RCC_PLLI2SM_DIV_58
2487 * @arg @ref LL_RCC_PLLI2SM_DIV_59
2488 * @arg @ref LL_RCC_PLLI2SM_DIV_60
2489 * @arg @ref LL_RCC_PLLI2SM_DIV_61
2490 * @arg @ref LL_RCC_PLLI2SM_DIV_62
2491 * @arg @ref LL_RCC_PLLI2SM_DIV_63
2492 * @param __PLLI2SN__ Between 50/192(*) and 432
2493 *
2494 * (*) value not defined in all devices.
2495 * @param __PLLI2SQ_R__ This parameter can be one of the following values:
2496 * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
2497 * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
2498 * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
2499 * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
2500 * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
2501 * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
2502 * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
2503 * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
2504 * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
2505 * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
2506 * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
2507 * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
2508 * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
2509 * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
2510 * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
2511 * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
2512 * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
2513 * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
2514 * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
2515 * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
2516 *
2517 * (*) value not defined in all devices.
2518 * @param __PLLI2SDIVQ_R__ This parameter can be one of the following values:
2519 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
2520 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
2521 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
2522 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
2523 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
2524 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
2525 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
2526 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
2527 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
2528 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
2529 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
2530 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
2531 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
2532 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
2533 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
2534 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
2535 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
2536 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
2537 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
2538 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
2539 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
2540 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
2541 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
2542 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
2543 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
2544 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
2545 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
2546 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
2547 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
2548 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
2549 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
2550 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
2551 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
2552 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
2553 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
2554 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
2555 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
2556 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
2557 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
2558 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
2559 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
2560 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
2561 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
2562 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
2563 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
2564 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
2565 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
2566 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
2567 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
2568 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
2569 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
2570 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
2571 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
2572 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
2573 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
2574 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
2575 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
2576 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
2577 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
2578 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
2579 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
2580 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
2581 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
2582 *
2583 * (*) value not defined in all devices.
2584 * @retval PLLI2S clock frequency (in Hz)
2585 */
2586 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
2587 #define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2588 (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos) + 1U)))
2589 #else
2590 #define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2591 (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos) * ((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVR_Pos)))
2592
2593 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
2594 #endif /* RCC_DCKCFGR_PLLI2SDIVQ || RCC_DCKCFGR_PLLI2SDIVR */
2595
2596 #if defined(SPDIFRX)
2597 /**
2598 * @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain
2599 * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
2600 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ());
2601 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2602 * @param __PLLM__ This parameter can be one of the following values:
2603 * @arg @ref LL_RCC_PLLI2SM_DIV_2
2604 * @arg @ref LL_RCC_PLLI2SM_DIV_3
2605 * @arg @ref LL_RCC_PLLI2SM_DIV_4
2606 * @arg @ref LL_RCC_PLLI2SM_DIV_5
2607 * @arg @ref LL_RCC_PLLI2SM_DIV_6
2608 * @arg @ref LL_RCC_PLLI2SM_DIV_7
2609 * @arg @ref LL_RCC_PLLI2SM_DIV_8
2610 * @arg @ref LL_RCC_PLLI2SM_DIV_9
2611 * @arg @ref LL_RCC_PLLI2SM_DIV_10
2612 * @arg @ref LL_RCC_PLLI2SM_DIV_11
2613 * @arg @ref LL_RCC_PLLI2SM_DIV_12
2614 * @arg @ref LL_RCC_PLLI2SM_DIV_13
2615 * @arg @ref LL_RCC_PLLI2SM_DIV_14
2616 * @arg @ref LL_RCC_PLLI2SM_DIV_15
2617 * @arg @ref LL_RCC_PLLI2SM_DIV_16
2618 * @arg @ref LL_RCC_PLLI2SM_DIV_17
2619 * @arg @ref LL_RCC_PLLI2SM_DIV_18
2620 * @arg @ref LL_RCC_PLLI2SM_DIV_19
2621 * @arg @ref LL_RCC_PLLI2SM_DIV_20
2622 * @arg @ref LL_RCC_PLLI2SM_DIV_21
2623 * @arg @ref LL_RCC_PLLI2SM_DIV_22
2624 * @arg @ref LL_RCC_PLLI2SM_DIV_23
2625 * @arg @ref LL_RCC_PLLI2SM_DIV_24
2626 * @arg @ref LL_RCC_PLLI2SM_DIV_25
2627 * @arg @ref LL_RCC_PLLI2SM_DIV_26
2628 * @arg @ref LL_RCC_PLLI2SM_DIV_27
2629 * @arg @ref LL_RCC_PLLI2SM_DIV_28
2630 * @arg @ref LL_RCC_PLLI2SM_DIV_29
2631 * @arg @ref LL_RCC_PLLI2SM_DIV_30
2632 * @arg @ref LL_RCC_PLLI2SM_DIV_31
2633 * @arg @ref LL_RCC_PLLI2SM_DIV_32
2634 * @arg @ref LL_RCC_PLLI2SM_DIV_33
2635 * @arg @ref LL_RCC_PLLI2SM_DIV_34
2636 * @arg @ref LL_RCC_PLLI2SM_DIV_35
2637 * @arg @ref LL_RCC_PLLI2SM_DIV_36
2638 * @arg @ref LL_RCC_PLLI2SM_DIV_37
2639 * @arg @ref LL_RCC_PLLI2SM_DIV_38
2640 * @arg @ref LL_RCC_PLLI2SM_DIV_39
2641 * @arg @ref LL_RCC_PLLI2SM_DIV_40
2642 * @arg @ref LL_RCC_PLLI2SM_DIV_41
2643 * @arg @ref LL_RCC_PLLI2SM_DIV_42
2644 * @arg @ref LL_RCC_PLLI2SM_DIV_43
2645 * @arg @ref LL_RCC_PLLI2SM_DIV_44
2646 * @arg @ref LL_RCC_PLLI2SM_DIV_45
2647 * @arg @ref LL_RCC_PLLI2SM_DIV_46
2648 * @arg @ref LL_RCC_PLLI2SM_DIV_47
2649 * @arg @ref LL_RCC_PLLI2SM_DIV_48
2650 * @arg @ref LL_RCC_PLLI2SM_DIV_49
2651 * @arg @ref LL_RCC_PLLI2SM_DIV_50
2652 * @arg @ref LL_RCC_PLLI2SM_DIV_51
2653 * @arg @ref LL_RCC_PLLI2SM_DIV_52
2654 * @arg @ref LL_RCC_PLLI2SM_DIV_53
2655 * @arg @ref LL_RCC_PLLI2SM_DIV_54
2656 * @arg @ref LL_RCC_PLLI2SM_DIV_55
2657 * @arg @ref LL_RCC_PLLI2SM_DIV_56
2658 * @arg @ref LL_RCC_PLLI2SM_DIV_57
2659 * @arg @ref LL_RCC_PLLI2SM_DIV_58
2660 * @arg @ref LL_RCC_PLLI2SM_DIV_59
2661 * @arg @ref LL_RCC_PLLI2SM_DIV_60
2662 * @arg @ref LL_RCC_PLLI2SM_DIV_61
2663 * @arg @ref LL_RCC_PLLI2SM_DIV_62
2664 * @arg @ref LL_RCC_PLLI2SM_DIV_63
2665 * @param __PLLI2SN__ Between 50 and 432
2666 * @param __PLLI2SP__ This parameter can be one of the following values:
2667 * @arg @ref LL_RCC_PLLI2SP_DIV_2
2668 * @arg @ref LL_RCC_PLLI2SP_DIV_4
2669 * @arg @ref LL_RCC_PLLI2SP_DIV_6
2670 * @arg @ref LL_RCC_PLLI2SP_DIV_8
2671 * @retval PLLI2S clock frequency (in Hz)
2672 */
2673 #define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2674 ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))
2675
2676 #endif /* SPDIFRX */
2677
2678 /**
2679 * @brief Helper macro to calculate the PLLI2S frequency used for I2S domain
2680 * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
2681 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
2682 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2683 * @param __PLLM__ This parameter can be one of the following values:
2684 * @arg @ref LL_RCC_PLLI2SM_DIV_2
2685 * @arg @ref LL_RCC_PLLI2SM_DIV_3
2686 * @arg @ref LL_RCC_PLLI2SM_DIV_4
2687 * @arg @ref LL_RCC_PLLI2SM_DIV_5
2688 * @arg @ref LL_RCC_PLLI2SM_DIV_6
2689 * @arg @ref LL_RCC_PLLI2SM_DIV_7
2690 * @arg @ref LL_RCC_PLLI2SM_DIV_8
2691 * @arg @ref LL_RCC_PLLI2SM_DIV_9
2692 * @arg @ref LL_RCC_PLLI2SM_DIV_10
2693 * @arg @ref LL_RCC_PLLI2SM_DIV_11
2694 * @arg @ref LL_RCC_PLLI2SM_DIV_12
2695 * @arg @ref LL_RCC_PLLI2SM_DIV_13
2696 * @arg @ref LL_RCC_PLLI2SM_DIV_14
2697 * @arg @ref LL_RCC_PLLI2SM_DIV_15
2698 * @arg @ref LL_RCC_PLLI2SM_DIV_16
2699 * @arg @ref LL_RCC_PLLI2SM_DIV_17
2700 * @arg @ref LL_RCC_PLLI2SM_DIV_18
2701 * @arg @ref LL_RCC_PLLI2SM_DIV_19
2702 * @arg @ref LL_RCC_PLLI2SM_DIV_20
2703 * @arg @ref LL_RCC_PLLI2SM_DIV_21
2704 * @arg @ref LL_RCC_PLLI2SM_DIV_22
2705 * @arg @ref LL_RCC_PLLI2SM_DIV_23
2706 * @arg @ref LL_RCC_PLLI2SM_DIV_24
2707 * @arg @ref LL_RCC_PLLI2SM_DIV_25
2708 * @arg @ref LL_RCC_PLLI2SM_DIV_26
2709 * @arg @ref LL_RCC_PLLI2SM_DIV_27
2710 * @arg @ref LL_RCC_PLLI2SM_DIV_28
2711 * @arg @ref LL_RCC_PLLI2SM_DIV_29
2712 * @arg @ref LL_RCC_PLLI2SM_DIV_30
2713 * @arg @ref LL_RCC_PLLI2SM_DIV_31
2714 * @arg @ref LL_RCC_PLLI2SM_DIV_32
2715 * @arg @ref LL_RCC_PLLI2SM_DIV_33
2716 * @arg @ref LL_RCC_PLLI2SM_DIV_34
2717 * @arg @ref LL_RCC_PLLI2SM_DIV_35
2718 * @arg @ref LL_RCC_PLLI2SM_DIV_36
2719 * @arg @ref LL_RCC_PLLI2SM_DIV_37
2720 * @arg @ref LL_RCC_PLLI2SM_DIV_38
2721 * @arg @ref LL_RCC_PLLI2SM_DIV_39
2722 * @arg @ref LL_RCC_PLLI2SM_DIV_40
2723 * @arg @ref LL_RCC_PLLI2SM_DIV_41
2724 * @arg @ref LL_RCC_PLLI2SM_DIV_42
2725 * @arg @ref LL_RCC_PLLI2SM_DIV_43
2726 * @arg @ref LL_RCC_PLLI2SM_DIV_44
2727 * @arg @ref LL_RCC_PLLI2SM_DIV_45
2728 * @arg @ref LL_RCC_PLLI2SM_DIV_46
2729 * @arg @ref LL_RCC_PLLI2SM_DIV_47
2730 * @arg @ref LL_RCC_PLLI2SM_DIV_48
2731 * @arg @ref LL_RCC_PLLI2SM_DIV_49
2732 * @arg @ref LL_RCC_PLLI2SM_DIV_50
2733 * @arg @ref LL_RCC_PLLI2SM_DIV_51
2734 * @arg @ref LL_RCC_PLLI2SM_DIV_52
2735 * @arg @ref LL_RCC_PLLI2SM_DIV_53
2736 * @arg @ref LL_RCC_PLLI2SM_DIV_54
2737 * @arg @ref LL_RCC_PLLI2SM_DIV_55
2738 * @arg @ref LL_RCC_PLLI2SM_DIV_56
2739 * @arg @ref LL_RCC_PLLI2SM_DIV_57
2740 * @arg @ref LL_RCC_PLLI2SM_DIV_58
2741 * @arg @ref LL_RCC_PLLI2SM_DIV_59
2742 * @arg @ref LL_RCC_PLLI2SM_DIV_60
2743 * @arg @ref LL_RCC_PLLI2SM_DIV_61
2744 * @arg @ref LL_RCC_PLLI2SM_DIV_62
2745 * @arg @ref LL_RCC_PLLI2SM_DIV_63
2746 * @param __PLLI2SN__ Between 50/192(*) and 432
2747 *
2748 * (*) value not defined in all devices.
2749 * @param __PLLI2SR__ This parameter can be one of the following values:
2750 * @arg @ref LL_RCC_PLLI2SR_DIV_2
2751 * @arg @ref LL_RCC_PLLI2SR_DIV_3
2752 * @arg @ref LL_RCC_PLLI2SR_DIV_4
2753 * @arg @ref LL_RCC_PLLI2SR_DIV_5
2754 * @arg @ref LL_RCC_PLLI2SR_DIV_6
2755 * @arg @ref LL_RCC_PLLI2SR_DIV_7
2756 * @retval PLLI2S clock frequency (in Hz)
2757 */
2758 #define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2759 ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
2760
2761 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
2762 /**
2763 * @brief Helper macro to calculate the PLLI2S frequency used for 48Mhz domain
2764 * @note ex: @ref __LL_RCC_CALC_PLLI2S_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
2765 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ ());
2766 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2767 * @param __PLLM__ This parameter can be one of the following values:
2768 * @arg @ref LL_RCC_PLLI2SM_DIV_2
2769 * @arg @ref LL_RCC_PLLI2SM_DIV_3
2770 * @arg @ref LL_RCC_PLLI2SM_DIV_4
2771 * @arg @ref LL_RCC_PLLI2SM_DIV_5
2772 * @arg @ref LL_RCC_PLLI2SM_DIV_6
2773 * @arg @ref LL_RCC_PLLI2SM_DIV_7
2774 * @arg @ref LL_RCC_PLLI2SM_DIV_8
2775 * @arg @ref LL_RCC_PLLI2SM_DIV_9
2776 * @arg @ref LL_RCC_PLLI2SM_DIV_10
2777 * @arg @ref LL_RCC_PLLI2SM_DIV_11
2778 * @arg @ref LL_RCC_PLLI2SM_DIV_12
2779 * @arg @ref LL_RCC_PLLI2SM_DIV_13
2780 * @arg @ref LL_RCC_PLLI2SM_DIV_14
2781 * @arg @ref LL_RCC_PLLI2SM_DIV_15
2782 * @arg @ref LL_RCC_PLLI2SM_DIV_16
2783 * @arg @ref LL_RCC_PLLI2SM_DIV_17
2784 * @arg @ref LL_RCC_PLLI2SM_DIV_18
2785 * @arg @ref LL_RCC_PLLI2SM_DIV_19
2786 * @arg @ref LL_RCC_PLLI2SM_DIV_20
2787 * @arg @ref LL_RCC_PLLI2SM_DIV_21
2788 * @arg @ref LL_RCC_PLLI2SM_DIV_22
2789 * @arg @ref LL_RCC_PLLI2SM_DIV_23
2790 * @arg @ref LL_RCC_PLLI2SM_DIV_24
2791 * @arg @ref LL_RCC_PLLI2SM_DIV_25
2792 * @arg @ref LL_RCC_PLLI2SM_DIV_26
2793 * @arg @ref LL_RCC_PLLI2SM_DIV_27
2794 * @arg @ref LL_RCC_PLLI2SM_DIV_28
2795 * @arg @ref LL_RCC_PLLI2SM_DIV_29
2796 * @arg @ref LL_RCC_PLLI2SM_DIV_30
2797 * @arg @ref LL_RCC_PLLI2SM_DIV_31
2798 * @arg @ref LL_RCC_PLLI2SM_DIV_32
2799 * @arg @ref LL_RCC_PLLI2SM_DIV_33
2800 * @arg @ref LL_RCC_PLLI2SM_DIV_34
2801 * @arg @ref LL_RCC_PLLI2SM_DIV_35
2802 * @arg @ref LL_RCC_PLLI2SM_DIV_36
2803 * @arg @ref LL_RCC_PLLI2SM_DIV_37
2804 * @arg @ref LL_RCC_PLLI2SM_DIV_38
2805 * @arg @ref LL_RCC_PLLI2SM_DIV_39
2806 * @arg @ref LL_RCC_PLLI2SM_DIV_40
2807 * @arg @ref LL_RCC_PLLI2SM_DIV_41
2808 * @arg @ref LL_RCC_PLLI2SM_DIV_42
2809 * @arg @ref LL_RCC_PLLI2SM_DIV_43
2810 * @arg @ref LL_RCC_PLLI2SM_DIV_44
2811 * @arg @ref LL_RCC_PLLI2SM_DIV_45
2812 * @arg @ref LL_RCC_PLLI2SM_DIV_46
2813 * @arg @ref LL_RCC_PLLI2SM_DIV_47
2814 * @arg @ref LL_RCC_PLLI2SM_DIV_48
2815 * @arg @ref LL_RCC_PLLI2SM_DIV_49
2816 * @arg @ref LL_RCC_PLLI2SM_DIV_50
2817 * @arg @ref LL_RCC_PLLI2SM_DIV_51
2818 * @arg @ref LL_RCC_PLLI2SM_DIV_52
2819 * @arg @ref LL_RCC_PLLI2SM_DIV_53
2820 * @arg @ref LL_RCC_PLLI2SM_DIV_54
2821 * @arg @ref LL_RCC_PLLI2SM_DIV_55
2822 * @arg @ref LL_RCC_PLLI2SM_DIV_56
2823 * @arg @ref LL_RCC_PLLI2SM_DIV_57
2824 * @arg @ref LL_RCC_PLLI2SM_DIV_58
2825 * @arg @ref LL_RCC_PLLI2SM_DIV_59
2826 * @arg @ref LL_RCC_PLLI2SM_DIV_60
2827 * @arg @ref LL_RCC_PLLI2SM_DIV_61
2828 * @arg @ref LL_RCC_PLLI2SM_DIV_62
2829 * @arg @ref LL_RCC_PLLI2SM_DIV_63
2830 * @param __PLLI2SN__ Between 50 and 432
2831 * @param __PLLI2SQ__ This parameter can be one of the following values:
2832 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
2833 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
2834 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
2835 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
2836 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
2837 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
2838 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
2839 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
2840 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
2841 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
2842 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
2843 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
2844 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
2845 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
2846 * @retval PLLI2S clock frequency (in Hz)
2847 */
2848 #define __LL_RCC_CALC_PLLI2S_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2849 ((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos))
2850
2851 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
2852 #endif /* RCC_PLLI2S_SUPPORT */
2853
2854 /**
2855 * @brief Helper macro to calculate the HCLK frequency
2856 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
2857 * @param __AHBPRESCALER__ This parameter can be one of the following values:
2858 * @arg @ref LL_RCC_SYSCLK_DIV_1
2859 * @arg @ref LL_RCC_SYSCLK_DIV_2
2860 * @arg @ref LL_RCC_SYSCLK_DIV_4
2861 * @arg @ref LL_RCC_SYSCLK_DIV_8
2862 * @arg @ref LL_RCC_SYSCLK_DIV_16
2863 * @arg @ref LL_RCC_SYSCLK_DIV_64
2864 * @arg @ref LL_RCC_SYSCLK_DIV_128
2865 * @arg @ref LL_RCC_SYSCLK_DIV_256
2866 * @arg @ref LL_RCC_SYSCLK_DIV_512
2867 * @retval HCLK clock frequency (in Hz)
2868 */
2869 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
2870
2871 /**
2872 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
2873 * @param __HCLKFREQ__ HCLK frequency
2874 * @param __APB1PRESCALER__ This parameter can be one of the following values:
2875 * @arg @ref LL_RCC_APB1_DIV_1
2876 * @arg @ref LL_RCC_APB1_DIV_2
2877 * @arg @ref LL_RCC_APB1_DIV_4
2878 * @arg @ref LL_RCC_APB1_DIV_8
2879 * @arg @ref LL_RCC_APB1_DIV_16
2880 * @retval PCLK1 clock frequency (in Hz)
2881 */
2882 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
2883
2884 /**
2885 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
2886 * @param __HCLKFREQ__ HCLK frequency
2887 * @param __APB2PRESCALER__ This parameter can be one of the following values:
2888 * @arg @ref LL_RCC_APB2_DIV_1
2889 * @arg @ref LL_RCC_APB2_DIV_2
2890 * @arg @ref LL_RCC_APB2_DIV_4
2891 * @arg @ref LL_RCC_APB2_DIV_8
2892 * @arg @ref LL_RCC_APB2_DIV_16
2893 * @retval PCLK2 clock frequency (in Hz)
2894 */
2895 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
2896
2897 /**
2898 * @}
2899 */
2900
2901 /**
2902 * @}
2903 */
2904
2905 /* Exported functions --------------------------------------------------------*/
2906 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
2907 * @{
2908 */
2909
2910 /** @defgroup RCC_LL_EF_HSE HSE
2911 * @{
2912 */
2913
2914 /**
2915 * @brief Enable the Clock Security System.
2916 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
2917 * @retval None
2918 */
LL_RCC_HSE_EnableCSS(void)2919 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
2920 {
2921 SET_BIT(RCC->CR, RCC_CR_CSSON);
2922 }
2923
2924 /**
2925 * @brief Enable HSE external oscillator (HSE Bypass)
2926 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
2927 * @retval None
2928 */
LL_RCC_HSE_EnableBypass(void)2929 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
2930 {
2931 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
2932 }
2933
2934 /**
2935 * @brief Disable HSE external oscillator (HSE Bypass)
2936 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
2937 * @retval None
2938 */
LL_RCC_HSE_DisableBypass(void)2939 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
2940 {
2941 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
2942 }
2943
2944 /**
2945 * @brief Enable HSE crystal oscillator (HSE ON)
2946 * @rmtoll CR HSEON LL_RCC_HSE_Enable
2947 * @retval None
2948 */
LL_RCC_HSE_Enable(void)2949 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
2950 {
2951 SET_BIT(RCC->CR, RCC_CR_HSEON);
2952 }
2953
2954 /**
2955 * @brief Disable HSE crystal oscillator (HSE ON)
2956 * @rmtoll CR HSEON LL_RCC_HSE_Disable
2957 * @retval None
2958 */
LL_RCC_HSE_Disable(void)2959 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
2960 {
2961 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
2962 }
2963
2964 /**
2965 * @brief Check if HSE oscillator Ready
2966 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
2967 * @retval State of bit (1 or 0).
2968 */
LL_RCC_HSE_IsReady(void)2969 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
2970 {
2971 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
2972 }
2973
2974 /**
2975 * @}
2976 */
2977
2978 /** @defgroup RCC_LL_EF_HSI HSI
2979 * @{
2980 */
2981
2982 /**
2983 * @brief Enable HSI oscillator
2984 * @rmtoll CR HSION LL_RCC_HSI_Enable
2985 * @retval None
2986 */
LL_RCC_HSI_Enable(void)2987 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
2988 {
2989 SET_BIT(RCC->CR, RCC_CR_HSION);
2990 }
2991
2992 /**
2993 * @brief Disable HSI oscillator
2994 * @rmtoll CR HSION LL_RCC_HSI_Disable
2995 * @retval None
2996 */
LL_RCC_HSI_Disable(void)2997 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
2998 {
2999 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
3000 }
3001
3002 /**
3003 * @brief Check if HSI clock is ready
3004 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
3005 * @retval State of bit (1 or 0).
3006 */
LL_RCC_HSI_IsReady(void)3007 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
3008 {
3009 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
3010 }
3011
3012 /**
3013 * @brief Get HSI Calibration value
3014 * @note When HSITRIM is written, HSICAL is updated with the sum of
3015 * HSITRIM and the factory trim value
3016 * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
3017 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
3018 */
LL_RCC_HSI_GetCalibration(void)3019 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
3020 {
3021 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
3022 }
3023
3024 /**
3025 * @brief Set HSI Calibration trimming
3026 * @note user-programmable trimming value that is added to the HSICAL
3027 * @note Default value is 16, which, when added to the HSICAL value,
3028 * should trim the HSI to 16 MHz +/- 1 %
3029 * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
3030 * @param Value Between Min_Data = 0 and Max_Data = 31
3031 * @retval None
3032 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)3033 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
3034 {
3035 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
3036 }
3037
3038 /**
3039 * @brief Get HSI Calibration trimming
3040 * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
3041 * @retval Between Min_Data = 0 and Max_Data = 31
3042 */
LL_RCC_HSI_GetCalibTrimming(void)3043 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
3044 {
3045 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
3046 }
3047
3048 /**
3049 * @}
3050 */
3051
3052 /** @defgroup RCC_LL_EF_LSE LSE
3053 * @{
3054 */
3055
3056 /**
3057 * @brief Enable Low Speed External (LSE) crystal.
3058 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
3059 * @retval None
3060 */
LL_RCC_LSE_Enable(void)3061 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
3062 {
3063 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
3064 }
3065
3066 /**
3067 * @brief Disable Low Speed External (LSE) crystal.
3068 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
3069 * @retval None
3070 */
LL_RCC_LSE_Disable(void)3071 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
3072 {
3073 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
3074 }
3075
3076 /**
3077 * @brief Enable external clock source (LSE bypass).
3078 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
3079 * @retval None
3080 */
LL_RCC_LSE_EnableBypass(void)3081 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
3082 {
3083 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
3084 }
3085
3086 /**
3087 * @brief Disable external clock source (LSE bypass).
3088 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
3089 * @retval None
3090 */
LL_RCC_LSE_DisableBypass(void)3091 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
3092 {
3093 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
3094 }
3095
3096 /**
3097 * @brief Check if LSE oscillator Ready
3098 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
3099 * @retval State of bit (1 or 0).
3100 */
LL_RCC_LSE_IsReady(void)3101 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
3102 {
3103 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
3104 }
3105
3106 #if defined(RCC_BDCR_LSEMOD)
3107 /**
3108 * @brief Enable LSE high drive mode.
3109 * @note LSE high drive mode can be enabled only when the LSE clock is disabled
3110 * @rmtoll BDCR LSEMOD LL_RCC_LSE_EnableHighDriveMode
3111 * @retval None
3112 */
LL_RCC_LSE_EnableHighDriveMode(void)3113 __STATIC_INLINE void LL_RCC_LSE_EnableHighDriveMode(void)
3114 {
3115 SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
3116 }
3117
3118 /**
3119 * @brief Disable LSE high drive mode.
3120 * @note LSE high drive mode can be disabled only when the LSE clock is disabled
3121 * @rmtoll BDCR LSEMOD LL_RCC_LSE_DisableHighDriveMode
3122 * @retval None
3123 */
LL_RCC_LSE_DisableHighDriveMode(void)3124 __STATIC_INLINE void LL_RCC_LSE_DisableHighDriveMode(void)
3125 {
3126 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
3127 }
3128 #endif /* RCC_BDCR_LSEMOD */
3129
3130 /**
3131 * @}
3132 */
3133
3134 /** @defgroup RCC_LL_EF_LSI LSI
3135 * @{
3136 */
3137
3138 /**
3139 * @brief Enable LSI Oscillator
3140 * @rmtoll CSR LSION LL_RCC_LSI_Enable
3141 * @retval None
3142 */
LL_RCC_LSI_Enable(void)3143 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
3144 {
3145 SET_BIT(RCC->CSR, RCC_CSR_LSION);
3146 }
3147
3148 /**
3149 * @brief Disable LSI Oscillator
3150 * @rmtoll CSR LSION LL_RCC_LSI_Disable
3151 * @retval None
3152 */
LL_RCC_LSI_Disable(void)3153 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
3154 {
3155 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
3156 }
3157
3158 /**
3159 * @brief Check if LSI is Ready
3160 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
3161 * @retval State of bit (1 or 0).
3162 */
LL_RCC_LSI_IsReady(void)3163 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
3164 {
3165 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
3166 }
3167
3168 /**
3169 * @}
3170 */
3171
3172 /** @defgroup RCC_LL_EF_System System
3173 * @{
3174 */
3175
3176 /**
3177 * @brief Configure the system clock source
3178 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
3179 * @param Source This parameter can be one of the following values:
3180 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
3181 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
3182 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
3183 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLLR (*)
3184 *
3185 * (*) value not defined in all devices.
3186 * @retval None
3187 */
LL_RCC_SetSysClkSource(uint32_t Source)3188 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
3189 {
3190 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
3191 }
3192
3193 /**
3194 * @brief Get the system clock source
3195 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
3196 * @retval Returned value can be one of the following values:
3197 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
3198 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
3199 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
3200 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLLR (*)
3201 *
3202 * (*) value not defined in all devices.
3203 */
LL_RCC_GetSysClkSource(void)3204 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
3205 {
3206 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
3207 }
3208
3209 /**
3210 * @brief Set AHB prescaler
3211 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
3212 * @param Prescaler This parameter can be one of the following values:
3213 * @arg @ref LL_RCC_SYSCLK_DIV_1
3214 * @arg @ref LL_RCC_SYSCLK_DIV_2
3215 * @arg @ref LL_RCC_SYSCLK_DIV_4
3216 * @arg @ref LL_RCC_SYSCLK_DIV_8
3217 * @arg @ref LL_RCC_SYSCLK_DIV_16
3218 * @arg @ref LL_RCC_SYSCLK_DIV_64
3219 * @arg @ref LL_RCC_SYSCLK_DIV_128
3220 * @arg @ref LL_RCC_SYSCLK_DIV_256
3221 * @arg @ref LL_RCC_SYSCLK_DIV_512
3222 * @retval None
3223 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)3224 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
3225 {
3226 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
3227 }
3228
3229 /**
3230 * @brief Set APB1 prescaler
3231 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
3232 * @param Prescaler This parameter can be one of the following values:
3233 * @arg @ref LL_RCC_APB1_DIV_1
3234 * @arg @ref LL_RCC_APB1_DIV_2
3235 * @arg @ref LL_RCC_APB1_DIV_4
3236 * @arg @ref LL_RCC_APB1_DIV_8
3237 * @arg @ref LL_RCC_APB1_DIV_16
3238 * @retval None
3239 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)3240 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
3241 {
3242 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
3243 }
3244
3245 /**
3246 * @brief Set APB2 prescaler
3247 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
3248 * @param Prescaler This parameter can be one of the following values:
3249 * @arg @ref LL_RCC_APB2_DIV_1
3250 * @arg @ref LL_RCC_APB2_DIV_2
3251 * @arg @ref LL_RCC_APB2_DIV_4
3252 * @arg @ref LL_RCC_APB2_DIV_8
3253 * @arg @ref LL_RCC_APB2_DIV_16
3254 * @retval None
3255 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)3256 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
3257 {
3258 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
3259 }
3260
3261 /**
3262 * @brief Get AHB prescaler
3263 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
3264 * @retval Returned value can be one of the following values:
3265 * @arg @ref LL_RCC_SYSCLK_DIV_1
3266 * @arg @ref LL_RCC_SYSCLK_DIV_2
3267 * @arg @ref LL_RCC_SYSCLK_DIV_4
3268 * @arg @ref LL_RCC_SYSCLK_DIV_8
3269 * @arg @ref LL_RCC_SYSCLK_DIV_16
3270 * @arg @ref LL_RCC_SYSCLK_DIV_64
3271 * @arg @ref LL_RCC_SYSCLK_DIV_128
3272 * @arg @ref LL_RCC_SYSCLK_DIV_256
3273 * @arg @ref LL_RCC_SYSCLK_DIV_512
3274 */
LL_RCC_GetAHBPrescaler(void)3275 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
3276 {
3277 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
3278 }
3279
3280 /**
3281 * @brief Get APB1 prescaler
3282 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
3283 * @retval Returned value can be one of the following values:
3284 * @arg @ref LL_RCC_APB1_DIV_1
3285 * @arg @ref LL_RCC_APB1_DIV_2
3286 * @arg @ref LL_RCC_APB1_DIV_4
3287 * @arg @ref LL_RCC_APB1_DIV_8
3288 * @arg @ref LL_RCC_APB1_DIV_16
3289 */
LL_RCC_GetAPB1Prescaler(void)3290 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
3291 {
3292 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
3293 }
3294
3295 /**
3296 * @brief Get APB2 prescaler
3297 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
3298 * @retval Returned value can be one of the following values:
3299 * @arg @ref LL_RCC_APB2_DIV_1
3300 * @arg @ref LL_RCC_APB2_DIV_2
3301 * @arg @ref LL_RCC_APB2_DIV_4
3302 * @arg @ref LL_RCC_APB2_DIV_8
3303 * @arg @ref LL_RCC_APB2_DIV_16
3304 */
LL_RCC_GetAPB2Prescaler(void)3305 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
3306 {
3307 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
3308 }
3309
3310 /**
3311 * @}
3312 */
3313
3314 /** @defgroup RCC_LL_EF_MCO MCO
3315 * @{
3316 */
3317
3318 #if defined(RCC_CFGR_MCO1EN)
3319 /**
3320 * @brief Enable MCO1 output
3321 * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Enable
3322 * @retval None
3323 */
LL_RCC_MCO1_Enable(void)3324 __STATIC_INLINE void LL_RCC_MCO1_Enable(void)
3325 {
3326 SET_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
3327 }
3328
3329 /**
3330 * @brief Disable MCO1 output
3331 * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Disable
3332 * @retval None
3333 */
LL_RCC_MCO1_Disable(void)3334 __STATIC_INLINE void LL_RCC_MCO1_Disable(void)
3335 {
3336 CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
3337 }
3338 #endif /* RCC_CFGR_MCO1EN */
3339
3340 #if defined(RCC_CFGR_MCO2EN)
3341 /**
3342 * @brief Enable MCO2 output
3343 * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Enable
3344 * @retval None
3345 */
LL_RCC_MCO2_Enable(void)3346 __STATIC_INLINE void LL_RCC_MCO2_Enable(void)
3347 {
3348 SET_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
3349 }
3350
3351 /**
3352 * @brief Disable MCO2 output
3353 * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Disable
3354 * @retval None
3355 */
LL_RCC_MCO2_Disable(void)3356 __STATIC_INLINE void LL_RCC_MCO2_Disable(void)
3357 {
3358 CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
3359 }
3360 #endif /* RCC_CFGR_MCO2EN */
3361
3362 /**
3363 * @brief Configure MCOx
3364 * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
3365 * CFGR MCO1PRE LL_RCC_ConfigMCO\n
3366 * CFGR MCO2 LL_RCC_ConfigMCO\n
3367 * CFGR MCO2PRE LL_RCC_ConfigMCO
3368 * @param MCOxSource This parameter can be one of the following values:
3369 * @arg @ref LL_RCC_MCO1SOURCE_HSI
3370 * @arg @ref LL_RCC_MCO1SOURCE_LSE
3371 * @arg @ref LL_RCC_MCO1SOURCE_HSE
3372 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
3373 * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
3374 * @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
3375 * @arg @ref LL_RCC_MCO2SOURCE_HSE
3376 * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
3377 * @param MCOxPrescaler This parameter can be one of the following values:
3378 * @arg @ref LL_RCC_MCO1_DIV_1
3379 * @arg @ref LL_RCC_MCO1_DIV_2
3380 * @arg @ref LL_RCC_MCO1_DIV_3
3381 * @arg @ref LL_RCC_MCO1_DIV_4
3382 * @arg @ref LL_RCC_MCO1_DIV_5
3383 * @arg @ref LL_RCC_MCO2_DIV_1
3384 * @arg @ref LL_RCC_MCO2_DIV_2
3385 * @arg @ref LL_RCC_MCO2_DIV_3
3386 * @arg @ref LL_RCC_MCO2_DIV_4
3387 * @arg @ref LL_RCC_MCO2_DIV_5
3388 * @retval None
3389 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)3390 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
3391 {
3392 MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) | (MCOxPrescaler << 16U));
3393 }
3394
3395 /**
3396 * @}
3397 */
3398
3399 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
3400 * @{
3401 */
3402 #if defined(FMPI2C1)
3403 /**
3404 * @brief Configure FMPI2C clock source
3405 * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_SetFMPI2CClockSource
3406 * @param FMPI2CxSource This parameter can be one of the following values:
3407 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
3408 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
3409 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
3410 * @retval None
3411 */
LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource)3412 __STATIC_INLINE void LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource)
3413 {
3414 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, FMPI2CxSource);
3415 }
3416 #endif /* FMPI2C1 */
3417
3418 #if defined(LPTIM1)
3419 /**
3420 * @brief Configure LPTIMx clock source
3421 * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource
3422 * @param LPTIMxSource This parameter can be one of the following values:
3423 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3424 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
3425 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3426 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3427 * @retval None
3428 */
LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)3429 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
3430 {
3431 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);
3432 }
3433 #endif /* LPTIM1 */
3434
3435 #if defined(SAI1)
3436 /**
3437 * @brief Configure SAIx clock source
3438 * @rmtoll DCKCFGR SAI1SRC LL_RCC_SetSAIClockSource\n
3439 * DCKCFGR SAI2SRC LL_RCC_SetSAIClockSource\n
3440 * DCKCFGR SAI1ASRC LL_RCC_SetSAIClockSource\n
3441 * DCKCFGR SAI1BSRC LL_RCC_SetSAIClockSource
3442 * @param SAIxSource This parameter can be one of the following values:
3443 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
3444 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
3445 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
3446 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
3447 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
3448 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
3449 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
3450 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
3451 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
3452 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
3453 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
3454 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
3455 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
3456 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
3457 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
3458 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
3459 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*)
3460 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
3461 *
3462 * (*) value not defined in all devices.
3463 * @retval None
3464 */
LL_RCC_SetSAIClockSource(uint32_t SAIxSource)3465 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
3466 {
3467 MODIFY_REG(RCC->DCKCFGR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
3468 }
3469 #endif /* SAI1 */
3470
3471 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
3472 /**
3473 * @brief Configure SDIO clock source
3474 * @rmtoll DCKCFGR SDIOSEL LL_RCC_SetSDIOClockSource\n
3475 * DCKCFGR2 SDIOSEL LL_RCC_SetSDIOClockSource
3476 * @param SDIOxSource This parameter can be one of the following values:
3477 * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
3478 * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
3479 * @retval None
3480 */
LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource)3481 __STATIC_INLINE void LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource)
3482 {
3483 #if defined(RCC_DCKCFGR_SDIOSEL)
3484 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, SDIOxSource);
3485 #else
3486 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, SDIOxSource);
3487 #endif /* RCC_DCKCFGR_SDIOSEL */
3488 }
3489 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
3490
3491 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
3492 /**
3493 * @brief Configure 48Mhz domain clock source
3494 * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetCK48MClockSource\n
3495 * DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource
3496 * @param CK48MxSource This parameter can be one of the following values:
3497 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
3498 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
3499 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
3500 *
3501 * (*) value not defined in all devices.
3502 * @retval None
3503 */
LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)3504 __STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)
3505 {
3506 #if defined(RCC_DCKCFGR_CK48MSEL)
3507 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, CK48MxSource);
3508 #else
3509 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);
3510 #endif /* RCC_DCKCFGR_CK48MSEL */
3511 }
3512
3513 #if defined(RNG)
3514 /**
3515 * @brief Configure RNG clock source
3516 * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetRNGClockSource\n
3517 * DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource
3518 * @param RNGxSource This parameter can be one of the following values:
3519 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
3520 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
3521 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
3522 *
3523 * (*) value not defined in all devices.
3524 * @retval None
3525 */
LL_RCC_SetRNGClockSource(uint32_t RNGxSource)3526 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
3527 {
3528 #if defined(RCC_DCKCFGR_CK48MSEL)
3529 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, RNGxSource);
3530 #else
3531 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);
3532 #endif /* RCC_DCKCFGR_CK48MSEL */
3533 }
3534 #endif /* RNG */
3535
3536 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
3537 /**
3538 * @brief Configure USB clock source
3539 * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetUSBClockSource\n
3540 * DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource
3541 * @param USBxSource This parameter can be one of the following values:
3542 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
3543 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
3544 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
3545 *
3546 * (*) value not defined in all devices.
3547 * @retval None
3548 */
LL_RCC_SetUSBClockSource(uint32_t USBxSource)3549 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
3550 {
3551 #if defined(RCC_DCKCFGR_CK48MSEL)
3552 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, USBxSource);
3553 #else
3554 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);
3555 #endif /* RCC_DCKCFGR_CK48MSEL */
3556 }
3557 #endif /* USB_OTG_FS || USB_OTG_HS */
3558 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
3559
3560 #if defined(CEC)
3561 /**
3562 * @brief Configure CEC clock source
3563 * @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource
3564 * @param Source This parameter can be one of the following values:
3565 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
3566 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
3567 * @retval None
3568 */
LL_RCC_SetCECClockSource(uint32_t Source)3569 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)
3570 {
3571 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);
3572 }
3573 #endif /* CEC */
3574
3575 /**
3576 * @brief Configure I2S clock source
3577 * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource\n
3578 * DCKCFGR I2SSRC LL_RCC_SetI2SClockSource\n
3579 * DCKCFGR I2S1SRC LL_RCC_SetI2SClockSource\n
3580 * DCKCFGR I2S2SRC LL_RCC_SetI2SClockSource
3581 * @param Source This parameter can be one of the following values:
3582 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
3583 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
3584 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
3585 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
3586 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
3587 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
3588 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
3589 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
3590 *
3591 * (*) value not defined in all devices.
3592 * @retval None
3593 */
LL_RCC_SetI2SClockSource(uint32_t Source)3594 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
3595 {
3596 #if defined(RCC_CFGR_I2SSRC)
3597 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
3598 #else
3599 MODIFY_REG(RCC->DCKCFGR, (Source & 0xFFFF0000U), (Source << 16U));
3600 #endif /* RCC_CFGR_I2SSRC */
3601 }
3602
3603 #if defined(DSI)
3604 /**
3605 * @brief Configure DSI clock source
3606 * @rmtoll DCKCFGR DSISEL LL_RCC_SetDSIClockSource
3607 * @param Source This parameter can be one of the following values:
3608 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
3609 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
3610 * @retval None
3611 */
LL_RCC_SetDSIClockSource(uint32_t Source)3612 __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
3613 {
3614 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, Source);
3615 }
3616 #endif /* DSI */
3617
3618 #if defined(DFSDM1_Channel0)
3619 /**
3620 * @brief Configure DFSDM Audio clock source
3621 * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_SetDFSDMAudioClockSource\n
3622 * DCKCFGR CKDFSDM2ASEL LL_RCC_SetDFSDMAudioClockSource
3623 * @param Source This parameter can be one of the following values:
3624 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
3625 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
3626 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
3627 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
3628 *
3629 * (*) value not defined in all devices.
3630 * @retval None
3631 */
LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)3632 __STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
3633 {
3634 MODIFY_REG(RCC->DCKCFGR, (Source & 0x0000FFFFU), (Source >> 16U));
3635 }
3636
3637 /**
3638 * @brief Configure DFSDM Kernel clock source
3639 * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_SetDFSDMClockSource
3640 * @param Source This parameter can be one of the following values:
3641 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
3642 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
3643 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
3644 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
3645 *
3646 * (*) value not defined in all devices.
3647 * @retval None
3648 */
LL_RCC_SetDFSDMClockSource(uint32_t Source)3649 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)
3650 {
3651 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, Source);
3652 }
3653 #endif /* DFSDM1_Channel0 */
3654
3655 #if defined(SPDIFRX)
3656 /**
3657 * @brief Configure SPDIFRX clock source
3658 * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_SetSPDIFRXClockSource
3659 * @param SPDIFRXxSource This parameter can be one of the following values:
3660 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
3661 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
3662 *
3663 * (*) value not defined in all devices.
3664 * @retval None
3665 */
LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource)3666 __STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource)
3667 {
3668 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, SPDIFRXxSource);
3669 }
3670 #endif /* SPDIFRX */
3671
3672 #if defined(FMPI2C1)
3673 /**
3674 * @brief Get FMPI2C clock source
3675 * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_GetFMPI2CClockSource
3676 * @param FMPI2Cx This parameter can be one of the following values:
3677 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE
3678 * @retval Returned value can be one of the following values:
3679 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
3680 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
3681 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
3682 */
LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx)3683 __STATIC_INLINE uint32_t LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx)
3684 {
3685 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, FMPI2Cx));
3686 }
3687 #endif /* FMPI2C1 */
3688
3689 #if defined(LPTIM1)
3690 /**
3691 * @brief Get LPTIMx clock source
3692 * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource
3693 * @param LPTIMx This parameter can be one of the following values:
3694 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
3695 * @retval Returned value can be one of the following values:
3696 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3697 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
3698 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3699 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3700 */
LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)3701 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
3702 {
3703 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));
3704 }
3705 #endif /* LPTIM1 */
3706
3707 #if defined(SAI1)
3708 /**
3709 * @brief Get SAIx clock source
3710 * @rmtoll DCKCFGR SAI1SEL LL_RCC_GetSAIClockSource\n
3711 * DCKCFGR SAI2SEL LL_RCC_GetSAIClockSource\n
3712 * DCKCFGR SAI1ASRC LL_RCC_GetSAIClockSource\n
3713 * DCKCFGR SAI1BSRC LL_RCC_GetSAIClockSource
3714 * @param SAIx This parameter can be one of the following values:
3715 * @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
3716 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
3717 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)
3718 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)
3719 *
3720 * (*) value not defined in all devices.
3721 * @retval Returned value can be one of the following values:
3722 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
3723 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
3724 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
3725 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
3726 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
3727 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
3728 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
3729 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
3730 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
3731 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
3732 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
3733 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
3734 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
3735 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
3736 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
3737 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
3738 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*)
3739 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
3740 *
3741 * (*) value not defined in all devices.
3742 */
LL_RCC_GetSAIClockSource(uint32_t SAIx)3743 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
3744 {
3745 return (uint32_t)(READ_BIT(RCC->DCKCFGR, SAIx) >> 16U | SAIx);
3746 }
3747 #endif /* SAI1 */
3748
3749 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
3750 /**
3751 * @brief Get SDIOx clock source
3752 * @rmtoll DCKCFGR SDIOSEL LL_RCC_GetSDIOClockSource\n
3753 * DCKCFGR2 SDIOSEL LL_RCC_GetSDIOClockSource
3754 * @param SDIOx This parameter can be one of the following values:
3755 * @arg @ref LL_RCC_SDIO_CLKSOURCE
3756 * @retval Returned value can be one of the following values:
3757 * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
3758 * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
3759 */
LL_RCC_GetSDIOClockSource(uint32_t SDIOx)3760 __STATIC_INLINE uint32_t LL_RCC_GetSDIOClockSource(uint32_t SDIOx)
3761 {
3762 #if defined(RCC_DCKCFGR_SDIOSEL)
3763 return (uint32_t)(READ_BIT(RCC->DCKCFGR, SDIOx));
3764 #else
3765 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDIOx));
3766 #endif /* RCC_DCKCFGR_SDIOSEL */
3767 }
3768 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
3769
3770 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
3771 /**
3772 * @brief Get 48Mhz domain clock source
3773 * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetCK48MClockSource\n
3774 * DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource
3775 * @param CK48Mx This parameter can be one of the following values:
3776 * @arg @ref LL_RCC_CK48M_CLKSOURCE
3777 * @retval Returned value can be one of the following values:
3778 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
3779 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
3780 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
3781 *
3782 * (*) value not defined in all devices.
3783 */
LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)3784 __STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)
3785 {
3786 #if defined(RCC_DCKCFGR_CK48MSEL)
3787 return (uint32_t)(READ_BIT(RCC->DCKCFGR, CK48Mx));
3788 #else
3789 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));
3790 #endif /* RCC_DCKCFGR_CK48MSEL */
3791 }
3792
3793 #if defined(RNG)
3794 /**
3795 * @brief Get RNGx clock source
3796 * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetRNGClockSource\n
3797 * DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource
3798 * @param RNGx This parameter can be one of the following values:
3799 * @arg @ref LL_RCC_RNG_CLKSOURCE
3800 * @retval Returned value can be one of the following values:
3801 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
3802 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
3803 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
3804 *
3805 * (*) value not defined in all devices.
3806 */
LL_RCC_GetRNGClockSource(uint32_t RNGx)3807 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
3808 {
3809 #if defined(RCC_DCKCFGR_CK48MSEL)
3810 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RNGx));
3811 #else
3812 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));
3813 #endif /* RCC_DCKCFGR_CK48MSEL */
3814 }
3815 #endif /* RNG */
3816
3817 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
3818 /**
3819 * @brief Get USBx clock source
3820 * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetUSBClockSource\n
3821 * DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource
3822 * @param USBx This parameter can be one of the following values:
3823 * @arg @ref LL_RCC_USB_CLKSOURCE
3824 * @retval Returned value can be one of the following values:
3825 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
3826 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
3827 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
3828 *
3829 * (*) value not defined in all devices.
3830 */
LL_RCC_GetUSBClockSource(uint32_t USBx)3831 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
3832 {
3833 #if defined(RCC_DCKCFGR_CK48MSEL)
3834 return (uint32_t)(READ_BIT(RCC->DCKCFGR, USBx));
3835 #else
3836 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));
3837 #endif /* RCC_DCKCFGR_CK48MSEL */
3838 }
3839 #endif /* USB_OTG_FS || USB_OTG_HS */
3840 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
3841
3842 #if defined(CEC)
3843 /**
3844 * @brief Get CEC Clock Source
3845 * @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource
3846 * @param CECx This parameter can be one of the following values:
3847 * @arg @ref LL_RCC_CEC_CLKSOURCE
3848 * @retval Returned value can be one of the following values:
3849 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
3850 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
3851 */
LL_RCC_GetCECClockSource(uint32_t CECx)3852 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
3853 {
3854 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));
3855 }
3856 #endif /* CEC */
3857
3858 /**
3859 * @brief Get I2S Clock Source
3860 * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource\n
3861 * DCKCFGR I2SSRC LL_RCC_GetI2SClockSource\n
3862 * DCKCFGR I2S1SRC LL_RCC_GetI2SClockSource\n
3863 * DCKCFGR I2S2SRC LL_RCC_GetI2SClockSource
3864 * @param I2Sx This parameter can be one of the following values:
3865 * @arg @ref LL_RCC_I2S1_CLKSOURCE
3866 * @arg @ref LL_RCC_I2S2_CLKSOURCE (*)
3867 * @retval Returned value can be one of the following values:
3868 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
3869 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
3870 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
3871 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
3872 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
3873 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
3874 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
3875 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
3876 *
3877 * (*) value not defined in all devices.
3878 */
LL_RCC_GetI2SClockSource(uint32_t I2Sx)3879 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
3880 {
3881 #if defined(RCC_CFGR_I2SSRC)
3882 return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
3883 #else
3884 return (uint32_t)(READ_BIT(RCC->DCKCFGR, I2Sx) >> 16U | I2Sx);
3885 #endif /* RCC_CFGR_I2SSRC */
3886 }
3887
3888 #if defined(DFSDM1_Channel0)
3889 /**
3890 * @brief Get DFSDM Audio Clock Source
3891 * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_GetDFSDMAudioClockSource\n
3892 * DCKCFGR CKDFSDM2ASEL LL_RCC_GetDFSDMAudioClockSource
3893 * @param DFSDMx This parameter can be one of the following values:
3894 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
3895 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)
3896 * @retval Returned value can be one of the following values:
3897 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
3898 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
3899 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
3900 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
3901 *
3902 * (*) value not defined in all devices.
3903 */
LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)3904 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
3905 {
3906 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx) << 16U | DFSDMx);
3907 }
3908
3909 /**
3910 * @brief Get DFSDM Audio Clock Source
3911 * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_GetDFSDMClockSource
3912 * @param DFSDMx This parameter can be one of the following values:
3913 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
3914 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)
3915 * @retval Returned value can be one of the following values:
3916 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
3917 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
3918 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
3919 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
3920 *
3921 * (*) value not defined in all devices.
3922 */
LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)3923 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
3924 {
3925 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx));
3926 }
3927 #endif /* DFSDM1_Channel0 */
3928
3929 #if defined(SPDIFRX)
3930 /**
3931 * @brief Get SPDIFRX clock source
3932 * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_GetSPDIFRXClockSource
3933 * @param SPDIFRXx This parameter can be one of the following values:
3934 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
3935 * @retval Returned value can be one of the following values:
3936 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
3937 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
3938 *
3939 * (*) value not defined in all devices.
3940 */
LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx)3941 __STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx)
3942 {
3943 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SPDIFRXx));
3944 }
3945 #endif /* SPDIFRX */
3946
3947 #if defined(DSI)
3948 /**
3949 * @brief Get DSI Clock Source
3950 * @rmtoll DCKCFGR DSISEL LL_RCC_GetDSIClockSource
3951 * @param DSIx This parameter can be one of the following values:
3952 * @arg @ref LL_RCC_DSI_CLKSOURCE
3953 * @retval Returned value can be one of the following values:
3954 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
3955 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
3956 */
LL_RCC_GetDSIClockSource(uint32_t DSIx)3957 __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
3958 {
3959 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DSIx));
3960 }
3961 #endif /* DSI */
3962
3963 /**
3964 * @}
3965 */
3966
3967 /** @defgroup RCC_LL_EF_RTC RTC
3968 * @{
3969 */
3970
3971 /**
3972 * @brief Set RTC Clock Source
3973 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
3974 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
3975 * set). The BDRST bit can be used to reset them.
3976 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
3977 * @param Source This parameter can be one of the following values:
3978 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3979 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
3980 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
3981 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
3982 * @retval None
3983 */
LL_RCC_SetRTCClockSource(uint32_t Source)3984 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
3985 {
3986 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
3987 }
3988
3989 /**
3990 * @brief Get RTC Clock Source
3991 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
3992 * @retval Returned value can be one of the following values:
3993 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3994 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
3995 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
3996 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
3997 */
LL_RCC_GetRTCClockSource(void)3998 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
3999 {
4000 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
4001 }
4002
4003 /**
4004 * @brief Enable RTC
4005 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
4006 * @retval None
4007 */
LL_RCC_EnableRTC(void)4008 __STATIC_INLINE void LL_RCC_EnableRTC(void)
4009 {
4010 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
4011 }
4012
4013 /**
4014 * @brief Disable RTC
4015 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
4016 * @retval None
4017 */
LL_RCC_DisableRTC(void)4018 __STATIC_INLINE void LL_RCC_DisableRTC(void)
4019 {
4020 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
4021 }
4022
4023 /**
4024 * @brief Check if RTC has been enabled or not
4025 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
4026 * @retval State of bit (1 or 0).
4027 */
LL_RCC_IsEnabledRTC(void)4028 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
4029 {
4030 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
4031 }
4032
4033 /**
4034 * @brief Force the Backup domain reset
4035 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
4036 * @retval None
4037 */
LL_RCC_ForceBackupDomainReset(void)4038 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
4039 {
4040 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
4041 }
4042
4043 /**
4044 * @brief Release the Backup domain reset
4045 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
4046 * @retval None
4047 */
LL_RCC_ReleaseBackupDomainReset(void)4048 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
4049 {
4050 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
4051 }
4052
4053 /**
4054 * @brief Set HSE Prescalers for RTC Clock
4055 * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
4056 * @param Prescaler This parameter can be one of the following values:
4057 * @arg @ref LL_RCC_RTC_NOCLOCK
4058 * @arg @ref LL_RCC_RTC_HSE_DIV_2
4059 * @arg @ref LL_RCC_RTC_HSE_DIV_3
4060 * @arg @ref LL_RCC_RTC_HSE_DIV_4
4061 * @arg @ref LL_RCC_RTC_HSE_DIV_5
4062 * @arg @ref LL_RCC_RTC_HSE_DIV_6
4063 * @arg @ref LL_RCC_RTC_HSE_DIV_7
4064 * @arg @ref LL_RCC_RTC_HSE_DIV_8
4065 * @arg @ref LL_RCC_RTC_HSE_DIV_9
4066 * @arg @ref LL_RCC_RTC_HSE_DIV_10
4067 * @arg @ref LL_RCC_RTC_HSE_DIV_11
4068 * @arg @ref LL_RCC_RTC_HSE_DIV_12
4069 * @arg @ref LL_RCC_RTC_HSE_DIV_13
4070 * @arg @ref LL_RCC_RTC_HSE_DIV_14
4071 * @arg @ref LL_RCC_RTC_HSE_DIV_15
4072 * @arg @ref LL_RCC_RTC_HSE_DIV_16
4073 * @arg @ref LL_RCC_RTC_HSE_DIV_17
4074 * @arg @ref LL_RCC_RTC_HSE_DIV_18
4075 * @arg @ref LL_RCC_RTC_HSE_DIV_19
4076 * @arg @ref LL_RCC_RTC_HSE_DIV_20
4077 * @arg @ref LL_RCC_RTC_HSE_DIV_21
4078 * @arg @ref LL_RCC_RTC_HSE_DIV_22
4079 * @arg @ref LL_RCC_RTC_HSE_DIV_23
4080 * @arg @ref LL_RCC_RTC_HSE_DIV_24
4081 * @arg @ref LL_RCC_RTC_HSE_DIV_25
4082 * @arg @ref LL_RCC_RTC_HSE_DIV_26
4083 * @arg @ref LL_RCC_RTC_HSE_DIV_27
4084 * @arg @ref LL_RCC_RTC_HSE_DIV_28
4085 * @arg @ref LL_RCC_RTC_HSE_DIV_29
4086 * @arg @ref LL_RCC_RTC_HSE_DIV_30
4087 * @arg @ref LL_RCC_RTC_HSE_DIV_31
4088 * @retval None
4089 */
LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)4090 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
4091 {
4092 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
4093 }
4094
4095 /**
4096 * @brief Get HSE Prescalers for RTC Clock
4097 * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
4098 * @retval Returned value can be one of the following values:
4099 * @arg @ref LL_RCC_RTC_NOCLOCK
4100 * @arg @ref LL_RCC_RTC_HSE_DIV_2
4101 * @arg @ref LL_RCC_RTC_HSE_DIV_3
4102 * @arg @ref LL_RCC_RTC_HSE_DIV_4
4103 * @arg @ref LL_RCC_RTC_HSE_DIV_5
4104 * @arg @ref LL_RCC_RTC_HSE_DIV_6
4105 * @arg @ref LL_RCC_RTC_HSE_DIV_7
4106 * @arg @ref LL_RCC_RTC_HSE_DIV_8
4107 * @arg @ref LL_RCC_RTC_HSE_DIV_9
4108 * @arg @ref LL_RCC_RTC_HSE_DIV_10
4109 * @arg @ref LL_RCC_RTC_HSE_DIV_11
4110 * @arg @ref LL_RCC_RTC_HSE_DIV_12
4111 * @arg @ref LL_RCC_RTC_HSE_DIV_13
4112 * @arg @ref LL_RCC_RTC_HSE_DIV_14
4113 * @arg @ref LL_RCC_RTC_HSE_DIV_15
4114 * @arg @ref LL_RCC_RTC_HSE_DIV_16
4115 * @arg @ref LL_RCC_RTC_HSE_DIV_17
4116 * @arg @ref LL_RCC_RTC_HSE_DIV_18
4117 * @arg @ref LL_RCC_RTC_HSE_DIV_19
4118 * @arg @ref LL_RCC_RTC_HSE_DIV_20
4119 * @arg @ref LL_RCC_RTC_HSE_DIV_21
4120 * @arg @ref LL_RCC_RTC_HSE_DIV_22
4121 * @arg @ref LL_RCC_RTC_HSE_DIV_23
4122 * @arg @ref LL_RCC_RTC_HSE_DIV_24
4123 * @arg @ref LL_RCC_RTC_HSE_DIV_25
4124 * @arg @ref LL_RCC_RTC_HSE_DIV_26
4125 * @arg @ref LL_RCC_RTC_HSE_DIV_27
4126 * @arg @ref LL_RCC_RTC_HSE_DIV_28
4127 * @arg @ref LL_RCC_RTC_HSE_DIV_29
4128 * @arg @ref LL_RCC_RTC_HSE_DIV_30
4129 * @arg @ref LL_RCC_RTC_HSE_DIV_31
4130 */
LL_RCC_GetRTC_HSEPrescaler(void)4131 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
4132 {
4133 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
4134 }
4135
4136 /**
4137 * @}
4138 */
4139
4140 #if defined(RCC_DCKCFGR_TIMPRE)
4141 /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
4142 * @{
4143 */
4144
4145 /**
4146 * @brief Set Timers Clock Prescalers
4147 * @rmtoll DCKCFGR TIMPRE LL_RCC_SetTIMPrescaler
4148 * @param Prescaler This parameter can be one of the following values:
4149 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
4150 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
4151 * @retval None
4152 */
LL_RCC_SetTIMPrescaler(uint32_t Prescaler)4153 __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
4154 {
4155 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE, Prescaler);
4156 }
4157
4158 /**
4159 * @brief Get Timers Clock Prescalers
4160 * @rmtoll DCKCFGR TIMPRE LL_RCC_GetTIMPrescaler
4161 * @retval Returned value can be one of the following values:
4162 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
4163 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
4164 */
LL_RCC_GetTIMPrescaler(void)4165 __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
4166 {
4167 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE));
4168 }
4169
4170 /**
4171 * @}
4172 */
4173 #endif /* RCC_DCKCFGR_TIMPRE */
4174
4175 /** @defgroup RCC_LL_EF_PLL PLL
4176 * @{
4177 */
4178
4179 /**
4180 * @brief Enable PLL
4181 * @rmtoll CR PLLON LL_RCC_PLL_Enable
4182 * @retval None
4183 */
LL_RCC_PLL_Enable(void)4184 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
4185 {
4186 SET_BIT(RCC->CR, RCC_CR_PLLON);
4187 }
4188
4189 /**
4190 * @brief Disable PLL
4191 * @note Cannot be disabled if the PLL clock is used as the system clock
4192 * @rmtoll CR PLLON LL_RCC_PLL_Disable
4193 * @retval None
4194 */
LL_RCC_PLL_Disable(void)4195 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
4196 {
4197 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
4198 }
4199
4200 /**
4201 * @brief Check if PLL Ready
4202 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
4203 * @retval State of bit (1 or 0).
4204 */
LL_RCC_PLL_IsReady(void)4205 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
4206 {
4207 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
4208 }
4209
4210 /**
4211 * @brief Configure PLL used for SYSCLK Domain
4212 * @note PLL Source and PLLM Divider can be written only when PLL,
4213 * PLLI2S and PLLSAI(*) are disabled
4214 * @note PLLN/PLLP can be written only when PLL is disabled
4215 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
4216 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
4217 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
4218 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS\n
4219 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS
4220 * @param Source This parameter can be one of the following values:
4221 * @arg @ref LL_RCC_PLLSOURCE_HSI
4222 * @arg @ref LL_RCC_PLLSOURCE_HSE
4223 * @param PLLM This parameter can be one of the following values:
4224 * @arg @ref LL_RCC_PLLM_DIV_2
4225 * @arg @ref LL_RCC_PLLM_DIV_3
4226 * @arg @ref LL_RCC_PLLM_DIV_4
4227 * @arg @ref LL_RCC_PLLM_DIV_5
4228 * @arg @ref LL_RCC_PLLM_DIV_6
4229 * @arg @ref LL_RCC_PLLM_DIV_7
4230 * @arg @ref LL_RCC_PLLM_DIV_8
4231 * @arg @ref LL_RCC_PLLM_DIV_9
4232 * @arg @ref LL_RCC_PLLM_DIV_10
4233 * @arg @ref LL_RCC_PLLM_DIV_11
4234 * @arg @ref LL_RCC_PLLM_DIV_12
4235 * @arg @ref LL_RCC_PLLM_DIV_13
4236 * @arg @ref LL_RCC_PLLM_DIV_14
4237 * @arg @ref LL_RCC_PLLM_DIV_15
4238 * @arg @ref LL_RCC_PLLM_DIV_16
4239 * @arg @ref LL_RCC_PLLM_DIV_17
4240 * @arg @ref LL_RCC_PLLM_DIV_18
4241 * @arg @ref LL_RCC_PLLM_DIV_19
4242 * @arg @ref LL_RCC_PLLM_DIV_20
4243 * @arg @ref LL_RCC_PLLM_DIV_21
4244 * @arg @ref LL_RCC_PLLM_DIV_22
4245 * @arg @ref LL_RCC_PLLM_DIV_23
4246 * @arg @ref LL_RCC_PLLM_DIV_24
4247 * @arg @ref LL_RCC_PLLM_DIV_25
4248 * @arg @ref LL_RCC_PLLM_DIV_26
4249 * @arg @ref LL_RCC_PLLM_DIV_27
4250 * @arg @ref LL_RCC_PLLM_DIV_28
4251 * @arg @ref LL_RCC_PLLM_DIV_29
4252 * @arg @ref LL_RCC_PLLM_DIV_30
4253 * @arg @ref LL_RCC_PLLM_DIV_31
4254 * @arg @ref LL_RCC_PLLM_DIV_32
4255 * @arg @ref LL_RCC_PLLM_DIV_33
4256 * @arg @ref LL_RCC_PLLM_DIV_34
4257 * @arg @ref LL_RCC_PLLM_DIV_35
4258 * @arg @ref LL_RCC_PLLM_DIV_36
4259 * @arg @ref LL_RCC_PLLM_DIV_37
4260 * @arg @ref LL_RCC_PLLM_DIV_38
4261 * @arg @ref LL_RCC_PLLM_DIV_39
4262 * @arg @ref LL_RCC_PLLM_DIV_40
4263 * @arg @ref LL_RCC_PLLM_DIV_41
4264 * @arg @ref LL_RCC_PLLM_DIV_42
4265 * @arg @ref LL_RCC_PLLM_DIV_43
4266 * @arg @ref LL_RCC_PLLM_DIV_44
4267 * @arg @ref LL_RCC_PLLM_DIV_45
4268 * @arg @ref LL_RCC_PLLM_DIV_46
4269 * @arg @ref LL_RCC_PLLM_DIV_47
4270 * @arg @ref LL_RCC_PLLM_DIV_48
4271 * @arg @ref LL_RCC_PLLM_DIV_49
4272 * @arg @ref LL_RCC_PLLM_DIV_50
4273 * @arg @ref LL_RCC_PLLM_DIV_51
4274 * @arg @ref LL_RCC_PLLM_DIV_52
4275 * @arg @ref LL_RCC_PLLM_DIV_53
4276 * @arg @ref LL_RCC_PLLM_DIV_54
4277 * @arg @ref LL_RCC_PLLM_DIV_55
4278 * @arg @ref LL_RCC_PLLM_DIV_56
4279 * @arg @ref LL_RCC_PLLM_DIV_57
4280 * @arg @ref LL_RCC_PLLM_DIV_58
4281 * @arg @ref LL_RCC_PLLM_DIV_59
4282 * @arg @ref LL_RCC_PLLM_DIV_60
4283 * @arg @ref LL_RCC_PLLM_DIV_61
4284 * @arg @ref LL_RCC_PLLM_DIV_62
4285 * @arg @ref LL_RCC_PLLM_DIV_63
4286 * @param PLLN Between 50/192(*) and 432
4287 *
4288 * (*) value not defined in all devices.
4289 * @param PLLP_R This parameter can be one of the following values:
4290 * @arg @ref LL_RCC_PLLP_DIV_2
4291 * @arg @ref LL_RCC_PLLP_DIV_4
4292 * @arg @ref LL_RCC_PLLP_DIV_6
4293 * @arg @ref LL_RCC_PLLP_DIV_8
4294 * @arg @ref LL_RCC_PLLR_DIV_2 (*)
4295 * @arg @ref LL_RCC_PLLR_DIV_3 (*)
4296 * @arg @ref LL_RCC_PLLR_DIV_4 (*)
4297 * @arg @ref LL_RCC_PLLR_DIV_5 (*)
4298 * @arg @ref LL_RCC_PLLR_DIV_6 (*)
4299 * @arg @ref LL_RCC_PLLR_DIV_7 (*)
4300 *
4301 * (*) value not defined in all devices.
4302 * @retval None
4303 */
LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP_R)4304 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R)
4305 {
4306 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN,
4307 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos);
4308 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, PLLP_R);
4309 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
4310 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, PLLP_R);
4311 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
4312 }
4313
4314 /**
4315 * @brief Configure PLL used for 48Mhz domain clock
4316 * @note PLL Source and PLLM Divider can be written only when PLL,
4317 * PLLI2S and PLLSAI(*) are disabled
4318 * @note PLLN/PLLQ can be written only when PLL is disabled
4319 * @note This can be selected for USB, RNG, SDIO
4320 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
4321 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
4322 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
4323 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
4324 * @param Source This parameter can be one of the following values:
4325 * @arg @ref LL_RCC_PLLSOURCE_HSI
4326 * @arg @ref LL_RCC_PLLSOURCE_HSE
4327 * @param PLLM This parameter can be one of the following values:
4328 * @arg @ref LL_RCC_PLLM_DIV_2
4329 * @arg @ref LL_RCC_PLLM_DIV_3
4330 * @arg @ref LL_RCC_PLLM_DIV_4
4331 * @arg @ref LL_RCC_PLLM_DIV_5
4332 * @arg @ref LL_RCC_PLLM_DIV_6
4333 * @arg @ref LL_RCC_PLLM_DIV_7
4334 * @arg @ref LL_RCC_PLLM_DIV_8
4335 * @arg @ref LL_RCC_PLLM_DIV_9
4336 * @arg @ref LL_RCC_PLLM_DIV_10
4337 * @arg @ref LL_RCC_PLLM_DIV_11
4338 * @arg @ref LL_RCC_PLLM_DIV_12
4339 * @arg @ref LL_RCC_PLLM_DIV_13
4340 * @arg @ref LL_RCC_PLLM_DIV_14
4341 * @arg @ref LL_RCC_PLLM_DIV_15
4342 * @arg @ref LL_RCC_PLLM_DIV_16
4343 * @arg @ref LL_RCC_PLLM_DIV_17
4344 * @arg @ref LL_RCC_PLLM_DIV_18
4345 * @arg @ref LL_RCC_PLLM_DIV_19
4346 * @arg @ref LL_RCC_PLLM_DIV_20
4347 * @arg @ref LL_RCC_PLLM_DIV_21
4348 * @arg @ref LL_RCC_PLLM_DIV_22
4349 * @arg @ref LL_RCC_PLLM_DIV_23
4350 * @arg @ref LL_RCC_PLLM_DIV_24
4351 * @arg @ref LL_RCC_PLLM_DIV_25
4352 * @arg @ref LL_RCC_PLLM_DIV_26
4353 * @arg @ref LL_RCC_PLLM_DIV_27
4354 * @arg @ref LL_RCC_PLLM_DIV_28
4355 * @arg @ref LL_RCC_PLLM_DIV_29
4356 * @arg @ref LL_RCC_PLLM_DIV_30
4357 * @arg @ref LL_RCC_PLLM_DIV_31
4358 * @arg @ref LL_RCC_PLLM_DIV_32
4359 * @arg @ref LL_RCC_PLLM_DIV_33
4360 * @arg @ref LL_RCC_PLLM_DIV_34
4361 * @arg @ref LL_RCC_PLLM_DIV_35
4362 * @arg @ref LL_RCC_PLLM_DIV_36
4363 * @arg @ref LL_RCC_PLLM_DIV_37
4364 * @arg @ref LL_RCC_PLLM_DIV_38
4365 * @arg @ref LL_RCC_PLLM_DIV_39
4366 * @arg @ref LL_RCC_PLLM_DIV_40
4367 * @arg @ref LL_RCC_PLLM_DIV_41
4368 * @arg @ref LL_RCC_PLLM_DIV_42
4369 * @arg @ref LL_RCC_PLLM_DIV_43
4370 * @arg @ref LL_RCC_PLLM_DIV_44
4371 * @arg @ref LL_RCC_PLLM_DIV_45
4372 * @arg @ref LL_RCC_PLLM_DIV_46
4373 * @arg @ref LL_RCC_PLLM_DIV_47
4374 * @arg @ref LL_RCC_PLLM_DIV_48
4375 * @arg @ref LL_RCC_PLLM_DIV_49
4376 * @arg @ref LL_RCC_PLLM_DIV_50
4377 * @arg @ref LL_RCC_PLLM_DIV_51
4378 * @arg @ref LL_RCC_PLLM_DIV_52
4379 * @arg @ref LL_RCC_PLLM_DIV_53
4380 * @arg @ref LL_RCC_PLLM_DIV_54
4381 * @arg @ref LL_RCC_PLLM_DIV_55
4382 * @arg @ref LL_RCC_PLLM_DIV_56
4383 * @arg @ref LL_RCC_PLLM_DIV_57
4384 * @arg @ref LL_RCC_PLLM_DIV_58
4385 * @arg @ref LL_RCC_PLLM_DIV_59
4386 * @arg @ref LL_RCC_PLLM_DIV_60
4387 * @arg @ref LL_RCC_PLLM_DIV_61
4388 * @arg @ref LL_RCC_PLLM_DIV_62
4389 * @arg @ref LL_RCC_PLLM_DIV_63
4390 * @param PLLN Between 50/192(*) and 432
4391 *
4392 * (*) value not defined in all devices.
4393 * @param PLLQ This parameter can be one of the following values:
4394 * @arg @ref LL_RCC_PLLQ_DIV_2
4395 * @arg @ref LL_RCC_PLLQ_DIV_3
4396 * @arg @ref LL_RCC_PLLQ_DIV_4
4397 * @arg @ref LL_RCC_PLLQ_DIV_5
4398 * @arg @ref LL_RCC_PLLQ_DIV_6
4399 * @arg @ref LL_RCC_PLLQ_DIV_7
4400 * @arg @ref LL_RCC_PLLQ_DIV_8
4401 * @arg @ref LL_RCC_PLLQ_DIV_9
4402 * @arg @ref LL_RCC_PLLQ_DIV_10
4403 * @arg @ref LL_RCC_PLLQ_DIV_11
4404 * @arg @ref LL_RCC_PLLQ_DIV_12
4405 * @arg @ref LL_RCC_PLLQ_DIV_13
4406 * @arg @ref LL_RCC_PLLQ_DIV_14
4407 * @arg @ref LL_RCC_PLLQ_DIV_15
4408 * @retval None
4409 */
LL_RCC_PLL_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)4410 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
4411 {
4412 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
4413 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);
4414 }
4415
4416 #if defined(DSI)
4417 /**
4418 * @brief Configure PLL used for DSI clock
4419 * @note PLL Source and PLLM Divider can be written only when PLL,
4420 * PLLI2S and PLLSAI are disabled
4421 * @note PLLN/PLLR can be written only when PLL is disabled
4422 * @note This can be selected for DSI
4423 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n
4424 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n
4425 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n
4426 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI
4427 * @param Source This parameter can be one of the following values:
4428 * @arg @ref LL_RCC_PLLSOURCE_HSI
4429 * @arg @ref LL_RCC_PLLSOURCE_HSE
4430 * @param PLLM This parameter can be one of the following values:
4431 * @arg @ref LL_RCC_PLLM_DIV_2
4432 * @arg @ref LL_RCC_PLLM_DIV_3
4433 * @arg @ref LL_RCC_PLLM_DIV_4
4434 * @arg @ref LL_RCC_PLLM_DIV_5
4435 * @arg @ref LL_RCC_PLLM_DIV_6
4436 * @arg @ref LL_RCC_PLLM_DIV_7
4437 * @arg @ref LL_RCC_PLLM_DIV_8
4438 * @arg @ref LL_RCC_PLLM_DIV_9
4439 * @arg @ref LL_RCC_PLLM_DIV_10
4440 * @arg @ref LL_RCC_PLLM_DIV_11
4441 * @arg @ref LL_RCC_PLLM_DIV_12
4442 * @arg @ref LL_RCC_PLLM_DIV_13
4443 * @arg @ref LL_RCC_PLLM_DIV_14
4444 * @arg @ref LL_RCC_PLLM_DIV_15
4445 * @arg @ref LL_RCC_PLLM_DIV_16
4446 * @arg @ref LL_RCC_PLLM_DIV_17
4447 * @arg @ref LL_RCC_PLLM_DIV_18
4448 * @arg @ref LL_RCC_PLLM_DIV_19
4449 * @arg @ref LL_RCC_PLLM_DIV_20
4450 * @arg @ref LL_RCC_PLLM_DIV_21
4451 * @arg @ref LL_RCC_PLLM_DIV_22
4452 * @arg @ref LL_RCC_PLLM_DIV_23
4453 * @arg @ref LL_RCC_PLLM_DIV_24
4454 * @arg @ref LL_RCC_PLLM_DIV_25
4455 * @arg @ref LL_RCC_PLLM_DIV_26
4456 * @arg @ref LL_RCC_PLLM_DIV_27
4457 * @arg @ref LL_RCC_PLLM_DIV_28
4458 * @arg @ref LL_RCC_PLLM_DIV_29
4459 * @arg @ref LL_RCC_PLLM_DIV_30
4460 * @arg @ref LL_RCC_PLLM_DIV_31
4461 * @arg @ref LL_RCC_PLLM_DIV_32
4462 * @arg @ref LL_RCC_PLLM_DIV_33
4463 * @arg @ref LL_RCC_PLLM_DIV_34
4464 * @arg @ref LL_RCC_PLLM_DIV_35
4465 * @arg @ref LL_RCC_PLLM_DIV_36
4466 * @arg @ref LL_RCC_PLLM_DIV_37
4467 * @arg @ref LL_RCC_PLLM_DIV_38
4468 * @arg @ref LL_RCC_PLLM_DIV_39
4469 * @arg @ref LL_RCC_PLLM_DIV_40
4470 * @arg @ref LL_RCC_PLLM_DIV_41
4471 * @arg @ref LL_RCC_PLLM_DIV_42
4472 * @arg @ref LL_RCC_PLLM_DIV_43
4473 * @arg @ref LL_RCC_PLLM_DIV_44
4474 * @arg @ref LL_RCC_PLLM_DIV_45
4475 * @arg @ref LL_RCC_PLLM_DIV_46
4476 * @arg @ref LL_RCC_PLLM_DIV_47
4477 * @arg @ref LL_RCC_PLLM_DIV_48
4478 * @arg @ref LL_RCC_PLLM_DIV_49
4479 * @arg @ref LL_RCC_PLLM_DIV_50
4480 * @arg @ref LL_RCC_PLLM_DIV_51
4481 * @arg @ref LL_RCC_PLLM_DIV_52
4482 * @arg @ref LL_RCC_PLLM_DIV_53
4483 * @arg @ref LL_RCC_PLLM_DIV_54
4484 * @arg @ref LL_RCC_PLLM_DIV_55
4485 * @arg @ref LL_RCC_PLLM_DIV_56
4486 * @arg @ref LL_RCC_PLLM_DIV_57
4487 * @arg @ref LL_RCC_PLLM_DIV_58
4488 * @arg @ref LL_RCC_PLLM_DIV_59
4489 * @arg @ref LL_RCC_PLLM_DIV_60
4490 * @arg @ref LL_RCC_PLLM_DIV_61
4491 * @arg @ref LL_RCC_PLLM_DIV_62
4492 * @arg @ref LL_RCC_PLLM_DIV_63
4493 * @param PLLN Between 50 and 432
4494 * @param PLLR This parameter can be one of the following values:
4495 * @arg @ref LL_RCC_PLLR_DIV_2
4496 * @arg @ref LL_RCC_PLLR_DIV_3
4497 * @arg @ref LL_RCC_PLLR_DIV_4
4498 * @arg @ref LL_RCC_PLLR_DIV_5
4499 * @arg @ref LL_RCC_PLLR_DIV_6
4500 * @arg @ref LL_RCC_PLLR_DIV_7
4501 * @retval None
4502 */
LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)4503 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4504 {
4505 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4506 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4507 }
4508 #endif /* DSI */
4509
4510 #if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
4511 /**
4512 * @brief Configure PLL used for I2S clock
4513 * @note PLL Source and PLLM Divider can be written only when PLL,
4514 * PLLI2S and PLLSAI are disabled
4515 * @note PLLN/PLLR can be written only when PLL is disabled
4516 * @note This can be selected for I2S
4517 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S\n
4518 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S\n
4519 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S\n
4520 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_I2S
4521 * @param Source This parameter can be one of the following values:
4522 * @arg @ref LL_RCC_PLLSOURCE_HSI
4523 * @arg @ref LL_RCC_PLLSOURCE_HSE
4524 * @param PLLM This parameter can be one of the following values:
4525 * @arg @ref LL_RCC_PLLM_DIV_2
4526 * @arg @ref LL_RCC_PLLM_DIV_3
4527 * @arg @ref LL_RCC_PLLM_DIV_4
4528 * @arg @ref LL_RCC_PLLM_DIV_5
4529 * @arg @ref LL_RCC_PLLM_DIV_6
4530 * @arg @ref LL_RCC_PLLM_DIV_7
4531 * @arg @ref LL_RCC_PLLM_DIV_8
4532 * @arg @ref LL_RCC_PLLM_DIV_9
4533 * @arg @ref LL_RCC_PLLM_DIV_10
4534 * @arg @ref LL_RCC_PLLM_DIV_11
4535 * @arg @ref LL_RCC_PLLM_DIV_12
4536 * @arg @ref LL_RCC_PLLM_DIV_13
4537 * @arg @ref LL_RCC_PLLM_DIV_14
4538 * @arg @ref LL_RCC_PLLM_DIV_15
4539 * @arg @ref LL_RCC_PLLM_DIV_16
4540 * @arg @ref LL_RCC_PLLM_DIV_17
4541 * @arg @ref LL_RCC_PLLM_DIV_18
4542 * @arg @ref LL_RCC_PLLM_DIV_19
4543 * @arg @ref LL_RCC_PLLM_DIV_20
4544 * @arg @ref LL_RCC_PLLM_DIV_21
4545 * @arg @ref LL_RCC_PLLM_DIV_22
4546 * @arg @ref LL_RCC_PLLM_DIV_23
4547 * @arg @ref LL_RCC_PLLM_DIV_24
4548 * @arg @ref LL_RCC_PLLM_DIV_25
4549 * @arg @ref LL_RCC_PLLM_DIV_26
4550 * @arg @ref LL_RCC_PLLM_DIV_27
4551 * @arg @ref LL_RCC_PLLM_DIV_28
4552 * @arg @ref LL_RCC_PLLM_DIV_29
4553 * @arg @ref LL_RCC_PLLM_DIV_30
4554 * @arg @ref LL_RCC_PLLM_DIV_31
4555 * @arg @ref LL_RCC_PLLM_DIV_32
4556 * @arg @ref LL_RCC_PLLM_DIV_33
4557 * @arg @ref LL_RCC_PLLM_DIV_34
4558 * @arg @ref LL_RCC_PLLM_DIV_35
4559 * @arg @ref LL_RCC_PLLM_DIV_36
4560 * @arg @ref LL_RCC_PLLM_DIV_37
4561 * @arg @ref LL_RCC_PLLM_DIV_38
4562 * @arg @ref LL_RCC_PLLM_DIV_39
4563 * @arg @ref LL_RCC_PLLM_DIV_40
4564 * @arg @ref LL_RCC_PLLM_DIV_41
4565 * @arg @ref LL_RCC_PLLM_DIV_42
4566 * @arg @ref LL_RCC_PLLM_DIV_43
4567 * @arg @ref LL_RCC_PLLM_DIV_44
4568 * @arg @ref LL_RCC_PLLM_DIV_45
4569 * @arg @ref LL_RCC_PLLM_DIV_46
4570 * @arg @ref LL_RCC_PLLM_DIV_47
4571 * @arg @ref LL_RCC_PLLM_DIV_48
4572 * @arg @ref LL_RCC_PLLM_DIV_49
4573 * @arg @ref LL_RCC_PLLM_DIV_50
4574 * @arg @ref LL_RCC_PLLM_DIV_51
4575 * @arg @ref LL_RCC_PLLM_DIV_52
4576 * @arg @ref LL_RCC_PLLM_DIV_53
4577 * @arg @ref LL_RCC_PLLM_DIV_54
4578 * @arg @ref LL_RCC_PLLM_DIV_55
4579 * @arg @ref LL_RCC_PLLM_DIV_56
4580 * @arg @ref LL_RCC_PLLM_DIV_57
4581 * @arg @ref LL_RCC_PLLM_DIV_58
4582 * @arg @ref LL_RCC_PLLM_DIV_59
4583 * @arg @ref LL_RCC_PLLM_DIV_60
4584 * @arg @ref LL_RCC_PLLM_DIV_61
4585 * @arg @ref LL_RCC_PLLM_DIV_62
4586 * @arg @ref LL_RCC_PLLM_DIV_63
4587 * @param PLLN Between 50 and 432
4588 * @param PLLR This parameter can be one of the following values:
4589 * @arg @ref LL_RCC_PLLR_DIV_2
4590 * @arg @ref LL_RCC_PLLR_DIV_3
4591 * @arg @ref LL_RCC_PLLR_DIV_4
4592 * @arg @ref LL_RCC_PLLR_DIV_5
4593 * @arg @ref LL_RCC_PLLR_DIV_6
4594 * @arg @ref LL_RCC_PLLR_DIV_7
4595 * @retval None
4596 */
LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)4597 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4598 {
4599 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4600 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4601 }
4602 #endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
4603
4604 #if defined(SPDIFRX)
4605 /**
4606 * @brief Configure PLL used for SPDIFRX clock
4607 * @note PLL Source and PLLM Divider can be written only when PLL,
4608 * PLLI2S and PLLSAI are disabled
4609 * @note PLLN/PLLR can be written only when PLL is disabled
4610 * @note This can be selected for SPDIFRX
4611 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SPDIFRX\n
4612 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SPDIFRX\n
4613 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SPDIFRX\n
4614 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SPDIFRX
4615 * @param Source This parameter can be one of the following values:
4616 * @arg @ref LL_RCC_PLLSOURCE_HSI
4617 * @arg @ref LL_RCC_PLLSOURCE_HSE
4618 * @param PLLM This parameter can be one of the following values:
4619 * @arg @ref LL_RCC_PLLM_DIV_2
4620 * @arg @ref LL_RCC_PLLM_DIV_3
4621 * @arg @ref LL_RCC_PLLM_DIV_4
4622 * @arg @ref LL_RCC_PLLM_DIV_5
4623 * @arg @ref LL_RCC_PLLM_DIV_6
4624 * @arg @ref LL_RCC_PLLM_DIV_7
4625 * @arg @ref LL_RCC_PLLM_DIV_8
4626 * @arg @ref LL_RCC_PLLM_DIV_9
4627 * @arg @ref LL_RCC_PLLM_DIV_10
4628 * @arg @ref LL_RCC_PLLM_DIV_11
4629 * @arg @ref LL_RCC_PLLM_DIV_12
4630 * @arg @ref LL_RCC_PLLM_DIV_13
4631 * @arg @ref LL_RCC_PLLM_DIV_14
4632 * @arg @ref LL_RCC_PLLM_DIV_15
4633 * @arg @ref LL_RCC_PLLM_DIV_16
4634 * @arg @ref LL_RCC_PLLM_DIV_17
4635 * @arg @ref LL_RCC_PLLM_DIV_18
4636 * @arg @ref LL_RCC_PLLM_DIV_19
4637 * @arg @ref LL_RCC_PLLM_DIV_20
4638 * @arg @ref LL_RCC_PLLM_DIV_21
4639 * @arg @ref LL_RCC_PLLM_DIV_22
4640 * @arg @ref LL_RCC_PLLM_DIV_23
4641 * @arg @ref LL_RCC_PLLM_DIV_24
4642 * @arg @ref LL_RCC_PLLM_DIV_25
4643 * @arg @ref LL_RCC_PLLM_DIV_26
4644 * @arg @ref LL_RCC_PLLM_DIV_27
4645 * @arg @ref LL_RCC_PLLM_DIV_28
4646 * @arg @ref LL_RCC_PLLM_DIV_29
4647 * @arg @ref LL_RCC_PLLM_DIV_30
4648 * @arg @ref LL_RCC_PLLM_DIV_31
4649 * @arg @ref LL_RCC_PLLM_DIV_32
4650 * @arg @ref LL_RCC_PLLM_DIV_33
4651 * @arg @ref LL_RCC_PLLM_DIV_34
4652 * @arg @ref LL_RCC_PLLM_DIV_35
4653 * @arg @ref LL_RCC_PLLM_DIV_36
4654 * @arg @ref LL_RCC_PLLM_DIV_37
4655 * @arg @ref LL_RCC_PLLM_DIV_38
4656 * @arg @ref LL_RCC_PLLM_DIV_39
4657 * @arg @ref LL_RCC_PLLM_DIV_40
4658 * @arg @ref LL_RCC_PLLM_DIV_41
4659 * @arg @ref LL_RCC_PLLM_DIV_42
4660 * @arg @ref LL_RCC_PLLM_DIV_43
4661 * @arg @ref LL_RCC_PLLM_DIV_44
4662 * @arg @ref LL_RCC_PLLM_DIV_45
4663 * @arg @ref LL_RCC_PLLM_DIV_46
4664 * @arg @ref LL_RCC_PLLM_DIV_47
4665 * @arg @ref LL_RCC_PLLM_DIV_48
4666 * @arg @ref LL_RCC_PLLM_DIV_49
4667 * @arg @ref LL_RCC_PLLM_DIV_50
4668 * @arg @ref LL_RCC_PLLM_DIV_51
4669 * @arg @ref LL_RCC_PLLM_DIV_52
4670 * @arg @ref LL_RCC_PLLM_DIV_53
4671 * @arg @ref LL_RCC_PLLM_DIV_54
4672 * @arg @ref LL_RCC_PLLM_DIV_55
4673 * @arg @ref LL_RCC_PLLM_DIV_56
4674 * @arg @ref LL_RCC_PLLM_DIV_57
4675 * @arg @ref LL_RCC_PLLM_DIV_58
4676 * @arg @ref LL_RCC_PLLM_DIV_59
4677 * @arg @ref LL_RCC_PLLM_DIV_60
4678 * @arg @ref LL_RCC_PLLM_DIV_61
4679 * @arg @ref LL_RCC_PLLM_DIV_62
4680 * @arg @ref LL_RCC_PLLM_DIV_63
4681 * @param PLLN Between 50 and 432
4682 * @param PLLR This parameter can be one of the following values:
4683 * @arg @ref LL_RCC_PLLR_DIV_2
4684 * @arg @ref LL_RCC_PLLR_DIV_3
4685 * @arg @ref LL_RCC_PLLR_DIV_4
4686 * @arg @ref LL_RCC_PLLR_DIV_5
4687 * @arg @ref LL_RCC_PLLR_DIV_6
4688 * @arg @ref LL_RCC_PLLR_DIV_7
4689 * @retval None
4690 */
LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)4691 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4692 {
4693 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4694 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4695 }
4696 #endif /* SPDIFRX */
4697
4698 #if defined(RCC_PLLCFGR_PLLR)
4699 #if defined(SAI1)
4700 /**
4701 * @brief Configure PLL used for SAI clock
4702 * @note PLL Source and PLLM Divider can be written only when PLL,
4703 * PLLI2S and PLLSAI are disabled
4704 * @note PLLN/PLLR can be written only when PLL is disabled
4705 * @note This can be selected for SAI
4706 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
4707 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
4708 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
4709 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SAI\n
4710 * DCKCFGR PLLDIVR LL_RCC_PLL_ConfigDomain_SAI
4711 * @param Source This parameter can be one of the following values:
4712 * @arg @ref LL_RCC_PLLSOURCE_HSI
4713 * @arg @ref LL_RCC_PLLSOURCE_HSE
4714 * @param PLLM This parameter can be one of the following values:
4715 * @arg @ref LL_RCC_PLLM_DIV_2
4716 * @arg @ref LL_RCC_PLLM_DIV_3
4717 * @arg @ref LL_RCC_PLLM_DIV_4
4718 * @arg @ref LL_RCC_PLLM_DIV_5
4719 * @arg @ref LL_RCC_PLLM_DIV_6
4720 * @arg @ref LL_RCC_PLLM_DIV_7
4721 * @arg @ref LL_RCC_PLLM_DIV_8
4722 * @arg @ref LL_RCC_PLLM_DIV_9
4723 * @arg @ref LL_RCC_PLLM_DIV_10
4724 * @arg @ref LL_RCC_PLLM_DIV_11
4725 * @arg @ref LL_RCC_PLLM_DIV_12
4726 * @arg @ref LL_RCC_PLLM_DIV_13
4727 * @arg @ref LL_RCC_PLLM_DIV_14
4728 * @arg @ref LL_RCC_PLLM_DIV_15
4729 * @arg @ref LL_RCC_PLLM_DIV_16
4730 * @arg @ref LL_RCC_PLLM_DIV_17
4731 * @arg @ref LL_RCC_PLLM_DIV_18
4732 * @arg @ref LL_RCC_PLLM_DIV_19
4733 * @arg @ref LL_RCC_PLLM_DIV_20
4734 * @arg @ref LL_RCC_PLLM_DIV_21
4735 * @arg @ref LL_RCC_PLLM_DIV_22
4736 * @arg @ref LL_RCC_PLLM_DIV_23
4737 * @arg @ref LL_RCC_PLLM_DIV_24
4738 * @arg @ref LL_RCC_PLLM_DIV_25
4739 * @arg @ref LL_RCC_PLLM_DIV_26
4740 * @arg @ref LL_RCC_PLLM_DIV_27
4741 * @arg @ref LL_RCC_PLLM_DIV_28
4742 * @arg @ref LL_RCC_PLLM_DIV_29
4743 * @arg @ref LL_RCC_PLLM_DIV_30
4744 * @arg @ref LL_RCC_PLLM_DIV_31
4745 * @arg @ref LL_RCC_PLLM_DIV_32
4746 * @arg @ref LL_RCC_PLLM_DIV_33
4747 * @arg @ref LL_RCC_PLLM_DIV_34
4748 * @arg @ref LL_RCC_PLLM_DIV_35
4749 * @arg @ref LL_RCC_PLLM_DIV_36
4750 * @arg @ref LL_RCC_PLLM_DIV_37
4751 * @arg @ref LL_RCC_PLLM_DIV_38
4752 * @arg @ref LL_RCC_PLLM_DIV_39
4753 * @arg @ref LL_RCC_PLLM_DIV_40
4754 * @arg @ref LL_RCC_PLLM_DIV_41
4755 * @arg @ref LL_RCC_PLLM_DIV_42
4756 * @arg @ref LL_RCC_PLLM_DIV_43
4757 * @arg @ref LL_RCC_PLLM_DIV_44
4758 * @arg @ref LL_RCC_PLLM_DIV_45
4759 * @arg @ref LL_RCC_PLLM_DIV_46
4760 * @arg @ref LL_RCC_PLLM_DIV_47
4761 * @arg @ref LL_RCC_PLLM_DIV_48
4762 * @arg @ref LL_RCC_PLLM_DIV_49
4763 * @arg @ref LL_RCC_PLLM_DIV_50
4764 * @arg @ref LL_RCC_PLLM_DIV_51
4765 * @arg @ref LL_RCC_PLLM_DIV_52
4766 * @arg @ref LL_RCC_PLLM_DIV_53
4767 * @arg @ref LL_RCC_PLLM_DIV_54
4768 * @arg @ref LL_RCC_PLLM_DIV_55
4769 * @arg @ref LL_RCC_PLLM_DIV_56
4770 * @arg @ref LL_RCC_PLLM_DIV_57
4771 * @arg @ref LL_RCC_PLLM_DIV_58
4772 * @arg @ref LL_RCC_PLLM_DIV_59
4773 * @arg @ref LL_RCC_PLLM_DIV_60
4774 * @arg @ref LL_RCC_PLLM_DIV_61
4775 * @arg @ref LL_RCC_PLLM_DIV_62
4776 * @arg @ref LL_RCC_PLLM_DIV_63
4777 * @param PLLN Between 50 and 432
4778 * @param PLLR This parameter can be one of the following values:
4779 * @arg @ref LL_RCC_PLLR_DIV_2
4780 * @arg @ref LL_RCC_PLLR_DIV_3
4781 * @arg @ref LL_RCC_PLLR_DIV_4
4782 * @arg @ref LL_RCC_PLLR_DIV_5
4783 * @arg @ref LL_RCC_PLLR_DIV_6
4784 * @arg @ref LL_RCC_PLLR_DIV_7
4785 * @param PLLDIVR This parameter can be one of the following values:
4786 * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
4787 * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
4788 * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
4789 * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
4790 * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
4791 * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
4792 * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
4793 * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
4794 * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
4795 * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
4796 * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
4797 * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
4798 * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
4799 * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
4800 * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
4801 * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
4802 * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
4803 * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
4804 * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
4805 * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
4806 * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
4807 * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
4808 * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
4809 * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
4810 * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
4811 * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
4812 * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
4813 * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
4814 * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
4815 * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
4816 * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
4817 *
4818 * (*) value not defined in all devices.
4819 * @retval None
4820 */
4821 #if defined(RCC_DCKCFGR_PLLDIVR)
LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR,uint32_t PLLDIVR)4822 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
4823 #else
4824 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4825 #endif /* RCC_DCKCFGR_PLLDIVR */
4826 {
4827 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4828 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4829 #if defined(RCC_DCKCFGR_PLLDIVR)
4830 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, PLLDIVR);
4831 #endif /* RCC_DCKCFGR_PLLDIVR */
4832 }
4833 #endif /* SAI1 */
4834 #endif /* RCC_PLLCFGR_PLLR */
4835
4836 /**
4837 * @brief Configure PLL clock source
4838 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
4839 * @param PLLSource This parameter can be one of the following values:
4840 * @arg @ref LL_RCC_PLLSOURCE_HSI
4841 * @arg @ref LL_RCC_PLLSOURCE_HSE
4842 * @retval None
4843 */
LL_RCC_PLL_SetMainSource(uint32_t PLLSource)4844 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
4845 {
4846 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
4847 }
4848
4849 /**
4850 * @brief Get the oscillator used as PLL clock source.
4851 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
4852 * @retval Returned value can be one of the following values:
4853 * @arg @ref LL_RCC_PLLSOURCE_HSI
4854 * @arg @ref LL_RCC_PLLSOURCE_HSE
4855 */
LL_RCC_PLL_GetMainSource(void)4856 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
4857 {
4858 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
4859 }
4860
4861 /**
4862 * @brief Get Main PLL multiplication factor for VCO
4863 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
4864 * @retval Between 50/192(*) and 432
4865 *
4866 * (*) value not defined in all devices.
4867 */
LL_RCC_PLL_GetN(void)4868 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
4869 {
4870 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
4871 }
4872
4873 /**
4874 * @brief Get Main PLL division factor for PLLP
4875 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
4876 * @retval Returned value can be one of the following values:
4877 * @arg @ref LL_RCC_PLLP_DIV_2
4878 * @arg @ref LL_RCC_PLLP_DIV_4
4879 * @arg @ref LL_RCC_PLLP_DIV_6
4880 * @arg @ref LL_RCC_PLLP_DIV_8
4881 */
LL_RCC_PLL_GetP(void)4882 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
4883 {
4884 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
4885 }
4886
4887 /**
4888 * @brief Get Main PLL division factor for PLLQ
4889 * @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock)
4890 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
4891 * @retval Returned value can be one of the following values:
4892 * @arg @ref LL_RCC_PLLQ_DIV_2
4893 * @arg @ref LL_RCC_PLLQ_DIV_3
4894 * @arg @ref LL_RCC_PLLQ_DIV_4
4895 * @arg @ref LL_RCC_PLLQ_DIV_5
4896 * @arg @ref LL_RCC_PLLQ_DIV_6
4897 * @arg @ref LL_RCC_PLLQ_DIV_7
4898 * @arg @ref LL_RCC_PLLQ_DIV_8
4899 * @arg @ref LL_RCC_PLLQ_DIV_9
4900 * @arg @ref LL_RCC_PLLQ_DIV_10
4901 * @arg @ref LL_RCC_PLLQ_DIV_11
4902 * @arg @ref LL_RCC_PLLQ_DIV_12
4903 * @arg @ref LL_RCC_PLLQ_DIV_13
4904 * @arg @ref LL_RCC_PLLQ_DIV_14
4905 * @arg @ref LL_RCC_PLLQ_DIV_15
4906 */
LL_RCC_PLL_GetQ(void)4907 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
4908 {
4909 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
4910 }
4911
4912 #if defined(RCC_PLLCFGR_PLLR)
4913 /**
4914 * @brief Get Main PLL division factor for PLLR
4915 * @note used for PLLCLK (system clock)
4916 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
4917 * @retval Returned value can be one of the following values:
4918 * @arg @ref LL_RCC_PLLR_DIV_2
4919 * @arg @ref LL_RCC_PLLR_DIV_3
4920 * @arg @ref LL_RCC_PLLR_DIV_4
4921 * @arg @ref LL_RCC_PLLR_DIV_5
4922 * @arg @ref LL_RCC_PLLR_DIV_6
4923 * @arg @ref LL_RCC_PLLR_DIV_7
4924 */
LL_RCC_PLL_GetR(void)4925 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
4926 {
4927 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
4928 }
4929 #endif /* RCC_PLLCFGR_PLLR */
4930
4931 #if defined(RCC_DCKCFGR_PLLDIVR)
4932 /**
4933 * @brief Get Main PLL division factor for PLLDIVR
4934 * @note used for PLLSAICLK (SAI1 and SAI2 clock)
4935 * @rmtoll DCKCFGR PLLDIVR LL_RCC_PLL_GetDIVR
4936 * @retval Returned value can be one of the following values:
4937 * @arg @ref LL_RCC_PLLDIVR_DIV_1
4938 * @arg @ref LL_RCC_PLLDIVR_DIV_2
4939 * @arg @ref LL_RCC_PLLDIVR_DIV_3
4940 * @arg @ref LL_RCC_PLLDIVR_DIV_4
4941 * @arg @ref LL_RCC_PLLDIVR_DIV_5
4942 * @arg @ref LL_RCC_PLLDIVR_DIV_6
4943 * @arg @ref LL_RCC_PLLDIVR_DIV_7
4944 * @arg @ref LL_RCC_PLLDIVR_DIV_8
4945 * @arg @ref LL_RCC_PLLDIVR_DIV_9
4946 * @arg @ref LL_RCC_PLLDIVR_DIV_10
4947 * @arg @ref LL_RCC_PLLDIVR_DIV_11
4948 * @arg @ref LL_RCC_PLLDIVR_DIV_12
4949 * @arg @ref LL_RCC_PLLDIVR_DIV_13
4950 * @arg @ref LL_RCC_PLLDIVR_DIV_14
4951 * @arg @ref LL_RCC_PLLDIVR_DIV_15
4952 * @arg @ref LL_RCC_PLLDIVR_DIV_16
4953 * @arg @ref LL_RCC_PLLDIVR_DIV_17
4954 * @arg @ref LL_RCC_PLLDIVR_DIV_18
4955 * @arg @ref LL_RCC_PLLDIVR_DIV_19
4956 * @arg @ref LL_RCC_PLLDIVR_DIV_20
4957 * @arg @ref LL_RCC_PLLDIVR_DIV_21
4958 * @arg @ref LL_RCC_PLLDIVR_DIV_22
4959 * @arg @ref LL_RCC_PLLDIVR_DIV_23
4960 * @arg @ref LL_RCC_PLLDIVR_DIV_24
4961 * @arg @ref LL_RCC_PLLDIVR_DIV_25
4962 * @arg @ref LL_RCC_PLLDIVR_DIV_26
4963 * @arg @ref LL_RCC_PLLDIVR_DIV_27
4964 * @arg @ref LL_RCC_PLLDIVR_DIV_28
4965 * @arg @ref LL_RCC_PLLDIVR_DIV_29
4966 * @arg @ref LL_RCC_PLLDIVR_DIV_30
4967 * @arg @ref LL_RCC_PLLDIVR_DIV_31
4968 */
LL_RCC_PLL_GetDIVR(void)4969 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void)
4970 {
4971 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR));
4972 }
4973 #endif /* RCC_DCKCFGR_PLLDIVR */
4974
4975 /**
4976 * @brief Get Division factor for the main PLL and other PLL
4977 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
4978 * @retval Returned value can be one of the following values:
4979 * @arg @ref LL_RCC_PLLM_DIV_2
4980 * @arg @ref LL_RCC_PLLM_DIV_3
4981 * @arg @ref LL_RCC_PLLM_DIV_4
4982 * @arg @ref LL_RCC_PLLM_DIV_5
4983 * @arg @ref LL_RCC_PLLM_DIV_6
4984 * @arg @ref LL_RCC_PLLM_DIV_7
4985 * @arg @ref LL_RCC_PLLM_DIV_8
4986 * @arg @ref LL_RCC_PLLM_DIV_9
4987 * @arg @ref LL_RCC_PLLM_DIV_10
4988 * @arg @ref LL_RCC_PLLM_DIV_11
4989 * @arg @ref LL_RCC_PLLM_DIV_12
4990 * @arg @ref LL_RCC_PLLM_DIV_13
4991 * @arg @ref LL_RCC_PLLM_DIV_14
4992 * @arg @ref LL_RCC_PLLM_DIV_15
4993 * @arg @ref LL_RCC_PLLM_DIV_16
4994 * @arg @ref LL_RCC_PLLM_DIV_17
4995 * @arg @ref LL_RCC_PLLM_DIV_18
4996 * @arg @ref LL_RCC_PLLM_DIV_19
4997 * @arg @ref LL_RCC_PLLM_DIV_20
4998 * @arg @ref LL_RCC_PLLM_DIV_21
4999 * @arg @ref LL_RCC_PLLM_DIV_22
5000 * @arg @ref LL_RCC_PLLM_DIV_23
5001 * @arg @ref LL_RCC_PLLM_DIV_24
5002 * @arg @ref LL_RCC_PLLM_DIV_25
5003 * @arg @ref LL_RCC_PLLM_DIV_26
5004 * @arg @ref LL_RCC_PLLM_DIV_27
5005 * @arg @ref LL_RCC_PLLM_DIV_28
5006 * @arg @ref LL_RCC_PLLM_DIV_29
5007 * @arg @ref LL_RCC_PLLM_DIV_30
5008 * @arg @ref LL_RCC_PLLM_DIV_31
5009 * @arg @ref LL_RCC_PLLM_DIV_32
5010 * @arg @ref LL_RCC_PLLM_DIV_33
5011 * @arg @ref LL_RCC_PLLM_DIV_34
5012 * @arg @ref LL_RCC_PLLM_DIV_35
5013 * @arg @ref LL_RCC_PLLM_DIV_36
5014 * @arg @ref LL_RCC_PLLM_DIV_37
5015 * @arg @ref LL_RCC_PLLM_DIV_38
5016 * @arg @ref LL_RCC_PLLM_DIV_39
5017 * @arg @ref LL_RCC_PLLM_DIV_40
5018 * @arg @ref LL_RCC_PLLM_DIV_41
5019 * @arg @ref LL_RCC_PLLM_DIV_42
5020 * @arg @ref LL_RCC_PLLM_DIV_43
5021 * @arg @ref LL_RCC_PLLM_DIV_44
5022 * @arg @ref LL_RCC_PLLM_DIV_45
5023 * @arg @ref LL_RCC_PLLM_DIV_46
5024 * @arg @ref LL_RCC_PLLM_DIV_47
5025 * @arg @ref LL_RCC_PLLM_DIV_48
5026 * @arg @ref LL_RCC_PLLM_DIV_49
5027 * @arg @ref LL_RCC_PLLM_DIV_50
5028 * @arg @ref LL_RCC_PLLM_DIV_51
5029 * @arg @ref LL_RCC_PLLM_DIV_52
5030 * @arg @ref LL_RCC_PLLM_DIV_53
5031 * @arg @ref LL_RCC_PLLM_DIV_54
5032 * @arg @ref LL_RCC_PLLM_DIV_55
5033 * @arg @ref LL_RCC_PLLM_DIV_56
5034 * @arg @ref LL_RCC_PLLM_DIV_57
5035 * @arg @ref LL_RCC_PLLM_DIV_58
5036 * @arg @ref LL_RCC_PLLM_DIV_59
5037 * @arg @ref LL_RCC_PLLM_DIV_60
5038 * @arg @ref LL_RCC_PLLM_DIV_61
5039 * @arg @ref LL_RCC_PLLM_DIV_62
5040 * @arg @ref LL_RCC_PLLM_DIV_63
5041 */
LL_RCC_PLL_GetDivider(void)5042 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
5043 {
5044 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
5045 }
5046
5047 /**
5048 * @brief Configure Spread Spectrum used for PLL
5049 * @note These bits must be written before enabling PLL
5050 * @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n
5051 * SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n
5052 * SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum
5053 * @param Mod Between Min_Data=0 and Max_Data=8191
5054 * @param Inc Between Min_Data=0 and Max_Data=32767
5055 * @param Sel This parameter can be one of the following values:
5056 * @arg @ref LL_RCC_SPREAD_SELECT_CENTER
5057 * @arg @ref LL_RCC_SPREAD_SELECT_DOWN
5058 * @retval None
5059 */
LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod,uint32_t Inc,uint32_t Sel)5060 __STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
5061 {
5062 MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel);
5063 }
5064
5065 /**
5066 * @brief Get Spread Spectrum Modulation Period for PLL
5067 * @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation
5068 * @retval Between Min_Data=0 and Max_Data=8191
5069 */
LL_RCC_PLL_GetPeriodModulation(void)5070 __STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
5071 {
5072 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
5073 }
5074
5075 /**
5076 * @brief Get Spread Spectrum Incrementation Step for PLL
5077 * @note Must be written before enabling PLL
5078 * @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation
5079 * @retval Between Min_Data=0 and Max_Data=32767
5080 */
LL_RCC_PLL_GetStepIncrementation(void)5081 __STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
5082 {
5083 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
5084 }
5085
5086 /**
5087 * @brief Get Spread Spectrum Selection for PLL
5088 * @note Must be written before enabling PLL
5089 * @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection
5090 * @retval Returned value can be one of the following values:
5091 * @arg @ref LL_RCC_SPREAD_SELECT_CENTER
5092 * @arg @ref LL_RCC_SPREAD_SELECT_DOWN
5093 */
LL_RCC_PLL_GetSpreadSelection(void)5094 __STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
5095 {
5096 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
5097 }
5098
5099 /**
5100 * @brief Enable Spread Spectrum for PLL.
5101 * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable
5102 * @retval None
5103 */
LL_RCC_PLL_SpreadSpectrum_Enable(void)5104 __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
5105 {
5106 SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
5107 }
5108
5109 /**
5110 * @brief Disable Spread Spectrum for PLL.
5111 * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable
5112 * @retval None
5113 */
LL_RCC_PLL_SpreadSpectrum_Disable(void)5114 __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
5115 {
5116 CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
5117 }
5118
5119 /**
5120 * @}
5121 */
5122
5123 #if defined(RCC_PLLI2S_SUPPORT)
5124 /** @defgroup RCC_LL_EF_PLLI2S PLLI2S
5125 * @{
5126 */
5127
5128 /**
5129 * @brief Enable PLLI2S
5130 * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable
5131 * @retval None
5132 */
LL_RCC_PLLI2S_Enable(void)5133 __STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
5134 {
5135 SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
5136 }
5137
5138 /**
5139 * @brief Disable PLLI2S
5140 * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable
5141 * @retval None
5142 */
LL_RCC_PLLI2S_Disable(void)5143 __STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
5144 {
5145 CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
5146 }
5147
5148 /**
5149 * @brief Check if PLLI2S Ready
5150 * @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady
5151 * @retval State of bit (1 or 0).
5152 */
LL_RCC_PLLI2S_IsReady(void)5153 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
5154 {
5155 return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
5156 }
5157
5158 #if (defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR))
5159 /**
5160 * @brief Configure PLLI2S used for SAI domain clock
5161 * @note PLL Source and PLLM Divider can be written only when PLL,
5162 * PLLI2S and PLLSAI(*) are disabled
5163 * @note PLLN/PLLQ/PLLR can be written only when PLLI2S is disabled
5164 * @note This can be selected for SAI
5165 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
5166 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
5167 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n
5168 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SAI\n
5169 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n
5170 * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
5171 * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_SAI\n
5172 * DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
5173 * DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_ConfigDomain_SAI
5174 * @param Source This parameter can be one of the following values:
5175 * @arg @ref LL_RCC_PLLSOURCE_HSI
5176 * @arg @ref LL_RCC_PLLSOURCE_HSE
5177 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
5178 *
5179 * (*) value not defined in all devices.
5180 * @param PLLM This parameter can be one of the following values:
5181 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5182 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5183 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5184 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5185 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5186 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5187 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5188 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5189 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5190 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5191 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5192 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5193 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5194 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5195 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5196 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5197 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5198 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5199 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5200 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5201 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5202 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5203 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5204 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5205 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5206 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5207 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5208 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5209 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5210 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5211 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5212 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5213 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5214 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5215 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5216 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5217 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5218 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5219 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5220 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5221 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5222 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5223 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5224 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5225 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5226 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5227 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5228 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5229 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5230 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5231 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5232 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5233 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5234 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5235 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5236 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5237 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5238 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5239 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5240 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5241 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5242 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5243 * @param PLLN Between 50/192(*) and 432
5244 *
5245 * (*) value not defined in all devices.
5246 * @param PLLQ_R This parameter can be one of the following values:
5247 * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
5248 * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
5249 * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
5250 * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
5251 * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
5252 * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
5253 * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
5254 * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
5255 * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
5256 * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
5257 * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
5258 * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
5259 * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
5260 * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
5261 * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
5262 * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
5263 * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
5264 * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
5265 * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
5266 * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
5267 *
5268 * (*) value not defined in all devices.
5269 * @param PLLDIVQ_R This parameter can be one of the following values:
5270 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
5271 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
5272 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
5273 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
5274 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
5275 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
5276 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
5277 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
5278 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
5279 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
5280 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
5281 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
5282 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
5283 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
5284 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
5285 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
5286 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
5287 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
5288 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
5289 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
5290 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
5291 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
5292 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
5293 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
5294 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
5295 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
5296 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
5297 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
5298 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
5299 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
5300 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
5301 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
5302 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
5303 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
5304 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
5305 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
5306 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
5307 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
5308 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
5309 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
5310 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
5311 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
5312 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
5313 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
5314 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
5315 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
5316 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
5317 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
5318 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
5319 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
5320 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
5321 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
5322 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
5323 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
5324 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
5325 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
5326 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
5327 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
5328 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
5329 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
5330 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
5331 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
5332 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
5333 *
5334 * (*) value not defined in all devices.
5335 * @retval None
5336 */
LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ_R,uint32_t PLLDIVQ_R)5337 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R)
5338 {
5339 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
5340 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
5341 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5342 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5343 #else
5344 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5345 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5346 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos);
5347 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
5348 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ, PLLQ_R);
5349 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, PLLDIVQ_R);
5350 #else
5351 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR, PLLQ_R);
5352 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, PLLDIVQ_R);
5353 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
5354 }
5355 #endif /* RCC_DCKCFGR_PLLI2SDIVQ && RCC_DCKCFGR_PLLI2SDIVR */
5356
5357 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
5358 /**
5359 * @brief Configure PLLI2S used for 48Mhz domain clock
5360 * @note PLL Source and PLLM Divider can be written only when PLL,
5361 * PLLI2S and PLLSAI(*) are disabled
5362 * @note PLLN/PLLQ can be written only when PLLI2S is disabled
5363 * @note This can be selected for RNG, USB, SDIO
5364 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_48M\n
5365 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_48M\n
5366 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_48M\n
5367 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_48M\n
5368 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_48M\n
5369 * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_48M
5370 * @param Source This parameter can be one of the following values:
5371 * @arg @ref LL_RCC_PLLSOURCE_HSI
5372 * @arg @ref LL_RCC_PLLSOURCE_HSE
5373 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
5374 *
5375 * (*) value not defined in all devices.
5376 * @param PLLM This parameter can be one of the following values:
5377 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5378 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5379 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5380 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5381 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5382 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5383 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5384 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5385 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5386 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5387 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5388 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5389 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5390 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5391 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5392 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5393 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5394 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5395 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5396 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5397 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5398 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5399 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5400 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5401 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5402 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5403 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5404 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5405 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5406 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5407 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5408 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5409 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5410 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5411 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5412 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5413 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5414 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5415 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5416 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5417 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5418 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5419 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5420 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5421 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5422 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5423 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5424 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5425 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5426 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5427 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5428 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5429 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5430 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5431 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5432 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5433 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5434 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5435 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5436 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5437 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5438 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5439 * @param PLLN Between 50 and 432
5440 * @param PLLQ This parameter can be one of the following values:
5441 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
5442 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
5443 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
5444 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
5445 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
5446 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
5447 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
5448 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
5449 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
5450 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
5451 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
5452 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
5453 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
5454 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
5455 * @retval None
5456 */
LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)5457 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
5458 {
5459 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
5460 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
5461 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5462 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5463 #else
5464 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5465 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5466 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ);
5467 }
5468 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
5469
5470 #if defined(SPDIFRX)
5471 /**
5472 * @brief Configure PLLI2S used for SPDIFRX domain clock
5473 * @note PLL Source and PLLM Divider can be written only when PLL,
5474 * PLLI2S and PLLSAI(*) are disabled
5475 * @note PLLN/PLLP can be written only when PLLI2S is disabled
5476 * @note This can be selected for SPDIFRX
5477 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
5478 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
5479 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
5480 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
5481 * PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
5482 * @param Source This parameter can be one of the following values:
5483 * @arg @ref LL_RCC_PLLSOURCE_HSI
5484 * @arg @ref LL_RCC_PLLSOURCE_HSE
5485 * @param PLLM This parameter can be one of the following values:
5486 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5487 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5488 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5489 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5490 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5491 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5492 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5493 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5494 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5495 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5496 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5497 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5498 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5499 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5500 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5501 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5502 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5503 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5504 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5505 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5506 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5507 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5508 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5509 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5510 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5511 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5512 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5513 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5514 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5515 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5516 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5517 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5518 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5519 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5520 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5521 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5522 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5523 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5524 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5525 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5526 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5527 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5528 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5529 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5530 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5531 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5532 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5533 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5534 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5535 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5536 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5537 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5538 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5539 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5540 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5541 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5542 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5543 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5544 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5545 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5546 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5547 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5548 * @param PLLN Between 50 and 432
5549 * @param PLLP This parameter can be one of the following values:
5550 * @arg @ref LL_RCC_PLLI2SP_DIV_2
5551 * @arg @ref LL_RCC_PLLI2SP_DIV_4
5552 * @arg @ref LL_RCC_PLLI2SP_DIV_6
5553 * @arg @ref LL_RCC_PLLI2SP_DIV_8
5554 * @retval None
5555 */
LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)5556 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
5557 {
5558 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
5559 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5560 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5561 #else
5562 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5563 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5564 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP);
5565 }
5566 #endif /* SPDIFRX */
5567
5568 /**
5569 * @brief Configure PLLI2S used for I2S1 domain clock
5570 * @note PLL Source and PLLM Divider can be written only when PLL,
5571 * PLLI2S and PLLSAI(*) are disabled
5572 * @note PLLN/PLLR can be written only when PLLI2S is disabled
5573 * @note This can be selected for I2S
5574 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
5575 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n
5576 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
5577 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_I2S\n
5578 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n
5579 * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S
5580 * @param Source This parameter can be one of the following values:
5581 * @arg @ref LL_RCC_PLLSOURCE_HSI
5582 * @arg @ref LL_RCC_PLLSOURCE_HSE
5583 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
5584 *
5585 * (*) value not defined in all devices.
5586 * @param PLLM This parameter can be one of the following values:
5587 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5588 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5589 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5590 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5591 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5592 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5593 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5594 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5595 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5596 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5597 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5598 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5599 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5600 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5601 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5602 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5603 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5604 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5605 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5606 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5607 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5608 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5609 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5610 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5611 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5612 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5613 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5614 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5615 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5616 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5617 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5618 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5619 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5620 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5621 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5622 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5623 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5624 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5625 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5626 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5627 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5628 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5629 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5630 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5631 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5632 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5633 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5634 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5635 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5636 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5637 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5638 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5639 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5640 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5641 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5642 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5643 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5644 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5645 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5646 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5647 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5648 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5649 * @param PLLN Between 50/192(*) and 432
5650 *
5651 * (*) value not defined in all devices.
5652 * @param PLLR This parameter can be one of the following values:
5653 * @arg @ref LL_RCC_PLLI2SR_DIV_2
5654 * @arg @ref LL_RCC_PLLI2SR_DIV_3
5655 * @arg @ref LL_RCC_PLLI2SR_DIV_4
5656 * @arg @ref LL_RCC_PLLI2SR_DIV_5
5657 * @arg @ref LL_RCC_PLLI2SR_DIV_6
5658 * @arg @ref LL_RCC_PLLI2SR_DIV_7
5659 * @retval None
5660 */
LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)5661 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
5662 {
5663 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
5664 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
5665 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5666 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5667 #else
5668 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5669 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5670 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR);
5671 }
5672
5673 /**
5674 * @brief Get I2SPLL multiplication factor for VCO
5675 * @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN
5676 * @retval Between 50/192(*) and 432
5677 *
5678 * (*) value not defined in all devices.
5679 */
LL_RCC_PLLI2S_GetN(void)5680 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
5681 {
5682 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
5683 }
5684
5685 #if defined(RCC_PLLI2SCFGR_PLLI2SQ)
5686 /**
5687 * @brief Get I2SPLL division factor for PLLI2SQ
5688 * @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ
5689 * @retval Returned value can be one of the following values:
5690 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
5691 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
5692 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
5693 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
5694 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
5695 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
5696 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
5697 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
5698 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
5699 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
5700 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
5701 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
5702 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
5703 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
5704 */
LL_RCC_PLLI2S_GetQ(void)5705 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)
5706 {
5707 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));
5708 }
5709 #endif /* RCC_PLLI2SCFGR_PLLI2SQ */
5710
5711 /**
5712 * @brief Get I2SPLL division factor for PLLI2SR
5713 * @note used for PLLI2SCLK (I2S clock)
5714 * @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR
5715 * @retval Returned value can be one of the following values:
5716 * @arg @ref LL_RCC_PLLI2SR_DIV_2
5717 * @arg @ref LL_RCC_PLLI2SR_DIV_3
5718 * @arg @ref LL_RCC_PLLI2SR_DIV_4
5719 * @arg @ref LL_RCC_PLLI2SR_DIV_5
5720 * @arg @ref LL_RCC_PLLI2SR_DIV_6
5721 * @arg @ref LL_RCC_PLLI2SR_DIV_7
5722 */
LL_RCC_PLLI2S_GetR(void)5723 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
5724 {
5725 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
5726 }
5727
5728 #if defined(RCC_PLLI2SCFGR_PLLI2SP)
5729 /**
5730 * @brief Get I2SPLL division factor for PLLI2SP
5731 * @note used for PLLSPDIFRXCLK (SPDIFRX clock)
5732 * @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP
5733 * @retval Returned value can be one of the following values:
5734 * @arg @ref LL_RCC_PLLI2SP_DIV_2
5735 * @arg @ref LL_RCC_PLLI2SP_DIV_4
5736 * @arg @ref LL_RCC_PLLI2SP_DIV_6
5737 * @arg @ref LL_RCC_PLLI2SP_DIV_8
5738 */
LL_RCC_PLLI2S_GetP(void)5739 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)
5740 {
5741 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));
5742 }
5743 #endif /* RCC_PLLI2SCFGR_PLLI2SP */
5744
5745 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
5746 /**
5747 * @brief Get I2SPLL division factor for PLLI2SDIVQ
5748 * @note used PLLSAICLK selected (SAI clock)
5749 * @rmtoll DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ
5750 * @retval Returned value can be one of the following values:
5751 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
5752 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
5753 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
5754 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
5755 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
5756 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
5757 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
5758 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
5759 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
5760 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
5761 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
5762 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
5763 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
5764 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
5765 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
5766 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
5767 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
5768 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
5769 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
5770 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
5771 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
5772 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
5773 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
5774 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
5775 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
5776 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
5777 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
5778 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
5779 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
5780 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
5781 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
5782 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
5783 */
LL_RCC_PLLI2S_GetDIVQ(void)5784 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)
5785 {
5786 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ));
5787 }
5788 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
5789
5790 #if defined(RCC_DCKCFGR_PLLI2SDIVR)
5791 /**
5792 * @brief Get I2SPLL division factor for PLLI2SDIVR
5793 * @note used PLLSAICLK selected (SAI clock)
5794 * @rmtoll DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_GetDIVR
5795 * @retval Returned value can be one of the following values:
5796 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1
5797 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2
5798 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3
5799 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4
5800 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5
5801 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6
5802 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7
5803 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8
5804 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9
5805 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10
5806 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11
5807 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12
5808 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13
5809 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14
5810 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15
5811 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16
5812 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17
5813 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18
5814 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19
5815 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20
5816 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21
5817 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22
5818 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23
5819 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24
5820 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25
5821 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26
5822 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27
5823 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28
5824 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29
5825 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30
5826 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31
5827 */
LL_RCC_PLLI2S_GetDIVR(void)5828 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVR(void)
5829 {
5830 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR));
5831 }
5832 #endif /* RCC_DCKCFGR_PLLI2SDIVR */
5833
5834 /**
5835 * @brief Get division factor for PLLI2S input clock
5836 * @rmtoll PLLCFGR PLLM LL_RCC_PLLI2S_GetDivider\n
5837 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_GetDivider
5838 * @retval Returned value can be one of the following values:
5839 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5840 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5841 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5842 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5843 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5844 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5845 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5846 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5847 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5848 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5849 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5850 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5851 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5852 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5853 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5854 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5855 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5856 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5857 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5858 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5859 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5860 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5861 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5862 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5863 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5864 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5865 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5866 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5867 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5868 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5869 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5870 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5871 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5872 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5873 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5874 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5875 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5876 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5877 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5878 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5879 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5880 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5881 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5882 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5883 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5884 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5885 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5886 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5887 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5888 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5889 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5890 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5891 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5892 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5893 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5894 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5895 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5896 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5897 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5898 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5899 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5900 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5901 */
LL_RCC_PLLI2S_GetDivider(void)5902 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void)
5903 {
5904 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5905 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM));
5906 #else
5907 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
5908 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5909 }
5910
5911 /**
5912 * @brief Get the oscillator used as PLL clock source.
5913 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_GetMainSource\n
5914 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_GetMainSource
5915 * @retval Returned value can be one of the following values:
5916 * @arg @ref LL_RCC_PLLSOURCE_HSI
5917 * @arg @ref LL_RCC_PLLSOURCE_HSE
5918 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
5919 *
5920 * (*) value not defined in all devices.
5921 */
LL_RCC_PLLI2S_GetMainSource(void)5922 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void)
5923 {
5924 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
5925 uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
5926 uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC);
5927 uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U;
5928 return (uint32_t)(pllsrc | plli2sssrc0 | plli2sssrc1);
5929 #else
5930 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
5931 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
5932 }
5933
5934 /**
5935 * @}
5936 */
5937 #endif /* RCC_PLLI2S_SUPPORT */
5938
5939 #if defined(RCC_PLLSAI_SUPPORT)
5940 /** @defgroup RCC_LL_EF_PLLSAI PLLSAI
5941 * @{
5942 */
5943
5944 /**
5945 * @brief Enable PLLSAI
5946 * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable
5947 * @retval None
5948 */
LL_RCC_PLLSAI_Enable(void)5949 __STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)
5950 {
5951 SET_BIT(RCC->CR, RCC_CR_PLLSAION);
5952 }
5953
5954 /**
5955 * @brief Disable PLLSAI
5956 * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable
5957 * @retval None
5958 */
LL_RCC_PLLSAI_Disable(void)5959 __STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)
5960 {
5961 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
5962 }
5963
5964 /**
5965 * @brief Check if PLLSAI Ready
5966 * @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady
5967 * @retval State of bit (1 or 0).
5968 */
LL_RCC_PLLSAI_IsReady(void)5969 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)
5970 {
5971 return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));
5972 }
5973
5974 /**
5975 * @brief Configure PLLSAI used for SAI domain clock
5976 * @note PLL Source and PLLM Divider can be written only when PLL,
5977 * PLLI2S and PLLSAI(*) are disabled
5978 * @note PLLN/PLLQ can be written only when PLLSAI is disabled
5979 * @note This can be selected for SAI
5980 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n
5981 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n
5982 * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_SAI\n
5983 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n
5984 * PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n
5985 * DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI
5986 * @param Source This parameter can be one of the following values:
5987 * @arg @ref LL_RCC_PLLSOURCE_HSI
5988 * @arg @ref LL_RCC_PLLSOURCE_HSE
5989 * @param PLLM This parameter can be one of the following values:
5990 * @arg @ref LL_RCC_PLLSAIM_DIV_2
5991 * @arg @ref LL_RCC_PLLSAIM_DIV_3
5992 * @arg @ref LL_RCC_PLLSAIM_DIV_4
5993 * @arg @ref LL_RCC_PLLSAIM_DIV_5
5994 * @arg @ref LL_RCC_PLLSAIM_DIV_6
5995 * @arg @ref LL_RCC_PLLSAIM_DIV_7
5996 * @arg @ref LL_RCC_PLLSAIM_DIV_8
5997 * @arg @ref LL_RCC_PLLSAIM_DIV_9
5998 * @arg @ref LL_RCC_PLLSAIM_DIV_10
5999 * @arg @ref LL_RCC_PLLSAIM_DIV_11
6000 * @arg @ref LL_RCC_PLLSAIM_DIV_12
6001 * @arg @ref LL_RCC_PLLSAIM_DIV_13
6002 * @arg @ref LL_RCC_PLLSAIM_DIV_14
6003 * @arg @ref LL_RCC_PLLSAIM_DIV_15
6004 * @arg @ref LL_RCC_PLLSAIM_DIV_16
6005 * @arg @ref LL_RCC_PLLSAIM_DIV_17
6006 * @arg @ref LL_RCC_PLLSAIM_DIV_18
6007 * @arg @ref LL_RCC_PLLSAIM_DIV_19
6008 * @arg @ref LL_RCC_PLLSAIM_DIV_20
6009 * @arg @ref LL_RCC_PLLSAIM_DIV_21
6010 * @arg @ref LL_RCC_PLLSAIM_DIV_22
6011 * @arg @ref LL_RCC_PLLSAIM_DIV_23
6012 * @arg @ref LL_RCC_PLLSAIM_DIV_24
6013 * @arg @ref LL_RCC_PLLSAIM_DIV_25
6014 * @arg @ref LL_RCC_PLLSAIM_DIV_26
6015 * @arg @ref LL_RCC_PLLSAIM_DIV_27
6016 * @arg @ref LL_RCC_PLLSAIM_DIV_28
6017 * @arg @ref LL_RCC_PLLSAIM_DIV_29
6018 * @arg @ref LL_RCC_PLLSAIM_DIV_30
6019 * @arg @ref LL_RCC_PLLSAIM_DIV_31
6020 * @arg @ref LL_RCC_PLLSAIM_DIV_32
6021 * @arg @ref LL_RCC_PLLSAIM_DIV_33
6022 * @arg @ref LL_RCC_PLLSAIM_DIV_34
6023 * @arg @ref LL_RCC_PLLSAIM_DIV_35
6024 * @arg @ref LL_RCC_PLLSAIM_DIV_36
6025 * @arg @ref LL_RCC_PLLSAIM_DIV_37
6026 * @arg @ref LL_RCC_PLLSAIM_DIV_38
6027 * @arg @ref LL_RCC_PLLSAIM_DIV_39
6028 * @arg @ref LL_RCC_PLLSAIM_DIV_40
6029 * @arg @ref LL_RCC_PLLSAIM_DIV_41
6030 * @arg @ref LL_RCC_PLLSAIM_DIV_42
6031 * @arg @ref LL_RCC_PLLSAIM_DIV_43
6032 * @arg @ref LL_RCC_PLLSAIM_DIV_44
6033 * @arg @ref LL_RCC_PLLSAIM_DIV_45
6034 * @arg @ref LL_RCC_PLLSAIM_DIV_46
6035 * @arg @ref LL_RCC_PLLSAIM_DIV_47
6036 * @arg @ref LL_RCC_PLLSAIM_DIV_48
6037 * @arg @ref LL_RCC_PLLSAIM_DIV_49
6038 * @arg @ref LL_RCC_PLLSAIM_DIV_50
6039 * @arg @ref LL_RCC_PLLSAIM_DIV_51
6040 * @arg @ref LL_RCC_PLLSAIM_DIV_52
6041 * @arg @ref LL_RCC_PLLSAIM_DIV_53
6042 * @arg @ref LL_RCC_PLLSAIM_DIV_54
6043 * @arg @ref LL_RCC_PLLSAIM_DIV_55
6044 * @arg @ref LL_RCC_PLLSAIM_DIV_56
6045 * @arg @ref LL_RCC_PLLSAIM_DIV_57
6046 * @arg @ref LL_RCC_PLLSAIM_DIV_58
6047 * @arg @ref LL_RCC_PLLSAIM_DIV_59
6048 * @arg @ref LL_RCC_PLLSAIM_DIV_60
6049 * @arg @ref LL_RCC_PLLSAIM_DIV_61
6050 * @arg @ref LL_RCC_PLLSAIM_DIV_62
6051 * @arg @ref LL_RCC_PLLSAIM_DIV_63
6052 * @param PLLN Between 49/50(*) and 432
6053 *
6054 * (*) value not defined in all devices.
6055 * @param PLLQ This parameter can be one of the following values:
6056 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
6057 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
6058 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
6059 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
6060 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
6061 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
6062 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
6063 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
6064 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
6065 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
6066 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
6067 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
6068 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
6069 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
6070 * @param PLLDIVQ This parameter can be one of the following values:
6071 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
6072 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
6073 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
6074 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
6075 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
6076 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
6077 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
6078 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
6079 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
6080 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
6081 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
6082 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
6083 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
6084 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
6085 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
6086 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
6087 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
6088 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
6089 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
6090 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
6091 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
6092 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
6093 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
6094 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
6095 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
6096 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
6097 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
6098 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
6099 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
6100 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
6101 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
6102 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
6103 * @retval None
6104 */
LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ,uint32_t PLLDIVQ)6105 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
6106 {
6107 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
6108 #if defined(RCC_PLLSAICFGR_PLLSAIM)
6109 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
6110 #else
6111 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
6112 #endif /* RCC_PLLSAICFGR_PLLSAIM */
6113 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ);
6114 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, PLLDIVQ);
6115 }
6116
6117 #if defined(RCC_PLLSAICFGR_PLLSAIP)
6118 /**
6119 * @brief Configure PLLSAI used for 48Mhz domain clock
6120 * @note PLL Source and PLLM Divider can be written only when PLL,
6121 * PLLI2S and PLLSAI(*) are disabled
6122 * @note PLLN/PLLP can be written only when PLLSAI is disabled
6123 * @note This can be selected for USB, RNG, SDIO
6124 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n
6125 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n
6126 * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_48M\n
6127 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n
6128 * PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M
6129 * @param Source This parameter can be one of the following values:
6130 * @arg @ref LL_RCC_PLLSOURCE_HSI
6131 * @arg @ref LL_RCC_PLLSOURCE_HSE
6132 * @param PLLM This parameter can be one of the following values:
6133 * @arg @ref LL_RCC_PLLSAIM_DIV_2
6134 * @arg @ref LL_RCC_PLLSAIM_DIV_3
6135 * @arg @ref LL_RCC_PLLSAIM_DIV_4
6136 * @arg @ref LL_RCC_PLLSAIM_DIV_5
6137 * @arg @ref LL_RCC_PLLSAIM_DIV_6
6138 * @arg @ref LL_RCC_PLLSAIM_DIV_7
6139 * @arg @ref LL_RCC_PLLSAIM_DIV_8
6140 * @arg @ref LL_RCC_PLLSAIM_DIV_9
6141 * @arg @ref LL_RCC_PLLSAIM_DIV_10
6142 * @arg @ref LL_RCC_PLLSAIM_DIV_11
6143 * @arg @ref LL_RCC_PLLSAIM_DIV_12
6144 * @arg @ref LL_RCC_PLLSAIM_DIV_13
6145 * @arg @ref LL_RCC_PLLSAIM_DIV_14
6146 * @arg @ref LL_RCC_PLLSAIM_DIV_15
6147 * @arg @ref LL_RCC_PLLSAIM_DIV_16
6148 * @arg @ref LL_RCC_PLLSAIM_DIV_17
6149 * @arg @ref LL_RCC_PLLSAIM_DIV_18
6150 * @arg @ref LL_RCC_PLLSAIM_DIV_19
6151 * @arg @ref LL_RCC_PLLSAIM_DIV_20
6152 * @arg @ref LL_RCC_PLLSAIM_DIV_21
6153 * @arg @ref LL_RCC_PLLSAIM_DIV_22
6154 * @arg @ref LL_RCC_PLLSAIM_DIV_23
6155 * @arg @ref LL_RCC_PLLSAIM_DIV_24
6156 * @arg @ref LL_RCC_PLLSAIM_DIV_25
6157 * @arg @ref LL_RCC_PLLSAIM_DIV_26
6158 * @arg @ref LL_RCC_PLLSAIM_DIV_27
6159 * @arg @ref LL_RCC_PLLSAIM_DIV_28
6160 * @arg @ref LL_RCC_PLLSAIM_DIV_29
6161 * @arg @ref LL_RCC_PLLSAIM_DIV_30
6162 * @arg @ref LL_RCC_PLLSAIM_DIV_31
6163 * @arg @ref LL_RCC_PLLSAIM_DIV_32
6164 * @arg @ref LL_RCC_PLLSAIM_DIV_33
6165 * @arg @ref LL_RCC_PLLSAIM_DIV_34
6166 * @arg @ref LL_RCC_PLLSAIM_DIV_35
6167 * @arg @ref LL_RCC_PLLSAIM_DIV_36
6168 * @arg @ref LL_RCC_PLLSAIM_DIV_37
6169 * @arg @ref LL_RCC_PLLSAIM_DIV_38
6170 * @arg @ref LL_RCC_PLLSAIM_DIV_39
6171 * @arg @ref LL_RCC_PLLSAIM_DIV_40
6172 * @arg @ref LL_RCC_PLLSAIM_DIV_41
6173 * @arg @ref LL_RCC_PLLSAIM_DIV_42
6174 * @arg @ref LL_RCC_PLLSAIM_DIV_43
6175 * @arg @ref LL_RCC_PLLSAIM_DIV_44
6176 * @arg @ref LL_RCC_PLLSAIM_DIV_45
6177 * @arg @ref LL_RCC_PLLSAIM_DIV_46
6178 * @arg @ref LL_RCC_PLLSAIM_DIV_47
6179 * @arg @ref LL_RCC_PLLSAIM_DIV_48
6180 * @arg @ref LL_RCC_PLLSAIM_DIV_49
6181 * @arg @ref LL_RCC_PLLSAIM_DIV_50
6182 * @arg @ref LL_RCC_PLLSAIM_DIV_51
6183 * @arg @ref LL_RCC_PLLSAIM_DIV_52
6184 * @arg @ref LL_RCC_PLLSAIM_DIV_53
6185 * @arg @ref LL_RCC_PLLSAIM_DIV_54
6186 * @arg @ref LL_RCC_PLLSAIM_DIV_55
6187 * @arg @ref LL_RCC_PLLSAIM_DIV_56
6188 * @arg @ref LL_RCC_PLLSAIM_DIV_57
6189 * @arg @ref LL_RCC_PLLSAIM_DIV_58
6190 * @arg @ref LL_RCC_PLLSAIM_DIV_59
6191 * @arg @ref LL_RCC_PLLSAIM_DIV_60
6192 * @arg @ref LL_RCC_PLLSAIM_DIV_61
6193 * @arg @ref LL_RCC_PLLSAIM_DIV_62
6194 * @arg @ref LL_RCC_PLLSAIM_DIV_63
6195 * @param PLLN Between 50 and 432
6196 * @param PLLP This parameter can be one of the following values:
6197 * @arg @ref LL_RCC_PLLSAIP_DIV_2
6198 * @arg @ref LL_RCC_PLLSAIP_DIV_4
6199 * @arg @ref LL_RCC_PLLSAIP_DIV_6
6200 * @arg @ref LL_RCC_PLLSAIP_DIV_8
6201 * @retval None
6202 */
LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)6203 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
6204 {
6205 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
6206 #if defined(RCC_PLLSAICFGR_PLLSAIM)
6207 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
6208 #else
6209 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
6210 #endif /* RCC_PLLSAICFGR_PLLSAIM */
6211 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP);
6212 }
6213 #endif /* RCC_PLLSAICFGR_PLLSAIP */
6214
6215 #if defined(LTDC)
6216 /**
6217 * @brief Configure PLLSAI used for LTDC domain clock
6218 * @note PLL Source and PLLM Divider can be written only when PLL,
6219 * PLLI2S and PLLSAI(*) are disabled
6220 * @note PLLN/PLLR can be written only when PLLSAI is disabled
6221 * @note This can be selected for LTDC
6222 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n
6223 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n
6224 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n
6225 * PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n
6226 * DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC
6227 * @param Source This parameter can be one of the following values:
6228 * @arg @ref LL_RCC_PLLSOURCE_HSI
6229 * @arg @ref LL_RCC_PLLSOURCE_HSE
6230 * @param PLLM This parameter can be one of the following values:
6231 * @arg @ref LL_RCC_PLLSAIM_DIV_2
6232 * @arg @ref LL_RCC_PLLSAIM_DIV_3
6233 * @arg @ref LL_RCC_PLLSAIM_DIV_4
6234 * @arg @ref LL_RCC_PLLSAIM_DIV_5
6235 * @arg @ref LL_RCC_PLLSAIM_DIV_6
6236 * @arg @ref LL_RCC_PLLSAIM_DIV_7
6237 * @arg @ref LL_RCC_PLLSAIM_DIV_8
6238 * @arg @ref LL_RCC_PLLSAIM_DIV_9
6239 * @arg @ref LL_RCC_PLLSAIM_DIV_10
6240 * @arg @ref LL_RCC_PLLSAIM_DIV_11
6241 * @arg @ref LL_RCC_PLLSAIM_DIV_12
6242 * @arg @ref LL_RCC_PLLSAIM_DIV_13
6243 * @arg @ref LL_RCC_PLLSAIM_DIV_14
6244 * @arg @ref LL_RCC_PLLSAIM_DIV_15
6245 * @arg @ref LL_RCC_PLLSAIM_DIV_16
6246 * @arg @ref LL_RCC_PLLSAIM_DIV_17
6247 * @arg @ref LL_RCC_PLLSAIM_DIV_18
6248 * @arg @ref LL_RCC_PLLSAIM_DIV_19
6249 * @arg @ref LL_RCC_PLLSAIM_DIV_20
6250 * @arg @ref LL_RCC_PLLSAIM_DIV_21
6251 * @arg @ref LL_RCC_PLLSAIM_DIV_22
6252 * @arg @ref LL_RCC_PLLSAIM_DIV_23
6253 * @arg @ref LL_RCC_PLLSAIM_DIV_24
6254 * @arg @ref LL_RCC_PLLSAIM_DIV_25
6255 * @arg @ref LL_RCC_PLLSAIM_DIV_26
6256 * @arg @ref LL_RCC_PLLSAIM_DIV_27
6257 * @arg @ref LL_RCC_PLLSAIM_DIV_28
6258 * @arg @ref LL_RCC_PLLSAIM_DIV_29
6259 * @arg @ref LL_RCC_PLLSAIM_DIV_30
6260 * @arg @ref LL_RCC_PLLSAIM_DIV_31
6261 * @arg @ref LL_RCC_PLLSAIM_DIV_32
6262 * @arg @ref LL_RCC_PLLSAIM_DIV_33
6263 * @arg @ref LL_RCC_PLLSAIM_DIV_34
6264 * @arg @ref LL_RCC_PLLSAIM_DIV_35
6265 * @arg @ref LL_RCC_PLLSAIM_DIV_36
6266 * @arg @ref LL_RCC_PLLSAIM_DIV_37
6267 * @arg @ref LL_RCC_PLLSAIM_DIV_38
6268 * @arg @ref LL_RCC_PLLSAIM_DIV_39
6269 * @arg @ref LL_RCC_PLLSAIM_DIV_40
6270 * @arg @ref LL_RCC_PLLSAIM_DIV_41
6271 * @arg @ref LL_RCC_PLLSAIM_DIV_42
6272 * @arg @ref LL_RCC_PLLSAIM_DIV_43
6273 * @arg @ref LL_RCC_PLLSAIM_DIV_44
6274 * @arg @ref LL_RCC_PLLSAIM_DIV_45
6275 * @arg @ref LL_RCC_PLLSAIM_DIV_46
6276 * @arg @ref LL_RCC_PLLSAIM_DIV_47
6277 * @arg @ref LL_RCC_PLLSAIM_DIV_48
6278 * @arg @ref LL_RCC_PLLSAIM_DIV_49
6279 * @arg @ref LL_RCC_PLLSAIM_DIV_50
6280 * @arg @ref LL_RCC_PLLSAIM_DIV_51
6281 * @arg @ref LL_RCC_PLLSAIM_DIV_52
6282 * @arg @ref LL_RCC_PLLSAIM_DIV_53
6283 * @arg @ref LL_RCC_PLLSAIM_DIV_54
6284 * @arg @ref LL_RCC_PLLSAIM_DIV_55
6285 * @arg @ref LL_RCC_PLLSAIM_DIV_56
6286 * @arg @ref LL_RCC_PLLSAIM_DIV_57
6287 * @arg @ref LL_RCC_PLLSAIM_DIV_58
6288 * @arg @ref LL_RCC_PLLSAIM_DIV_59
6289 * @arg @ref LL_RCC_PLLSAIM_DIV_60
6290 * @arg @ref LL_RCC_PLLSAIM_DIV_61
6291 * @arg @ref LL_RCC_PLLSAIM_DIV_62
6292 * @arg @ref LL_RCC_PLLSAIM_DIV_63
6293 * @param PLLN Between 49/50(*) and 432
6294 *
6295 * (*) value not defined in all devices.
6296 * @param PLLR This parameter can be one of the following values:
6297 * @arg @ref LL_RCC_PLLSAIR_DIV_2
6298 * @arg @ref LL_RCC_PLLSAIR_DIV_3
6299 * @arg @ref LL_RCC_PLLSAIR_DIV_4
6300 * @arg @ref LL_RCC_PLLSAIR_DIV_5
6301 * @arg @ref LL_RCC_PLLSAIR_DIV_6
6302 * @arg @ref LL_RCC_PLLSAIR_DIV_7
6303 * @param PLLDIVR This parameter can be one of the following values:
6304 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
6305 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
6306 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
6307 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
6308 * @retval None
6309 */
LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR,uint32_t PLLDIVR)6310 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
6311 {
6312 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
6313 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR);
6314 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, PLLDIVR);
6315 }
6316 #endif /* LTDC */
6317
6318 /**
6319 * @brief Get division factor for PLLSAI input clock
6320 * @rmtoll PLLCFGR PLLM LL_RCC_PLLSAI_GetDivider\n
6321 * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_GetDivider
6322 * @retval Returned value can be one of the following values:
6323 * @arg @ref LL_RCC_PLLSAIM_DIV_2
6324 * @arg @ref LL_RCC_PLLSAIM_DIV_3
6325 * @arg @ref LL_RCC_PLLSAIM_DIV_4
6326 * @arg @ref LL_RCC_PLLSAIM_DIV_5
6327 * @arg @ref LL_RCC_PLLSAIM_DIV_6
6328 * @arg @ref LL_RCC_PLLSAIM_DIV_7
6329 * @arg @ref LL_RCC_PLLSAIM_DIV_8
6330 * @arg @ref LL_RCC_PLLSAIM_DIV_9
6331 * @arg @ref LL_RCC_PLLSAIM_DIV_10
6332 * @arg @ref LL_RCC_PLLSAIM_DIV_11
6333 * @arg @ref LL_RCC_PLLSAIM_DIV_12
6334 * @arg @ref LL_RCC_PLLSAIM_DIV_13
6335 * @arg @ref LL_RCC_PLLSAIM_DIV_14
6336 * @arg @ref LL_RCC_PLLSAIM_DIV_15
6337 * @arg @ref LL_RCC_PLLSAIM_DIV_16
6338 * @arg @ref LL_RCC_PLLSAIM_DIV_17
6339 * @arg @ref LL_RCC_PLLSAIM_DIV_18
6340 * @arg @ref LL_RCC_PLLSAIM_DIV_19
6341 * @arg @ref LL_RCC_PLLSAIM_DIV_20
6342 * @arg @ref LL_RCC_PLLSAIM_DIV_21
6343 * @arg @ref LL_RCC_PLLSAIM_DIV_22
6344 * @arg @ref LL_RCC_PLLSAIM_DIV_23
6345 * @arg @ref LL_RCC_PLLSAIM_DIV_24
6346 * @arg @ref LL_RCC_PLLSAIM_DIV_25
6347 * @arg @ref LL_RCC_PLLSAIM_DIV_26
6348 * @arg @ref LL_RCC_PLLSAIM_DIV_27
6349 * @arg @ref LL_RCC_PLLSAIM_DIV_28
6350 * @arg @ref LL_RCC_PLLSAIM_DIV_29
6351 * @arg @ref LL_RCC_PLLSAIM_DIV_30
6352 * @arg @ref LL_RCC_PLLSAIM_DIV_31
6353 * @arg @ref LL_RCC_PLLSAIM_DIV_32
6354 * @arg @ref LL_RCC_PLLSAIM_DIV_33
6355 * @arg @ref LL_RCC_PLLSAIM_DIV_34
6356 * @arg @ref LL_RCC_PLLSAIM_DIV_35
6357 * @arg @ref LL_RCC_PLLSAIM_DIV_36
6358 * @arg @ref LL_RCC_PLLSAIM_DIV_37
6359 * @arg @ref LL_RCC_PLLSAIM_DIV_38
6360 * @arg @ref LL_RCC_PLLSAIM_DIV_39
6361 * @arg @ref LL_RCC_PLLSAIM_DIV_40
6362 * @arg @ref LL_RCC_PLLSAIM_DIV_41
6363 * @arg @ref LL_RCC_PLLSAIM_DIV_42
6364 * @arg @ref LL_RCC_PLLSAIM_DIV_43
6365 * @arg @ref LL_RCC_PLLSAIM_DIV_44
6366 * @arg @ref LL_RCC_PLLSAIM_DIV_45
6367 * @arg @ref LL_RCC_PLLSAIM_DIV_46
6368 * @arg @ref LL_RCC_PLLSAIM_DIV_47
6369 * @arg @ref LL_RCC_PLLSAIM_DIV_48
6370 * @arg @ref LL_RCC_PLLSAIM_DIV_49
6371 * @arg @ref LL_RCC_PLLSAIM_DIV_50
6372 * @arg @ref LL_RCC_PLLSAIM_DIV_51
6373 * @arg @ref LL_RCC_PLLSAIM_DIV_52
6374 * @arg @ref LL_RCC_PLLSAIM_DIV_53
6375 * @arg @ref LL_RCC_PLLSAIM_DIV_54
6376 * @arg @ref LL_RCC_PLLSAIM_DIV_55
6377 * @arg @ref LL_RCC_PLLSAIM_DIV_56
6378 * @arg @ref LL_RCC_PLLSAIM_DIV_57
6379 * @arg @ref LL_RCC_PLLSAIM_DIV_58
6380 * @arg @ref LL_RCC_PLLSAIM_DIV_59
6381 * @arg @ref LL_RCC_PLLSAIM_DIV_60
6382 * @arg @ref LL_RCC_PLLSAIM_DIV_61
6383 * @arg @ref LL_RCC_PLLSAIM_DIV_62
6384 * @arg @ref LL_RCC_PLLSAIM_DIV_63
6385 */
LL_RCC_PLLSAI_GetDivider(void)6386 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDivider(void)
6387 {
6388 #if defined(RCC_PLLSAICFGR_PLLSAIM)
6389 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM));
6390 #else
6391 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
6392 #endif /* RCC_PLLSAICFGR_PLLSAIM */
6393 }
6394
6395 /**
6396 * @brief Get SAIPLL multiplication factor for VCO
6397 * @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN
6398 * @retval Between 49/50(*) and 432
6399 *
6400 * (*) value not defined in all devices.
6401 */
LL_RCC_PLLSAI_GetN(void)6402 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void)
6403 {
6404 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
6405 }
6406
6407 /**
6408 * @brief Get SAIPLL division factor for PLLSAIQ
6409 * @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ
6410 * @retval Returned value can be one of the following values:
6411 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
6412 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
6413 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
6414 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
6415 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
6416 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
6417 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
6418 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
6419 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
6420 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
6421 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
6422 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
6423 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
6424 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
6425 */
LL_RCC_PLLSAI_GetQ(void)6426 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void)
6427 {
6428 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ));
6429 }
6430
6431 #if defined(RCC_PLLSAICFGR_PLLSAIR)
6432 /**
6433 * @brief Get SAIPLL division factor for PLLSAIR
6434 * @note used for PLLSAICLK (SAI clock)
6435 * @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR
6436 * @retval Returned value can be one of the following values:
6437 * @arg @ref LL_RCC_PLLSAIR_DIV_2
6438 * @arg @ref LL_RCC_PLLSAIR_DIV_3
6439 * @arg @ref LL_RCC_PLLSAIR_DIV_4
6440 * @arg @ref LL_RCC_PLLSAIR_DIV_5
6441 * @arg @ref LL_RCC_PLLSAIR_DIV_6
6442 * @arg @ref LL_RCC_PLLSAIR_DIV_7
6443 */
LL_RCC_PLLSAI_GetR(void)6444 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void)
6445 {
6446 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR));
6447 }
6448 #endif /* RCC_PLLSAICFGR_PLLSAIR */
6449
6450 #if defined(RCC_PLLSAICFGR_PLLSAIP)
6451 /**
6452 * @brief Get SAIPLL division factor for PLLSAIP
6453 * @note used for PLL48MCLK (48M domain clock)
6454 * @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP
6455 * @retval Returned value can be one of the following values:
6456 * @arg @ref LL_RCC_PLLSAIP_DIV_2
6457 * @arg @ref LL_RCC_PLLSAIP_DIV_4
6458 * @arg @ref LL_RCC_PLLSAIP_DIV_6
6459 * @arg @ref LL_RCC_PLLSAIP_DIV_8
6460 */
LL_RCC_PLLSAI_GetP(void)6461 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void)
6462 {
6463 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP));
6464 }
6465 #endif /* RCC_PLLSAICFGR_PLLSAIP */
6466
6467 /**
6468 * @brief Get SAIPLL division factor for PLLSAIDIVQ
6469 * @note used PLLSAICLK selected (SAI clock)
6470 * @rmtoll DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ
6471 * @retval Returned value can be one of the following values:
6472 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
6473 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
6474 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
6475 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
6476 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
6477 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
6478 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
6479 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
6480 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
6481 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
6482 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
6483 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
6484 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
6485 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
6486 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
6487 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
6488 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
6489 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
6490 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
6491 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
6492 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
6493 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
6494 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
6495 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
6496 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
6497 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
6498 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
6499 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
6500 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
6501 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
6502 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
6503 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
6504 */
LL_RCC_PLLSAI_GetDIVQ(void)6505 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void)
6506 {
6507 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ));
6508 }
6509
6510 #if defined(RCC_DCKCFGR_PLLSAIDIVR)
6511 /**
6512 * @brief Get SAIPLL division factor for PLLSAIDIVR
6513 * @note used for LTDC domain clock
6514 * @rmtoll DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR
6515 * @retval Returned value can be one of the following values:
6516 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
6517 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
6518 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
6519 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
6520 */
LL_RCC_PLLSAI_GetDIVR(void)6521 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void)
6522 {
6523 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR));
6524 }
6525 #endif /* RCC_DCKCFGR_PLLSAIDIVR */
6526
6527 /**
6528 * @}
6529 */
6530 #endif /* RCC_PLLSAI_SUPPORT */
6531
6532 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
6533 * @{
6534 */
6535
6536 /**
6537 * @brief Clear LSI ready interrupt flag
6538 * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
6539 * @retval None
6540 */
LL_RCC_ClearFlag_LSIRDY(void)6541 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
6542 {
6543 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
6544 }
6545
6546 /**
6547 * @brief Clear LSE ready interrupt flag
6548 * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
6549 * @retval None
6550 */
LL_RCC_ClearFlag_LSERDY(void)6551 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
6552 {
6553 SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
6554 }
6555
6556 /**
6557 * @brief Clear HSI ready interrupt flag
6558 * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
6559 * @retval None
6560 */
LL_RCC_ClearFlag_HSIRDY(void)6561 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
6562 {
6563 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
6564 }
6565
6566 /**
6567 * @brief Clear HSE ready interrupt flag
6568 * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
6569 * @retval None
6570 */
LL_RCC_ClearFlag_HSERDY(void)6571 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
6572 {
6573 SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
6574 }
6575
6576 /**
6577 * @brief Clear PLL ready interrupt flag
6578 * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
6579 * @retval None
6580 */
LL_RCC_ClearFlag_PLLRDY(void)6581 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
6582 {
6583 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
6584 }
6585
6586 #if defined(RCC_PLLI2S_SUPPORT)
6587 /**
6588 * @brief Clear PLLI2S ready interrupt flag
6589 * @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY
6590 * @retval None
6591 */
LL_RCC_ClearFlag_PLLI2SRDY(void)6592 __STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
6593 {
6594 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
6595 }
6596
6597 #endif /* RCC_PLLI2S_SUPPORT */
6598
6599 #if defined(RCC_PLLSAI_SUPPORT)
6600 /**
6601 * @brief Clear PLLSAI ready interrupt flag
6602 * @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY
6603 * @retval None
6604 */
LL_RCC_ClearFlag_PLLSAIRDY(void)6605 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void)
6606 {
6607 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
6608 }
6609
6610 #endif /* RCC_PLLSAI_SUPPORT */
6611
6612 /**
6613 * @brief Clear Clock security system interrupt flag
6614 * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
6615 * @retval None
6616 */
LL_RCC_ClearFlag_HSECSS(void)6617 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
6618 {
6619 SET_BIT(RCC->CIR, RCC_CIR_CSSC);
6620 }
6621
6622 /**
6623 * @brief Check if LSI ready interrupt occurred or not
6624 * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
6625 * @retval State of bit (1 or 0).
6626 */
LL_RCC_IsActiveFlag_LSIRDY(void)6627 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
6628 {
6629 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
6630 }
6631
6632 /**
6633 * @brief Check if LSE ready interrupt occurred or not
6634 * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
6635 * @retval State of bit (1 or 0).
6636 */
LL_RCC_IsActiveFlag_LSERDY(void)6637 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
6638 {
6639 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
6640 }
6641
6642 /**
6643 * @brief Check if HSI ready interrupt occurred or not
6644 * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
6645 * @retval State of bit (1 or 0).
6646 */
LL_RCC_IsActiveFlag_HSIRDY(void)6647 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
6648 {
6649 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
6650 }
6651
6652 /**
6653 * @brief Check if HSE ready interrupt occurred or not
6654 * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
6655 * @retval State of bit (1 or 0).
6656 */
LL_RCC_IsActiveFlag_HSERDY(void)6657 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
6658 {
6659 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
6660 }
6661
6662 /**
6663 * @brief Check if PLL ready interrupt occurred or not
6664 * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
6665 * @retval State of bit (1 or 0).
6666 */
LL_RCC_IsActiveFlag_PLLRDY(void)6667 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
6668 {
6669 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
6670 }
6671
6672 #if defined(RCC_PLLI2S_SUPPORT)
6673 /**
6674 * @brief Check if PLLI2S ready interrupt occurred or not
6675 * @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY
6676 * @retval State of bit (1 or 0).
6677 */
LL_RCC_IsActiveFlag_PLLI2SRDY(void)6678 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
6679 {
6680 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
6681 }
6682 #endif /* RCC_PLLI2S_SUPPORT */
6683
6684 #if defined(RCC_PLLSAI_SUPPORT)
6685 /**
6686 * @brief Check if PLLSAI ready interrupt occurred or not
6687 * @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY
6688 * @retval State of bit (1 or 0).
6689 */
LL_RCC_IsActiveFlag_PLLSAIRDY(void)6690 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void)
6691 {
6692 return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF));
6693 }
6694 #endif /* RCC_PLLSAI_SUPPORT */
6695
6696 /**
6697 * @brief Check if Clock security system interrupt occurred or not
6698 * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
6699 * @retval State of bit (1 or 0).
6700 */
LL_RCC_IsActiveFlag_HSECSS(void)6701 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
6702 {
6703 return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
6704 }
6705
6706 /**
6707 * @brief Check if RCC flag Independent Watchdog reset is set or not.
6708 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
6709 * @retval State of bit (1 or 0).
6710 */
LL_RCC_IsActiveFlag_IWDGRST(void)6711 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
6712 {
6713 return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
6714 }
6715
6716 /**
6717 * @brief Check if RCC flag Low Power reset is set or not.
6718 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
6719 * @retval State of bit (1 or 0).
6720 */
LL_RCC_IsActiveFlag_LPWRRST(void)6721 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
6722 {
6723 return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
6724 }
6725
6726 /**
6727 * @brief Check if RCC flag Pin reset is set or not.
6728 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
6729 * @retval State of bit (1 or 0).
6730 */
LL_RCC_IsActiveFlag_PINRST(void)6731 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
6732 {
6733 return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
6734 }
6735
6736 /**
6737 * @brief Check if RCC flag POR/PDR reset is set or not.
6738 * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
6739 * @retval State of bit (1 or 0).
6740 */
LL_RCC_IsActiveFlag_PORRST(void)6741 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
6742 {
6743 return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
6744 }
6745
6746 /**
6747 * @brief Check if RCC flag Software reset is set or not.
6748 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
6749 * @retval State of bit (1 or 0).
6750 */
LL_RCC_IsActiveFlag_SFTRST(void)6751 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
6752 {
6753 return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
6754 }
6755
6756 /**
6757 * @brief Check if RCC flag Window Watchdog reset is set or not.
6758 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
6759 * @retval State of bit (1 or 0).
6760 */
LL_RCC_IsActiveFlag_WWDGRST(void)6761 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
6762 {
6763 return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
6764 }
6765
6766 #if defined(RCC_CSR_BORRSTF)
6767 /**
6768 * @brief Check if RCC flag BOR reset is set or not.
6769 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
6770 * @retval State of bit (1 or 0).
6771 */
LL_RCC_IsActiveFlag_BORRST(void)6772 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
6773 {
6774 return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
6775 }
6776 #endif /* RCC_CSR_BORRSTF */
6777
6778 /**
6779 * @brief Set RMVF bit to clear the reset flags.
6780 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
6781 * @retval None
6782 */
LL_RCC_ClearResetFlags(void)6783 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
6784 {
6785 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
6786 }
6787
6788 /**
6789 * @}
6790 */
6791
6792 /** @defgroup RCC_LL_EF_IT_Management IT Management
6793 * @{
6794 */
6795
6796 /**
6797 * @brief Enable LSI ready interrupt
6798 * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
6799 * @retval None
6800 */
LL_RCC_EnableIT_LSIRDY(void)6801 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
6802 {
6803 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
6804 }
6805
6806 /**
6807 * @brief Enable LSE ready interrupt
6808 * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
6809 * @retval None
6810 */
LL_RCC_EnableIT_LSERDY(void)6811 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
6812 {
6813 SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
6814 }
6815
6816 /**
6817 * @brief Enable HSI ready interrupt
6818 * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
6819 * @retval None
6820 */
LL_RCC_EnableIT_HSIRDY(void)6821 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
6822 {
6823 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
6824 }
6825
6826 /**
6827 * @brief Enable HSE ready interrupt
6828 * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
6829 * @retval None
6830 */
LL_RCC_EnableIT_HSERDY(void)6831 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
6832 {
6833 SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
6834 }
6835
6836 /**
6837 * @brief Enable PLL ready interrupt
6838 * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
6839 * @retval None
6840 */
LL_RCC_EnableIT_PLLRDY(void)6841 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
6842 {
6843 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
6844 }
6845
6846 #if defined(RCC_PLLI2S_SUPPORT)
6847 /**
6848 * @brief Enable PLLI2S ready interrupt
6849 * @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY
6850 * @retval None
6851 */
LL_RCC_EnableIT_PLLI2SRDY(void)6852 __STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
6853 {
6854 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
6855 }
6856 #endif /* RCC_PLLI2S_SUPPORT */
6857
6858 #if defined(RCC_PLLSAI_SUPPORT)
6859 /**
6860 * @brief Enable PLLSAI ready interrupt
6861 * @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY
6862 * @retval None
6863 */
LL_RCC_EnableIT_PLLSAIRDY(void)6864 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void)
6865 {
6866 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
6867 }
6868 #endif /* RCC_PLLSAI_SUPPORT */
6869
6870 /**
6871 * @brief Disable LSI ready interrupt
6872 * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
6873 * @retval None
6874 */
LL_RCC_DisableIT_LSIRDY(void)6875 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
6876 {
6877 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
6878 }
6879
6880 /**
6881 * @brief Disable LSE ready interrupt
6882 * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
6883 * @retval None
6884 */
LL_RCC_DisableIT_LSERDY(void)6885 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
6886 {
6887 CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
6888 }
6889
6890 /**
6891 * @brief Disable HSI ready interrupt
6892 * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
6893 * @retval None
6894 */
LL_RCC_DisableIT_HSIRDY(void)6895 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
6896 {
6897 CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
6898 }
6899
6900 /**
6901 * @brief Disable HSE ready interrupt
6902 * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
6903 * @retval None
6904 */
LL_RCC_DisableIT_HSERDY(void)6905 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
6906 {
6907 CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
6908 }
6909
6910 /**
6911 * @brief Disable PLL ready interrupt
6912 * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
6913 * @retval None
6914 */
LL_RCC_DisableIT_PLLRDY(void)6915 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
6916 {
6917 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
6918 }
6919
6920 #if defined(RCC_PLLI2S_SUPPORT)
6921 /**
6922 * @brief Disable PLLI2S ready interrupt
6923 * @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY
6924 * @retval None
6925 */
LL_RCC_DisableIT_PLLI2SRDY(void)6926 __STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
6927 {
6928 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
6929 }
6930
6931 #endif /* RCC_PLLI2S_SUPPORT */
6932
6933 #if defined(RCC_PLLSAI_SUPPORT)
6934 /**
6935 * @brief Disable PLLSAI ready interrupt
6936 * @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY
6937 * @retval None
6938 */
LL_RCC_DisableIT_PLLSAIRDY(void)6939 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void)
6940 {
6941 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
6942 }
6943 #endif /* RCC_PLLSAI_SUPPORT */
6944
6945 /**
6946 * @brief Checks if LSI ready interrupt source is enabled or disabled.
6947 * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
6948 * @retval State of bit (1 or 0).
6949 */
LL_RCC_IsEnabledIT_LSIRDY(void)6950 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
6951 {
6952 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
6953 }
6954
6955 /**
6956 * @brief Checks if LSE ready interrupt source is enabled or disabled.
6957 * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
6958 * @retval State of bit (1 or 0).
6959 */
LL_RCC_IsEnabledIT_LSERDY(void)6960 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
6961 {
6962 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
6963 }
6964
6965 /**
6966 * @brief Checks if HSI ready interrupt source is enabled or disabled.
6967 * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
6968 * @retval State of bit (1 or 0).
6969 */
LL_RCC_IsEnabledIT_HSIRDY(void)6970 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
6971 {
6972 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
6973 }
6974
6975 /**
6976 * @brief Checks if HSE ready interrupt source is enabled or disabled.
6977 * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
6978 * @retval State of bit (1 or 0).
6979 */
LL_RCC_IsEnabledIT_HSERDY(void)6980 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
6981 {
6982 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
6983 }
6984
6985 /**
6986 * @brief Checks if PLL ready interrupt source is enabled or disabled.
6987 * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
6988 * @retval State of bit (1 or 0).
6989 */
LL_RCC_IsEnabledIT_PLLRDY(void)6990 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
6991 {
6992 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
6993 }
6994
6995 #if defined(RCC_PLLI2S_SUPPORT)
6996 /**
6997 * @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
6998 * @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
6999 * @retval State of bit (1 or 0).
7000 */
LL_RCC_IsEnabledIT_PLLI2SRDY(void)7001 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
7002 {
7003 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
7004 }
7005
7006 #endif /* RCC_PLLI2S_SUPPORT */
7007
7008 #if defined(RCC_PLLSAI_SUPPORT)
7009 /**
7010 * @brief Checks if PLLSAI ready interrupt source is enabled or disabled.
7011 * @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY
7012 * @retval State of bit (1 or 0).
7013 */
LL_RCC_IsEnabledIT_PLLSAIRDY(void)7014 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void)
7015 {
7016 return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE));
7017 }
7018 #endif /* RCC_PLLSAI_SUPPORT */
7019
7020 /**
7021 * @}
7022 */
7023
7024 #if defined(USE_FULL_LL_DRIVER)
7025 /** @defgroup RCC_LL_EF_Init De-initialization function
7026 * @{
7027 */
7028 ErrorStatus LL_RCC_DeInit(void);
7029 /**
7030 * @}
7031 */
7032
7033 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
7034 * @{
7035 */
7036 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
7037 #if defined(FMPI2C1)
7038 uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource);
7039 #endif /* FMPI2C1 */
7040 #if defined(LPTIM1)
7041 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
7042 #endif /* LPTIM1 */
7043 #if defined(SAI1)
7044 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
7045 #endif /* SAI1 */
7046 #if defined(SDIO)
7047 uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource);
7048 #endif /* SDIO */
7049 #if defined(RNG)
7050 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
7051 #endif /* RNG */
7052 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
7053 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
7054 #endif /* USB_OTG_FS || USB_OTG_HS */
7055 #if defined(DFSDM1_Channel0)
7056 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
7057 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
7058 #endif /* DFSDM1_Channel0 */
7059 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
7060 #if defined(CEC)
7061 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
7062 #endif /* CEC */
7063 #if defined(LTDC)
7064 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
7065 #endif /* LTDC */
7066 #if defined(SPDIFRX)
7067 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
7068 #endif /* SPDIFRX */
7069 #if defined(DSI)
7070 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
7071 #endif /* DSI */
7072 /**
7073 * @}
7074 */
7075 #endif /* USE_FULL_LL_DRIVER */
7076
7077 /**
7078 * @}
7079 */
7080
7081 /**
7082 * @}
7083 */
7084
7085 #endif /* defined(RCC) */
7086
7087 /**
7088 * @}
7089 */
7090
7091 #ifdef __cplusplus
7092 }
7093 #endif
7094
7095 #endif /* __STM32F4xx_LL_RCC_H */
7096
7097
