1 /**
2 ******************************************************************************
3 * @file stm32l0xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17
18 /* Define to prevent recursive inclusion -------------------------------------*/
19 #ifndef __STM32L0xx_LL_RCC_H
20 #define __STM32L0xx_LL_RCC_H
21
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25
26 /* Includes ------------------------------------------------------------------*/
27 #include "stm32l0xx.h"
28
29 /** @addtogroup STM32L0xx_LL_Driver
30 * @{
31 */
32
33 #if defined(RCC)
34
35 /** @defgroup RCC_LL RCC
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
42 * @{
43 */
44
45 /**
46 * @}
47 */
48
49 /* Private constants ---------------------------------------------------------*/
50 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
51 * @{
52 */
53
54 /**
55 * @}
56 */
57
58 /* Private macros ------------------------------------------------------------*/
59 #if defined(USE_FULL_LL_DRIVER)
60 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
61 * @{
62 */
63 /**
64 * @}
65 */
66 #endif /*USE_FULL_LL_DRIVER*/
67 /* Exported types ------------------------------------------------------------*/
68 #if defined(USE_FULL_LL_DRIVER)
69 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
70 * @{
71 */
72
73 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
74 * @{
75 */
76
77 /**
78 * @brief RCC Clocks Frequency Structure
79 */
80 typedef struct
81 {
82 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
83 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
84 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
85 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
86 } LL_RCC_ClocksTypeDef;
87
88 /**
89 * @}
90 */
91
92 /**
93 * @}
94 */
95 #endif /* USE_FULL_LL_DRIVER */
96
97 /* Exported constants --------------------------------------------------------*/
98 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
99 * @{
100 */
101
102 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
103 * @brief Defines used to adapt values of different oscillators
104 * @note These values could be modified in the user environment according to
105 * HW set-up.
106 * @{
107 */
108 #if !defined (HSE_VALUE)
109 #define HSE_VALUE (8000000U) /*!< Value of the HSE oscillator in Hz */
110 #endif /* HSE_VALUE */
111
112 #if !defined (HSI_VALUE)
113 #define HSI_VALUE (16000000U) /*!< Value of the HSI oscillator in Hz */
114 #endif /* HSI_VALUE */
115
116 #if !defined (LSE_VALUE)
117 #define LSE_VALUE (32768U) /*!< Value of the LSE oscillator in Hz */
118 #endif /* LSE_VALUE */
119
120 #if !defined (LSI_VALUE)
121 #define LSI_VALUE (37000U) /*!< Value of the LSI oscillator in Hz */
122 #endif /* LSI_VALUE */
123 #if defined(RCC_HSI48_SUPPORT)
124
125 #if !defined (HSI48_VALUE)
126 #define HSI48_VALUE (48000000U) /*!< Value of the HSI48 oscillator in Hz */
127 #endif /* HSI48_VALUE */
128 #endif /* RCC_HSI48_SUPPORT */
129 /**
130 * @}
131 */
132
133 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
134 * @brief Flags defines which can be used with LL_RCC_WriteReg function
135 * @{
136 */
137 #define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */
138 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
139 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
140 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
141 #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */
142 #define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */
143 #if defined(RCC_HSI48_SUPPORT)
144 #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */
145 #endif /* RCC_HSI48_SUPPORT */
146 #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */
147 #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */
148 /**
149 * @}
150 */
151
152 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
153 * @brief Flags defines which can be used with LL_RCC_ReadReg function
154 * @{
155 */
156 #define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
157 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
158 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
159 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
160 #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
161 #define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */
162 #if defined(RCC_HSI48_SUPPORT)
163 #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
164 #endif /* RCC_HSI48_SUPPORT */
165 #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
166 #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
167 #define LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF /*!< Firewall reset flag */
168 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
169 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
170 #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
171 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
172 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
173 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
174 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
175 /**
176 * @}
177 */
178
179 /** @defgroup RCC_LL_EC_IT IT Defines
180 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
181 * @{
182 */
183 #define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */
184 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
185 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
186 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
187 #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */
188 #define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable */
189 #if defined(RCC_HSI48_SUPPORT)
190 #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */
191 #endif /* RCC_HSI48_SUPPORT */
192 #define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */
193 /**
194 * @}
195 */
196
197 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
198 * @{
199 */
200 #define LL_RCC_LSEDRIVE_LOW (0x00000000U) /*!< Xtal mode lower driving capability */
201 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
202 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
203 #define LL_RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV /*!< Xtal mode higher driving capability */
204 /**
205 * @}
206 */
207
208 /** @defgroup RCC_LL_EC_RTC_HSE_DIV RTC HSE Prescaler
209 * @{
210 */
211 #define LL_RCC_RTC_HSE_DIV_2 0x00000000U /*!< HSE is divided by 2 for RTC clock */
212 #define LL_RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /*!< HSE is divided by 4 for RTC clock */
213 #define LL_RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /*!< HSE is divided by 8 for RTC clock */
214 #define LL_RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /*!< HSE is divided by 16 for RTC clock */
215 /**
216 * @}
217 */
218
219 /** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges
220 * @{
221 */
222 #define LL_RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */
223 #define LL_RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz*/
224 #define LL_RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */
225 #define LL_RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */
226 #define LL_RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */
227 #define LL_RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */
228 #define LL_RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */
229 /**
230 * @}
231 */
232
233 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
234 * @{
235 */
236 #define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */
237 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
238 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
239 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
240 /**
241 * @}
242 */
243
244 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
245 * @{
246 */
247 #define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */
248 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
249 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
250 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
251 /**
252 * @}
253 */
254
255 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
256 * @{
257 */
258 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
259 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
260 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
261 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
262 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
263 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
264 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
265 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
266 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
267 /**
268 * @}
269 */
270
271 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
272 * @{
273 */
274 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
275 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
276 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
277 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
278 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
279 /**
280 * @}
281 */
282
283 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
284 * @{
285 */
286 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
287 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
288 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
289 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
290 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
291 /**
292 * @}
293 */
294
295 /** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection
296 * @{
297 */
298 #define LL_RCC_STOP_WAKEUPCLOCK_MSI (0x00000000U) /*!< MSI selection after wake-up from STOP */
299 #define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */
300 /**
301 * @}
302 */
303
304 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
305 * @{
306 */
307 #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */
308 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */
309 #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */
310 #define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_MSI /*!< MSI selection as MCO source */
311 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */
312 #define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO source */
313 #define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO source */
314 #if defined(RCC_CFGR_MCOSEL_HSI48)
315 #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_HSI48 /*!< HSI48 selection as MCO source */
316 #endif /* RCC_CFGR_MCOSEL_HSI48 */
317 #define LL_RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCOSEL_PLL /*!< PLLCLK selection as MCO source */
318 /**
319 * @}
320 */
321
322 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
323 * @{
324 */
325 #define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO Clock divided by 1 */
326 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */
327 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */
328 #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */
329 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */
330 /**
331 * @}
332 */
333 #if defined(USE_FULL_LL_DRIVER)
334 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
335 * @{
336 */
337 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
338 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
339 /**
340 * @}
341 */
342 #endif /* USE_FULL_LL_DRIVER */
343
344 /** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection
345 * @{
346 */
347 #if defined(RCC_CCIPR_USART1SEL)
348 #define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | 0x00000000U) /*!< PCLK2 selected as USART1 clock */
349 #define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK selected as USART1 clock */
350 #define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI selected as USART1 clock */
351 #define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE selected as USART1 clock*/
352 #endif /* RCC_CCIPR_USART1SEL */
353 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | 0x00000000U) /*!< PCLK1 selected as USART2 clock */
354 #define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK selected as USART2 clock */
355 #define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI selected as USART2 clock */
356 #define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) /*!< LSE selected as USART2 clock*/
357 /**
358 * @}
359 */
360
361
362
363 /** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection
364 * @{
365 */
366 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 selected as LPUART1 clock */
367 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYSCLK selected as LPUART1 clock */
368 #define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI selected as LPUART1 clock */
369 #define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE selected as LPUART1 clock*/
370 /**
371 * @}
372 */
373
374 /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
375 * @{
376 */
377 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) | (0x00000000U >> 4U)) /*!< PCLK1 selected as I2C1 clock */
378 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) | (RCC_CCIPR_I2C1SEL_0 >> 4U)) /*!< SYSCLK selected as I2C1 clock */
379 #define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) | (RCC_CCIPR_I2C1SEL_1 >> 4U)) /*!< HSI selected as I2C1 clock */
380 #if defined(RCC_CCIPR_I2C3SEL)
381 #define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) | (0x00000000U >> 4U)) /*!< PCLK1 selected as I2C3 clock */
382 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) | (RCC_CCIPR_I2C3SEL_0 >> 4U)) /*!< SYSCLK selected as I2C3 clock */
383 #define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) | (RCC_CCIPR_I2C3SEL_1 >> 4U)) /*!< HSI selected as I2C3 clock */
384 #endif /*RCC_CCIPR_I2C3SEL*/
385 /**
386 * @}
387 */
388
389 /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
390 * @{
391 */
392 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (0x00000000U) /*!< PCLK1 selected as LPTIM1 clock */
393 #define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 /*!< LSI selected as LPTIM1 clock */
394 #define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 /*!< HSI selected as LPTIM1 clock */
395 #define LL_RCC_LPTIM1_CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL /*!< LSE selected as LPTIM1 clock*/
396 /**
397 * @}
398 */
399
400 #if defined(RCC_CCIPR_HSI48SEL)
401
402 #if defined(RNG)
403 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
404 * @{
405 */
406 #define LL_RCC_RNG_CLKSOURCE_PLL (0x00000000U) /*!< PLL selected as RNG clock */
407 #define LL_RCC_RNG_CLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL /*!< HSI48 selected as RNG clock*/
408 /**
409 * @}
410 */
411 #endif /* RNG */
412 #if defined(USB)
413 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
414 * @{
415 */
416 #define LL_RCC_USB_CLKSOURCE_PLL (0x00000000U) /*!< PLL selected as USB clock */
417 #define LL_RCC_USB_CLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL /*!< HSI48 selected as USB clock*/
418 /**
419 * @}
420 */
421
422 #endif /* USB */
423 #endif /* RCC_CCIPR_HSI48SEL */
424
425
426 /** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source
427 * @{
428 */
429 #if defined(RCC_CCIPR_USART1SEL)
430 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 clock source selection bits */
431 #endif /* RCC_CCIPR_USART1SEL */
432 #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 clock source selection bits */
433 /**
434 * @}
435 */
436
437
438 /** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
439 * @{
440 */
441 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 clock source selection bits */
442 /**
443 * @}
444 */
445
446 /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
447 * @{
448 */
449 #define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL /*!< I2C1 clock source selection bits */
450 #if defined(RCC_CCIPR_I2C3SEL)
451 #define LL_RCC_I2C3_CLKSOURCE RCC_CCIPR_I2C3SEL /*!< I2C3 clock source selection bits */
452 #endif /*RCC_CCIPR_I2C3SEL*/
453 /**
454 * @}
455 */
456
457 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
458 * @{
459 */
460 #define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 clock source selection bits */
461 /**
462 * @}
463 */
464
465 #if defined(RCC_CCIPR_HSI48SEL)
466 #if defined(RNG)
467 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
468 * @{
469 */
470 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_HSI48SEL /*!< HSI48 RC clock source selection bit for RNG*/
471 /**
472 * @}
473 */
474 #endif /* RNG */
475
476 #if defined(USB)
477 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
478 * @{
479 */
480 #define LL_RCC_USB_CLKSOURCE RCC_CCIPR_HSI48SEL /*!< HSI48 RC clock source selection bit for USB*/
481 /**
482 * @}
483 */
484
485 #endif /* USB */
486 #endif /* RCC_CCIPR_HSI48SEL */
487
488 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
489 * @{
490 */
491 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
492 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
493 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
494 #define LL_RCC_RTC_CLKSOURCE_HSE RCC_CSR_RTCSEL_HSE /*!< HSE oscillator clock divided by a programmable prescaler
495 (selection through @ref LL_RCC_SetRTC_HSEPrescaler function ) */
496 /**
497 * @}
498 */
499
500 /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
501 * @{
502 */
503 #define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock * 3 */
504 #define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock * 4 */
505 #define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock * 6 */
506 #define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock * 8 */
507 #define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock * 12 */
508 #define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock * 16 */
509 #define LL_RCC_PLL_MUL_24 RCC_CFGR_PLLMUL24 /*!< PLL input clock * 24 */
510 #define LL_RCC_PLL_MUL_32 RCC_CFGR_PLLMUL32 /*!< PLL input clock * 32 */
511 #define LL_RCC_PLL_MUL_48 RCC_CFGR_PLLMUL48 /*!< PLL input clock * 48 */
512 /**
513 * @}
514 */
515
516 /** @defgroup RCC_LL_EC_PLL_DIV PLL division factor
517 * @{
518 */
519 #define LL_RCC_PLL_DIV_2 RCC_CFGR_PLLDIV2 /*!< PLL clock output = PLLVCO / 2 */
520 #define LL_RCC_PLL_DIV_3 RCC_CFGR_PLLDIV3 /*!< PLL clock output = PLLVCO / 3 */
521 #define LL_RCC_PLL_DIV_4 RCC_CFGR_PLLDIV4 /*!< PLL clock output = PLLVCO / 4 */
522 /**
523 * @}
524 */
525
526 /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
527 * @{
528 */
529 #define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */
530 #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
531 /**
532 * @}
533 */
534
535 /**
536 * @}
537 */
538
539 /* Exported macro ------------------------------------------------------------*/
540 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
541 * @{
542 */
543
544 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
545 * @{
546 */
547
548 /**
549 * @brief Write a value in RCC register
550 * @param __REG__ Register to be written
551 * @param __VALUE__ Value to be written in the register
552 * @retval None
553 */
554 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
555
556 /**
557 * @brief Read a value in RCC register
558 * @param __REG__ Register to be read
559 * @retval Register value
560 */
561 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
562 /**
563 * @}
564 */
565
566 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
567 * @{
568 */
569
570 /**
571 * @brief Helper macro to calculate the PLLCLK frequency
572 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,
573 * @ref LL_RCC_PLL_GetMultiplicator (),
574 * @ref LL_RCC_PLL_GetDivider ());
575 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
576 * @param __PLLMUL__ This parameter can be one of the following values:
577 * @arg @ref LL_RCC_PLL_MUL_3
578 * @arg @ref LL_RCC_PLL_MUL_4
579 * @arg @ref LL_RCC_PLL_MUL_6
580 * @arg @ref LL_RCC_PLL_MUL_8
581 * @arg @ref LL_RCC_PLL_MUL_12
582 * @arg @ref LL_RCC_PLL_MUL_16
583 * @arg @ref LL_RCC_PLL_MUL_24
584 * @arg @ref LL_RCC_PLL_MUL_32
585 * @arg @ref LL_RCC_PLL_MUL_48
586 * @param __PLLDIV__ This parameter can be one of the following values:
587 * @arg @ref LL_RCC_PLL_DIV_2
588 * @arg @ref LL_RCC_PLL_DIV_3
589 * @arg @ref LL_RCC_PLL_DIV_4
590 * @retval PLL clock frequency (in Hz)
591 */
592 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLDIV__) ((__INPUTFREQ__) * (PLLMulTable[(__PLLMUL__) >> RCC_CFGR_PLLMUL_Pos]) / (((__PLLDIV__) >> RCC_CFGR_PLLDIV_Pos)+1UL))
593
594 /**
595 * @brief Helper macro to calculate the HCLK frequency
596 * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
597 * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
598 * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
599 * @param __AHBPRESCALER__ This parameter can be one of the following values:
600 * @arg @ref LL_RCC_SYSCLK_DIV_1
601 * @arg @ref LL_RCC_SYSCLK_DIV_2
602 * @arg @ref LL_RCC_SYSCLK_DIV_4
603 * @arg @ref LL_RCC_SYSCLK_DIV_8
604 * @arg @ref LL_RCC_SYSCLK_DIV_16
605 * @arg @ref LL_RCC_SYSCLK_DIV_64
606 * @arg @ref LL_RCC_SYSCLK_DIV_128
607 * @arg @ref LL_RCC_SYSCLK_DIV_256
608 * @arg @ref LL_RCC_SYSCLK_DIV_512
609 * @retval HCLK clock frequency (in Hz)
610 */
611 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
612
613 /**
614 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
615 * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
616 * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
617 * @param __HCLKFREQ__ HCLK frequency
618 * @param __APB1PRESCALER__ This parameter can be one of the following values:
619 * @arg @ref LL_RCC_APB1_DIV_1
620 * @arg @ref LL_RCC_APB1_DIV_2
621 * @arg @ref LL_RCC_APB1_DIV_4
622 * @arg @ref LL_RCC_APB1_DIV_8
623 * @arg @ref LL_RCC_APB1_DIV_16
624 * @retval PCLK1 clock frequency (in Hz)
625 */
626 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
627
628 /**
629 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
630 * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
631 * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
632 * @param __HCLKFREQ__ HCLK frequency
633 * @param __APB2PRESCALER__ This parameter can be one of the following values:
634 * @arg @ref LL_RCC_APB2_DIV_1
635 * @arg @ref LL_RCC_APB2_DIV_2
636 * @arg @ref LL_RCC_APB2_DIV_4
637 * @arg @ref LL_RCC_APB2_DIV_8
638 * @arg @ref LL_RCC_APB2_DIV_16
639 * @retval PCLK2 clock frequency (in Hz)
640 */
641 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
642
643 /**
644 * @brief Helper macro to calculate the MSI frequency (in Hz)
645 * @note: __MSIRANGE__can be retrieved by @ref LL_RCC_MSI_GetRange
646 * ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange())
647 * @param __MSIRANGE__ This parameter can be one of the following values:
648 * @arg @ref LL_RCC_MSIRANGE_0
649 * @arg @ref LL_RCC_MSIRANGE_1
650 * @arg @ref LL_RCC_MSIRANGE_2
651 * @arg @ref LL_RCC_MSIRANGE_3
652 * @arg @ref LL_RCC_MSIRANGE_4
653 * @arg @ref LL_RCC_MSIRANGE_5
654 * @arg @ref LL_RCC_MSIRANGE_6
655 * @retval MSI clock frequency (in Hz)
656 */
657 #define __LL_RCC_CALC_MSI_FREQ(__MSIRANGE__) (32768UL * ( 1UL << (((__MSIRANGE__) >> RCC_ICSCR_MSIRANGE_Pos) + 1UL) ))
658
659 /**
660 * @}
661 */
662
663 /**
664 * @}
665 */
666
667 /* Exported functions --------------------------------------------------------*/
668 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
669 * @{
670 */
671
672 /** @defgroup RCC_LL_EF_HSE HSE
673 * @{
674 */
675
676 #if defined(RCC_HSECSS_SUPPORT)
677 /**
678 * @brief Enable the Clock Security System.
679 * @rmtoll CR CSSHSEON LL_RCC_HSE_EnableCSS
680 * @retval None
681 */
LL_RCC_HSE_EnableCSS(void)682 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
683 {
684 SET_BIT(RCC->CR, RCC_CR_CSSON);
685 }
686 #endif /* RCC_HSECSS_SUPPORT */
687
688 /**
689 * @brief Enable HSE external oscillator (HSE Bypass)
690 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
691 * @retval None
692 */
LL_RCC_HSE_EnableBypass(void)693 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
694 {
695 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
696 }
697
698 /**
699 * @brief Disable HSE external oscillator (HSE Bypass)
700 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
701 * @retval None
702 */
LL_RCC_HSE_DisableBypass(void)703 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
704 {
705 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
706 }
707
708 /**
709 * @brief Enable HSE crystal oscillator (HSE ON)
710 * @rmtoll CR HSEON LL_RCC_HSE_Enable
711 * @retval None
712 */
LL_RCC_HSE_Enable(void)713 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
714 {
715 SET_BIT(RCC->CR, RCC_CR_HSEON);
716 }
717
718 /**
719 * @brief Disable HSE crystal oscillator (HSE ON)
720 * @rmtoll CR HSEON LL_RCC_HSE_Disable
721 * @retval None
722 */
LL_RCC_HSE_Disable(void)723 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
724 {
725 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
726 }
727
728 /**
729 * @brief Check if HSE oscillator Ready
730 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
731 * @retval State of bit (1 or 0).
732 */
LL_RCC_HSE_IsReady(void)733 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
734 {
735 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL);
736 }
737
738 /**
739 * @brief Configure the RTC prescaler (divider)
740 * @rmtoll CR RTCPRE LL_RCC_SetRTC_HSEPrescaler
741 * @param Div This parameter can be one of the following values:
742 * @arg @ref LL_RCC_RTC_HSE_DIV_2
743 * @arg @ref LL_RCC_RTC_HSE_DIV_4
744 * @arg @ref LL_RCC_RTC_HSE_DIV_8
745 * @arg @ref LL_RCC_RTC_HSE_DIV_16
746 * @retval None
747 */
LL_RCC_SetRTC_HSEPrescaler(uint32_t Div)748 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Div)
749 {
750 MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, Div);
751 }
752
753 /**
754 * @brief Get the RTC divider (prescaler)
755 * @rmtoll CR RTCPRE LL_RCC_GetRTC_HSEPrescaler
756 * @retval Returned value can be one of the following values:
757 * @arg @ref LL_RCC_RTC_HSE_DIV_2
758 * @arg @ref LL_RCC_RTC_HSE_DIV_4
759 * @arg @ref LL_RCC_RTC_HSE_DIV_8
760 * @arg @ref LL_RCC_RTC_HSE_DIV_16
761 */
LL_RCC_GetRTC_HSEPrescaler(void)762 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
763 {
764 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE));
765 }
766
767 /**
768 * @}
769 */
770
771 /** @defgroup RCC_LL_EF_HSI HSI
772 * @{
773 */
774
775 /**
776 * @brief Enable HSI oscillator
777 * @rmtoll CR HSION LL_RCC_HSI_Enable
778 * @retval None
779 */
LL_RCC_HSI_Enable(void)780 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
781 {
782 SET_BIT(RCC->CR, RCC_CR_HSION);
783 }
784
785 /**
786 * @brief Disable HSI oscillator
787 * @rmtoll CR HSION LL_RCC_HSI_Disable
788 * @retval None
789 */
LL_RCC_HSI_Disable(void)790 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
791 {
792 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
793 }
794
795 /**
796 * @brief Check if HSI clock is ready
797 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
798 * @retval State of bit (1 or 0).
799 */
LL_RCC_HSI_IsReady(void)800 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
801 {
802 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL);
803 }
804
805 /**
806 * @brief Enable HSI even in stop mode
807 * @note HSI oscillator is forced ON even in Stop mode
808 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
809 * @retval None
810 */
LL_RCC_HSI_EnableInStopMode(void)811 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
812 {
813 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
814 }
815
816 /**
817 * @brief Disable HSI in stop mode
818 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
819 * @retval None
820 */
LL_RCC_HSI_DisableInStopMode(void)821 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
822 {
823 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
824 }
825
826 /**
827 * @brief Enable HSI Divider (it divides by 4)
828 * @rmtoll CR HSIDIVEN LL_RCC_HSI_EnableDivider
829 * @retval None
830 */
LL_RCC_HSI_EnableDivider(void)831 __STATIC_INLINE void LL_RCC_HSI_EnableDivider(void)
832 {
833 SET_BIT(RCC->CR, RCC_CR_HSIDIVEN);
834 }
835
836 /**
837 * @brief Disable HSI Divider (it divides by 4)
838 * @rmtoll CR HSIDIVEN LL_RCC_HSI_DisableDivider
839 * @retval None
840 */
LL_RCC_HSI_DisableDivider(void)841 __STATIC_INLINE void LL_RCC_HSI_DisableDivider(void)
842 {
843 CLEAR_BIT(RCC->CR, RCC_CR_HSIDIVEN);
844 }
845
846
847
848 #if defined(RCC_CR_HSIOUTEN)
849 /**
850 * @brief Enable HSI Output
851 * @rmtoll CR HSIOUTEN LL_RCC_HSI_EnableOutput
852 * @retval None
853 */
LL_RCC_HSI_EnableOutput(void)854 __STATIC_INLINE void LL_RCC_HSI_EnableOutput(void)
855 {
856 SET_BIT(RCC->CR, RCC_CR_HSIOUTEN);
857 }
858
859 /**
860 * @brief Disable HSI Output
861 * @rmtoll CR HSIOUTEN LL_RCC_HSI_DisableOutput
862 * @retval None
863 */
LL_RCC_HSI_DisableOutput(void)864 __STATIC_INLINE void LL_RCC_HSI_DisableOutput(void)
865 {
866 CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN);
867 }
868 #endif /* RCC_CR_HSIOUTEN */
869
870 /**
871 * @brief Get HSI Calibration value
872 * @note When HSITRIM is written, HSICAL is updated with the sum of
873 * HSITRIM and the factory trim value
874 * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
875 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
876 */
LL_RCC_HSI_GetCalibration(void)877 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
878 {
879 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
880 }
881
882 /**
883 * @brief Set HSI Calibration trimming
884 * @note user-programmable trimming value that is added to the HSICAL
885 * @note Default value is 16, which, when added to the HSICAL value,
886 * should trim the HSI to 16 MHz +/- 1 %
887 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
888 * @param Value between Min_Data = 0x00 and Max_Data = 0x1F
889 * @retval None
890 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)891 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
892 {
893 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
894 }
895
896 /**
897 * @brief Get HSI Calibration trimming
898 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
899 * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
900 */
LL_RCC_HSI_GetCalibTrimming(void)901 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
902 {
903 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
904 }
905
906 /**
907 * @}
908 */
909
910 #if defined(RCC_HSI48_SUPPORT)
911 /** @defgroup RCC_LL_EF_HSI48 HSI48
912 * @{
913 */
914
915 /**
916 * @brief Enable HSI48
917 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable
918 * @retval None
919 */
LL_RCC_HSI48_Enable(void)920 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
921 {
922 SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
923 }
924
925 /**
926 * @brief Disable HSI48
927 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable
928 * @retval None
929 */
LL_RCC_HSI48_Disable(void)930 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
931 {
932 CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
933 }
934
935 /**
936 * @brief Check if HSI48 oscillator Ready
937 * @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady
938 * @retval State of bit (1 or 0).
939 */
LL_RCC_HSI48_IsReady(void)940 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
941 {
942 return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == RCC_CRRCR_HSI48RDY) ? 1UL : 0UL);
943 }
944
945 /**
946 * @brief Get HSI48 Calibration value
947 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
948 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
949 */
LL_RCC_HSI48_GetCalibration(void)950 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
951 {
952 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
953 }
954
955 #if defined(RCC_CRRCR_HSI48DIV6OUTEN)
956 /**
957 * @brief Enable HSI48 Divider (it divides by 6)
958 * @rmtoll CRRCR HSI48DIV6OUTEN LL_RCC_HSI48_EnableDivider
959 * @retval None
960 */
LL_RCC_HSI48_EnableDivider(void)961 __STATIC_INLINE void LL_RCC_HSI48_EnableDivider(void)
962 {
963 SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN);
964 }
965
966 /**
967 * @brief Disable HSI48 Divider (it divides by 6)
968 * @rmtoll CRRCR HSI48DIV6OUTEN LL_RCC_HSI48_DisableDivider
969 * @retval None
970 */
LL_RCC_HSI48_DisableDivider(void)971 __STATIC_INLINE void LL_RCC_HSI48_DisableDivider(void)
972 {
973 CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN);
974 }
975
976 /**
977 * @brief Check if HSI48 Divider is enabled (it divides by 6)
978 * @rmtoll CRRCR HSI48DIV6OUTEN LL_RCC_HSI48_IsDivided
979 * @retval State of bit (1 or 0).
980 */
LL_RCC_HSI48_IsDivided(void)981 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsDivided(void)
982 {
983 return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN) == RCC_CRRCR_HSI48DIV6OUTEN) ? 1UL : 0UL);
984 }
985
986 #endif /*RCC_CRRCR_HSI48DIV6OUTEN*/
987
988 /**
989 * @}
990 */
991
992 #endif /* RCC_HSI48_SUPPORT */
993
994 /** @defgroup RCC_LL_EF_LSE LSE
995 * @{
996 */
997
998 /**
999 * @brief Enable Low Speed External (LSE) crystal.
1000 * @rmtoll CSR LSEON LL_RCC_LSE_Enable
1001 * @retval None
1002 */
LL_RCC_LSE_Enable(void)1003 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
1004 {
1005 SET_BIT(RCC->CSR, RCC_CSR_LSEON);
1006 }
1007
1008 /**
1009 * @brief Disable Low Speed External (LSE) crystal.
1010 * @rmtoll CSR LSEON LL_RCC_LSE_Disable
1011 * @retval None
1012 */
LL_RCC_LSE_Disable(void)1013 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
1014 {
1015 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);
1016 }
1017
1018 /**
1019 * @brief Enable external clock source (LSE bypass).
1020 * @rmtoll CSR LSEBYP LL_RCC_LSE_EnableBypass
1021 * @retval None
1022 */
LL_RCC_LSE_EnableBypass(void)1023 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
1024 {
1025 SET_BIT(RCC->CSR, RCC_CSR_LSEBYP);
1026 }
1027
1028 /**
1029 * @brief Disable external clock source (LSE bypass).
1030 * @rmtoll CSR LSEBYP LL_RCC_LSE_DisableBypass
1031 * @retval None
1032 */
LL_RCC_LSE_DisableBypass(void)1033 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
1034 {
1035 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP);
1036 }
1037
1038 /**
1039 * @brief Set LSE oscillator drive capability
1040 * @note The oscillator is in Xtal mode when it is not in bypass mode.
1041 * @rmtoll CSR LSEDRV LL_RCC_LSE_SetDriveCapability
1042 * @param LSEDrive This parameter can be one of the following values:
1043 * @arg @ref LL_RCC_LSEDRIVE_LOW
1044 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1045 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1046 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1047 * @retval None
1048 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)1049 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
1050 {
1051 MODIFY_REG(RCC->CSR, RCC_CSR_LSEDRV, LSEDrive);
1052 }
1053
1054 /**
1055 * @brief Get LSE oscillator drive capability
1056 * @rmtoll CSR LSEDRV LL_RCC_LSE_GetDriveCapability
1057 * @retval Returned value can be one of the following values:
1058 * @arg @ref LL_RCC_LSEDRIVE_LOW
1059 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1060 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1061 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1062 */
LL_RCC_LSE_GetDriveCapability(void)1063 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
1064 {
1065 return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_LSEDRV));
1066 }
1067
1068 /**
1069 * @brief Enable Clock security system on LSE.
1070 * @rmtoll CSR LSECSSON LL_RCC_LSE_EnableCSS
1071 * @retval None
1072 */
LL_RCC_LSE_EnableCSS(void)1073 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
1074 {
1075 SET_BIT(RCC->CSR, RCC_CSR_LSECSSON);
1076 }
1077
1078 /**
1079 * @brief Disable Clock security system on LSE.
1080 * @note Clock security system can be disabled only after a LSE
1081 * failure detection. In that case it MUST be disabled by software.
1082 * @rmtoll CSR LSECSSON LL_RCC_LSE_DisableCSS
1083 * @retval None
1084 */
LL_RCC_LSE_DisableCSS(void)1085 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
1086 {
1087 CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON);
1088 }
1089
1090 /**
1091 * @brief Check if LSE oscillator Ready
1092 * @rmtoll CSR LSERDY LL_RCC_LSE_IsReady
1093 * @retval State of bit (1 or 0).
1094 */
LL_RCC_LSE_IsReady(void)1095 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
1096 {
1097 return ((READ_BIT(RCC->CSR, RCC_CSR_LSERDY) == RCC_CSR_LSERDY) ? 1UL : 0UL);
1098 }
1099
1100 /**
1101 * @brief Check if CSS on LSE failure Detection
1102 * @rmtoll CSR LSECSSD LL_RCC_LSE_IsCSSDetected
1103 * @retval State of bit (1 or 0).
1104 */
LL_RCC_LSE_IsCSSDetected(void)1105 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
1106 {
1107 return ((READ_BIT(RCC->CSR, RCC_CSR_LSECSSD) == RCC_CSR_LSECSSD) ? 1UL : 0UL);
1108 }
1109
1110 /**
1111 * @}
1112 */
1113
1114 /** @defgroup RCC_LL_EF_LSI LSI
1115 * @{
1116 */
1117
1118 /**
1119 * @brief Enable LSI Oscillator
1120 * @rmtoll CSR LSION LL_RCC_LSI_Enable
1121 * @retval None
1122 */
LL_RCC_LSI_Enable(void)1123 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
1124 {
1125 SET_BIT(RCC->CSR, RCC_CSR_LSION);
1126 }
1127
1128 /**
1129 * @brief Disable LSI Oscillator
1130 * @rmtoll CSR LSION LL_RCC_LSI_Disable
1131 * @retval None
1132 */
LL_RCC_LSI_Disable(void)1133 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
1134 {
1135 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
1136 }
1137
1138 /**
1139 * @brief Check if LSI is Ready
1140 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
1141 * @retval State of bit (1 or 0).
1142 */
LL_RCC_LSI_IsReady(void)1143 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
1144 {
1145 return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) ? 1UL : 0UL);
1146 }
1147
1148 /**
1149 * @}
1150 */
1151
1152 /** @defgroup RCC_LL_EF_MSI MSI
1153 * @{
1154 */
1155
1156 /**
1157 * @brief Enable MSI oscillator
1158 * @rmtoll CR MSION LL_RCC_MSI_Enable
1159 * @retval None
1160 */
LL_RCC_MSI_Enable(void)1161 __STATIC_INLINE void LL_RCC_MSI_Enable(void)
1162 {
1163 SET_BIT(RCC->CR, RCC_CR_MSION);
1164 }
1165
1166 /**
1167 * @brief Disable MSI oscillator
1168 * @rmtoll CR MSION LL_RCC_MSI_Disable
1169 * @retval None
1170 */
LL_RCC_MSI_Disable(void)1171 __STATIC_INLINE void LL_RCC_MSI_Disable(void)
1172 {
1173 CLEAR_BIT(RCC->CR, RCC_CR_MSION);
1174 }
1175
1176 /**
1177 * @brief Check if MSI oscillator Ready
1178 * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
1179 * @retval State of bit (1 or 0).
1180 */
LL_RCC_MSI_IsReady(void)1181 __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
1182 {
1183 return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL);
1184 }
1185
1186 /**
1187 * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
1188 * @rmtoll ICSCR MSIRANGE LL_RCC_MSI_SetRange
1189 * @param Range This parameter can be one of the following values:
1190 * @arg @ref LL_RCC_MSIRANGE_0
1191 * @arg @ref LL_RCC_MSIRANGE_1
1192 * @arg @ref LL_RCC_MSIRANGE_2
1193 * @arg @ref LL_RCC_MSIRANGE_3
1194 * @arg @ref LL_RCC_MSIRANGE_4
1195 * @arg @ref LL_RCC_MSIRANGE_5
1196 * @arg @ref LL_RCC_MSIRANGE_6
1197 * @retval None
1198 */
LL_RCC_MSI_SetRange(uint32_t Range)1199 __STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
1200 {
1201 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, Range);
1202 }
1203
1204 /**
1205 * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
1206 * @rmtoll ICSCR MSIRANGE LL_RCC_MSI_GetRange
1207 * @retval Returned value can be one of the following values:
1208 * @arg @ref LL_RCC_MSIRANGE_0
1209 * @arg @ref LL_RCC_MSIRANGE_1
1210 * @arg @ref LL_RCC_MSIRANGE_2
1211 * @arg @ref LL_RCC_MSIRANGE_3
1212 * @arg @ref LL_RCC_MSIRANGE_4
1213 * @arg @ref LL_RCC_MSIRANGE_5
1214 * @arg @ref LL_RCC_MSIRANGE_6
1215 */
LL_RCC_MSI_GetRange(void)1216 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
1217 {
1218 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE));
1219 }
1220
1221 /**
1222 * @brief Get MSI Calibration value
1223 * @note When MSITRIM is written, MSICAL is updated with the sum of
1224 * MSITRIM and the factory trim value
1225 * @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration
1226 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
1227 */
LL_RCC_MSI_GetCalibration(void)1228 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
1229 {
1230 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos);
1231 }
1232
1233 /**
1234 * @brief Set MSI Calibration trimming
1235 * @note user-programmable trimming value that is added to the MSICAL
1236 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
1237 * @param Value between Min_Data = 0x00 and Max_Data = 0xFF
1238 * @retval None
1239 */
LL_RCC_MSI_SetCalibTrimming(uint32_t Value)1240 __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
1241 {
1242 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
1243 }
1244
1245 /**
1246 * @brief Get MSI Calibration trimming
1247 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming
1248 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
1249 */
LL_RCC_MSI_GetCalibTrimming(void)1250 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
1251 {
1252 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
1253 }
1254
1255 /**
1256 * @}
1257 */
1258
1259 /** @defgroup RCC_LL_EF_System System
1260 * @{
1261 */
1262
1263 /**
1264 * @brief Configure the system clock source
1265 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
1266 * @param Source This parameter can be one of the following values:
1267 * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
1268 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
1269 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
1270 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
1271 * @retval None
1272 */
LL_RCC_SetSysClkSource(uint32_t Source)1273 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
1274 {
1275 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
1276 }
1277
1278 /**
1279 * @brief Get the system clock source
1280 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
1281 * @retval Returned value can be one of the following values:
1282 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
1283 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
1284 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
1285 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
1286 */
LL_RCC_GetSysClkSource(void)1287 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
1288 {
1289 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
1290 }
1291
1292 /**
1293 * @brief Set AHB prescaler
1294 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
1295 * @param Prescaler This parameter can be one of the following values:
1296 * @arg @ref LL_RCC_SYSCLK_DIV_1
1297 * @arg @ref LL_RCC_SYSCLK_DIV_2
1298 * @arg @ref LL_RCC_SYSCLK_DIV_4
1299 * @arg @ref LL_RCC_SYSCLK_DIV_8
1300 * @arg @ref LL_RCC_SYSCLK_DIV_16
1301 * @arg @ref LL_RCC_SYSCLK_DIV_64
1302 * @arg @ref LL_RCC_SYSCLK_DIV_128
1303 * @arg @ref LL_RCC_SYSCLK_DIV_256
1304 * @arg @ref LL_RCC_SYSCLK_DIV_512
1305 * @retval None
1306 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)1307 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
1308 {
1309 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
1310 }
1311
1312 /**
1313 * @brief Set APB1 prescaler
1314 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
1315 * @param Prescaler This parameter can be one of the following values:
1316 * @arg @ref LL_RCC_APB1_DIV_1
1317 * @arg @ref LL_RCC_APB1_DIV_2
1318 * @arg @ref LL_RCC_APB1_DIV_4
1319 * @arg @ref LL_RCC_APB1_DIV_8
1320 * @arg @ref LL_RCC_APB1_DIV_16
1321 * @retval None
1322 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)1323 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
1324 {
1325 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
1326 }
1327
1328 /**
1329 * @brief Set APB2 prescaler
1330 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
1331 * @param Prescaler This parameter can be one of the following values:
1332 * @arg @ref LL_RCC_APB2_DIV_1
1333 * @arg @ref LL_RCC_APB2_DIV_2
1334 * @arg @ref LL_RCC_APB2_DIV_4
1335 * @arg @ref LL_RCC_APB2_DIV_8
1336 * @arg @ref LL_RCC_APB2_DIV_16
1337 * @retval None
1338 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)1339 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
1340 {
1341 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
1342 }
1343
1344 /**
1345 * @brief Get AHB prescaler
1346 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
1347 * @retval Returned value can be one of the following values:
1348 * @arg @ref LL_RCC_SYSCLK_DIV_1
1349 * @arg @ref LL_RCC_SYSCLK_DIV_2
1350 * @arg @ref LL_RCC_SYSCLK_DIV_4
1351 * @arg @ref LL_RCC_SYSCLK_DIV_8
1352 * @arg @ref LL_RCC_SYSCLK_DIV_16
1353 * @arg @ref LL_RCC_SYSCLK_DIV_64
1354 * @arg @ref LL_RCC_SYSCLK_DIV_128
1355 * @arg @ref LL_RCC_SYSCLK_DIV_256
1356 * @arg @ref LL_RCC_SYSCLK_DIV_512
1357 */
LL_RCC_GetAHBPrescaler(void)1358 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
1359 {
1360 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
1361 }
1362
1363 /**
1364 * @brief Get APB1 prescaler
1365 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
1366 * @retval Returned value can be one of the following values:
1367 * @arg @ref LL_RCC_APB1_DIV_1
1368 * @arg @ref LL_RCC_APB1_DIV_2
1369 * @arg @ref LL_RCC_APB1_DIV_4
1370 * @arg @ref LL_RCC_APB1_DIV_8
1371 * @arg @ref LL_RCC_APB1_DIV_16
1372 */
LL_RCC_GetAPB1Prescaler(void)1373 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
1374 {
1375 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
1376 }
1377
1378 /**
1379 * @brief Get APB2 prescaler
1380 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
1381 * @retval Returned value can be one of the following values:
1382 * @arg @ref LL_RCC_APB2_DIV_1
1383 * @arg @ref LL_RCC_APB2_DIV_2
1384 * @arg @ref LL_RCC_APB2_DIV_4
1385 * @arg @ref LL_RCC_APB2_DIV_8
1386 * @arg @ref LL_RCC_APB2_DIV_16
1387 */
LL_RCC_GetAPB2Prescaler(void)1388 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
1389 {
1390 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
1391 }
1392
1393 /**
1394 * @brief Set Clock After Wake-Up From Stop mode
1395 * @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop
1396 * @param Clock This parameter can be one of the following values:
1397 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
1398 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
1399 * @retval None
1400 */
LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)1401 __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
1402 {
1403 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
1404 }
1405
1406 /**
1407 * @brief Get Clock After Wake-Up From Stop mode
1408 * @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop
1409 * @retval Returned value can be one of the following values:
1410 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
1411 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
1412 */
LL_RCC_GetClkAfterWakeFromStop(void)1413 __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
1414 {
1415 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
1416 }
1417
1418 /**
1419 * @}
1420 */
1421
1422 /** @defgroup RCC_LL_EF_MCO MCO
1423 * @{
1424 */
1425
1426 /**
1427 * @brief Configure MCOx
1428 * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
1429 * CFGR MCOPRE LL_RCC_ConfigMCO
1430 * @param MCOxSource This parameter can be one of the following values:
1431 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
1432 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
1433 * @arg @ref LL_RCC_MCO1SOURCE_HSI
1434 * @arg @ref LL_RCC_MCO1SOURCE_MSI
1435 * @arg @ref LL_RCC_MCO1SOURCE_HSE
1436 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
1437 * @arg @ref LL_RCC_MCO1SOURCE_LSI
1438 * @arg @ref LL_RCC_MCO1SOURCE_LSE
1439 * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
1440 *
1441 * (*) value not defined in all devices.
1442 * @param MCOxPrescaler This parameter can be one of the following values:
1443 * @arg @ref LL_RCC_MCO1_DIV_1
1444 * @arg @ref LL_RCC_MCO1_DIV_2
1445 * @arg @ref LL_RCC_MCO1_DIV_4
1446 * @arg @ref LL_RCC_MCO1_DIV_8
1447 * @arg @ref LL_RCC_MCO1_DIV_16
1448 * @retval None
1449 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)1450 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
1451 {
1452 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
1453 }
1454
1455 /**
1456 * @}
1457 */
1458
1459 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
1460 * @{
1461 */
1462
1463 /**
1464 * @brief Configure USARTx clock source
1465 * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
1466 * @param USARTxSource This parameter can be one of the following values:
1467 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
1468 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK (*)
1469 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI (*)
1470 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE (*)
1471 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
1472 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
1473 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
1474 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
1475 *
1476 * (*) value not defined in all devices.
1477 * @retval None
1478 */
LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)1479 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
1480 {
1481 MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
1482 }
1483
1484 /**
1485 * @brief Configure LPUART1x clock source
1486 * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
1487 * @param LPUARTxSource This parameter can be one of the following values:
1488 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
1489 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
1490 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
1491 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
1492 * @retval None
1493 */
LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)1494 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
1495 {
1496 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
1497 }
1498
1499 /**
1500 * @brief Configure I2Cx clock source
1501 * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource
1502 * @param I2CxSource This parameter can be one of the following values:
1503 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
1504 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1505 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
1506 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 (*)
1507 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
1508 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
1509 *
1510 * (*) value not defined in all devices.
1511 * @retval None
1512 */
LL_RCC_SetI2CClockSource(uint32_t I2CxSource)1513 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
1514 {
1515 MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4U) & 0x000FF000U), ((I2CxSource << 4U) & 0x000FF000U));
1516 }
1517
1518 /**
1519 * @brief Configure LPTIMx clock source
1520 * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource
1521 * @param LPTIMxSource This parameter can be one of the following values:
1522 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
1523 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
1524 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
1525 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
1526 * @retval None
1527 */
LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)1528 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
1529 {
1530 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, LPTIMxSource);
1531 }
1532
1533 #if defined(RCC_CCIPR_HSI48SEL)
1534 #if defined(RNG)
1535 /**
1536 * @brief Configure RNG clock source
1537 * @rmtoll CCIPR HSI48SEL LL_RCC_SetRNGClockSource
1538 * @param RNGxSource This parameter can be one of the following values:
1539 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
1540 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
1541 * @retval None
1542 */
LL_RCC_SetRNGClockSource(uint32_t RNGxSource)1543 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
1544 {
1545 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, RNGxSource);
1546 }
1547 #endif /* RNG */
1548
1549 #if defined(USB)
1550 /**
1551 * @brief Configure USB clock source
1552 * @rmtoll CCIPR HSI48SEL LL_RCC_SetUSBClockSource
1553 * @param USBxSource This parameter can be one of the following values:
1554 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
1555 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
1556 * @retval None
1557 */
LL_RCC_SetUSBClockSource(uint32_t USBxSource)1558 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
1559 {
1560 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, USBxSource);
1561 }
1562 #endif /* USB */
1563
1564 #endif /* RCC_CCIPR_HSI48SEL */
1565
1566 /**
1567 * @brief Get USARTx clock source
1568 * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
1569 * @param USARTx This parameter can be one of the following values:
1570 * @arg @ref LL_RCC_USART1_CLKSOURCE (*)
1571 * @arg @ref LL_RCC_USART2_CLKSOURCE
1572 * @retval Returned value can be one of the following values:
1573 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
1574 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK (*)
1575 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI (*)
1576 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE (*)
1577 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
1578 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
1579 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
1580 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
1581 *
1582 * (*) value not defined in all devices.
1583 */
LL_RCC_GetUSARTClockSource(uint32_t USARTx)1584 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
1585 {
1586 return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));
1587 }
1588
1589
1590
1591 /**
1592 * @brief Get LPUARTx clock source
1593 * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
1594 * @param LPUARTx This parameter can be one of the following values:
1595 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
1596 * @retval Returned value can be one of the following values:
1597 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
1598 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
1599 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
1600 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
1601 */
LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)1602 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
1603 {
1604 return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
1605 }
1606
1607 /**
1608 * @brief Get I2Cx clock source
1609 * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource
1610 * @param I2Cx This parameter can be one of the following values:
1611 * @arg @ref LL_RCC_I2C1_CLKSOURCE
1612 * @arg @ref LL_RCC_I2C3_CLKSOURCE
1613 * @retval Returned value can be one of the following values:
1614 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
1615 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1616 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
1617 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 (*)
1618 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
1619 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
1620 *
1621 * (*) value not defined in all devices.
1622 */
LL_RCC_GetI2CClockSource(uint32_t I2Cx)1623 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
1624 {
1625 return (uint32_t)((READ_BIT(RCC->CCIPR, I2Cx) >> 4U) | (I2Cx << 4U));
1626 }
1627
1628 /**
1629 * @brief Get LPTIMx clock source
1630 * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
1631 * @param LPTIMx This parameter can be one of the following values:
1632 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
1633 * @retval Returned value can be one of the following values:
1634 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
1635 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
1636 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
1637 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
1638 */
LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)1639 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
1640 {
1641 return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx));
1642 }
1643
1644 #if defined(RCC_CCIPR_HSI48SEL)
1645 #if defined(RNG)
1646 /**
1647 * @brief Get RNGx clock source
1648 * @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource
1649 * @param RNGx This parameter can be one of the following values:
1650 * @arg @ref LL_RCC_RNG_CLKSOURCE
1651 * @retval Returned value can be one of the following values:
1652 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
1653 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
1654 */
LL_RCC_GetRNGClockSource(uint32_t RNGx)1655 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
1656 {
1657 return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
1658 }
1659 #endif /* RNG */
1660
1661 #if defined(USB)
1662 /**
1663 * @brief Get USBx clock source
1664 * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource
1665 * @param USBx This parameter can be one of the following values:
1666 * @arg @ref LL_RCC_USB_CLKSOURCE
1667 * @retval Returned value can be one of the following values:
1668 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
1669 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
1670 */
LL_RCC_GetUSBClockSource(uint32_t USBx)1671 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
1672 {
1673 return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
1674 }
1675 #endif /* USB */
1676
1677 #endif /* RCC_CCIPR_HSI48SEL */
1678
1679 /**
1680 * @}
1681 */
1682
1683 /** @defgroup RCC_LL_EF_RTC RTC
1684 * @{
1685 */
1686
1687 /**
1688 * @brief Set RTC Clock Source
1689 * @note Once the RTC clock source has been selected, it cannot be changed any more unless
1690 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
1691 * set). The RTCRST bit can be used to reset them.
1692 * @rmtoll CSR RTCSEL LL_RCC_SetRTCClockSource
1693 * @param Source This parameter can be one of the following values:
1694 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
1695 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
1696 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
1697 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
1698 * @retval None
1699 */
LL_RCC_SetRTCClockSource(uint32_t Source)1700 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
1701 {
1702 MODIFY_REG(RCC->CSR, RCC_CSR_RTCSEL, Source);
1703 }
1704
1705 /**
1706 * @brief Get RTC Clock Source
1707 * @rmtoll CSR RTCSEL LL_RCC_GetRTCClockSource
1708 * @retval Returned value can be one of the following values:
1709 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
1710 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
1711 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
1712 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
1713 */
LL_RCC_GetRTCClockSource(void)1714 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
1715 {
1716 return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL));
1717 }
1718
1719 /**
1720 * @brief Enable RTC
1721 * @rmtoll CSR RTCEN LL_RCC_EnableRTC
1722 * @retval None
1723 */
LL_RCC_EnableRTC(void)1724 __STATIC_INLINE void LL_RCC_EnableRTC(void)
1725 {
1726 SET_BIT(RCC->CSR, RCC_CSR_RTCEN);
1727 }
1728
1729 /**
1730 * @brief Disable RTC
1731 * @rmtoll CSR RTCEN LL_RCC_DisableRTC
1732 * @retval None
1733 */
LL_RCC_DisableRTC(void)1734 __STATIC_INLINE void LL_RCC_DisableRTC(void)
1735 {
1736 CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN);
1737 }
1738
1739 /**
1740 * @brief Check if RTC has been enabled or not
1741 * @rmtoll CSR RTCEN LL_RCC_IsEnabledRTC
1742 * @retval State of bit (1 or 0).
1743 */
LL_RCC_IsEnabledRTC(void)1744 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
1745 {
1746 return ((READ_BIT(RCC->CSR, RCC_CSR_RTCEN) == RCC_CSR_RTCEN) ? 1UL : 0UL);
1747 }
1748
1749 /**
1750 * @brief Force the Backup domain reset
1751 * @rmtoll CSR RTCRST LL_RCC_ForceBackupDomainReset
1752 * @retval None
1753 */
LL_RCC_ForceBackupDomainReset(void)1754 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
1755 {
1756 SET_BIT(RCC->CSR, RCC_CSR_RTCRST);
1757 }
1758
1759 /**
1760 * @brief Release the Backup domain reset
1761 * @rmtoll CSR RTCRST LL_RCC_ReleaseBackupDomainReset
1762 * @retval None
1763 */
LL_RCC_ReleaseBackupDomainReset(void)1764 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
1765 {
1766 CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST);
1767 }
1768
1769 /**
1770 * @}
1771 */
1772
1773 /** @defgroup RCC_LL_EF_PLL PLL
1774 * @{
1775 */
1776
1777 /**
1778 * @brief Enable PLL
1779 * @rmtoll CR PLLON LL_RCC_PLL_Enable
1780 * @retval None
1781 */
LL_RCC_PLL_Enable(void)1782 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
1783 {
1784 SET_BIT(RCC->CR, RCC_CR_PLLON);
1785 }
1786
1787 /**
1788 * @brief Disable PLL
1789 * @note Cannot be disabled if the PLL clock is used as the system clock
1790 * @rmtoll CR PLLON LL_RCC_PLL_Disable
1791 * @retval None
1792 */
LL_RCC_PLL_Disable(void)1793 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
1794 {
1795 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
1796 }
1797
1798 /**
1799 * @brief Check if PLL Ready
1800 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
1801 * @retval State of bit (1 or 0).
1802 */
LL_RCC_PLL_IsReady(void)1803 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
1804 {
1805 return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL);
1806 }
1807
1808 /**
1809 * @brief Configure PLL used for SYSCLK Domain
1810 * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
1811 * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n
1812 * CFGR PLLDIV LL_RCC_PLL_ConfigDomain_SYS
1813 * @param Source This parameter can be one of the following values:
1814 * @arg @ref LL_RCC_PLLSOURCE_HSI
1815 * @arg @ref LL_RCC_PLLSOURCE_HSE
1816 * @param PLLMul This parameter can be one of the following values:
1817 * @arg @ref LL_RCC_PLL_MUL_3
1818 * @arg @ref LL_RCC_PLL_MUL_4
1819 * @arg @ref LL_RCC_PLL_MUL_6
1820 * @arg @ref LL_RCC_PLL_MUL_8
1821 * @arg @ref LL_RCC_PLL_MUL_12
1822 * @arg @ref LL_RCC_PLL_MUL_16
1823 * @arg @ref LL_RCC_PLL_MUL_24
1824 * @arg @ref LL_RCC_PLL_MUL_32
1825 * @arg @ref LL_RCC_PLL_MUL_48
1826 * @param PLLDiv This parameter can be one of the following values:
1827 * @arg @ref LL_RCC_PLL_DIV_2
1828 * @arg @ref LL_RCC_PLL_DIV_3
1829 * @arg @ref LL_RCC_PLL_DIV_4
1830 * @retval None
1831 */
LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source,uint32_t PLLMul,uint32_t PLLDiv)1832 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv)
1833 {
1834 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV, Source | PLLMul | PLLDiv);
1835 }
1836
1837 /**
1838 * @brief Configure PLL clock source
1839 * @rmtoll CFGR PLLSRC LL_RCC_PLL_SetMainSource
1840 * @param PLLSource This parameter can be one of the following values:
1841 * @arg @ref LL_RCC_PLLSOURCE_HSI
1842 * @arg @ref LL_RCC_PLLSOURCE_HSE
1843 * @retval None
1844 */
LL_RCC_PLL_SetMainSource(uint32_t PLLSource)1845 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
1846 {
1847 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource);
1848 }
1849
1850 /**
1851 * @brief Get the oscillator used as PLL clock source.
1852 * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource
1853 * @retval Returned value can be one of the following values:
1854 * @arg @ref LL_RCC_PLLSOURCE_HSI
1855 * @arg @ref LL_RCC_PLLSOURCE_HSE
1856 */
LL_RCC_PLL_GetMainSource(void)1857 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
1858 {
1859 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
1860 }
1861
1862 /**
1863 * @brief Get PLL multiplication Factor
1864 * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator
1865 * @retval Returned value can be one of the following values:
1866 * @arg @ref LL_RCC_PLL_MUL_3
1867 * @arg @ref LL_RCC_PLL_MUL_4
1868 * @arg @ref LL_RCC_PLL_MUL_6
1869 * @arg @ref LL_RCC_PLL_MUL_8
1870 * @arg @ref LL_RCC_PLL_MUL_12
1871 * @arg @ref LL_RCC_PLL_MUL_16
1872 * @arg @ref LL_RCC_PLL_MUL_24
1873 * @arg @ref LL_RCC_PLL_MUL_32
1874 * @arg @ref LL_RCC_PLL_MUL_48
1875 */
LL_RCC_PLL_GetMultiplicator(void)1876 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
1877 {
1878 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL));
1879 }
1880
1881 /**
1882 * @brief Get Division factor for the main PLL and other PLL
1883 * @rmtoll CFGR PLLDIV LL_RCC_PLL_GetDivider
1884 * @retval Returned value can be one of the following values:
1885 * @arg @ref LL_RCC_PLL_DIV_2
1886 * @arg @ref LL_RCC_PLL_DIV_3
1887 * @arg @ref LL_RCC_PLL_DIV_4
1888 */
LL_RCC_PLL_GetDivider(void)1889 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
1890 {
1891 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV));
1892 }
1893
1894 /**
1895 * @}
1896 */
1897
1898 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
1899 * @{
1900 */
1901
1902 /**
1903 * @brief Clear LSI ready interrupt flag
1904 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
1905 * @retval None
1906 */
LL_RCC_ClearFlag_LSIRDY(void)1907 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
1908 {
1909 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
1910 }
1911
1912 /**
1913 * @brief Clear LSE ready interrupt flag
1914 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
1915 * @retval None
1916 */
LL_RCC_ClearFlag_LSERDY(void)1917 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
1918 {
1919 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
1920 }
1921
1922 /**
1923 * @brief Clear MSI ready interrupt flag
1924 * @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY
1925 * @retval None
1926 */
LL_RCC_ClearFlag_MSIRDY(void)1927 __STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
1928 {
1929 SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
1930 }
1931
1932 /**
1933 * @brief Clear HSI ready interrupt flag
1934 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
1935 * @retval None
1936 */
LL_RCC_ClearFlag_HSIRDY(void)1937 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
1938 {
1939 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
1940 }
1941
1942 /**
1943 * @brief Clear HSE ready interrupt flag
1944 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
1945 * @retval None
1946 */
LL_RCC_ClearFlag_HSERDY(void)1947 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
1948 {
1949 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
1950 }
1951
1952 /**
1953 * @brief Clear PLL ready interrupt flag
1954 * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
1955 * @retval None
1956 */
LL_RCC_ClearFlag_PLLRDY(void)1957 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
1958 {
1959 SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
1960 }
1961
1962 #if defined(RCC_HSI48_SUPPORT)
1963 /**
1964 * @brief Clear HSI48 ready interrupt flag
1965 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
1966 * @retval None
1967 */
LL_RCC_ClearFlag_HSI48RDY(void)1968 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
1969 {
1970 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
1971 }
1972 #endif /* RCC_HSI48_SUPPORT */
1973
1974 #if defined(RCC_HSECSS_SUPPORT)
1975 /**
1976 * @brief Clear Clock security system interrupt flag
1977 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
1978 * @retval None
1979 */
LL_RCC_ClearFlag_HSECSS(void)1980 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
1981 {
1982 SET_BIT(RCC->CICR, RCC_CICR_CSSC);
1983 }
1984 #endif /* RCC_HSECSS_SUPPORT */
1985
1986 /**
1987 * @brief Clear LSE Clock security system interrupt flag
1988 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
1989 * @retval None
1990 */
LL_RCC_ClearFlag_LSECSS(void)1991 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
1992 {
1993 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
1994 }
1995
1996 /**
1997 * @brief Check if LSI ready interrupt occurred or not
1998 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
1999 * @retval State of bit (1 or 0).
2000 */
LL_RCC_IsActiveFlag_LSIRDY(void)2001 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
2002 {
2003 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL);
2004 }
2005
2006 /**
2007 * @brief Check if LSE ready interrupt occurred or not
2008 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
2009 * @retval State of bit (1 or 0).
2010 */
LL_RCC_IsActiveFlag_LSERDY(void)2011 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
2012 {
2013 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL);
2014 }
2015
2016 /**
2017 * @brief Check if MSI ready interrupt occurred or not
2018 * @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
2019 * @retval State of bit (1 or 0).
2020 */
LL_RCC_IsActiveFlag_MSIRDY(void)2021 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
2022 {
2023 return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == RCC_CIFR_MSIRDYF) ? 1UL : 0UL);
2024 }
2025
2026 /**
2027 * @brief Check if HSI ready interrupt occurred or not
2028 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
2029 * @retval State of bit (1 or 0).
2030 */
LL_RCC_IsActiveFlag_HSIRDY(void)2031 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
2032 {
2033 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL);
2034 }
2035
2036 /**
2037 * @brief Check if HSE ready interrupt occurred or not
2038 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
2039 * @retval State of bit (1 or 0).
2040 */
LL_RCC_IsActiveFlag_HSERDY(void)2041 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
2042 {
2043 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL);
2044 }
2045
2046 /**
2047 * @brief Check if PLL ready interrupt occurred or not
2048 * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
2049 * @retval State of bit (1 or 0).
2050 */
LL_RCC_IsActiveFlag_PLLRDY(void)2051 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
2052 {
2053 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == RCC_CIFR_PLLRDYF) ? 1UL : 0UL);
2054 }
2055
2056 #if defined(RCC_HSI48_SUPPORT)
2057 /**
2058 * @brief Check if HSI48 ready interrupt occurred or not
2059 * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
2060 * @retval State of bit (1 or 0).
2061 */
LL_RCC_IsActiveFlag_HSI48RDY(void)2062 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
2063 {
2064 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == RCC_CIFR_HSI48RDYF) ? 1UL : 0UL);
2065 }
2066 #endif /* RCC_HSI48_SUPPORT */
2067
2068 #if defined(RCC_HSECSS_SUPPORT)
2069 /**
2070 * @brief Check if Clock security system interrupt occurred or not
2071 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
2072 * @retval State of bit (1 or 0).
2073 */
LL_RCC_IsActiveFlag_HSECSS(void)2074 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
2075 {
2076 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == RCC_CIFR_CSSF) ? 1UL : 0UL);
2077 }
2078 #endif /* RCC_HSECSS_SUPPORT */
2079
2080 /**
2081 * @brief Check if LSE Clock security system interrupt occurred or not
2082 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
2083 * @retval State of bit (1 or 0).
2084 */
LL_RCC_IsActiveFlag_LSECSS(void)2085 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
2086 {
2087 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == RCC_CIFR_LSECSSF) ? 1UL : 0UL);
2088 }
2089
2090 /**
2091 * @brief Check if HSI Divider is enabled (it divides by 4)
2092 * @rmtoll CR HSIDIVF LL_RCC_IsActiveFlag_HSIDIV
2093 * @retval State of bit (1 or 0).
2094 */
LL_RCC_IsActiveFlag_HSIDIV(void)2095 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIDIV(void)
2096 {
2097 return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == RCC_CR_HSIDIVF) ? 1UL : 0UL);
2098 }
2099
2100 #if defined(RCC_CSR_FWRSTF)
2101 /**
2102 * @brief Check if RCC flag FW reset is set or not.
2103 * @rmtoll CSR FWRSTF LL_RCC_IsActiveFlag_FWRST
2104 * @retval State of bit (1 or 0).
2105 */
LL_RCC_IsActiveFlag_FWRST(void)2106 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void)
2107 {
2108 return ((READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == RCC_CSR_FWRSTF) ? 1UL : 0UL);
2109 }
2110 #endif /* RCC_CSR_FWRSTF */
2111
2112 /**
2113 * @brief Check if RCC flag Independent Watchdog reset is set or not.
2114 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
2115 * @retval State of bit (1 or 0).
2116 */
LL_RCC_IsActiveFlag_IWDGRST(void)2117 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
2118 {
2119 return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL);
2120 }
2121
2122 /**
2123 * @brief Check if RCC flag Low Power reset is set or not.
2124 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
2125 * @retval State of bit (1 or 0).
2126 */
LL_RCC_IsActiveFlag_LPWRRST(void)2127 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
2128 {
2129 return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL);
2130 }
2131
2132 /**
2133 * @brief Check if RCC flag is set or not.
2134 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
2135 * @retval State of bit (1 or 0).
2136 */
LL_RCC_IsActiveFlag_OBLRST(void)2137 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
2138 {
2139 return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL);
2140 }
2141
2142 /**
2143 * @brief Check if RCC flag Pin reset is set or not.
2144 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
2145 * @retval State of bit (1 or 0).
2146 */
LL_RCC_IsActiveFlag_PINRST(void)2147 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
2148 {
2149 return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL);
2150 }
2151
2152 /**
2153 * @brief Check if RCC flag POR/PDR reset is set or not.
2154 * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
2155 * @retval State of bit (1 or 0).
2156 */
LL_RCC_IsActiveFlag_PORRST(void)2157 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
2158 {
2159 return ((READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == RCC_CSR_PORRSTF) ? 1UL : 0UL);
2160 }
2161
2162 /**
2163 * @brief Check if RCC flag Software reset is set or not.
2164 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
2165 * @retval State of bit (1 or 0).
2166 */
LL_RCC_IsActiveFlag_SFTRST(void)2167 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
2168 {
2169 return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL);
2170 }
2171
2172 /**
2173 * @brief Check if RCC flag Window Watchdog reset is set or not.
2174 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
2175 * @retval State of bit (1 or 0).
2176 */
LL_RCC_IsActiveFlag_WWDGRST(void)2177 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
2178 {
2179 return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL);
2180 }
2181
2182 /**
2183 * @brief Set RMVF bit to clear the reset flags.
2184 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
2185 * @retval None
2186 */
LL_RCC_ClearResetFlags(void)2187 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
2188 {
2189 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
2190 }
2191
2192 /**
2193 * @}
2194 */
2195
2196 /** @defgroup RCC_LL_EF_IT_Management IT Management
2197 * @{
2198 */
2199
2200 /**
2201 * @brief Enable LSI ready interrupt
2202 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
2203 * @retval None
2204 */
LL_RCC_EnableIT_LSIRDY(void)2205 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
2206 {
2207 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
2208 }
2209
2210 /**
2211 * @brief Enable LSE ready interrupt
2212 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
2213 * @retval None
2214 */
LL_RCC_EnableIT_LSERDY(void)2215 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
2216 {
2217 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
2218 }
2219
2220 /**
2221 * @brief Enable MSI ready interrupt
2222 * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY
2223 * @retval None
2224 */
LL_RCC_EnableIT_MSIRDY(void)2225 __STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
2226 {
2227 SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
2228 }
2229
2230 /**
2231 * @brief Enable HSI ready interrupt
2232 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
2233 * @retval None
2234 */
LL_RCC_EnableIT_HSIRDY(void)2235 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
2236 {
2237 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
2238 }
2239
2240 /**
2241 * @brief Enable HSE ready interrupt
2242 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
2243 * @retval None
2244 */
LL_RCC_EnableIT_HSERDY(void)2245 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
2246 {
2247 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
2248 }
2249
2250 /**
2251 * @brief Enable PLL ready interrupt
2252 * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
2253 * @retval None
2254 */
LL_RCC_EnableIT_PLLRDY(void)2255 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
2256 {
2257 SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
2258 }
2259
2260 #if defined(RCC_HSI48_SUPPORT)
2261 /**
2262 * @brief Enable HSI48 ready interrupt
2263 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
2264 * @retval None
2265 */
LL_RCC_EnableIT_HSI48RDY(void)2266 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
2267 {
2268 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
2269 }
2270 #endif /* RCC_HSI48_SUPPORT */
2271
2272 /**
2273 * @brief Enable LSE clock security system interrupt
2274 * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
2275 * @retval None
2276 */
LL_RCC_EnableIT_LSECSS(void)2277 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
2278 {
2279 SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
2280 }
2281
2282 /**
2283 * @brief Disable LSI ready interrupt
2284 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
2285 * @retval None
2286 */
LL_RCC_DisableIT_LSIRDY(void)2287 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
2288 {
2289 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
2290 }
2291
2292 /**
2293 * @brief Disable LSE ready interrupt
2294 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
2295 * @retval None
2296 */
LL_RCC_DisableIT_LSERDY(void)2297 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
2298 {
2299 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
2300 }
2301
2302 /**
2303 * @brief Disable MSI ready interrupt
2304 * @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY
2305 * @retval None
2306 */
LL_RCC_DisableIT_MSIRDY(void)2307 __STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
2308 {
2309 CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
2310 }
2311
2312 /**
2313 * @brief Disable HSI ready interrupt
2314 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
2315 * @retval None
2316 */
LL_RCC_DisableIT_HSIRDY(void)2317 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
2318 {
2319 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
2320 }
2321
2322 /**
2323 * @brief Disable HSE ready interrupt
2324 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
2325 * @retval None
2326 */
LL_RCC_DisableIT_HSERDY(void)2327 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
2328 {
2329 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
2330 }
2331
2332 /**
2333 * @brief Disable PLL ready interrupt
2334 * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
2335 * @retval None
2336 */
LL_RCC_DisableIT_PLLRDY(void)2337 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
2338 {
2339 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
2340 }
2341
2342 #if defined(RCC_HSI48_SUPPORT)
2343 /**
2344 * @brief Disable HSI48 ready interrupt
2345 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
2346 * @retval None
2347 */
LL_RCC_DisableIT_HSI48RDY(void)2348 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
2349 {
2350 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
2351 }
2352 #endif /* RCC_HSI48_SUPPORT */
2353
2354 /**
2355 * @brief Disable LSE clock security system interrupt
2356 * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
2357 * @retval None
2358 */
LL_RCC_DisableIT_LSECSS(void)2359 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
2360 {
2361 CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
2362 }
2363
2364 /**
2365 * @brief Checks if LSI ready interrupt source is enabled or disabled.
2366 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
2367 * @retval State of bit (1 or 0).
2368 */
LL_RCC_IsEnabledIT_LSIRDY(void)2369 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
2370 {
2371 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL);
2372 }
2373
2374 /**
2375 * @brief Checks if LSE ready interrupt source is enabled or disabled.
2376 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
2377 * @retval State of bit (1 or 0).
2378 */
LL_RCC_IsEnabledIT_LSERDY(void)2379 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
2380 {
2381 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL);
2382 }
2383
2384 /**
2385 * @brief Checks if MSI ready interrupt source is enabled or disabled.
2386 * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
2387 * @retval State of bit (1 or 0).
2388 */
LL_RCC_IsEnabledIT_MSIRDY(void)2389 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
2390 {
2391 return ((READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == RCC_CIER_MSIRDYIE) ? 1UL : 0UL);
2392 }
2393
2394 /**
2395 * @brief Checks if HSI ready interrupt source is enabled or disabled.
2396 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
2397 * @retval State of bit (1 or 0).
2398 */
LL_RCC_IsEnabledIT_HSIRDY(void)2399 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
2400 {
2401 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL);
2402 }
2403
2404 /**
2405 * @brief Checks if HSE ready interrupt source is enabled or disabled.
2406 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
2407 * @retval State of bit (1 or 0).
2408 */
LL_RCC_IsEnabledIT_HSERDY(void)2409 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
2410 {
2411 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL);
2412 }
2413
2414 /**
2415 * @brief Checks if PLL ready interrupt source is enabled or disabled.
2416 * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
2417 * @retval State of bit (1 or 0).
2418 */
LL_RCC_IsEnabledIT_PLLRDY(void)2419 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
2420 {
2421 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == RCC_CIER_PLLRDYIE) ? 1UL : 0UL);
2422 }
2423
2424 #if defined(RCC_HSI48_SUPPORT)
2425 /**
2426 * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
2427 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
2428 * @retval State of bit (1 or 0).
2429 */
LL_RCC_IsEnabledIT_HSI48RDY(void)2430 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
2431 {
2432 return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL);
2433 }
2434 #endif /* RCC_HSI48_SUPPORT */
2435
2436 /**
2437 * @brief Checks if LSECSS interrupt source is enabled or disabled.
2438 * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
2439 * @retval State of bit (1 or 0).
2440 */
LL_RCC_IsEnabledIT_LSECSS(void)2441 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
2442 {
2443 return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL);
2444 }
2445
2446 /**
2447 * @}
2448 */
2449
2450 #if defined(USE_FULL_LL_DRIVER)
2451 /** @defgroup RCC_LL_EF_Init De-initialization function
2452 * @{
2453 */
2454 ErrorStatus LL_RCC_DeInit(void);
2455 /**
2456 * @}
2457 */
2458
2459 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
2460 * @{
2461 */
2462 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
2463 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
2464 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
2465 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
2466 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
2467 #if defined(USB_OTG_FS) || defined(USB)
2468 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
2469 #endif /* USB_OTG_FS || USB */
2470 /**
2471 * @}
2472 */
2473 #endif /* USE_FULL_LL_DRIVER */
2474
2475 /**
2476 * @}
2477 */
2478
2479 /**
2480 * @}
2481 */
2482
2483 #endif /* RCC */
2484
2485 /**
2486 * @}
2487 */
2488
2489 #ifdef __cplusplus
2490 }
2491 #endif
2492
2493 #endif /* __STM32L0xx_LL_RCC_H */
2494
2495
