1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_hsem.h
4 * @author MCD Application Team
5 * @brief Header file of HSEM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WBAxx_LL_HSEM_H
21 #define STM32WBAxx_LL_HSEM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbaxx.h"
29
30 /** @addtogroup STM32WBAxx_LL_Driver
31 * @{
32 */
33
34 #if defined(HSEM)
35
36 /** @defgroup HSEM_LL HSEM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44
45 /* Exported types ------------------------------------------------------------*/
46 /* Exported constants --------------------------------------------------------*/
47
48 /** @defgroup HSEM_LL_Exported_Constants HSEM Exported Constants
49 * @{
50 */
51
52 /** @defgroup HSEM_LL_EC_LOCKID LOCKID Defines
53 * @{
54 */
55 #define LL_HSEM_LOCKID_NONE 0U
56 #define LL_HSEM_LOCKID_CPU1 HSEM_CR_LOCKID_CPU1
57 #define LL_HSEM_LOCKID HSEM_CR_LOCKID_CURRENT
58 /**
59 * @}
60 */
61
62 /** @defgroup HSEM_LL_EC_ATTRIBUTES Attributes Defines
63 * @brief HSEM Privilege/NPrivilege and Secure/NSecure Attributes
64 * @{
65 */
66 #define LL_HSEM_NSEC_PRIV HSEM_R_PRIV /*!< NSecure and Privileged attribute */
67 #define LL_HSEM_NSEC_NPRIV 0x0U /*!< NSecure and NPrivileged attribute */
68 #define LL_HSEM_SEC_PRIV (HSEM_R_SEC | HSEM_R_PRIV) /*!< Secure and Privileged attribute */
69 #define LL_HSEM_SEC_NPRIV HSEM_R_SEC /*!< Secure and NPrivileged attribute */
70 /**
71 * @}
72 */
73
74 /** @defgroup HSEM_LL_EC_GET_FLAG Get Flags Defines
75 * @brief Flags defines which can be used with LL_HSEM_ReadReg function
76 * @{
77 */
78
79 #define LL_HSEM_SEMAPHORE_0 HSEM_IER_ISE0
80 #define LL_HSEM_SEMAPHORE_1 HSEM_IER_ISE1
81 #define LL_HSEM_SEMAPHORE_2 HSEM_IER_ISE2
82 #define LL_HSEM_SEMAPHORE_3 HSEM_IER_ISE3
83 #define LL_HSEM_SEMAPHORE_4 HSEM_IER_ISE4
84 #define LL_HSEM_SEMAPHORE_5 HSEM_IER_ISE5
85 #define LL_HSEM_SEMAPHORE_6 HSEM_IER_ISE6
86 #define LL_HSEM_SEMAPHORE_7 HSEM_IER_ISE7
87 #define LL_HSEM_SEMAPHORE_8 HSEM_IER_ISE8
88 #define LL_HSEM_SEMAPHORE_9 HSEM_IER_ISE9
89 #define LL_HSEM_SEMAPHORE_10 HSEM_IER_ISE10
90 #define LL_HSEM_SEMAPHORE_11 HSEM_IER_ISE11
91 #define LL_HSEM_SEMAPHORE_12 HSEM_IER_ISE12
92 #define LL_HSEM_SEMAPHORE_13 HSEM_IER_ISE13
93 #define LL_HSEM_SEMAPHORE_14 HSEM_IER_ISE14
94 #define LL_HSEM_SEMAPHORE_15 HSEM_IER_ISE15
95 #define LL_HSEM_SEMAPHORE_16 HSEM_IER_ISE16
96 #define LL_HSEM_SEMAPHORE_17 HSEM_IER_ISE17
97 #define LL_HSEM_SEMAPHORE_18 HSEM_IER_ISE18
98 #define LL_HSEM_SEMAPHORE_19 HSEM_IER_ISE19
99 #define LL_HSEM_SEMAPHORE_20 HSEM_IER_ISE20
100 #define LL_HSEM_SEMAPHORE_21 HSEM_IER_ISE21
101 #define LL_HSEM_SEMAPHORE_22 HSEM_IER_ISE22
102 #define LL_HSEM_SEMAPHORE_23 HSEM_IER_ISE23
103 #define LL_HSEM_SEMAPHORE_24 HSEM_IER_ISE24
104 #define LL_HSEM_SEMAPHORE_25 HSEM_IER_ISE25
105 #define LL_HSEM_SEMAPHORE_26 HSEM_IER_ISE26
106 #define LL_HSEM_SEMAPHORE_27 HSEM_IER_ISE27
107 #define LL_HSEM_SEMAPHORE_28 HSEM_IER_ISE28
108 #define LL_HSEM_SEMAPHORE_29 HSEM_IER_ISE29
109 #define LL_HSEM_SEMAPHORE_30 HSEM_IER_ISE30
110 #define LL_HSEM_SEMAPHORE_31 HSEM_IER_ISE31
111 #define LL_HSEM_SEMAPHORE_ALL 0xFFFFFFFFU
112 /**
113 * @}
114 */
115
116 /**
117 * @}
118 */
119
120 /* Exported macro ------------------------------------------------------------*/
121 /** @defgroup HSEM_LL_Exported_Macros HSEM Exported Macros
122 * @{
123 */
124
125 /** @defgroup HSEM_LL_EM_WRITE_READ Common Write and read registers Macros
126 * @{
127 */
128
129 /**
130 * @brief Write a value in HSEM register
131 * @param __INSTANCE__ HSEM Instance
132 * @param __REG__ Register to be written
133 * @param __VALUE__ Value to be written in the register
134 * @retval None
135 */
136 #define LL_HSEM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
137
138 /**
139 * @brief Read a value in HSEM register
140 * @param __INSTANCE__ HSEM Instance
141 * @param __REG__ Register to be read
142 * @retval Register value
143 */
144 #define LL_HSEM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
145 /**
146 * @}
147 */
148
149 /**
150 * @}
151 */
152
153 /* Exported functions --------------------------------------------------------*/
154 /** @defgroup HSEM_LL_Exported_Functions HSEM Exported Functions
155 * @{
156 */
157
158 /** @defgroup HSEM_LL_EF_Data_Management Data_Management
159 * @{
160 */
161
162
163 /**
164 * @brief Return 1 if the semaphore is locked, else return 0.
165 * @rmtoll R LOCK LL_HSEM_IsSemaphoreLocked
166 * @param HSEMx HSEM Instance.
167 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
168 * @retval State of bit (1 or 0).
169 */
LL_HSEM_IsSemaphoreLocked(const HSEM_TypeDef * HSEMx,uint32_t Semaphore)170 __STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(const HSEM_TypeDef *HSEMx, uint32_t Semaphore)
171 {
172 return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL);
173 }
174
175 /**
176 * @brief Get core id.
177 * @rmtoll R LOCKID LL_HSEM_GetCoreId
178 * @param HSEMx HSEM Instance.
179 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
180 * @retval Returned value can be one of the following values:
181 * @arg @ref LL_HSEM_LOCKID_NONE
182 * @arg @ref LL_HSEM_LOCKID_CPU1
183 */
LL_HSEM_GetCoreId(const HSEM_TypeDef * HSEMx,uint32_t Semaphore)184 __STATIC_INLINE uint32_t LL_HSEM_GetCoreId(const HSEM_TypeDef *HSEMx, uint32_t Semaphore)
185 {
186 return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCKID_Msk));
187 }
188
189 /**
190 * @brief Get process id.
191 * @rmtoll R PROCID LL_HSEM_GetProcessId
192 * @param HSEMx HSEM Instance.
193 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
194 * @retval Process number. Value between Min_Data=0 and Max_Data=255
195 */
LL_HSEM_GetProcessId(const HSEM_TypeDef * HSEMx,uint32_t Semaphore)196 __STATIC_INLINE uint32_t LL_HSEM_GetProcessId(const HSEM_TypeDef *HSEMx, uint32_t Semaphore)
197 {
198 return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk));
199 }
200
201 /**
202 * @brief Get the lock by writing in R register.
203 * @note The R register has to be read to determined if the lock is taken.
204 * @rmtoll R LOCK LL_HSEM_SetLock
205 * @rmtoll R LOCKID LL_HSEM_SetLock
206 * @rmtoll R PROCID LL_HSEM_SetLock
207 * @rmtoll R SEC LL_HSEM_SetLock
208 * @rmtoll R PRIV LL_HSEM_SetLock
209 * @param HSEMx HSEM Instance.
210 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
211 * @param process Process id. Value between Min_Data=0 and Max_Data=255
212 * @param attribute Security and privilege attributes. Value can be one of the following:
213 * @arg @ref LL_HSEM_NSEC_PRIV
214 * @arg @ref LL_HSEM_NSEC_NPRIV
215 * @arg @ref LL_HSEM_SEC_PRIV
216 * @arg @ref LL_HSEM_SEC_NPRIV
217 * @retval None
218 */
LL_HSEM_SetLock(HSEM_TypeDef * HSEMx,uint32_t Semaphore,uint32_t process,uint32_t attribute)219 __STATIC_INLINE void LL_HSEM_SetLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process, uint32_t attribute)
220 {
221 WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_LOCKID | process | attribute));
222 }
223
224 /**
225 * @brief Get the lock with 2-step lock.
226 * @rmtoll R LOCK LL_HSEM_2StepLock
227 * @rmtoll R LOCKID LL_HSEM_2StepLock
228 * @rmtoll R PROCID LL_HSEM_2StepLock
229 * @rmtoll R SEC LL_HSEM_2StepLock
230 * @rmtoll R PRIV LL_HSEM_2StepLock
231 * @param HSEMx HSEM Instance.
232 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
233 * @param process Process id. Value between Min_Data=0 and Max_Data=255
234 * @param attribute Security and privilege attributes. Value can be one of the following:
235 * @arg @ref LL_HSEM_NSEC_PRIV
236 * @arg @ref LL_HSEM_NSEC_NPRIV
237 * @arg @ref LL_HSEM_SEC_PRIV
238 * @arg @ref LL_HSEM_SEC_NPRIV
239 * @retval 1 lock fail, 0 lock successful or already locked by same process and core
240 */
LL_HSEM_2StepLock(HSEM_TypeDef * HSEMx,uint32_t Semaphore,uint32_t process,uint32_t attribute)241 __STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process, uint32_t attribute)
242 {
243 WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_LOCKID | process | attribute));
244 return ((HSEMx->R[Semaphore] != (HSEM_R_LOCK | LL_HSEM_LOCKID | process | attribute)) ? 1UL : 0UL);
245 }
246
247 /**
248 * @brief Get the lock with 1-step lock.
249 * @rmtoll RLR LOCK LL_HSEM_1StepLock
250 * @rmtoll RLR LOCKID LL_HSEM_1StepLock
251 * @rmtoll RLR PROCID LL_HSEM_1StepLock
252 * @rmtoll RLR SEC LL_HSEM_1StepLock
253 * @rmtoll RLR PRIV LL_HSEM_1StepLock
254 * @param HSEMx HSEM Instance.
255 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
256 * @param attribute Security and privilege attributes. Value can be one of the following:
257 * @arg @ref LL_HSEM_NSEC_PRIV
258 * @arg @ref LL_HSEM_NSEC_NPRIV
259 * @arg @ref LL_HSEM_SEC_PRIV
260 * @arg @ref LL_HSEM_SEC_NPRIV
261 * @retval 1 lock fail, 0 lock successful or already locked by same core
262 */
LL_HSEM_1StepLock(const HSEM_TypeDef * HSEMx,uint32_t Semaphore,uint32_t attribute)263 __STATIC_INLINE uint32_t LL_HSEM_1StepLock(const HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t attribute)
264 {
265 return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_LOCKID | attribute)) ? 1UL : 0UL);
266 }
267
268 /**
269 * @brief Release the lock of the semaphore.
270 * @note In case of LL_HSEM_1StepLock usage to lock a semaphore, the process is 0.
271 * @rmtoll R LOCK LL_HSEM_ReleaseLock
272 * @rmtoll R SEC LL_HSEM_ReleaseLock
273 * @rmtoll R PRIV LL_HSEM_ReleaseLock
274 * @param HSEMx HSEM Instance.
275 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
276 * @param process Process number. Value between Min_Data=0 and Max_Data=255
277 * @param attribute Security and privilege attributes. Value can be one of the following:
278 * @arg @ref LL_HSEM_NSEC_PRIV
279 * @arg @ref LL_HSEM_NSEC_NPRIV
280 * @arg @ref LL_HSEM_SEC_PRIV
281 * @arg @ref LL_HSEM_SEC_NPRIV
282 * @retval None
283 */
LL_HSEM_ReleaseLock(HSEM_TypeDef * HSEMx,uint32_t Semaphore,uint32_t process,uint32_t attribute)284 __STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process, uint32_t attribute)
285 {
286 WRITE_REG(HSEMx->R[Semaphore], (LL_HSEM_LOCKID | process | attribute));
287 }
288
289 /**
290 * @brief Get the lock status of the semaphore.
291 * @rmtoll R LOCK LL_HSEM_GetStatus
292 * @param HSEMx HSEM Instance.
293 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
294 * @retval 0 semaphore is free, 1 semaphore is locked */
LL_HSEM_GetStatus(const HSEM_TypeDef * HSEMx,uint32_t Semaphore)295 __STATIC_INLINE uint32_t LL_HSEM_GetStatus(const HSEM_TypeDef *HSEMx, uint32_t Semaphore)
296 {
297 return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL);
298 }
299
300 /**
301 * @brief Set the key.
302 * @rmtoll KEYR KEY LL_HSEM_SetKey
303 * @param HSEMx HSEM Instance.
304 * @param key Key value.
305 * @retval None
306 */
LL_HSEM_SetKey(HSEM_TypeDef * HSEMx,uint32_t key)307 __STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key)
308 {
309 WRITE_REG(HSEMx->KEYR, key << HSEM_KEYR_KEY_Pos);
310 }
311
312 /**
313 * @brief Get the key.
314 * @rmtoll KEYR KEY LL_HSEM_GetKey
315 * @param HSEMx HSEM Instance.
316 * @retval key to unlock all semaphore from the same core
317 */
LL_HSEM_GetKey(const HSEM_TypeDef * HSEMx)318 __STATIC_INLINE uint32_t LL_HSEM_GetKey(const HSEM_TypeDef *HSEMx)
319 {
320 return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos);
321 }
322
323 /**
324 * @brief Release all semaphore with the same core id.
325 * @rmtoll CR KEY LL_HSEM_ResetAllLock
326 * @param HSEMx HSEM Instance.
327 * @param key Key value.
328 * @param core This parameter can be one of the following values:
329 * @arg @ref LL_HSEM_LOCKID_CPU1
330 * @param attribute Security and privilege attributes. Value can be one of the following:
331 * @arg @ref LL_HSEM_NSEC_PRIV
332 * @arg @ref LL_HSEM_NSEC_NPRIV
333 * @arg @ref LL_HSEM_SEC_PRIV
334 * @arg @ref LL_HSEM_SEC_NPRIV
335 * @retval None
336 */
LL_HSEM_ResetAllLock(HSEM_TypeDef * HSEMx,uint32_t key,uint32_t core,uint32_t attribute)337 __STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core, uint32_t attribute)
338 {
339 WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core | attribute);
340 }
341
342 #if defined(HSEM_SECCFGR_SEC0)
343 /**
344 * @brief Set semaphore accessible by secure only.
345 * @rmtoll SECCFGR SEC LL_HSEM_SetSemaphoreSecure
346 * @param HSEMx HSEM Instance.
347 * @param SemMask This parameter can be a combination of the following values:
348 * @arg @ref LL_HSEM_SEMAPHORE_0
349 * @arg @ref LL_HSEM_SEMAPHORE_1
350 * @arg @ref LL_HSEM_SEMAPHORE_2
351 * @arg @ref LL_HSEM_SEMAPHORE_3
352 * @arg @ref LL_HSEM_SEMAPHORE_4
353 * @arg @ref LL_HSEM_SEMAPHORE_5
354 * @arg @ref LL_HSEM_SEMAPHORE_6
355 * @arg @ref LL_HSEM_SEMAPHORE_7
356 * @arg @ref LL_HSEM_SEMAPHORE_8
357 * @arg @ref LL_HSEM_SEMAPHORE_9
358 * @arg @ref LL_HSEM_SEMAPHORE_10
359 * @arg @ref LL_HSEM_SEMAPHORE_11
360 * @arg @ref LL_HSEM_SEMAPHORE_12
361 * @arg @ref LL_HSEM_SEMAPHORE_13
362 * @arg @ref LL_HSEM_SEMAPHORE_14
363 * @arg @ref LL_HSEM_SEMAPHORE_15
364 * @arg @ref LL_HSEM_SEMAPHORE_16
365 * @arg @ref LL_HSEM_SEMAPHORE_ALL
366 * @retval None
367 */
LL_HSEM_SetSemaphoreSecure(HSEM_TypeDef * HSEMx,uint32_t SemMask)368 __STATIC_INLINE void LL_HSEM_SetSemaphoreSecure(HSEM_TypeDef *HSEMx, uint32_t SemMask)
369 {
370 SET_BIT(HSEMx->SECCFGR, SemMask);
371 }
372
373 /**
374 * @brief Set semaphore accessible by secure and non-secure.
375 * @rmtoll SECCFGR SEC LL_HSEM_SetSemaphoreNonSecure
376 * @param HSEMx HSEM Instance.
377 * @param SemMask This parameter can be a combination of the following values:
378 * @arg @ref LL_HSEM_SEMAPHORE_0
379 * @arg @ref LL_HSEM_SEMAPHORE_1
380 * @arg @ref LL_HSEM_SEMAPHORE_2
381 * @arg @ref LL_HSEM_SEMAPHORE_3
382 * @arg @ref LL_HSEM_SEMAPHORE_4
383 * @arg @ref LL_HSEM_SEMAPHORE_5
384 * @arg @ref LL_HSEM_SEMAPHORE_6
385 * @arg @ref LL_HSEM_SEMAPHORE_7
386 * @arg @ref LL_HSEM_SEMAPHORE_8
387 * @arg @ref LL_HSEM_SEMAPHORE_9
388 * @arg @ref LL_HSEM_SEMAPHORE_10
389 * @arg @ref LL_HSEM_SEMAPHORE_11
390 * @arg @ref LL_HSEM_SEMAPHORE_12
391 * @arg @ref LL_HSEM_SEMAPHORE_13
392 * @arg @ref LL_HSEM_SEMAPHORE_14
393 * @arg @ref LL_HSEM_SEMAPHORE_15
394 * @arg @ref LL_HSEM_SEMAPHORE_16
395 * @arg @ref LL_HSEM_SEMAPHORE_ALL
396 * @retval None
397 */
LL_HSEM_SetSemaphoreNonSecure(HSEM_TypeDef * HSEMx,uint32_t SemMask)398 __STATIC_INLINE void LL_HSEM_SetSemaphoreNonSecure(HSEM_TypeDef *HSEMx, uint32_t SemMask)
399 {
400 CLEAR_BIT(HSEMx->SECCFGR, SemMask);
401 }
402
403 /**
404 * @brief Get security attribute of semaphore.
405 * @rmtoll SECCFGR SEC LL_HSEM_GetSemaphoreSecure
406 * @param HSEMx HSEM Instance.
407 * @retval Security attribute of semaphores
408 */
LL_HSEM_GetSemaphoreSecure(const HSEM_TypeDef * HSEMx)409 __STATIC_INLINE uint32_t LL_HSEM_GetSemaphoreSecure(const HSEM_TypeDef *HSEMx)
410 {
411 return HSEMx->SECCFGR;
412 }
413
414 /**
415 * @brief Set semaphore accessible by privilege only.
416 * @rmtoll PRIVCFGR PRIV LL_HSEM_SetSemaphorePrivilege
417 * @param HSEMx HSEM Instance.
418 * @param SemMask This parameter can be a combination of the following values:
419 * @arg @ref LL_HSEM_SEMAPHORE_0
420 * @arg @ref LL_HSEM_SEMAPHORE_1
421 * @arg @ref LL_HSEM_SEMAPHORE_2
422 * @arg @ref LL_HSEM_SEMAPHORE_3
423 * @arg @ref LL_HSEM_SEMAPHORE_4
424 * @arg @ref LL_HSEM_SEMAPHORE_5
425 * @arg @ref LL_HSEM_SEMAPHORE_6
426 * @arg @ref LL_HSEM_SEMAPHORE_7
427 * @arg @ref LL_HSEM_SEMAPHORE_8
428 * @arg @ref LL_HSEM_SEMAPHORE_9
429 * @arg @ref LL_HSEM_SEMAPHORE_10
430 * @arg @ref LL_HSEM_SEMAPHORE_11
431 * @arg @ref LL_HSEM_SEMAPHORE_12
432 * @arg @ref LL_HSEM_SEMAPHORE_13
433 * @arg @ref LL_HSEM_SEMAPHORE_14
434 * @arg @ref LL_HSEM_SEMAPHORE_15
435 * @arg @ref LL_HSEM_SEMAPHORE_16
436 * @arg @ref LL_HSEM_SEMAPHORE_ALL
437 * @retval None
438 */
LL_HSEM_SetSemaphorePrivilege(HSEM_TypeDef * HSEMx,uint32_t SemMask)439 __STATIC_INLINE void LL_HSEM_SetSemaphorePrivilege(HSEM_TypeDef *HSEMx, uint32_t SemMask)
440 {
441 SET_BIT(HSEMx->PRIVCFGR, SemMask);
442 }
443
444 /**
445 * @brief Set semaphore accessible by privilege and non-privilege.
446 * @rmtoll PRIVCFGR PRIV LL_HSEM_SetSemaphoreNonPrivilege
447 * @param HSEMx HSEM Instance.
448 * @param SemMask This parameter can be a combination of the following values:
449 * @arg @ref LL_HSEM_SEMAPHORE_0
450 * @arg @ref LL_HSEM_SEMAPHORE_1
451 * @arg @ref LL_HSEM_SEMAPHORE_2
452 * @arg @ref LL_HSEM_SEMAPHORE_3
453 * @arg @ref LL_HSEM_SEMAPHORE_4
454 * @arg @ref LL_HSEM_SEMAPHORE_5
455 * @arg @ref LL_HSEM_SEMAPHORE_6
456 * @arg @ref LL_HSEM_SEMAPHORE_7
457 * @arg @ref LL_HSEM_SEMAPHORE_8
458 * @arg @ref LL_HSEM_SEMAPHORE_9
459 * @arg @ref LL_HSEM_SEMAPHORE_10
460 * @arg @ref LL_HSEM_SEMAPHORE_11
461 * @arg @ref LL_HSEM_SEMAPHORE_12
462 * @arg @ref LL_HSEM_SEMAPHORE_13
463 * @arg @ref LL_HSEM_SEMAPHORE_14
464 * @arg @ref LL_HSEM_SEMAPHORE_15
465 * @arg @ref LL_HSEM_SEMAPHORE_16
466 * @arg @ref LL_HSEM_SEMAPHORE_ALL
467 * @retval None
468 */
LL_HSEM_SetSemaphoreNonPrivilege(HSEM_TypeDef * HSEMx,uint32_t SemMask)469 __STATIC_INLINE void LL_HSEM_SetSemaphoreNonPrivilege(HSEM_TypeDef *HSEMx, uint32_t SemMask)
470 {
471 CLEAR_BIT(HSEMx->PRIVCFGR, SemMask);
472 }
473
474 /**
475 * @brief Get privilege attribute of semaphore.
476 * @rmtoll PRIVCFGR PRIV LL_HSEM_GetSemaphorePrivilege
477 * @param HSEMx HSEM Instance.
478 * @retval Privilege attribute of semaphores
479 */
LL_HSEM_GetSemaphorePrivilege(const HSEM_TypeDef * HSEMx)480 __STATIC_INLINE uint32_t LL_HSEM_GetSemaphorePrivilege(const HSEM_TypeDef *HSEMx)
481 {
482 return HSEMx->PRIVCFGR;
483 }
484
485 #endif
486 /**
487 * @}
488 */
489
490 /** @defgroup HSEM_LL_EF_IT_Management IT_Management
491 * @{
492 */
493
494 /**
495 * @brief Enable interrupt.
496 * @rmtoll IER ISEM LL_HSEM_EnableIT_IER
497 * @param HSEMx HSEM Instance.
498 * @param SemaphoreMask This parameter can be a combination of the following values:
499 * @arg @ref LL_HSEM_SEMAPHORE_0
500 * @arg @ref LL_HSEM_SEMAPHORE_1
501 * @arg @ref LL_HSEM_SEMAPHORE_2
502 * @arg @ref LL_HSEM_SEMAPHORE_3
503 * @arg @ref LL_HSEM_SEMAPHORE_4
504 * @arg @ref LL_HSEM_SEMAPHORE_5
505 * @arg @ref LL_HSEM_SEMAPHORE_6
506 * @arg @ref LL_HSEM_SEMAPHORE_7
507 * @arg @ref LL_HSEM_SEMAPHORE_8
508 * @arg @ref LL_HSEM_SEMAPHORE_9
509 * @arg @ref LL_HSEM_SEMAPHORE_10
510 * @arg @ref LL_HSEM_SEMAPHORE_11
511 * @arg @ref LL_HSEM_SEMAPHORE_12
512 * @arg @ref LL_HSEM_SEMAPHORE_13
513 * @arg @ref LL_HSEM_SEMAPHORE_14
514 * @arg @ref LL_HSEM_SEMAPHORE_15
515 * @arg @ref LL_HSEM_SEMAPHORE_16
516 * @arg @ref LL_HSEM_SEMAPHORE_17
517 * @arg @ref LL_HSEM_SEMAPHORE_18
518 * @arg @ref LL_HSEM_SEMAPHORE_19
519 * @arg @ref LL_HSEM_SEMAPHORE_20
520 * @arg @ref LL_HSEM_SEMAPHORE_21
521 * @arg @ref LL_HSEM_SEMAPHORE_22
522 * @arg @ref LL_HSEM_SEMAPHORE_23
523 * @arg @ref LL_HSEM_SEMAPHORE_24
524 * @arg @ref LL_HSEM_SEMAPHORE_25
525 * @arg @ref LL_HSEM_SEMAPHORE_26
526 * @arg @ref LL_HSEM_SEMAPHORE_27
527 * @arg @ref LL_HSEM_SEMAPHORE_28
528 * @arg @ref LL_HSEM_SEMAPHORE_29
529 * @arg @ref LL_HSEM_SEMAPHORE_30
530 * @arg @ref LL_HSEM_SEMAPHORE_31
531 * @arg @ref LL_HSEM_SEMAPHORE_ALL
532 * @retval None
533 */
LL_HSEM_EnableIT_IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)534 __STATIC_INLINE void LL_HSEM_EnableIT_IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
535 {
536 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
537 SET_BIT(HSEMx->SIER, SemaphoreMask);
538 #else
539 SET_BIT(HSEMx->IER, SemaphoreMask);
540 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
541 }
542
543 /**
544 * @brief Disable interrupt.
545 * @rmtoll IER ISEM LL_HSEM_DisableIT_IER
546 * @param HSEMx HSEM Instance.
547 * @param SemaphoreMask This parameter can be a combination of the following values:
548 * @arg @ref LL_HSEM_SEMAPHORE_0
549 * @arg @ref LL_HSEM_SEMAPHORE_1
550 * @arg @ref LL_HSEM_SEMAPHORE_2
551 * @arg @ref LL_HSEM_SEMAPHORE_3
552 * @arg @ref LL_HSEM_SEMAPHORE_4
553 * @arg @ref LL_HSEM_SEMAPHORE_5
554 * @arg @ref LL_HSEM_SEMAPHORE_6
555 * @arg @ref LL_HSEM_SEMAPHORE_7
556 * @arg @ref LL_HSEM_SEMAPHORE_8
557 * @arg @ref LL_HSEM_SEMAPHORE_9
558 * @arg @ref LL_HSEM_SEMAPHORE_10
559 * @arg @ref LL_HSEM_SEMAPHORE_11
560 * @arg @ref LL_HSEM_SEMAPHORE_12
561 * @arg @ref LL_HSEM_SEMAPHORE_13
562 * @arg @ref LL_HSEM_SEMAPHORE_14
563 * @arg @ref LL_HSEM_SEMAPHORE_15
564 * @arg @ref LL_HSEM_SEMAPHORE_16
565 * @arg @ref LL_HSEM_SEMAPHORE_17
566 * @arg @ref LL_HSEM_SEMAPHORE_18
567 * @arg @ref LL_HSEM_SEMAPHORE_19
568 * @arg @ref LL_HSEM_SEMAPHORE_20
569 * @arg @ref LL_HSEM_SEMAPHORE_21
570 * @arg @ref LL_HSEM_SEMAPHORE_22
571 * @arg @ref LL_HSEM_SEMAPHORE_23
572 * @arg @ref LL_HSEM_SEMAPHORE_24
573 * @arg @ref LL_HSEM_SEMAPHORE_25
574 * @arg @ref LL_HSEM_SEMAPHORE_26
575 * @arg @ref LL_HSEM_SEMAPHORE_27
576 * @arg @ref LL_HSEM_SEMAPHORE_28
577 * @arg @ref LL_HSEM_SEMAPHORE_29
578 * @arg @ref LL_HSEM_SEMAPHORE_30
579 * @arg @ref LL_HSEM_SEMAPHORE_31
580 * @arg @ref LL_HSEM_SEMAPHORE_ALL
581 * @retval None
582 */
LL_HSEM_DisableIT_IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)583 __STATIC_INLINE void LL_HSEM_DisableIT_IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
584 {
585 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
586 CLEAR_BIT(HSEMx->SIER, SemaphoreMask);
587 #else
588 CLEAR_BIT(HSEMx->IER, SemaphoreMask);
589 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
590 }
591
592 /**
593 * @brief Check if interrupt is enabled.
594 * @rmtoll IER ISEM LL_HSEM_IsEnabledIT_IER
595 * @param HSEMx HSEM Instance.
596 * @param SemaphoreMask This parameter can be a combination of the following values:
597 * @arg @ref LL_HSEM_SEMAPHORE_0
598 * @arg @ref LL_HSEM_SEMAPHORE_1
599 * @arg @ref LL_HSEM_SEMAPHORE_2
600 * @arg @ref LL_HSEM_SEMAPHORE_3
601 * @arg @ref LL_HSEM_SEMAPHORE_4
602 * @arg @ref LL_HSEM_SEMAPHORE_5
603 * @arg @ref LL_HSEM_SEMAPHORE_6
604 * @arg @ref LL_HSEM_SEMAPHORE_7
605 * @arg @ref LL_HSEM_SEMAPHORE_8
606 * @arg @ref LL_HSEM_SEMAPHORE_9
607 * @arg @ref LL_HSEM_SEMAPHORE_10
608 * @arg @ref LL_HSEM_SEMAPHORE_11
609 * @arg @ref LL_HSEM_SEMAPHORE_12
610 * @arg @ref LL_HSEM_SEMAPHORE_13
611 * @arg @ref LL_HSEM_SEMAPHORE_14
612 * @arg @ref LL_HSEM_SEMAPHORE_15
613 * @arg @ref LL_HSEM_SEMAPHORE_16
614 * @arg @ref LL_HSEM_SEMAPHORE_17
615 * @arg @ref LL_HSEM_SEMAPHORE_18
616 * @arg @ref LL_HSEM_SEMAPHORE_19
617 * @arg @ref LL_HSEM_SEMAPHORE_20
618 * @arg @ref LL_HSEM_SEMAPHORE_21
619 * @arg @ref LL_HSEM_SEMAPHORE_22
620 * @arg @ref LL_HSEM_SEMAPHORE_23
621 * @arg @ref LL_HSEM_SEMAPHORE_24
622 * @arg @ref LL_HSEM_SEMAPHORE_25
623 * @arg @ref LL_HSEM_SEMAPHORE_26
624 * @arg @ref LL_HSEM_SEMAPHORE_27
625 * @arg @ref LL_HSEM_SEMAPHORE_28
626 * @arg @ref LL_HSEM_SEMAPHORE_29
627 * @arg @ref LL_HSEM_SEMAPHORE_30
628 * @arg @ref LL_HSEM_SEMAPHORE_31
629 * @arg @ref LL_HSEM_SEMAPHORE_ALL
630 * @retval State of bit (1 or 0).
631 */
LL_HSEM_IsEnabledIT_IER(const HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)632 __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_IER(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
633 {
634 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
635 return ((READ_BIT(HSEMx->SIER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
636 #else
637 return ((READ_BIT(HSEMx->IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
638 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
639 }
640
641
642 /**
643 * @}
644 */
645
646 /** @defgroup HSEM_LL_EF_FLAG_Management FLAG_Management
647 * @{
648 */
649
650 /**
651 * @brief Clear interrupt status.
652 * @rmtoll ICR ISEM LL_HSEM_ClearFlag_ICR
653 * @param HSEMx HSEM Instance.
654 * @param SemaphoreMask This parameter can be a combination of the following values:
655 * @arg @ref LL_HSEM_SEMAPHORE_0
656 * @arg @ref LL_HSEM_SEMAPHORE_1
657 * @arg @ref LL_HSEM_SEMAPHORE_2
658 * @arg @ref LL_HSEM_SEMAPHORE_3
659 * @arg @ref LL_HSEM_SEMAPHORE_4
660 * @arg @ref LL_HSEM_SEMAPHORE_5
661 * @arg @ref LL_HSEM_SEMAPHORE_6
662 * @arg @ref LL_HSEM_SEMAPHORE_7
663 * @arg @ref LL_HSEM_SEMAPHORE_8
664 * @arg @ref LL_HSEM_SEMAPHORE_9
665 * @arg @ref LL_HSEM_SEMAPHORE_10
666 * @arg @ref LL_HSEM_SEMAPHORE_11
667 * @arg @ref LL_HSEM_SEMAPHORE_12
668 * @arg @ref LL_HSEM_SEMAPHORE_13
669 * @arg @ref LL_HSEM_SEMAPHORE_14
670 * @arg @ref LL_HSEM_SEMAPHORE_15
671 * @arg @ref LL_HSEM_SEMAPHORE_16
672 * @arg @ref LL_HSEM_SEMAPHORE_17
673 * @arg @ref LL_HSEM_SEMAPHORE_18
674 * @arg @ref LL_HSEM_SEMAPHORE_19
675 * @arg @ref LL_HSEM_SEMAPHORE_20
676 * @arg @ref LL_HSEM_SEMAPHORE_21
677 * @arg @ref LL_HSEM_SEMAPHORE_22
678 * @arg @ref LL_HSEM_SEMAPHORE_23
679 * @arg @ref LL_HSEM_SEMAPHORE_24
680 * @arg @ref LL_HSEM_SEMAPHORE_25
681 * @arg @ref LL_HSEM_SEMAPHORE_26
682 * @arg @ref LL_HSEM_SEMAPHORE_27
683 * @arg @ref LL_HSEM_SEMAPHORE_28
684 * @arg @ref LL_HSEM_SEMAPHORE_29
685 * @arg @ref LL_HSEM_SEMAPHORE_30
686 * @arg @ref LL_HSEM_SEMAPHORE_31
687 * @arg @ref LL_HSEM_SEMAPHORE_ALL
688 * @retval None
689 */
LL_HSEM_ClearFlag_ICR(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)690 __STATIC_INLINE void LL_HSEM_ClearFlag_ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
691 {
692 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
693 WRITE_REG(HSEMx->SICR, SemaphoreMask);
694 #else
695 WRITE_REG(HSEMx->ICR, SemaphoreMask);
696 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
697 }
698
699 /**
700 * @brief Get interrupt status from ISR register.
701 * @rmtoll ISR ISEM LL_HSEM_IsActiveFlag_ISR
702 * @param HSEMx HSEM Instance.
703 * @param SemaphoreMask This parameter can be a combination of the following values:
704 * @arg @ref LL_HSEM_SEMAPHORE_0
705 * @arg @ref LL_HSEM_SEMAPHORE_1
706 * @arg @ref LL_HSEM_SEMAPHORE_2
707 * @arg @ref LL_HSEM_SEMAPHORE_3
708 * @arg @ref LL_HSEM_SEMAPHORE_4
709 * @arg @ref LL_HSEM_SEMAPHORE_5
710 * @arg @ref LL_HSEM_SEMAPHORE_6
711 * @arg @ref LL_HSEM_SEMAPHORE_7
712 * @arg @ref LL_HSEM_SEMAPHORE_8
713 * @arg @ref LL_HSEM_SEMAPHORE_9
714 * @arg @ref LL_HSEM_SEMAPHORE_10
715 * @arg @ref LL_HSEM_SEMAPHORE_11
716 * @arg @ref LL_HSEM_SEMAPHORE_12
717 * @arg @ref LL_HSEM_SEMAPHORE_13
718 * @arg @ref LL_HSEM_SEMAPHORE_14
719 * @arg @ref LL_HSEM_SEMAPHORE_15
720 * @arg @ref LL_HSEM_SEMAPHORE_16
721 * @arg @ref LL_HSEM_SEMAPHORE_17
722 * @arg @ref LL_HSEM_SEMAPHORE_18
723 * @arg @ref LL_HSEM_SEMAPHORE_19
724 * @arg @ref LL_HSEM_SEMAPHORE_20
725 * @arg @ref LL_HSEM_SEMAPHORE_21
726 * @arg @ref LL_HSEM_SEMAPHORE_22
727 * @arg @ref LL_HSEM_SEMAPHORE_23
728 * @arg @ref LL_HSEM_SEMAPHORE_24
729 * @arg @ref LL_HSEM_SEMAPHORE_25
730 * @arg @ref LL_HSEM_SEMAPHORE_26
731 * @arg @ref LL_HSEM_SEMAPHORE_27
732 * @arg @ref LL_HSEM_SEMAPHORE_28
733 * @arg @ref LL_HSEM_SEMAPHORE_29
734 * @arg @ref LL_HSEM_SEMAPHORE_30
735 * @arg @ref LL_HSEM_SEMAPHORE_31
736 * @arg @ref LL_HSEM_SEMAPHORE_ALL
737 * @retval State of bit (1 or 0).
738 */
LL_HSEM_IsActiveFlag_ISR(const HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)739 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_ISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
740 {
741 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
742 return ((READ_BIT(HSEMx->SISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
743 #else
744 return ((READ_BIT(HSEMx->ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
745 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
746 }
747
748 /**
749 * @brief Get interrupt status from MISR register.
750 * @rmtoll MISR ISEM LL_HSEM_IsActiveFlag_MISR
751 * @param HSEMx HSEM Instance.
752 * @param SemaphoreMask This parameter can be a combination of the following values:
753 * @arg @ref LL_HSEM_SEMAPHORE_0
754 * @arg @ref LL_HSEM_SEMAPHORE_1
755 * @arg @ref LL_HSEM_SEMAPHORE_2
756 * @arg @ref LL_HSEM_SEMAPHORE_3
757 * @arg @ref LL_HSEM_SEMAPHORE_4
758 * @arg @ref LL_HSEM_SEMAPHORE_5
759 * @arg @ref LL_HSEM_SEMAPHORE_6
760 * @arg @ref LL_HSEM_SEMAPHORE_7
761 * @arg @ref LL_HSEM_SEMAPHORE_8
762 * @arg @ref LL_HSEM_SEMAPHORE_9
763 * @arg @ref LL_HSEM_SEMAPHORE_10
764 * @arg @ref LL_HSEM_SEMAPHORE_11
765 * @arg @ref LL_HSEM_SEMAPHORE_12
766 * @arg @ref LL_HSEM_SEMAPHORE_13
767 * @arg @ref LL_HSEM_SEMAPHORE_14
768 * @arg @ref LL_HSEM_SEMAPHORE_15
769 * @arg @ref LL_HSEM_SEMAPHORE_16
770 * @arg @ref LL_HSEM_SEMAPHORE_17
771 * @arg @ref LL_HSEM_SEMAPHORE_18
772 * @arg @ref LL_HSEM_SEMAPHORE_19
773 * @arg @ref LL_HSEM_SEMAPHORE_20
774 * @arg @ref LL_HSEM_SEMAPHORE_21
775 * @arg @ref LL_HSEM_SEMAPHORE_22
776 * @arg @ref LL_HSEM_SEMAPHORE_23
777 * @arg @ref LL_HSEM_SEMAPHORE_24
778 * @arg @ref LL_HSEM_SEMAPHORE_25
779 * @arg @ref LL_HSEM_SEMAPHORE_26
780 * @arg @ref LL_HSEM_SEMAPHORE_27
781 * @arg @ref LL_HSEM_SEMAPHORE_28
782 * @arg @ref LL_HSEM_SEMAPHORE_29
783 * @arg @ref LL_HSEM_SEMAPHORE_30
784 * @arg @ref LL_HSEM_SEMAPHORE_31
785 * @arg @ref LL_HSEM_SEMAPHORE_ALL
786 * @retval State of bit (1 or 0).
787 */
LL_HSEM_IsActiveFlag_MISR(const HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)788 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_MISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
789 {
790 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
791 return ((READ_BIT(HSEMx->SMISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
792 #else
793 return ((READ_BIT(HSEMx->MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
794 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
795 }
796
797 /**
798 * @}
799 */
800
801 /**
802 * @}
803 */
804
805 /**
806 * @}
807 */
808
809 #endif /* defined(HSEM) */
810
811 /**
812 * @}
813 */
814
815 #ifdef __cplusplus
816 }
817 #endif
818
819 #endif /* __STM32WBAxx_LL_HSEM_H */
820
