1 /** 2 ****************************************************************************** 3 * @file stm32g0xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2018 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32G0xx_HAL_H 22 #define STM32G0xx_HAL_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32g0xx_hal_conf.h" 30 31 /** @addtogroup STM32G0xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @defgroup HAL HAL 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup HAL_TICK_FREQ Tick Frequency 41 * @{ 42 */ 43 typedef enum 44 { 45 HAL_TICK_FREQ_10HZ = 100U, 46 HAL_TICK_FREQ_100HZ = 10U, 47 HAL_TICK_FREQ_1KHZ = 1U, 48 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 49 } HAL_TickFreqTypeDef; 50 /** 51 * @} 52 */ 53 54 /* Exported constants --------------------------------------------------------*/ 55 /** @defgroup HAL_Exported_Constants HAL Exported Constants 56 * @{ 57 */ 58 59 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 60 * @{ 61 */ 62 63 /** @defgroup SYSCFG_BootMode Boot Mode 64 * @{ 65 */ 66 #define SYSCFG_BOOT_MAINFLASH 0x00000000U /*!< Main Flash memory mapped at 0x0000 0000 */ 67 #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x0000 0000 */ 68 #define SYSCFG_BOOT_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< Embedded SRAM mapped at 0x0000 0000 */ 69 70 /** 71 * @} 72 */ 73 74 /** @defgroup SYSCFG_Break Break 75 * @{ 76 */ 77 #define SYSCFG_BREAK_SP SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM Parity error signal with Break Input of TIM1/15/16/17 */ 78 #if defined(SYSCFG_CFGR2_PVDL) 79 #define SYSCFG_BREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ 80 #endif /* SYSCFG_CFGR2_PVDL */ 81 #define SYSCFG_BREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM0+ with Break Input of TIM1/15/16/17 */ 82 #define SYSCFG_BREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC of CortexM0+ with Break Input of TIM1/15/16/17 */ 83 /** 84 * @} 85 */ 86 87 #if defined(SYSCFG_CDEN_SUPPORT) 88 /** @defgroup SYSCFG_ClampingDiode Clamping Diode 89 * @{ 90 */ 91 #define SYSCFG_CDEN_PA1 SYSCFG_CFGR2_PA1_CDEN /*!< Enables Clamping Diode on PA1 */ 92 #define SYSCFG_CDEN_PA3 SYSCFG_CFGR2_PA3_CDEN /*!< Enables Clamping Diode on PA3 */ 93 #define SYSCFG_CDEN_PA5 SYSCFG_CFGR2_PA5_CDEN /*!< Enables Clamping Diode on PA5 */ 94 #define SYSCFG_CDEN_PA6 SYSCFG_CFGR2_PA6_CDEN /*!< Enables Clamping Diode on PA6 */ 95 #define SYSCFG_CDEN_PA13 SYSCFG_CFGR2_PA13_CDEN /*!< Enables Clamping Diode on PA13 */ 96 #define SYSCFG_CDEN_PB0 SYSCFG_CFGR2_PB0_CDEN /*!< Enables Clamping Diode on PB0 */ 97 #define SYSCFG_CDEN_PB1 SYSCFG_CFGR2_PB1_CDEN /*!< Enables Clamping Diode on PB1 */ 98 #define SYSCFG_CDEN_PB2 SYSCFG_CFGR2_PB2_CDEN /*!< Enables Clamping Diode on PB2 */ 99 100 /** 101 * @} 102 */ 103 #endif /* SYSCFG_CDEN_SUPPORT */ 104 105 /** @defgroup HAL_Pin_remapping Pin remapping 106 * @{ 107 */ 108 /* Only available on cut2.0 */ 109 #define SYSCFG_REMAP_PA11 SYSCFG_CFGR1_PA11_RMP /*!< PA11 pad behaves digitally as PA9 GPIO pin */ 110 #define SYSCFG_REMAP_PA12 SYSCFG_CFGR1_PA12_RMP /*!< PA12 pad behaves digitally as PA10 GPIO pin */ 111 /** 112 * @} 113 */ 114 115 /** @defgroup HAL_IR_ENV_SEL IR Modulation Envelope signal selection 116 * @{ 117 */ 118 #define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< 00: Timer16 is selected as IR Modulation envelope source */ 119 #define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< 01: USART1 is selected as IR Modulation envelope source */ 120 #if defined(USART4) 121 #define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART4 is selected as IR Modulation envelope source */ 122 #else 123 #define HAL_SYSCFG_IRDA_ENV_SEL_USART2 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART2 is selected as IR Modulation envelope source */ 124 #endif /* USART4 */ 125 126 /** 127 * @} 128 */ 129 130 /** @defgroup HAL_IR_POL_SEL IR output polarity selection 131 * @{ 132 */ 133 #define HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED 0x00000000U /*!< 00: IR output polarity not inverted */ 134 #define HAL_SYSCFG_IRDA_POLARITY_INVERTED SYSCFG_CFGR1_IR_POL /*!< 01: IR output polarity inverted */ 135 136 /** 137 * @} 138 */ 139 140 #if defined(VREFBUF) 141 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale 142 * @{ 143 */ 144 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0x00000000U /*!< Voltage reference scale 0: VREF_OUT1 around 2.048 V. 145 This requires VDDA equal to or higher than 2.4 V. */ 146 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1: VREF_OUT1 around 2.5 V. 147 This requires VDDA equal to or higher than 2.8 V. */ 148 149 /** 150 * @} 151 */ 152 153 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance 154 * @{ 155 */ 156 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ 157 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 158 159 /** 160 * @} 161 */ 162 #endif /* VREFBUF */ 163 164 /** @defgroup SYSCFG_FastModePlus_GPIO Fast mode Plus on GPIO 165 * @{ 166 */ 167 168 /** @brief Fast mode Plus driving capability on a specific GPIO 169 */ 170 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast mode Plus on PB6 */ 171 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast mode Plus on PB7 */ 172 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast mode Plus on PB8 */ 173 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast mode Plus on PB9 */ 174 #define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP /*!< Enable Fast mode Plus on PA9 */ 175 #define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast mode Plus on PA10 */ 176 177 /** 178 * @} 179 */ 180 181 /** @defgroup SYSCFG_FastModePlus_I2Cx Fast mode Plus driving capability activation for I2Cx 182 * @{ 183 */ 184 185 /** @brief Fast mode Plus driving capability on a specific GPIO 186 */ 187 #define SYSCFG_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast mode Plus on I2C1 */ 188 #define SYSCFG_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast mode Plus on I2C2 */ 189 #if defined (I2C3) 190 #define SYSCFG_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast mode Plus on I2C3 */ 191 #endif /* I2C3 */ 192 193 /** 194 * @} 195 */ 196 #if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE) 197 /** @defgroup SYSCFG_UCPDx_STROBE SYSCFG Dead Battery feature configuration 198 * @{ 199 */ 200 #define SYSCFG_UCPD1_STROBE SYSCFG_CFGR1_UCPD1_STROBE /*!< UCPD1 Dead battery sw configuration */ 201 #define SYSCFG_UCPD2_STROBE SYSCFG_CFGR1_UCPD2_STROBE /*!< UCPD2 Dead battery sw configuration */ 202 /** 203 * @} 204 */ 205 #endif /* SYSCFG_CFGR1_UCPD1_STROBE) || SYSCFG_CFGR1_UCPD2_STROBE */ 206 207 /** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper 208 * @brief ISR Wrapper 209 * @{ 210 */ 211 #define HAL_SYSCFG_ITLINE0 0x00000000U /*!< Internal define for macro handling */ 212 #define HAL_SYSCFG_ITLINE1 0x00000001U /*!< Internal define for macro handling */ 213 #define HAL_SYSCFG_ITLINE2 0x00000002U /*!< Internal define for macro handling */ 214 #define HAL_SYSCFG_ITLINE3 0x00000003U /*!< Internal define for macro handling */ 215 #define HAL_SYSCFG_ITLINE4 0x00000004U /*!< Internal define for macro handling */ 216 #define HAL_SYSCFG_ITLINE5 0x00000005U /*!< Internal define for macro handling */ 217 #define HAL_SYSCFG_ITLINE6 0x00000006U /*!< Internal define for macro handling */ 218 #define HAL_SYSCFG_ITLINE7 0x00000007U /*!< Internal define for macro handling */ 219 #define HAL_SYSCFG_ITLINE8 0x00000008U /*!< Internal define for macro handling */ 220 #define HAL_SYSCFG_ITLINE9 0x00000009U /*!< Internal define for macro handling */ 221 #define HAL_SYSCFG_ITLINE10 0x0000000AU /*!< Internal define for macro handling */ 222 #define HAL_SYSCFG_ITLINE11 0x0000000BU /*!< Internal define for macro handling */ 223 #define HAL_SYSCFG_ITLINE12 0x0000000CU /*!< Internal define for macro handling */ 224 #define HAL_SYSCFG_ITLINE13 0x0000000DU /*!< Internal define for macro handling */ 225 #define HAL_SYSCFG_ITLINE14 0x0000000EU /*!< Internal define for macro handling */ 226 #define HAL_SYSCFG_ITLINE15 0x0000000FU /*!< Internal define for macro handling */ 227 #define HAL_SYSCFG_ITLINE16 0x00000010U /*!< Internal define for macro handling */ 228 #define HAL_SYSCFG_ITLINE17 0x00000011U /*!< Internal define for macro handling */ 229 #define HAL_SYSCFG_ITLINE18 0x00000012U /*!< Internal define for macro handling */ 230 #define HAL_SYSCFG_ITLINE19 0x00000013U /*!< Internal define for macro handling */ 231 #define HAL_SYSCFG_ITLINE20 0x00000014U /*!< Internal define for macro handling */ 232 #define HAL_SYSCFG_ITLINE21 0x00000015U /*!< Internal define for macro handling */ 233 #define HAL_SYSCFG_ITLINE22 0x00000016U /*!< Internal define for macro handling */ 234 #define HAL_SYSCFG_ITLINE23 0x00000017U /*!< Internal define for macro handling */ 235 #define HAL_SYSCFG_ITLINE24 0x00000018U /*!< Internal define for macro handling */ 236 #define HAL_SYSCFG_ITLINE25 0x00000019U /*!< Internal define for macro handling */ 237 #define HAL_SYSCFG_ITLINE26 0x0000001AU /*!< Internal define for macro handling */ 238 #define HAL_SYSCFG_ITLINE27 0x0000001BU /*!< Internal define for macro handling */ 239 #define HAL_SYSCFG_ITLINE28 0x0000001CU /*!< Internal define for macro handling */ 240 #define HAL_SYSCFG_ITLINE29 0x0000001DU /*!< Internal define for macro handling */ 241 #define HAL_SYSCFG_ITLINE30 0x0000001EU /*!< Internal define for macro handling */ 242 #define HAL_SYSCFG_ITLINE31 0x0000001FU /*!< Internal define for macro handling */ 243 244 #define HAL_ITLINE_WWDG ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG) /*!< WWDG has expired .... */ 245 #if defined (PWR_PVD_SUPPORT) 246 #define HAL_ITLINE_PVDOUT ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT) /*!< Power voltage detection Interrupt .... */ 247 #endif /* PWR_PVD_SUPPORT */ 248 #if defined (PWR_PVM_SUPPORT) 249 #define HAL_ITLINE_PVMOUT ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVMOUT) /*!< Power voltage monitor Interrupt .... */ 250 #endif /* PWR_PVM_SUPPORT */ 251 #define HAL_ITLINE_RTC ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC) /*!< RTC -> exti[19] Interrupt */ 252 #define HAL_ITLINE_TAMPER ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_TAMPER) /*!< TAMPER -> exti[21] interrupt .... */ 253 #define HAL_ITLINE_FLASH_ECC ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ECC) /*!< Flash ECC Interrupt */ 254 #define HAL_ITLINE_FLASH_ITF ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF) /*!< Flash ITF Interrupt */ 255 #define HAL_ITLINE_CLK_CTRL ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL) /*!< CLK Control Interrupt */ 256 #if defined (CRS) 257 #define HAL_ITLINE_CRS ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS) /*!< CRS Interrupt */ 258 #endif /*CRS */ 259 #define HAL_ITLINE_EXTI0 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0) /*!< External Interrupt 0 */ 260 #define HAL_ITLINE_EXTI1 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1) /*!< External Interrupt 1 */ 261 #define HAL_ITLINE_EXTI2 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2) /*!< External Interrupt 2 */ 262 #define HAL_ITLINE_EXTI3 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3) /*!< External Interrupt 3 */ 263 #define HAL_ITLINE_EXTI4 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4) /*!< EXTI4 Interrupt */ 264 #define HAL_ITLINE_EXTI5 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5) /*!< EXTI5 Interrupt */ 265 #define HAL_ITLINE_EXTI6 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6) /*!< EXTI6 Interrupt */ 266 #define HAL_ITLINE_EXTI7 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7) /*!< EXTI7 Interrupt */ 267 #define HAL_ITLINE_EXTI8 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8) /*!< EXTI8 Interrupt */ 268 #define HAL_ITLINE_EXTI9 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9) /*!< EXTI9 Interrupt */ 269 #define HAL_ITLINE_EXTI10 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10) /*!< EXTI10 Interrupt */ 270 #define HAL_ITLINE_EXTI11 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11) /*!< EXTI11 Interrupt */ 271 #define HAL_ITLINE_EXTI12 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12) /*!< EXTI12 Interrupt */ 272 #define HAL_ITLINE_EXTI13 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13) /*!< EXTI13 Interrupt */ 273 #define HAL_ITLINE_EXTI14 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14) /*!< EXTI14 Interrupt */ 274 #define HAL_ITLINE_EXTI15 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15) /*!< EXTI15 Interrupt */ 275 #if defined (UCPD1) 276 #define HAL_ITLINE_UCPD1 ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_UCPD1) /*!< UCPD1 Interrupt */ 277 #endif /* UCPD1 */ 278 #if defined (UCPD2) 279 #define HAL_ITLINE_UCPD2 ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_UCPD2) /*!< UCPD2 Interrupt */ 280 #endif /* UCPD2 */ 281 #if defined (STM32G0C1xx) || defined (STM32G0B1xx) || defined (STM32G0B0xx) 282 #define HAL_ITLINE_USB ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_USB) /*!< USB Interrupt */ 283 #endif /* STM32G0C1xx) || STM32G0B1xx) || STM32G0B0xx */ 284 #define HAL_ITLINE_DMA1_CH1 ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1) /*!< DMA1 Channel 1 Interrupt */ 285 #define HAL_ITLINE_DMA1_CH2 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2) /*!< DMA1 Channel 2 Interrupt */ 286 #define HAL_ITLINE_DMA1_CH3 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3) /*!< DMA1 Channel 3 Interrupt */ 287 #define HAL_ITLINE_DMAMUX1 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMAMUX1) /*!< DMAMUX1 Interrupt */ 288 #define HAL_ITLINE_DMA1_CH4 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4) /*!< DMA1 Channel 4 Interrupt */ 289 #define HAL_ITLINE_DMA1_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5) /*!< DMA1 Channel 5 Interrupt */ 290 #if defined(DMA1_Channel7) 291 #define HAL_ITLINE_DMA1_CH6 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6) /*!< DMA1 Channel 6 Interrupt */ 292 #define HAL_ITLINE_DMA1_CH7 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7) /*!< DMA1 Channel 7 Interrupt */ 293 #endif /* DMA1_Channel7 */ 294 #if defined (DMA2) 295 #define HAL_ITLINE_DMA2_CH1 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH1) /*!< DMA2 Channel 1 Interrupt */ 296 #define HAL_ITLINE_DMA2_CH2 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH2) /*!< DMA2 Channel 2 Interrupt */ 297 #define HAL_ITLINE_DMA2_CH3 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3) /*!< DMA2 Channel 3 Interrupt */ 298 #define HAL_ITLINE_DMA2_CH4 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4) /*!< DMA2 Channel 4 Interrupt */ 299 #define HAL_ITLINE_DMA2_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5) /*!< DMA2 Channel 5 Interrupt */ 300 #endif /* DMA2 */ 301 #define HAL_ITLINE_ADC ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC) /*!< ADC Interrupt */ 302 #if defined (COMP1) 303 #define HAL_ITLINE_COMP1 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1) /*!< COMP1 Interrupt -> exti[17] */ 304 #endif /* COMP1 */ 305 #if defined (COMP2) 306 #define HAL_ITLINE_COMP2 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2) /*!< COMP2 Interrupt -> exti[18] */ 307 #endif /* COMP2 */ 308 #if defined (COMP3) 309 #define HAL_ITLINE_COMP3 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP3) /*!< COMP3 Interrupt -> exti[1x] */ 310 #endif /* COMP3 */ 311 #define HAL_ITLINE_TIM1_BRK ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK) /*!< TIM1 BRK Interrupt */ 312 #define HAL_ITLINE_TIM1_UPD ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD) /*!< TIM1 UPD Interrupt */ 313 #define HAL_ITLINE_TIM1_TRG ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG) /*!< TIM1 TRG Interrupt */ 314 #define HAL_ITLINE_TIM1_CCU ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU) /*!< TIM1 CCU Interrupt */ 315 #define HAL_ITLINE_TIM1_CC ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC) /*!< TIM1 CC Interrupt */ 316 #if defined (TIM2) 317 #define HAL_ITLINE_TIM2 ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB) /*!< TIM2 Interrupt */ 318 #endif /* TIM2 */ 319 #define HAL_ITLINE_TIM3 ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB) /*!< TIM3 Interrupt */ 320 #if defined (TIM4) 321 #define HAL_ITLINE_TIM4 ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM4_GLB) /*!< TIM4 Interrupt */ 322 #endif /* TIM4 */ 323 #if defined(TIM6) 324 #define HAL_ITLINE_TIM6 ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB) /*!< TIM6 Interrupt */ 325 #endif /* TIM6 */ 326 #if defined(DAC1) 327 #define HAL_ITLINE_DAC ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC) /*!< DAC Interrupt */ 328 #endif /* DAC1 */ 329 #if defined(LPTIM1) 330 #define HAL_ITLINE_LPTIM1 ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_LPTIM1_GLB) /*!< LPTIM1 Interrupt -> exti[29] */ 331 #endif /* LPTIM1 */ 332 #if defined(TIM7) 333 #define HAL_ITLINE_TIM7 ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB) /*!< TIM7 Interrupt */ 334 #endif /* TIM7 */ 335 #if defined(LPTIM2) 336 #define HAL_ITLINE_LPTIM2 ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_LPTIM2_GLB) /*!< LPTIM2 Interrupt -> exti[30] */ 337 #endif /* LPTIM2 */ 338 #define HAL_ITLINE_TIM14 ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB) /*!< TIM14 Interrupt */ 339 #if defined(TIM15) 340 #define HAL_ITLINE_TIM15 ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB) /*!< TIM15 Interrupt */ 341 #endif /* TIM15 */ 342 #define HAL_ITLINE_TIM16 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB) /*!< TIM16 Interrupt */ 343 #if defined (FDCAN1) || defined (FDCAN2) 344 #define HAL_ITLINE_FDCAN1_IT0 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_FDCAN1_IT0) /*!< FDCAN1_IT0 Interrupt */ 345 #define HAL_ITLINE_FDCAN2_IT0 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_FDCAN2_IT0) /*!< FDCAN2_IT0 Interrupt */ 346 #endif /* FDCAN1 || FDCAN2 */ 347 #define HAL_ITLINE_TIM17 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB) /*!< TIM17 Interrupt */ 348 #if defined (FDCAN1) || defined (FDCAN2) 349 #define HAL_ITLINE_FDCAN1_IT1 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_FDCAN1_IT1) /*!< FDCAN1_IT1 Interrupt */ 350 #define HAL_ITLINE_FDCAN2_IT1 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_FDCAN2_IT1) /*!< FDCAN2_IT1 Interrupt */ 351 #endif /* FDCAN1 || FDCAN2 */ 352 #define HAL_ITLINE_I2C1 ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB) /*!< I2C1 Interrupt -> exti[23] */ 353 #define HAL_ITLINE_I2C2 ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB) /*!< I2C2 Interrupt -> exti[24] */ 354 #if defined (I2C3) 355 #define HAL_ITLINE_I2C3 ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C3_GLB) /*!< I2C3 Interrupt -> exti[22] */ 356 #endif /* I2C3 */ 357 #define HAL_ITLINE_SPI1 ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1) /*!< SPI1 Interrupt */ 358 #define HAL_ITLINE_SPI2 ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2) /*!< SPI2 Interrupt */ 359 #if defined (SPI3) 360 #define HAL_ITLINE_SPI3 ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI3) /*!< SPI3 Interrupt */ 361 #endif /* SPI3 */ 362 #define HAL_ITLINE_USART1 ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB) /*!< USART1 GLB Interrupt -> exti[25] */ 363 #define HAL_ITLINE_USART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB) /*!< USART2 GLB Interrupt -> exti[26] */ 364 #if defined (LPUART2) 365 #define HAL_ITLINE_LPUART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_LPUART2_GLB) /*!< LPUART2 GLB Interrupt -> exti[26] */ 366 #endif /* LPUART2 */ 367 #if defined(USART3) 368 #define HAL_ITLINE_USART3 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB) /*!< USART3 Interrupt .... */ 369 #endif /* USART3 */ 370 #if defined(USART4) 371 #define HAL_ITLINE_USART4 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB) /*!< USART4 Interrupt .... */ 372 #endif /* USART4 */ 373 #if defined (LPUART1) 374 #define HAL_ITLINE_LPUART1 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_LPUART1_GLB) /*!< LPUART1 Interrupt -> exti[28]*/ 375 #endif /* LPUART1 */ 376 #if defined (USART5) 377 #define HAL_ITLINE_USART5 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB) /*!< USART5 Interrupt .... */ 378 #endif /* USART5 */ 379 #if defined (USART6) 380 #define HAL_ITLINE_USART6 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB) /*!< USART6 Interrupt .... */ 381 #endif /* USART6 */ 382 #if defined (CEC) 383 #define HAL_ITLINE_CEC ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC) /*!< CEC Interrupt -> exti[27] */ 384 #endif /* CEC */ 385 #if defined (RNG) 386 #define HAL_ITLINE_RNG ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_RNG) /*!< RNG Interrupt */ 387 #endif /* RNG */ 388 #if defined (AES) 389 #define HAL_ITLINE_AES ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_AES) /*!< AES Interrupt */ 390 #endif /* AES */ 391 /** 392 * @} 393 */ 394 395 /** 396 * @} 397 */ 398 399 /** 400 * @} 401 */ 402 403 /* Exported macros -----------------------------------------------------------*/ 404 /** @defgroup HAL_Exported_Macros HAL Exported Macros 405 * @{ 406 */ 407 408 /** @defgroup DBG_Exported_Macros DBG Exported Macros 409 * @{ 410 */ 411 412 /** @brief Freeze and Unfreeze Peripherals in Debug mode 413 */ 414 #if defined(DBG_APB_FZ1_DBG_TIM2_STOP) 415 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP) 416 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP) 417 #endif /* DBG_APB_FZ1_DBG_TIM2_STOP */ 418 419 #if defined(DBG_APB_FZ1_DBG_TIM3_STOP) 420 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP) 421 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP) 422 #endif /* DBG_APB_FZ1_DBG_TIM3_STOP */ 423 424 #if defined(DBG_APB_FZ1_DBG_TIM4_STOP) 425 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM4_STOP) 426 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM4_STOP) 427 #endif /* DBG_APB_FZ1_DBG_TIM4_STOP */ 428 429 #if defined(DBG_APB_FZ1_DBG_TIM6_STOP) 430 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM6_STOP) 431 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM6_STOP) 432 #endif /* DBG_APB_FZ1_DBG_TIM6_STOP */ 433 434 #if defined(DBG_APB_FZ1_DBG_TIM7_STOP) 435 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM7_STOP) 436 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM7_STOP) 437 #endif /* DBG_APB_FZ1_DBG_TIM7_STOP */ 438 439 #if defined(DBG_APB_FZ1_DBG_RTC_STOP) 440 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP) 441 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP) 442 #endif /* DBG_APB_FZ1_DBG_RTC_STOP */ 443 444 #if defined(DBG_APB_FZ1_DBG_WWDG_STOP) 445 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP) 446 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP) 447 #endif /* DBG_APB_FZ1_DBG_WWDG_STOP */ 448 449 #if defined(DBG_APB_FZ1_DBG_IWDG_STOP) 450 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP) 451 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP) 452 #endif /* DBG_APB_FZ1_DBG_IWDG_STOP */ 453 454 #if defined(DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP) 455 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP) 456 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP) 457 #endif /* DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP */ 458 459 #if defined(DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP) 460 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP) 461 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP) 462 #endif /* DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP */ 463 464 #if defined(DBG_APB_FZ1_DBG_LPTIM1_STOP) 465 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM1_STOP) 466 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM1_STOP) 467 #endif /* DBG_APB_FZ1_DBG_LPTIM1_STOP */ 468 469 #if defined(DBG_APB_FZ1_DBG_LPTIM2_STOP) 470 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM2_STOP) 471 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM2_STOP) 472 #endif /* DBG_APB_FZ1_DBG_LPTIM2_STOP */ 473 474 #if defined(DBG_APB_FZ2_DBG_TIM1_STOP) 475 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP) 476 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP) 477 #endif /* DBG_APB_FZ2_DBG_TIM1_STOP */ 478 479 #if defined(DBG_APB_FZ2_DBG_TIM14_STOP) 480 #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP) 481 #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP) 482 #endif /* DBG_APB_FZ2_DBG_TIM14_STOP */ 483 484 #if defined(DBG_APB_FZ2_DBG_TIM15_STOP) 485 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP) 486 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP) 487 #endif /* DBG_APB_FZ2_DBG_TIM15_STOP */ 488 489 #if defined(DBG_APB_FZ2_DBG_TIM16_STOP) 490 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP) 491 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP) 492 #endif /* DBG_APB_FZ2_DBG_TIM16_STOP */ 493 494 #if defined(DBG_APB_FZ2_DBG_TIM17_STOP) 495 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP) 496 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP) 497 #endif /* DBG_APB_FZ2_DBG_TIM17_STOP */ 498 499 /** 500 * @} 501 */ 502 503 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 504 * @{ 505 */ 506 507 /** 508 * @brief ISR wrapper check 509 * @note Allow to determine interrupt source per line. 510 */ 511 #define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF)) 512 513 /** @brief Main Flash memory mapped at 0x00000000 514 */ 515 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE) 516 517 /** @brief System Flash memory mapped at 0x00000000 518 */ 519 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0) 520 521 /** @brief Embedded SRAM mapped at 0x00000000 522 */ 523 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() \ 524 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, (SYSCFG_CFGR1_MEM_MODE_1|SYSCFG_CFGR1_MEM_MODE_0)) 525 526 /** 527 * @brief Return the boot mode as configured by user. 528 * @retval The boot mode as configured by user. The returned value can be one 529 * of the following values @ref SYSCFG_BootMode 530 */ 531 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE) 532 533 /** @brief SYSCFG Break ECC lock. 534 * Enable and lock the connection of Flash ECC error connection to TIM1 Break input. 535 * @note The selected configuration is locked and can be unlocked only by system reset. 536 */ 537 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) 538 539 540 /** @brief SYSCFG Break Cortex-M0+ Lockup lock. 541 * Enables and locks the connection of Cortex-M0+ LOCKUP (Hardfault) output to TIM1/15/16/17 Break input 542 * @note The selected configuration is locked and can be unlocked only by system reset. 543 */ 544 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) 545 546 #if defined(SYSCFG_CFGR2_PVDL) 547 /** @brief SYSCFG Break PVD lock. 548 * Enables and locks the PVD connection with Timer1/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register 549 * @note The selected configuration is locked and can be unlocked only by system reset 550 */ 551 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) 552 #endif /* SYSCFG_CFGR2_PVDL */ 553 554 /** @brief SYSCFG Break SRAM PARITY lock 555 * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/15/16/17 556 * @note The selected configuration is locked and can only be unlocked by system reset 557 */ 558 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2,SYSCFG_CFGR2_SPL) 559 560 /** @brief Parity check on RAM disable macro 561 * @note Disabling the parity check on RAM locks the configuration bit. 562 * To re-enable the parity check on RAM perform a system reset. 563 */ 564 #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SPF) 565 566 /** @brief Set the PEF bit to clear the SRAM Parity Error Flag. 567 */ 568 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) 569 570 /** @brief Fast-mode Plus driving capability enable/disable macros 571 * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO 572 */ 573 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 574 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 575 }while(0U) 576 577 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 578 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 579 }while(0U) 580 581 #if defined(SYSCFG_CDEN_SUPPORT) 582 /** @brief Clamping Diode on specific pins enable/disable macros 583 * @param __PIN__ This parameter can be a combination of values @ref SYSCFG_ClampingDiode 584 */ 585 #define __HAL_SYSCFG_CLAMPINGDIODE_ENABLE(__PIN__) do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\ 586 SET_BIT(SYSCFG->CFGR2, (__PIN__));\ 587 }while(0U) 588 589 #define __HAL_SYSCFG_CLAMPINGDIODE_DISABLE(__PIN__) do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\ 590 CLEAR_BIT(SYSCFG->CFGR2, (__PIN__));\ 591 }while(0U) 592 #endif /* SYSCFG_CDEN_SUPPORT */ 593 594 /** @brief ISR wrapper check 595 * @note Allow to determine interrupt source per line. 596 */ 597 #define __HAL_SYSCFG_GET_PENDING_IT(__SOURCE__) \ 598 (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFFU)) 599 600 /** @brief selection of the modulation envelope signal macro, using bits [7:6] of SYSCFG_CFGR1 register 601 * @param __SOURCE__ This parameter can be a value of @ref HAL_IR_ENV_SEL 602 */ 603 #define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__)));\ 604 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD);\ 605 SET_BIT(SYSCFG->CFGR1, (__SOURCE__));\ 606 }while(0U) 607 608 #define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0U) 609 610 /** @brief IROut Polarity Selection, using bit[5] of SYSCFG_CFGR1 register 611 * @param __SEL__ This parameter can be a value of @ref HAL_IR_POL_SEL 612 */ 613 #define __HAL_SYSCFG_IRDA_OUT_POLARITY_SELECTION(__SEL__) do { assert_param(IS_HAL_SYSCFG_IRDA_POL_SEL((__SEL__)));\ 614 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL);\ 615 SET_BIT(SYSCFG->CFGR1,(__SEL__));\ 616 }while(0U) 617 618 /** 619 * @brief Return the IROut Polarity mode as configured by user. 620 * @retval The IROut polarity as configured by user. The returned value can be one 621 * of @ref HAL_IR_POL_SEL 622 */ 623 #define __HAL_SYSCFG_GET_POLARITY() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL) 624 625 /** @brief Break input to TIM1/15/16/17 capability enable/disable macros 626 * @param __BREAK__ This parameter can be a value of @ref SYSCFG_Break 627 */ 628 #define __HAL_SYSCFG_BREAK_ENABLE(__BREAK__) do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\ 629 SET_BIT(SYSCFG->CFGR2, (__BREAK__));\ 630 }while(0U) 631 632 #define __HAL_SYSCFG_BREAK_DISABLE(__BREAK__) do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\ 633 CLEAR_BIT(SYSCFG->CFGR2, (__BREAK__));\ 634 }while(0U) 635 636 637 /** 638 * @} 639 */ 640 641 /** 642 * @} 643 */ 644 645 /* Private macros ------------------------------------------------------------*/ 646 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros 647 * @{ 648 */ 649 #if defined (PWR_PVD_SUPPORT) 650 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_SP) || \ 651 ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ 652 ((__CONFIG__) == SYSCFG_BREAK_ECC) || \ 653 ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) 654 #else 655 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_SP) || \ 656 ((__CONFIG__) == SYSCFG_BREAK_ECC) || \ 657 ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) 658 #endif /* PWR_PVD_SUPPORT */ 659 660 #if defined(SYSCFG_CDEN_SUPPORT) 661 #define IS_SYSCFG_CLAMPINGDIODE(__PIN__) ((((__PIN__) & SYSCFG_CDEN_PA1) == SYSCFG_CDEN_PA1) || \ 662 (((__PIN__) & SYSCFG_CDEN_PA3) == SYSCFG_CDEN_PA3) || \ 663 (((__PIN__) & SYSCFG_CDEN_PA5) == SYSCFG_CDEN_PA5) || \ 664 (((__PIN__) & SYSCFG_CDEN_PA6) == SYSCFG_CDEN_PA6) || \ 665 (((__PIN__) & SYSCFG_CDEN_PA13) == SYSCFG_CDEN_PA13) || \ 666 (((__PIN__) & SYSCFG_CDEN_PB0) == SYSCFG_CDEN_PB0) || \ 667 (((__PIN__) & SYSCFG_CDEN_PB1) == SYSCFG_CDEN_PB1) || \ 668 (((__PIN__) & SYSCFG_CDEN_PB2) == SYSCFG_CDEN_PB2)) 669 #endif /* SYSCFG_CDEN_SUPPORT */ 670 671 #if defined (USART4) 672 #define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \ 673 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \ 674 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4)) 675 #else 676 #define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \ 677 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \ 678 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART2)) 679 #endif /* USART4 */ 680 #define IS_HAL_SYSCFG_IRDA_POL_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED) || \ 681 ((SEL) == HAL_SYSCFG_IRDA_POLARITY_INVERTED)) 682 683 #if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE) 684 #define IS_SYSCFG_DBATT_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_UCPD1_STROBE) || \ 685 ((__CONFIG__) == SYSCFG_UCPD2_STROBE) || \ 686 ((__CONFIG__) == (SYSCFG_UCPD1_STROBE | SYSCFG_UCPD2_STROBE))) 687 #endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */ 688 #if defined(VREFBUF) 689 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ 690 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1)) 691 692 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 693 ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) 694 695 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) 696 #endif /* VREFBUF */ 697 698 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \ 699 (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \ 700 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 701 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 702 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ 703 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 704 705 #define IS_HAL_REMAP_PIN(RMP) (((RMP) == SYSCFG_REMAP_PA11) || \ 706 ((RMP) == SYSCFG_REMAP_PA12) || \ 707 ((RMP) == (SYSCFG_REMAP_PA11 | SYSCFG_REMAP_PA12))) 708 /** 709 * @} 710 */ 711 712 /** @defgroup HAL_Private_Macros HAL Private Macros 713 * @{ 714 */ 715 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ 716 ((FREQ) == HAL_TICK_FREQ_100HZ) || \ 717 ((FREQ) == HAL_TICK_FREQ_1KHZ)) 718 /** 719 * @} 720 */ 721 /* Exported functions --------------------------------------------------------*/ 722 723 /** @defgroup HAL_Exported_Functions HAL Exported Functions 724 * @{ 725 */ 726 727 /** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions 728 * @{ 729 */ 730 731 /* Initialization and Configuration functions ******************************/ 732 HAL_StatusTypeDef HAL_Init(void); 733 HAL_StatusTypeDef HAL_DeInit(void); 734 void HAL_MspInit(void); 735 void HAL_MspDeInit(void); 736 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 737 738 /** 739 * @} 740 */ 741 742 /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions 743 * @{ 744 */ 745 746 /* Peripheral Control functions ************************************************/ 747 void HAL_IncTick(void); 748 void HAL_Delay(uint32_t Delay); 749 uint32_t HAL_GetTick(void); 750 uint32_t HAL_GetTickPrio(void); 751 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 752 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 753 void HAL_SuspendTick(void); 754 void HAL_ResumeTick(void); 755 uint32_t HAL_GetHalVersion(void); 756 uint32_t HAL_GetREVID(void); 757 uint32_t HAL_GetDEVID(void); 758 uint32_t HAL_GetUIDw0(void); 759 uint32_t HAL_GetUIDw1(void); 760 uint32_t HAL_GetUIDw2(void); 761 762 /** 763 * @} 764 */ 765 766 /** @defgroup HAL_Exported_Functions_Group3 DBGMCU Control functions 767 * @{ 768 */ 769 770 /* DBGMCU Peripheral Control functions *****************************************/ 771 void HAL_DBGMCU_EnableDBGStopMode(void); 772 void HAL_DBGMCU_DisableDBGStopMode(void); 773 void HAL_DBGMCU_EnableDBGStandbyMode(void); 774 void HAL_DBGMCU_DisableDBGStandbyMode(void); 775 776 /** 777 * @} 778 */ 779 780 /* Exported variables ---------------------------------------------------------*/ 781 /** @addtogroup HAL_Exported_Variables 782 * @{ 783 */ 784 extern __IO uint32_t uwTick; 785 extern uint32_t uwTickPrio; 786 extern HAL_TickFreqTypeDef uwTickFreq; 787 /** 788 * @} 789 */ 790 791 /** @defgroup HAL_Exported_Functions_Group4 SYSCFG configuration functions 792 * @{ 793 */ 794 795 /* SYSCFG Control functions ****************************************************/ 796 797 #if defined(VREFBUF) 798 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 799 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); 800 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 801 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); 802 void HAL_SYSCFG_DisableVREFBUF(void); 803 #endif /* VREFBUF */ 804 805 void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); 806 void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); 807 void HAL_SYSCFG_EnableRemap(uint32_t PinRemap); 808 void HAL_SYSCFG_DisableRemap(uint32_t PinRemap); 809 #if defined(SYSCFG_CDEN_SUPPORT) 810 void HAL_SYSCFG_EnableClampingDiode(uint32_t PinConfig); 811 void HAL_SYSCFG_DisableClampingDiode(uint32_t PinConfig); 812 #endif /* SYSCFG_CDEN_SUPPORT */ 813 #if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE) 814 void HAL_SYSCFG_StrobeDBattpinsConfig(uint32_t ConfigDeadBattery); 815 #endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */ 816 /** 817 * @} 818 */ 819 820 /** 821 * @} 822 */ 823 824 /** 825 * @} 826 */ 827 828 /** 829 * @} 830 */ 831 832 #ifdef __cplusplus 833 } 834 #endif 835 836 #endif /* STM32G0xx_HAL_H */ 837 838
