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Searched refs:GTZC_CFGR3_GPU2D_Pos (Results 1 – 7 of 7) sorted by relevance

/hal_stm32-3.6.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_gtzc.h285 #define GTZC_PERIPH_GPU2D (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GPU2D_Pos)
/hal_stm32-3.6.0/stm32cube/stm32u5xx/soc/
Dstm32u5f7xx.h22285 #define GTZC_CFGR3_GPU2D_Pos (23U) macro
22286 #define GTZC_CFGR3_GPU2D_Msk (0x01UL << GTZC_CFGR3_GPU2D_Pos)
22503 #define GTZC_TZSC1_SECCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
22655 #define GTZC_TZSC1_PRIVCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
22807 #define GTZC_TZIC1_IER3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
23025 #define GTZC_TZIC1_SR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
23243 #define GTZC_TZIC1_FCR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
Dstm32u599xx.h24466 #define GTZC_CFGR3_GPU2D_Pos (23U) macro
24467 #define GTZC_CFGR3_GPU2D_Msk (0x01UL << GTZC_CFGR3_GPU2D_Pos)
24678 #define GTZC_TZSC1_SECCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
24828 #define GTZC_TZSC1_PRIVCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
24978 #define GTZC_TZIC1_IER3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
25190 #define GTZC_TZIC1_SR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
25402 #define GTZC_TZIC1_FCR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
Dstm32u5g7xx.h22901 #define GTZC_CFGR3_GPU2D_Pos (23U) macro
22902 #define GTZC_CFGR3_GPU2D_Msk (0x01UL << GTZC_CFGR3_GPU2D_Pos)
23129 #define GTZC_TZSC1_SECCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
23287 #define GTZC_TZSC1_PRIVCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
23445 #define GTZC_TZIC1_IER3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
23673 #define GTZC_TZIC1_SR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
23901 #define GTZC_TZIC1_FCR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
Dstm32u5a9xx.h25082 #define GTZC_CFGR3_GPU2D_Pos (23U) macro
25083 #define GTZC_CFGR3_GPU2D_Msk (0x01UL << GTZC_CFGR3_GPU2D_Pos)
25304 #define GTZC_TZSC1_SECCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
25460 #define GTZC_TZSC1_PRIVCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
25616 #define GTZC_TZIC1_IER3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
25838 #define GTZC_TZIC1_SR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
26060 #define GTZC_TZIC1_FCR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
Dstm32u5f9xx.h25428 #define GTZC_CFGR3_GPU2D_Pos (23U) macro
25429 #define GTZC_CFGR3_GPU2D_Msk (0x01UL << GTZC_CFGR3_GPU2D_Pos)
25648 #define GTZC_TZSC1_SECCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
25802 #define GTZC_TZSC1_PRIVCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
25956 #define GTZC_TZIC1_IER3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
26176 #define GTZC_TZIC1_SR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
26396 #define GTZC_TZIC1_FCR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
Dstm32u5g9xx.h26044 #define GTZC_CFGR3_GPU2D_Pos (23U) macro
26045 #define GTZC_CFGR3_GPU2D_Msk (0x01UL << GTZC_CFGR3_GPU2D_Pos)
26274 #define GTZC_TZSC1_SECCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
26434 #define GTZC_TZSC1_PRIVCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
26594 #define GTZC_TZIC1_IER3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
26824 #define GTZC_TZIC1_SR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
27054 #define GTZC_TZIC1_FCR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos