Home
last modified time | relevance | path

Searched refs:GTZC_CFGR3_GFXMMU_REG_Pos (Results 1 – 7 of 7) sorted by relevance

/hal_stm32-3.6.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_gtzc.h289 #define GTZC_PERIPH_GFXMMU_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GFXMMU_REG_Pos)
/hal_stm32-3.6.0/stm32cube/stm32u5xx/soc/
Dstm32u5f7xx.h22289 #define GTZC_CFGR3_GFXMMU_REG_Pos (25U) macro
22290 #define GTZC_CFGR3_GFXMMU_REG_Msk (0x01UL << GTZC_CFGR3_GFXMMU_REG_Pos)
22507 #define GTZC_TZSC1_SECCFGR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
22659 #define GTZC_TZSC1_PRIVCFGR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
22811 #define GTZC_TZIC1_IER3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
23029 #define GTZC_TZIC1_SR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
23247 #define GTZC_TZIC1_FCR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
Dstm32u599xx.h24470 #define GTZC_CFGR3_GFXMMU_REG_Pos (25U) macro
24471 #define GTZC_CFGR3_GFXMMU_REG_Msk (0x01UL << GTZC_CFGR3_GFXMMU_REG_Pos)
24682 #define GTZC_TZSC1_SECCFGR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
24832 #define GTZC_TZSC1_PRIVCFGR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
24982 #define GTZC_TZIC1_IER3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
25194 #define GTZC_TZIC1_SR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
25406 #define GTZC_TZIC1_FCR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
Dstm32u5g7xx.h22905 #define GTZC_CFGR3_GFXMMU_REG_Pos (25U) macro
22906 #define GTZC_CFGR3_GFXMMU_REG_Msk (0x01UL << GTZC_CFGR3_GFXMMU_REG_Pos)
23133 #define GTZC_TZSC1_SECCFGR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
23291 #define GTZC_TZSC1_PRIVCFGR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
23449 #define GTZC_TZIC1_IER3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
23677 #define GTZC_TZIC1_SR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
23905 #define GTZC_TZIC1_FCR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
Dstm32u5a9xx.h25086 #define GTZC_CFGR3_GFXMMU_REG_Pos (25U) macro
25087 #define GTZC_CFGR3_GFXMMU_REG_Msk (0x01UL << GTZC_CFGR3_GFXMMU_REG_Pos)
25308 #define GTZC_TZSC1_SECCFGR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
25464 #define GTZC_TZSC1_PRIVCFGR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
25620 #define GTZC_TZIC1_IER3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
25842 #define GTZC_TZIC1_SR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
26064 #define GTZC_TZIC1_FCR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
Dstm32u5f9xx.h25432 #define GTZC_CFGR3_GFXMMU_REG_Pos (25U) macro
25433 #define GTZC_CFGR3_GFXMMU_REG_Msk (0x01UL << GTZC_CFGR3_GFXMMU_REG_Pos)
25652 #define GTZC_TZSC1_SECCFGR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
25806 #define GTZC_TZSC1_PRIVCFGR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
25960 #define GTZC_TZIC1_IER3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
26180 #define GTZC_TZIC1_SR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
26400 #define GTZC_TZIC1_FCR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
Dstm32u5g9xx.h26048 #define GTZC_CFGR3_GFXMMU_REG_Pos (25U) macro
26049 #define GTZC_CFGR3_GFXMMU_REG_Msk (0x01UL << GTZC_CFGR3_GFXMMU_REG_Pos)
26278 #define GTZC_TZSC1_SECCFGR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
26438 #define GTZC_TZSC1_PRIVCFGR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
26598 #define GTZC_TZIC1_IER3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
26828 #define GTZC_TZIC1_SR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos
27058 #define GTZC_TZIC1_FCR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos