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Searched refs:GTZC_CFGR2_TIM8_Pos (Results 1 – 20 of 20) sorted by relevance

/hal_stm32-3.6.0/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_hal_gtzc.h202 #define GTZC_PERIPH_TIM8 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM8_Pos)
/hal_stm32-3.6.0/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_hal_gtzc.h262 #define GTZC_PERIPH_TIM8 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM8_Pos)
/hal_stm32-3.6.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_gtzc.h225 #define GTZC_PERIPH_TIM8 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM8_Pos)
/hal_stm32-3.6.0/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h16471 #define GTZC_CFGR2_TIM8_Pos (0U) macro
16472 #define GTZC_CFGR2_TIM8_Msk ( 0x01UL << GTZC_CFGR2_TIM8_Pos )
16591 #define GTZC_TZSC_SECCFGR2_TIM8SEC_Pos GTZC_CFGR2_TIM8_Pos
16693 #define GTZC_TZSC_PRIVCFGR2_TIM8PRIV_Pos GTZC_CFGR2_TIM8_Pos
16815 #define GTZC_TZIC_IER2_TIM8IE_Pos GTZC_CFGR2_TIM8_Pos
16955 #define GTZC_TZIC_SR2_TIM8F_Pos GTZC_CFGR2_TIM8_Pos
17095 #define GTZC_TZIC_FCR2_TIM8FC_Pos GTZC_CFGR2_TIM8_Pos
Dstm32l562xx.h17216 #define GTZC_CFGR2_TIM8_Pos (0U) macro
17217 #define GTZC_CFGR2_TIM8_Msk ( 0x01UL << GTZC_CFGR2_TIM8_Pos )
17340 #define GTZC_TZSC_SECCFGR2_TIM8SEC_Pos GTZC_CFGR2_TIM8_Pos
17446 #define GTZC_TZSC_PRIVCFGR2_TIM8PRIV_Pos GTZC_CFGR2_TIM8_Pos
17574 #define GTZC_TZIC_IER2_TIM8IE_Pos GTZC_CFGR2_TIM8_Pos
17720 #define GTZC_TZIC_SR2_TIM8F_Pos GTZC_CFGR2_TIM8_Pos
17866 #define GTZC_TZIC_FCR2_TIM8FC_Pos GTZC_CFGR2_TIM8_Pos
/hal_stm32-3.6.0/stm32cube/stm32u5xx/soc/
Dstm32u535xx.h17888 #define GTZC_CFGR2_TIM8_Pos (2U) macro
17889 #define GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos)
18052 #define GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
18166 #define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
18280 #define GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
18442 #define GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
18604 #define GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
Dstm32u545xx.h18440 #define GTZC_CFGR2_TIM8_Pos (2U) macro
18441 #define GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos)
18612 #define GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
18732 #define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
18852 #define GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
19022 #define GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
19192 #define GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
Dstm32u575xx.h19455 #define GTZC_CFGR2_TIM8_Pos (2U) macro
19456 #define GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos)
19641 #define GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
19771 #define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
19901 #define GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
20087 #define GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
20273 #define GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
Dstm32u5f7xx.h22225 #define GTZC_CFGR2_TIM8_Pos (2U) macro
22226 #define GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos)
22443 #define GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
22595 #define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
22747 #define GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
22965 #define GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
23183 #define GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
Dstm32u595xx.h20632 #define GTZC_CFGR2_TIM8_Pos (2U) macro
20633 #define GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos)
20834 #define GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
20974 #define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
21114 #define GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
21316 #define GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
21518 #define GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
Dstm32u5a5xx.h21242 #define GTZC_CFGR2_TIM8_Pos (2U) macro
21243 #define GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos)
21454 #define GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
21600 #define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
21746 #define GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
21958 #define GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
22170 #define GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
Dstm32u585xx.h20065 #define GTZC_CFGR2_TIM8_Pos (2U) macro
20066 #define GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos)
20261 #define GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
20397 #define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
20533 #define GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
20729 #define GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
20925 #define GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
Dstm32u599xx.h24406 #define GTZC_CFGR2_TIM8_Pos (2U) macro
24407 #define GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos)
24618 #define GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
24768 #define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
24918 #define GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
25130 #define GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
25342 #define GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
Dstm32u5g7xx.h22835 #define GTZC_CFGR2_TIM8_Pos (2U) macro
22836 #define GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos)
23063 #define GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
23221 #define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
23379 #define GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
23607 #define GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
23835 #define GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
Dstm32u5a9xx.h25016 #define GTZC_CFGR2_TIM8_Pos (2U) macro
25017 #define GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos)
25238 #define GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
25394 #define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
25550 #define GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
25772 #define GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
25994 #define GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
Dstm32u5f9xx.h25366 #define GTZC_CFGR2_TIM8_Pos (2U) macro
25367 #define GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos)
25586 #define GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
25740 #define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
25894 #define GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
26114 #define GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
26334 #define GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
Dstm32u5g9xx.h25976 #define GTZC_CFGR2_TIM8_Pos (2U) macro
25977 #define GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos)
26206 #define GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
26366 #define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
26526 #define GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
26756 #define GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
26986 #define GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
/hal_stm32-3.6.0/stm32cube/stm32h5xx/soc/
Dstm32h562xx.h17070 #define GTZC_CFGR2_TIM8_Pos (10U) macro
17071 #define GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos)
17259 #define GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
17403 #define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
17547 #define GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
17736 #define GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
17924 #define GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
Dstm32h563xx.h19168 #define GTZC_CFGR2_TIM8_Pos (10U) macro
19169 #define GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos)
19363 #define GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
19513 #define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
19663 #define GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
19858 #define GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
20052 #define GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
Dstm32h573xx.h19749 #define GTZC_CFGR2_TIM8_Pos (10U) macro
19750 #define GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos)
19952 #define GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
20108 #define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
20264 #define GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
20467 #define GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos
20669 #define GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos