Searched refs:FSMC_BWTR2_ADDSET_Pos (Results 1 – 13 of 13) sorted by relevance
7056 #define FSMC_BWTR2_ADDSET_Pos (0U) macro7057 #define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */7059 #define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */7060 #define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */7061 #define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */7062 #define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
7356 #define FSMC_BWTR2_ADDSET_Pos (0U) macro7357 #define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */7359 #define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */7360 #define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */7361 #define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */7362 #define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
7174 #define FSMC_BWTR2_ADDSET_Pos (0U) macro7175 #define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */7177 #define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */7178 #define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */7179 #define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */7180 #define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
7494 #define FSMC_BWTR2_ADDSET_Pos (0U) macro7495 #define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */7497 #define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */7498 #define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */7499 #define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */7500 #define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
7170 #define FSMC_BWTR2_ADDSET_Pos (0U) macro7171 #define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */7173 #define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */7174 #define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */7175 #define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */7176 #define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
7530 #define FSMC_BWTR2_ADDSET_Pos (0U) macro7531 #define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */7533 #define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */7534 #define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */7535 #define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */7536 #define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
7168 #define FSMC_BWTR2_ADDSET_Pos (0U) macro7169 #define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */7171 #define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */7172 #define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */7173 #define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */7174 #define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
7238 #define FSMC_BWTR2_ADDSET_Pos (0U) macro7239 #define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */7241 #define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */7242 #define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */7243 #define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */7244 #define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
7535 #define FSMC_BWTR2_ADDSET_Pos (0U) macro7536 #define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */7538 #define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */7539 #define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */7540 #define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */7541 #define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
7162 #define FSMC_BWTR2_ADDSET_Pos (0U) macro7163 #define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */7165 #define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */7166 #define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */7167 #define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */7168 #define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
7012 #define FSMC_BWTR2_ADDSET_Pos (0U) macro7013 #define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */7015 #define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */7016 #define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */7017 #define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */7018 #define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
7461 #define FSMC_BWTR2_ADDSET_Pos (0U) macro7462 #define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */7464 #define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */7465 #define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */7466 #define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */7467 #define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
7311 #define FSMC_BWTR2_ADDSET_Pos (0U) macro7312 #define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */7314 #define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */7315 #define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */7316 #define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */7317 #define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
