Searched refs:FSMC_BTR3_ADDSET_Pos (Results 1 – 13 of 13) sorted by relevance
6895 #define FSMC_BTR3_ADDSET_Pos (0U) macro6896 #define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */6898 #define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */6899 #define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */6900 #define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */6901 #define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
7195 #define FSMC_BTR3_ADDSET_Pos (0U) macro7196 #define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */7198 #define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */7199 #define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */7200 #define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */7201 #define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
7013 #define FSMC_BTR3_ADDSET_Pos (0U) macro7014 #define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */7016 #define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */7017 #define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */7018 #define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */7019 #define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
7333 #define FSMC_BTR3_ADDSET_Pos (0U) macro7334 #define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */7336 #define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */7337 #define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */7338 #define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */7339 #define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
7009 #define FSMC_BTR3_ADDSET_Pos (0U) macro7010 #define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */7012 #define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */7013 #define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */7014 #define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */7015 #define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
7369 #define FSMC_BTR3_ADDSET_Pos (0U) macro7370 #define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */7372 #define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */7373 #define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */7374 #define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */7375 #define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
7007 #define FSMC_BTR3_ADDSET_Pos (0U) macro7008 #define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */7010 #define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */7011 #define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */7012 #define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */7013 #define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
7077 #define FSMC_BTR3_ADDSET_Pos (0U) macro7078 #define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */7080 #define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */7081 #define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */7082 #define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */7083 #define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
7374 #define FSMC_BTR3_ADDSET_Pos (0U) macro7375 #define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */7377 #define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */7378 #define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */7379 #define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */7380 #define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
7001 #define FSMC_BTR3_ADDSET_Pos (0U) macro7002 #define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */7004 #define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */7005 #define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */7006 #define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */7007 #define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
6851 #define FSMC_BTR3_ADDSET_Pos (0U) macro6852 #define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */6854 #define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */6855 #define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */6856 #define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */6857 #define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
7300 #define FSMC_BTR3_ADDSET_Pos (0U) macro7301 #define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */7303 #define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */7304 #define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */7305 #define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */7306 #define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
7150 #define FSMC_BTR3_ADDSET_Pos (0U) macro7151 #define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */7153 #define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */7154 #define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */7155 #define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */7156 #define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
