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Searched refs:ADC_CSR_AWD3_Pos (Results 1 – 25 of 29) sorted by relevance

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/hal_stm32-3.6.0/stm32cube/stm32f4xx/soc/
Dstm32f405xx.h1590 #define ADC_CSR_AWD3_Pos (16U) macro
1591 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
Dstm32f407xx.h1694 #define ADC_CSR_AWD3_Pos (16U) macro
1695 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
Dstm32f415xx.h1664 #define ADC_CSR_AWD3_Pos (16U) macro
1665 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
Dstm32f427xx.h1788 #define ADC_CSR_AWD3_Pos (16U) macro
1789 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
Dstm32f417xx.h1768 #define ADC_CSR_AWD3_Pos (16U) macro
1769 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
Dstm32f446xx.h1711 #define ADC_CSR_AWD3_Pos (16U) macro
1712 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
Dstm32f437xx.h1866 #define ADC_CSR_AWD3_Pos (16U) macro
1867 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
Dstm32f439xx.h1920 #define ADC_CSR_AWD3_Pos (16U) macro
1921 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
Dstm32f429xx.h1844 #define ADC_CSR_AWD3_Pos (16U) macro
1845 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
/hal_stm32-3.6.0/stm32cube/stm32f2xx/soc/
Dstm32f215xx.h1642 #define ADC_CSR_AWD3_Pos (16U) macro
1643 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
Dstm32f205xx.h1592 #define ADC_CSR_AWD3_Pos (16U) macro
1593 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
Dstm32f217xx.h1746 #define ADC_CSR_AWD3_Pos (16U) macro
1747 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
Dstm32f207xx.h1696 #define ADC_CSR_AWD3_Pos (16U) macro
1697 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
/hal_stm32-3.6.0/stm32cube/stm32f7xx/soc/
Dstm32f722xx.h1704 #define ADC_CSR_AWD3_Pos (16U) macro
1705 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
Dstm32f723xx.h1720 #define ADC_CSR_AWD3_Pos (16U) macro
1721 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
Dstm32f733xx.h1754 #define ADC_CSR_AWD3_Pos (16U) macro
1755 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
Dstm32f730xx.h1754 #define ADC_CSR_AWD3_Pos (16U) macro
1755 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
Dstm32f732xx.h1738 #define ADC_CSR_AWD3_Pos (16U) macro
1739 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
Dstm32f746xx.h1942 #define ADC_CSR_AWD3_Pos (16U) macro
1943 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
Dstm32f745xx.h1887 #define ADC_CSR_AWD3_Pos (16U) macro
1888 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
Dstm32f765xx.h2044 #define ADC_CSR_AWD3_Pos (16U) macro
2045 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
Dstm32f750xx.h2017 #define ADC_CSR_AWD3_Pos (16U) macro
2018 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
Dstm32f756xx.h2017 #define ADC_CSR_AWD3_Pos (16U) macro
2018 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
Dstm32f767xx.h2138 #define ADC_CSR_AWD3_Pos (16U) macro
2139 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
Dstm32f777xx.h2213 #define ADC_CSR_AWD3_Pos (16U) macro
2214 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */

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