1 /*
2 * Copyright (c) 2022 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/ztest.h>
8 #include <soc.h>
9 #include <zephyr/drivers/clock_control.h>
10 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
11 #include <zephyr/logging/log.h>
12
13 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lptim1))
14
15 #undef DT_DRV_COMPAT
16 #define DT_DRV_COMPAT st_stm32_lptim
17
18 #if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
19 #define STM32_LPTIM_OPT_CLOCK_SUPPORT 1
20 #else
21 #define STM32_LPTIM_OPT_CLOCK_SUPPORT 0
22 #endif
23
ZTEST(stm32_common_devices_clocks,test_lptim_clk_config)24 ZTEST(stm32_common_devices_clocks, test_lptim_clk_config)
25 {
26 static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(lptim1));
27
28 uint32_t dev_dt_clk_freq, dev_actual_clk_freq;
29 uint32_t dev_actual_clk_src;
30 int r;
31
32 /* Test clock_on(gating clock) */
33 r = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
34 (clock_control_subsys_t) &pclken[0]);
35 zassert_true((r == 0), "Could not enable LPTIM gating clock");
36
37 zassert_true(__HAL_RCC_LPTIM1_IS_CLK_ENABLED(), "LPTIM1 gating clock should be on");
38 TC_PRINT("LPTIM1 gating clock on\n");
39
40 if (IS_ENABLED(STM32_LPTIM_OPT_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(lptim1)) > 1) {
41 /* Test clock_on(domain_clk) */
42 r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
43 (clock_control_subsys_t) &pclken[1],
44 NULL);
45 zassert_true((r == 0), "Could not enable LPTIM1 domain clock");
46 TC_PRINT("LPTIM1 source clock configured\n");
47
48 /* Test clock source */
49 dev_actual_clk_src = __HAL_RCC_GET_LPTIM1_SOURCE();
50
51 if (pclken[1].bus == STM32_SRC_LSE) {
52 zassert_equal(dev_actual_clk_src, RCC_LPTIM1CLKSOURCE_LSE,
53 "Expected LPTIM1 src: LSE (0x%lx). Actual LPTIM1 src: 0x%x",
54 RCC_LPTIM1CLKSOURCE_LSE, dev_actual_clk_src);
55 } else if (pclken[1].bus == STM32_SRC_LSI) {
56 zassert_equal(dev_actual_clk_src, RCC_LPTIM1CLKSOURCE_LSI,
57 "Expected LPTIM1 src: LSI (0x%lx). Actual LPTIM1 src: 0x%x",
58 RCC_LPTIM1CLKSOURCE_LSI, dev_actual_clk_src);
59 } else {
60 zassert_true(0, "Unexpected domain clk (%d)", dev_actual_clk_src);
61 }
62
63 /* Test get_rate(srce clk) */
64 r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
65 (clock_control_subsys_t) &pclken[1],
66 &dev_dt_clk_freq);
67 zassert_true((r == 0), "Could not get LPTIM1 clk srce freq");
68
69 dev_actual_clk_freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_LPTIM1);
70 zassert_equal(dev_dt_clk_freq, dev_actual_clk_freq,
71 "Expected DT freq: %d Hz. Actual freq: %d Hz",
72 dev_dt_clk_freq, dev_actual_clk_freq);
73
74 TC_PRINT("LPTIM1 clock source rate: %d Hz\n", dev_dt_clk_freq);
75 } else {
76 zassert_true((DT_NUM_CLOCKS(DT_NODELABEL(lptim1)) == 1), "test config issue");
77 /* No domain clock available, get rate from gating clock */
78
79 /* Test get_rate */
80 r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
81 (clock_control_subsys_t) &pclken[0],
82 &dev_dt_clk_freq);
83 zassert_true((r == 0), "Could not get LPTIM1 clk freq");
84
85 dev_actual_clk_freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_LPTIM1);
86 zassert_equal(dev_dt_clk_freq, dev_actual_clk_freq,
87 "Expected DT freq: %d Hz. Actual freq: %d Hz",
88 dev_dt_clk_freq, dev_actual_clk_freq);
89
90 TC_PRINT("LPTIM1 clock source rate: %d Hz\n", dev_dt_clk_freq);
91 }
92
93 /* Test clock_off(reg_clk) */
94 r = clock_control_off(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
95 (clock_control_subsys_t) &pclken[0]);
96 zassert_true((r == 0), "Could not disable LPTIM1 gating clk");
97
98 zassert_true(!__HAL_RCC_LPTIM1_IS_CLK_ENABLED(), "LPTIM1 gating clk should be off");
99 TC_PRINT("LPTIM1 gating clk off\n");
100
101 /* Test clock_off(domain clk) */
102 /* Not supported today */
103 }
104 #endif
105
