1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_gtzc.c
4 * @author MCD Application Team
5 * @brief GTZC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of GTZC peripheral:
8 * + TZSC Initialization and Configuration functions
9 * + TZSC-MPCWM Initialization and Configuration functions
10 * + MPCBB Initialization and Configuration functions
11 * + TZSC, TZSC-MPCWM and MPCBB Lock functions
12 * + TZIC Initialization and Configuration functions
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2021 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### GTZC main features #####
28 ==============================================================================
29 [..]
30 (+) Global TrustZone Controller (GTZC) composed of three sub-blocks:
31 (++) TZSC: TrustZone security controller
32 This sub-block defines the secure/privileged state of master and slave
33 peripherals. It also controls the secure/privileged state of subregions
34 for the watermark memory peripheral controller (MPCWM).
35 (++) MPCBB: Block-Based memory protection controller
36 This sub-block defines the secure/privileged state of all blocks
37 (512-byte pages) of the associated SRAM.
38 (++) TZIC: TrustZone illegal access controller
39 This sub-block gathers all illegal access events in the system and
40 generates a secure interrupt towards NVIC.
41
42 (+) These sub-blocks are used to configure TrustZone system security in
43 a product having bus agents with programmable-security and privileged
44 attributes (securable) such as:
45 (++) on-chip RAM with programmable secure and/or privilege blocks (pages)
46 (++) AHB and APB peripherals with programmable security and/or privilege access
47 (++) AHB master granted as secure and/or privilege
48 (++) off-chip memories with secure and/or privilege areas
49
50 [..]
51 (+) TZIC accessible only with secure privileged transactions.
52 (+) Secure and non-secure access supported for privileged and unprivileged
53 part of TZSC and MPCBB
54 (+) Set of registers to define product security settings:
55 (++) Secure and privilege blocks for internal memories
56 (++) Secure and privilege regions for external memories
57 (++) Secure and privileged access mode for securable peripherals
58
59 ==============================================================================
60 ##### How to use this driver #####
61 ==============================================================================
62 [..]
63 The GTZC HAL driver can be used as follows:
64
65 (#) Configure or get back securable peripherals attributes using
66 HAL_GTZC_TZSC_ConfigPeriphAttributes() / HAL_GTZC_TZSC_GetConfigPeriphAttributes()
67
68 (#) Configure or get back MPCWM memories attributes using
69 HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes() / HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes()
70
71 (#) Lock TZSC sub-block or get lock status using HAL_GTZC_TZSC_Lock() /
72 HAL_GTZC_TZSC_GetLock()
73
74 (#) Configure or get back MPCBB memories complete configuration using
75 HAL_GTZC_MPCBB_ConfigMem() / HAL_GTZC_MPCBB_GetConfigMem()
76
77 (#) Configure or get back MPCBB memories attributes using
78 HAL_GTZC_MPCBB_ConfigMemAttributes() / HAL_GTZC_MPCBB_GetConfigMemAttributes()
79
80 (#) Lock MPCBB configuration or get lock status using HAL_GTZC_MPCBB_Lock() /
81 HAL_GTZC_MPCBB_GetLock()
82
83 (#) Lock MPCBB super-blocks or get lock status using HAL_GTZC_MPCBB_LockConfig() /
84 HAL_GTZC_MPCBB_GetLockConfig()
85
86 (#) Illegal access detection can be configured through TZIC sub-block using
87 following functions: HAL_GTZC_TZIC_DisableIT() / HAL_GTZC_TZIC_EnableIT()
88
89 (#) Illegal access flags can be retrieved through HAL_GTZC_TZIC_GetFlag() and
90 HAL_GTZC_TZIC_ClearFlag() functions
91
92 (#) Illegal access interrupt service routines are served by HAL_GTZC_IRQHandler()
93 and user can add his own code using HAL_GTZC_TZIC_Callback()
94
95 @endverbatim
96 ******************************************************************************
97 */
98
99 /* Includes ------------------------------------------------------------------*/
100 #include "stm32u5xx_hal.h"
101
102 /** @addtogroup STM32U5xx_HAL_Driver
103 * @{
104 */
105
106 /** @defgroup GTZC GTZC
107 * @brief GTZC HAL module driver
108 * @{
109 */
110
111 #ifdef HAL_GTZC_MODULE_ENABLED
112
113 /* Private typedef -----------------------------------------------------------*/
114 /* Private constants ---------------------------------------------------------*/
115
116 /** @defgroup GTZC_Private_Constants GTZC Private Constants
117 * @{
118 */
119
120 /* Definitions for TZSC_MPCWM */
121 #define TZSC_MPCWM1_MEM_SIZE 0x10000000U /* 256MB max size */
122 #define TZSC_MPCWM2_MEM_SIZE 0x10000000U /* 256MB max size */
123 #define TZSC_MPCWM3_MEM_SIZE 0x10000000U /* 256MB max size */
124 #define TZSC_MPCWM4_MEM_SIZE 0x00000800U /* 2KB max size */
125 #define TZSC_MPCWM5_MEM_SIZE 0x10000000U /* 256MB max size */
126 #if defined (HSPI1)
127 #define TZSC_MPCWM6_MEM_SIZE 0x10000000U /* 256MB max size */
128 #endif /* HSPI1 */
129
130 /* Definitions for GTZC TZSC & TZIC ALL register values */
131 /* TZSC1 / TZIC1 instances */
132 #if defined(STM32U599xx) || defined(STM32U595xx) || defined(STM32U5A9xx) || defined (STM32U5A5xx)
133 #define TZSC1_SECCFGR1_ALL (0x00EFFFFFUL)
134 #define TZSC1_SECCFGR2_ALL (0x000007FFUL)
135 #define TZSC1_SECCFGR3_ALL (0x0FFFFFFFUL)
136
137 #define TZSC1_PRIVCFGR1_ALL (0x00EFFFFFUL)
138 #define TZSC1_PRIVCFGR2_ALL (0x000007FFUL)
139 #define TZSC1_PRIVCFGR3_ALL (0x0FFFFFFFUL)
140
141 #define TZIC1_IER1_ALL (0x00EFFFFFUL)
142 #define TZIC1_IER2_ALL (0x000007FFUL)
143 #define TZIC1_IER3_ALL (0x0FFFFFFFUL)
144 #define TZIC1_IER4_ALL (0xFF1FC01FUL)
145
146 #define TZIC1_FCR1_ALL (0x00EFFFFFUL)
147 #define TZIC1_FCR2_ALL (0x000007FFUL)
148 #define TZIC1_FCR3_ALL (0x0FFFFFFFUL)
149 #define TZIC1_FCR4_ALL (0xFF1FC01FUL)
150
151 #elif defined(STM32U5F9xx) || defined(STM32U5G9xx)
152 #define TZSC1_SECCFGR1_ALL (0x00EFFFFFUL)
153 #define TZSC1_SECCFGR2_ALL (0x00000FFFUL)
154 #define TZSC1_SECCFGR3_ALL (0x1FFFFFFFUL)
155
156 #define TZSC1_PRIVCFGR1_ALL (0x00EFFFFFUL)
157 #define TZSC1_PRIVCFGR2_ALL (0x00000FFFUL)
158 #define TZSC1_PRIVCFGR3_ALL (0x1FFFFFFFUL)
159
160 #define TZIC1_IER1_ALL (0x00EFFFFFUL)
161 #define TZIC1_IER2_ALL (0x00000FFFUL)
162 #define TZIC1_IER3_ALL (0x1FFFFFFFUL)
163 #define TZIC1_IER4_ALL (0xFFDFC01FUL)
164
165 #define TZIC1_FCR1_ALL (0x00EFFFFFUL)
166 #define TZIC1_FCR2_ALL (0x00000FFFUL)
167 #define TZIC1_FCR3_ALL (0x1FFFFFFFUL)
168 #define TZIC1_FCR4_ALL (0xFFDFC01FUL)
169 #else
170 #define TZSC1_SECCFGR1_ALL (0x000FFFFFUL)
171 #define TZSC1_SECCFGR2_ALL (0x000001FFUL)
172 #define TZSC1_SECCFGR3_ALL (0x007FFFFFUL)
173
174 #define TZSC1_PRIVCFGR1_ALL (0x000FFFFFUL)
175 #define TZSC1_PRIVCFGR2_ALL (0x000001FFUL)
176 #define TZSC1_PRIVCFGR3_ALL (0x007FFFFFUL)
177
178 #define TZIC1_IER1_ALL (0x000FFFFFUL)
179 #define TZIC1_IER2_ALL (0x000001FFUL)
180 #define TZIC1_IER3_ALL (0x007FFFFFUL)
181 #define TZIC1_IER4_ALL (0x3F0FC01FUL)
182
183 #define TZIC1_FCR1_ALL (0x000FFFFFUL)
184 #define TZIC1_FCR2_ALL (0x000001FFUL)
185 #define TZIC1_FCR3_ALL (0x007FFFFFUL)
186 #define TZIC1_FCR4_ALL (0x3F0FC01FUL)
187 #endif /* STM32U599xx || STM32U595xx || STM32U5A9xx || STM32U5A5xx */
188
189 /* TZSC2 / TZIC2 instances */
190 #define TZSC2_SECCFGR1_ALL (0x00001BFFUL)
191
192 #define TZSC2_PRIVCFGR1_ALL (0x00001BFFUL)
193
194 #define TZIC2_IER1_ALL (0x00001BFFUL)
195 #define TZIC2_IER2_ALL (0x0300C07FUL)
196
197 #define TZIC2_FCR1_ALL (0x00001BFFUL)
198 #define TZIC2_FCR2_ALL (0x0300C07FUL)
199
200 #define REG_SIZE 32U
201 /**
202 * @}
203 */
204
205 /* Private macros ------------------------------------------------------------*/
206
207 /** @defgroup GTZC_Private_Macros GTZC Private Macros
208 * @{
209 */
210
211 #define IS_ADDRESS_IN(mem, address) \
212 ( ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
213 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) \
214 || ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
215 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) )
216
217 #define IS_ADDRESS_IN_S(mem, address) \
218 ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
219 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
220
221 #define IS_ADDRESS_IN_NS(mem, address) \
222 ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
223 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
224
225 #define GTZC_BASE_ADDRESS(mem)\
226 ( mem ## _BASE )
227
228 /**
229 * @}
230 */
231
232 /* Private variables ---------------------------------------------------------*/
233 /* Private function prototypes -----------------------------------------------*/
234 /* Exported functions --------------------------------------------------------*/
235
236 /** @defgroup GTZC_Exported_Functions GTZC Exported Functions
237 * @{
238 */
239
240 /** @defgroup GTZC_Exported_Functions_Group1 TZSC Configuration functions
241 * @brief TZSC Configuration functions
242 *
243 @verbatim
244 ==============================================================================
245 ##### TZSC Configuration functions #####
246 ==============================================================================
247 [..]
248 This section provides functions allowing to configure TZSC
249 TZSC: TrustZone Security Controller
250 @endverbatim
251 * @{
252 */
253
254 /**
255 * @brief Configure TZSC on a single peripheral or on all peripherals.
256 * @note Secure and non-secure attributes can only be set from the secure
257 * state when the system implements the security (TZEN=1).
258 * @note Privilege and non-privilege attributes can only be set from the
259 * privilege state when TZEN=0 or TZEN=1
260 * @note Security and privilege attributes can be set independently.
261 * @note Default state is non-secure and unprivileged access allowed.
262 * @param PeriphId Peripheral identifier
263 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
264 * Use GTZC_PERIPH_ALL to select all peripherals.
265 * @param PeriphAttributes Peripheral attributes, see @ref GTZC_TZSC_PeriphAttributes.
266 * @retval HAL status.
267 */
HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,uint32_t PeriphAttributes)268 HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,
269 uint32_t PeriphAttributes)
270 {
271 uint32_t register_address;
272
273 /* check entry parameters */
274 if ((PeriphAttributes > (GTZC_TZSC_PERIPH_SEC | GTZC_TZSC_PERIPH_PRIV))
275 || (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
276 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
277 && (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) != 0U)))
278 {
279 return HAL_ERROR;
280 }
281
282 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
283 {
284 /* special case where same attributes are applied to all peripherals */
285
286 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
287 /* secure configuration */
288 if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC)
289 {
290 SET_BIT(GTZC_TZSC1->SECCFGR1, TZSC1_SECCFGR1_ALL);
291 SET_BIT(GTZC_TZSC1->SECCFGR2, TZSC1_SECCFGR2_ALL);
292 SET_BIT(GTZC_TZSC1->SECCFGR3, TZSC1_SECCFGR3_ALL);
293 SET_BIT(GTZC_TZSC2->SECCFGR1, TZSC2_SECCFGR1_ALL);
294 }
295 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC)
296 {
297 CLEAR_BIT(GTZC_TZSC1->SECCFGR1, TZSC1_SECCFGR1_ALL);
298 CLEAR_BIT(GTZC_TZSC1->SECCFGR2, TZSC1_SECCFGR2_ALL);
299 CLEAR_BIT(GTZC_TZSC1->SECCFGR3, TZSC1_SECCFGR3_ALL);
300 CLEAR_BIT(GTZC_TZSC2->SECCFGR1, TZSC2_SECCFGR1_ALL);
301 }
302 else
303 {
304 /* do nothing */
305 }
306 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
307
308 /* privilege configuration */
309 if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV)
310 {
311 SET_BIT(GTZC_TZSC1->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL);
312 SET_BIT(GTZC_TZSC1->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL);
313 SET_BIT(GTZC_TZSC1->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL);
314 SET_BIT(GTZC_TZSC2->PRIVCFGR1, TZSC2_PRIVCFGR1_ALL);
315 }
316 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV)
317 {
318 CLEAR_BIT(GTZC_TZSC1->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL);
319 CLEAR_BIT(GTZC_TZSC1->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL);
320 CLEAR_BIT(GTZC_TZSC1->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL);
321 CLEAR_BIT(GTZC_TZSC2->PRIVCFGR1, TZSC2_PRIVCFGR1_ALL);
322 }
323 else
324 {
325 /* do nothing */
326 }
327 }
328 else
329 {
330 /* common case where only one peripheral is configured */
331
332 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
333 /* secure configuration */
334 register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->SECCFGR1)
335 + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
336 if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC)
337 {
338 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
339 }
340 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC)
341 {
342 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
343 }
344 else
345 {
346 /* do nothing */
347 }
348 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
349
350 /* privilege configuration */
351 register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->PRIVCFGR1)
352 + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
353 if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV)
354 {
355 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
356 }
357 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV)
358 {
359 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
360 }
361 else
362 {
363 /* do nothing */
364 }
365 }
366 return HAL_OK;
367 }
368
369 /**
370 * @brief Get TZSC configuration on a single peripheral or on all peripherals.
371 * @param PeriphId Peripheral identifier.
372 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
373 * Use GTZC_PERIPH_ALL to select all peripherals.
374 * @param PeriphAttributes Peripheral attribute pointer.
375 * This parameter can be a value of @ref GTZC_TZSC_PeriphAttributes.
376 * If PeriphId target a single peripheral, pointer on a single element.
377 * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array of
378 * GTZC_TZSC_PERIPH_NUMBER elements is to be provided.
379 * @retval HAL status.
380 */
HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,uint32_t * PeriphAttributes)381 HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,
382 uint32_t *PeriphAttributes)
383 {
384 uint32_t i;
385 uint32_t reg_value;
386 uint32_t register_address;
387
388 /* check entry parameters */
389 if ((PeriphAttributes == NULL)
390 || (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
391 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
392 && (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) != 0U)))
393 {
394 return HAL_ERROR;
395 }
396
397 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
398 {
399 /* get secure configuration: read each register and deploy each bit value
400 * of corresponding index in the destination array
401 */
402 reg_value = READ_REG(GTZC_TZSC1->SECCFGR1);
403 for (i = 0U; i < 32U; i++)
404 {
405 if (((reg_value & (1UL << i)) >> i) != 0U)
406 {
407 PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
408 }
409 else
410 {
411 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
412 }
413 }
414
415 reg_value = READ_REG(GTZC_TZSC1->SECCFGR2);
416 for (i = 32U; i < 64U; i++)
417 {
418 if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
419 {
420 PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
421 }
422 else
423 {
424 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
425 }
426 }
427
428 reg_value = READ_REG(GTZC_TZSC1->SECCFGR3);
429 for (i = 64U; i < 96U; i++)
430 {
431 if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U)
432 {
433 PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
434 }
435 else
436 {
437 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
438 }
439 }
440
441 reg_value = READ_REG(GTZC_TZSC2->SECCFGR1);
442 for (i = 96U; i < GTZC_TZSC_PERIPH_NUMBER; i++)
443 {
444 if (((reg_value & (1UL << (i - 96U))) >> (i - 96U)) != 0U)
445 {
446 PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
447 }
448 else
449 {
450 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
451 }
452 }
453
454 /* get privilege configuration: read each register and deploy each bit value
455 * of corresponding index in the destination array
456 */
457 reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR1);
458 for (i = 0U; i < 32U; i++)
459 {
460 if (((reg_value & (1UL << i)) >> i) != 0U)
461 {
462 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
463 }
464 else
465 {
466 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
467 }
468 }
469
470 reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR2);
471 for (i = 32U; i < 64U; i++)
472 {
473 if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
474 {
475 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
476 }
477 else
478 {
479 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
480 }
481 }
482
483 reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR3);
484 for (i = 64U; i < 96U; i++)
485 {
486 if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U)
487 {
488 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
489 }
490 else
491 {
492 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
493 }
494 }
495
496 reg_value = READ_REG(GTZC_TZSC2->PRIVCFGR1);
497 for (i = 96U; i < GTZC_TZSC_PERIPH_NUMBER; i++)
498 {
499 if (((reg_value & (1UL << (i - 96U))) >> (i - 96U)) != 0U)
500 {
501 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
502 }
503 else
504 {
505 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
506 }
507 }
508 }
509 else
510 {
511 /* common case where only one peripheral is configured */
512
513 /* secure configuration */
514 register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->SECCFGR1)
515 + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
516
517 if (((READ_BIT(*(__IO uint32_t *)register_address,
518 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
519 != 0U)
520 {
521 *PeriphAttributes = GTZC_TZSC_PERIPH_SEC;
522 }
523 else
524 {
525 *PeriphAttributes = GTZC_TZSC_PERIPH_NSEC;
526 }
527
528 /* privilege configuration */
529 register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->PRIVCFGR1)
530 + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
531 if (((READ_BIT(*(__IO uint32_t *)register_address,
532 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
533 != 0U)
534 {
535 *PeriphAttributes |= GTZC_TZSC_PERIPH_PRIV;
536 }
537 else
538 {
539 *PeriphAttributes |= GTZC_TZSC_PERIPH_NPRIV;
540 }
541 }
542 return HAL_OK;
543 }
544
545 /**
546 * @}
547 */
548
549 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
550
551 /** @defgroup GTZC_Exported_Functions_Group2 MPCWM Configuration functions
552 * @brief MPCWM Configuration functions
553 *
554 @verbatim
555 ==============================================================================
556 ##### MPCWM Configuration functions #####
557 ==============================================================================
558 [..]
559 This section provides functions allowing to configure MPCWM
560 MPCWM is Memory Protection Controller WaterMark
561 @endverbatim
562 * @{
563 */
564
565 /**
566 * @brief Configure a TZSC-MPCWM area.
567 * @param MemBaseAddress WM identifier.
568 * @param pMPCWM_Desc TZSC-MPCWM descriptor pointer.
569 * The structure description is available in @ref GTZC_Exported_Types.
570 * @retval HAL status.
571 */
HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress,const MPCWM_ConfigTypeDef * pMPCWM_Desc)572 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress,
573 const MPCWM_ConfigTypeDef *pMPCWM_Desc)
574 {
575 uint32_t register_address;
576 uint32_t reg_value;
577 uint32_t size;
578 /* granularity value depends on selected memory */
579 uint32_t granularity = (MemBaseAddress == BKPSRAM_BASE) ? \
580 GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1;
581
582 /* check entry parameters */
583 if ((pMPCWM_Desc->AreaId > GTZC_TZSC_MPCWM_ID2) ||
584 #if defined (FMC_BANK3)
585 (((MemBaseAddress == BKPSRAM_BASE) || (MemBaseAddress == FMC_BANK3)) &&
586 #else
587 ((MemBaseAddress == BKPSRAM_BASE) &&
588 #endif /* FMC_BANK3 */
589 (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2)) ||
590 ((pMPCWM_Desc->Offset % granularity) != 0U) ||
591 ((pMPCWM_Desc->Length % granularity) != 0U))
592 {
593 return HAL_ERROR;
594 }
595
596 /* check descriptor content vs. memory capacity */
597 switch (MemBaseAddress)
598 {
599 case OCTOSPI1_BASE:
600 size = TZSC_MPCWM1_MEM_SIZE;
601 if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
602 {
603 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1AR);
604 }
605 else
606 {
607 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
608 * (Parameter already checked)
609 */
610 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR);
611 }
612 break;
613 #if defined (FMC_BANK1)
614 case FMC_BANK1:
615 size = TZSC_MPCWM1_MEM_SIZE;
616 if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
617 {
618 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2AR);
619 }
620 else
621 {
622 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
623 * (Parameter already checked)
624 */
625 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR);
626 }
627 break;
628 #endif /* FMC_BANK1 */
629 #if defined (FMC_BANK3)
630 case FMC_BANK3:
631 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
632 * (Parameter already checked)
633 */
634 size = TZSC_MPCWM3_MEM_SIZE;
635 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM3AR);
636 break;
637 #endif /* FMC_BANK3 */
638 case BKPSRAM_BASE:
639 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
640 * (Parameter already checked)
641 */
642 size = TZSC_MPCWM4_MEM_SIZE;
643 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM4AR);
644 break;
645 #if defined (OCTOSPI2_BASE)
646 case OCTOSPI2_BASE:
647 size = TZSC_MPCWM5_MEM_SIZE;
648 if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
649 {
650 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5AR);
651 }
652 else
653 {
654 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
655 * (Parameter already checked)
656 */
657 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5BR);
658 }
659 break;
660 #endif /* OCTOSPI2_BASE */
661 #if defined (HSPI1)
662 case HSPI1_BASE:
663 size = TZSC_MPCWM6_MEM_SIZE;
664 if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
665 {
666 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM6AR);
667 }
668 else
669 {
670 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
671 * (Parameter already checked)
672 */
673 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM6BR);
674 }
675 break;
676 #endif /* HSPI1 */
677 default:
678 return HAL_ERROR;
679 break;
680 }
681
682 if ((pMPCWM_Desc->Offset > size) ||
683 ((pMPCWM_Desc->Offset + pMPCWM_Desc->Length) > size))
684 {
685 return HAL_ERROR;
686 }
687
688 /* Write watermark start and length value */
689 reg_value = ((pMPCWM_Desc->Offset / granularity)
690 << GTZC_TZSC_MPCWMR_SUBZ_START_Pos) & GTZC_TZSC_MPCWMR_SUBZ_START_Msk;
691 reg_value |= ((pMPCWM_Desc->Length / granularity)
692 << GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk;
693 MODIFY_REG(*(__IO uint32_t *)register_address, GTZC_TZSC_MPCWMR_SUBZ_START_Msk | \
694 GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk, reg_value);
695
696 /* Write watermark configuration value */
697 reg_value = (pMPCWM_Desc->Attribute << GTZC_TZSC_MPCWM_CFGR_SEC_Pos) | \
698 pMPCWM_Desc->Lock | \
699 pMPCWM_Desc->AreaStatus;
700 MODIFY_REG(*(__IO uint32_t *)(register_address - 4U), (GTZC_TZSC_MPCWM_CFGR_PRIV | GTZC_TZSC_MPCWM_CFGR_SEC | \
701 GTZC_TZSC_MPCWM_CFGR_SRLOCK | GTZC_TZSC_MPCWM_CFGR_SREN), \
702 reg_value);
703
704 return HAL_OK;
705 }
706
707 /**
708 * @brief Get a TZSC-MPCWM area configuration.
709 * @param MemBaseAddress WM identifier.
710 * @param pMPCWM_Desc pointer to a TZSC-MPCWM descriptor.
711 * When the WaterMark memory supports two sub-regions A and B. pMPCWM_Desc argument must point to an array of
712 * two MPCWM_ConfigTypeDef structures.
713 * The structure description is available in @ref GTZC_Exported_Types.
714 * @retval HAL status.
715 */
HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress,MPCWM_ConfigTypeDef * pMPCWM_Desc)716 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress,
717 MPCWM_ConfigTypeDef *pMPCWM_Desc)
718 {
719 uint32_t register_address_regionA;
720 uint32_t register_address_regionB = 0U;
721 uint32_t reg_value;
722 uint32_t granularity = (MemBaseAddress == BKPSRAM_BASE) ? \
723 GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1;
724
725 /* Loading the subregion A & B addresses into their specific variables */
726 switch (MemBaseAddress)
727 {
728 case OCTOSPI1_BASE:
729 register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM1AR);
730 register_address_regionB = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR);
731 break;
732 #if defined (FMC_BANK1)
733 case FMC_BANK1:
734 register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM2AR);
735 register_address_regionB = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR);
736 break;
737 #endif /* FMC_BANK1 */
738 #if defined (FMC_BANK3)
739 case FMC_BANK3:
740 register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM3AR);
741 break;
742 #endif /* FMC_BANK3 */
743 case BKPSRAM_BASE:
744 register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM4AR);
745 break;
746 #if defined (OCTOSPI2_BASE)
747 case OCTOSPI2_BASE:
748 register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM5AR);
749 register_address_regionB = (uint32_t) &(GTZC_TZSC1_S->MPCWM5BR);
750 break;
751 #endif /* OCTOSPI2_BASE */
752 #if defined (HSPI1)
753 case HSPI1_BASE:
754 register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM6AR);
755 register_address_regionB = (uint32_t) &(GTZC_TZSC1_S->MPCWM6BR);
756 break;
757 #endif /* HSPI1 */
758 default:
759 return HAL_ERROR;
760 break;
761 }
762
763 /* read register and update the descriptor for first area*/
764 reg_value = READ_REG(*(__IO uint32_t *)register_address_regionA);
765 pMPCWM_Desc[0].AreaId = GTZC_TZSC_MPCWM_ID1;
766 pMPCWM_Desc[0].Offset = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_START_Msk)
767 >> GTZC_TZSC_MPCWMR_SUBZ_START_Pos) * granularity;
768 pMPCWM_Desc[0].Length = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk)
769 >> GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) * granularity;
770
771 /* read configuration register and update the descriptor for first area*/
772 reg_value = READ_REG(*(__IO uint32_t *)(register_address_regionA - 4U));
773 pMPCWM_Desc[0].Attribute = (reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \
774 GTZC_TZSC_MPCWM_CFGR_SEC)) >> GTZC_TZSC_MPCWM_CFGR_SEC_Pos;
775 pMPCWM_Desc[0].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK;
776 pMPCWM_Desc[0].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN;
777
778 if (register_address_regionB != 0U)
779 {
780 /* read register and update the descriptor for second area*/
781 reg_value = READ_REG(*(__IO uint32_t *)register_address_regionB);
782 pMPCWM_Desc[1].AreaId = GTZC_TZSC_MPCWM_ID2;
783 pMPCWM_Desc[1].Offset = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_START_Msk)
784 >> GTZC_TZSC_MPCWMR_SUBZ_START_Pos) * granularity;
785 pMPCWM_Desc[1].Length = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk)
786 >> GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) * granularity;
787
788 /* read configuration register and update the descriptor for second area*/
789 reg_value = READ_REG(*(__IO uint32_t *)(register_address_regionB - 4U));
790 pMPCWM_Desc[1].Attribute = (reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \
791 GTZC_TZSC_MPCWM_CFGR_SEC)) >> GTZC_TZSC_MPCWM_CFGR_SEC_Pos;
792 pMPCWM_Desc[1].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK;
793 pMPCWM_Desc[1].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN;
794 }
795
796 return HAL_OK;
797 }
798
799 /**
800 * @}
801 */
802
803 /** @defgroup GTZC_Exported_Functions_Group3 TZSC Lock functions
804 * @brief TZSC Lock functions
805 *
806 @verbatim
807 ==============================================================================
808 ##### TZSC Lock functions #####
809 ==============================================================================
810 [..]
811 This section provides functions allowing to manage the TZSC (TrustZone
812 Security Controller) lock. It includes lock enable, and current value read.
813 @endverbatim
814 * @{
815 */
816
817 /**
818 * @brief Lock TZSC configuration.
819 * @note This function locks the configuration of TZSC_SECCFGRx and TZSC_PRIVCFGRx
820 * registers until next reset
821 * @param TZSC_Instance TZSC sub-block instance.
822 */
HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef * TZSC_Instance)823 void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance)
824 {
825 SET_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk);
826 }
827
828 /**
829 * @brief Get TZSC configuration lock state.
830 * @param TZSC_Instance TZSC sub-block instance.
831 * @retval Lock State (GTZC_TZSC_LOCK_OFF or GTZC_TZSC_LOCK_ON)
832 */
HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef * TZSC_Instance)833 uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance)
834 {
835 return READ_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk);
836 }
837
838 /**
839 * @}
840 */
841 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
842
843 /** @defgroup GTZC_Exported_Functions_Group4 MPCBB Configuration functions
844 * @brief MPCBB Configuration functions
845 *
846 @verbatim
847 ==============================================================================
848 ##### MPCBB Configuration functions #####
849 ==============================================================================
850 [..]
851 This section provides functions allowing to configure MPCBB
852 MPCBB is Memory Protection Controller Block Base
853 @endverbatim
854 * @{
855 */
856
857 /**
858 * @brief Set a complete MPCBB configuration on the SRAM passed as parameter.
859 * @param MemBaseAddress MPCBB identifier.
860 * @param pMPCBB_desc pointer to MPCBB descriptor.
861 * The structure description is available in @ref GTZC_Exported_Types.
862 * @retval HAL status.
863 */
HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,const MPCBB_ConfigTypeDef * pMPCBB_desc)864 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,
865 const MPCBB_ConfigTypeDef *pMPCBB_desc)
866 {
867 GTZC_MPCBB_TypeDef *mpcbb_ptr;
868 uint32_t mem_size;
869 uint32_t size_in_superblocks;
870 uint32_t i;
871
872 /* check entry parameters */
873 if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
874 && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
875 #if defined (SRAM3_BASE)
876 && !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
877 #endif /* SRAM3_BASE */
878 && !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
879 #if defined (SRAM5_BASE)
880 && !(IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress))
881 #endif /* SRAM5_BASE */
882 #if defined (SRAM6_BASE)
883 && !(IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress))
884 #endif /* SRAM6_BASE */
885 )
886 || ((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE)
887 && (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE))
888 || ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED)
889 && (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED)))
890 {
891 return HAL_ERROR;
892 }
893
894 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
895 {
896 mpcbb_ptr = GTZC_MPCBB1;
897 mem_size = GTZC_MEM_SIZE(SRAM1);
898 }
899 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
900 {
901 mpcbb_ptr = GTZC_MPCBB2;
902 mem_size = GTZC_MEM_SIZE(SRAM2);
903 }
904 #if defined (SRAM3_BASE)
905 else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
906 {
907 mpcbb_ptr = GTZC_MPCBB3;
908 mem_size = GTZC_MEM_SIZE(SRAM3);
909 }
910 #endif /* SRAM3_BASE */
911 else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
912 {
913 mpcbb_ptr = GTZC_MPCBB4;
914 mem_size = GTZC_MEM_SIZE(SRAM4);
915 }
916 #if defined (SRAM5_BASE)
917 else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress))
918 {
919 mpcbb_ptr = GTZC_MPCBB5;
920 mem_size = GTZC_MEM_SIZE(SRAM5);
921 }
922 #endif /* SRAM5_BASE */
923 #if defined (SRAM6_BASE)
924 else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress))
925 {
926 mpcbb_ptr = GTZC_MPCBB6;
927 mem_size = GTZC_MEM_SIZE(SRAM6);
928 }
929 #endif /* SRAM6_BASE */
930 else
931 {
932 return HAL_ERROR;
933 }
934
935 /* translate mem_size in number of super-blocks */
936 size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
937
938 /* write PRIVCFGR register information */
939 for (i = 0U; i < size_in_superblocks; i++)
940 {
941 WRITE_REG(mpcbb_ptr->PRIVCFGR[i],
942 pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i]);
943 }
944
945 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
946 uint32_t size_mask;
947 uint32_t reg_value;
948
949 /* write SECCFGR register information */
950 for (i = 0U; i < size_in_superblocks; i++)
951 {
952 WRITE_REG(mpcbb_ptr->SECCFGR[i],
953 pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i]);
954 }
955
956 #if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk)
957 if (size_in_superblocks >= 32U)
958 {
959 size_mask = 0xFFFFFFFFU;
960 MODIFY_REG(mpcbb_ptr->CFGLOCKR2, 0x000FFFFFUL, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[1]);
961 }
962 else
963 #endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */
964 {
965 size_mask = (1UL << (size_in_superblocks & 0x1FU)) - 1U;
966 }
967 /* limitation: code not portable with memory > 512K */
968 MODIFY_REG(mpcbb_ptr->CFGLOCKR1, size_mask, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0]);
969
970 /* write InvertSecureState and SecureRWIllegalMode properties */
971 reg_value = pMPCBB_desc->InvertSecureState;
972 reg_value |= pMPCBB_desc->SecureRWIllegalMode;
973
974 /* write configuration and lock register information */
975 MODIFY_REG(mpcbb_ptr->CR,
976 GTZC_MPCBB_CR_INVSECSTATE_Msk | GTZC_MPCBB_CR_SRWILADIS_Msk, reg_value);
977 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
978
979 return HAL_OK;
980 }
981
982 /**
983 * @brief Get a complete MPCBB configuration on the SRAM passed as parameter.
984 * @param MemBaseAddress MPCBB identifier.
985 * @param pMPCBB_desc pointer to a MPCBB descriptor.
986 * The structure description is available in @ref GTZC_Exported_Types.
987 * @retval HAL status.
988 */
HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,MPCBB_ConfigTypeDef * pMPCBB_desc)989 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,
990 MPCBB_ConfigTypeDef *pMPCBB_desc)
991 {
992 GTZC_MPCBB_TypeDef *mpcbb_ptr;
993 uint32_t mem_size;
994 uint32_t size_in_superblocks;
995 uint32_t i;
996
997 /* check entry parameters */
998 if (!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
999 && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
1000 #if defined (SRAM3_BASE)
1001 && !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
1002 #endif /* SRAM3_BASE */
1003 && !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
1004 #if defined (SRAM5_BASE)
1005 && !(IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress))
1006 #endif /* SRAM5_BASE */
1007 #if defined (SRAM6_BASE)
1008 && !(IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress))
1009 #endif /* SRAM6_BASE */
1010 )
1011 {
1012 return HAL_ERROR;
1013 }
1014
1015 /* read InvertSecureState and SecureRWIllegalMode properties */
1016 /* assume their Position/Mask is identical for all sub-blocks */
1017 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
1018 {
1019 mpcbb_ptr = GTZC_MPCBB1;
1020 mem_size = GTZC_MEM_SIZE(SRAM1);
1021 }
1022 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
1023 {
1024 mpcbb_ptr = GTZC_MPCBB2;
1025 mem_size = GTZC_MEM_SIZE(SRAM2);
1026 }
1027 #if defined (SRAM3_BASE)
1028 else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
1029 {
1030 mpcbb_ptr = GTZC_MPCBB3;
1031 mem_size = GTZC_MEM_SIZE(SRAM3);
1032 }
1033 #endif /* SRAM3_BASE */
1034 else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
1035 {
1036 mpcbb_ptr = GTZC_MPCBB4;
1037 mem_size = GTZC_MEM_SIZE(SRAM4);
1038 }
1039 #if defined (SRAM5_BASE)
1040 else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress))
1041 {
1042 mpcbb_ptr = GTZC_MPCBB5;
1043 mem_size = GTZC_MEM_SIZE(SRAM5);
1044 }
1045 #endif /* SRAM5_BASE */
1046 #if defined (SRAM6_BASE)
1047 else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress))
1048 {
1049 mpcbb_ptr = GTZC_MPCBB6;
1050 mem_size = GTZC_MEM_SIZE(SRAM6);
1051 }
1052 #endif /* SRAM6_BASE */
1053 else
1054 {
1055 return HAL_ERROR;
1056 }
1057
1058 /* translate mem_size in number of super-blocks */
1059 size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
1060
1061 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1062 uint32_t reg_value;
1063
1064 /* read configuration and lock register information */
1065 reg_value = READ_REG(mpcbb_ptr->CR);
1066 pMPCBB_desc->InvertSecureState = (reg_value & GTZC_MPCBB_CR_INVSECSTATE_Msk);
1067 pMPCBB_desc->SecureRWIllegalMode = (reg_value & GTZC_MPCBB_CR_SRWILADIS_Msk);
1068
1069 /* limitation: code not portable with memory > 512K */
1070 pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0] = READ_REG(mpcbb_ptr->CFGLOCKR1);
1071
1072 #if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk)
1073 pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[1] = READ_REG(mpcbb_ptr->CFGLOCKR2);
1074 #endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */
1075
1076 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1077
1078 /* read SECCFGR / PRIVCFGR registers information */
1079 for (i = 0U; i < size_in_superblocks; i++)
1080 {
1081 pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i] = mpcbb_ptr->SECCFGR[i];
1082 pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i] = mpcbb_ptr->PRIVCFGR[i];
1083 }
1084
1085 return HAL_OK;
1086 }
1087
1088 /**
1089 * @brief Set a MPCBB attribute configuration on the SRAM passed as parameter
1090 * for a number of blocks.
1091 * @param MemAddress MPCBB identifier, and start block to configure
1092 * (must be 512 Bytes aligned).
1093 * @param NbBlocks Number of blocks to configure
1094 * (Block size is 512 Bytes).
1095 * @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
1096 * with each element must be GTZC_MPCBB_BLOCK_NSEC or GTZC_MPCBB_BLOCK_SEC,
1097 * and GTZC_MPCBB_BLOCK_NPRIV or GTZC_MPCBB_BLOCK_PRIV.
1098 * @retval HAL status.
1099 */
HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,uint32_t NbBlocks,const uint32_t * pMemAttributes)1100 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,
1101 uint32_t NbBlocks,
1102 const uint32_t *pMemAttributes)
1103 {
1104 GTZC_MPCBB_TypeDef *mpcbb_ptr;
1105 uint32_t base_address;
1106 uint32_t end_address;
1107 uint32_t block_start;
1108 uint32_t offset_reg_start;
1109 uint32_t offset_bit_start;
1110 uint32_t i;
1111 uint32_t do_attr_change;
1112
1113 /* firstly check that MemAddress is well 512 Bytes aligned */
1114 if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U)
1115 {
1116 return HAL_ERROR;
1117 }
1118
1119 /* check entry parameters and deduce physical base address */
1120 end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U;
1121 if (((IS_ADDRESS_IN_NS(SRAM1, MemAddress))
1122 && (IS_ADDRESS_IN_NS(SRAM1, end_address))) != 0U)
1123 {
1124 mpcbb_ptr = GTZC_MPCBB1;
1125 base_address = SRAM1_BASE_NS;
1126 }
1127 else if (((IS_ADDRESS_IN_S(SRAM1, MemAddress))
1128 && (IS_ADDRESS_IN_S(SRAM1, end_address))) != 0U)
1129 {
1130 mpcbb_ptr = GTZC_MPCBB1;
1131 base_address = SRAM1_BASE_S;
1132 }
1133 else if (((IS_ADDRESS_IN_NS(SRAM2, MemAddress))
1134 && (IS_ADDRESS_IN_NS(SRAM2, end_address))) != 0U)
1135 {
1136 mpcbb_ptr = GTZC_MPCBB2;
1137 base_address = SRAM2_BASE_NS;
1138 }
1139 else if (((IS_ADDRESS_IN_S(SRAM2, MemAddress))
1140 && (IS_ADDRESS_IN_S(SRAM2, end_address))) != 0U)
1141 {
1142 mpcbb_ptr = GTZC_MPCBB2;
1143 base_address = SRAM2_BASE_S;
1144 }
1145 #if defined (SRAM3_BASE)
1146 else if (((IS_ADDRESS_IN_NS(SRAM3, MemAddress))
1147 && (IS_ADDRESS_IN_NS(SRAM3, end_address))) != 0U)
1148 {
1149 mpcbb_ptr = GTZC_MPCBB3;
1150 base_address = SRAM3_BASE_NS;
1151 }
1152 else if (((IS_ADDRESS_IN_S(SRAM3, MemAddress))
1153 && (IS_ADDRESS_IN_S(SRAM3, end_address))) != 0U)
1154 {
1155 mpcbb_ptr = GTZC_MPCBB3;
1156 base_address = SRAM3_BASE_S;
1157 }
1158 #endif /* SRAM3_BASE */
1159 else if (((IS_ADDRESS_IN_NS(SRAM4, MemAddress))
1160 && (IS_ADDRESS_IN_NS(SRAM4, end_address))) != 0U)
1161 {
1162 mpcbb_ptr = GTZC_MPCBB4;
1163 base_address = SRAM4_BASE_NS;
1164 }
1165 else if (((IS_ADDRESS_IN_S(SRAM4, MemAddress))
1166 && (IS_ADDRESS_IN_S(SRAM4, end_address))) != 0U)
1167 {
1168 mpcbb_ptr = GTZC_MPCBB4;
1169 base_address = SRAM4_BASE_S;
1170 }
1171 #if defined (SRAM5_BASE)
1172 else if (((IS_ADDRESS_IN_NS(SRAM5, MemAddress))
1173 && (IS_ADDRESS_IN_NS(SRAM5, end_address))) != 0U)
1174 {
1175 mpcbb_ptr = GTZC_MPCBB5;
1176 base_address = SRAM5_BASE_NS;
1177 }
1178 else if (((IS_ADDRESS_IN_S(SRAM5, MemAddress))
1179 && (IS_ADDRESS_IN_S(SRAM5, end_address))) != 0U)
1180 {
1181 mpcbb_ptr = GTZC_MPCBB5;
1182 base_address = SRAM5_BASE_S;
1183 }
1184 #endif /* SRAM5_BASE */
1185 #if defined (SRAM6_BASE)
1186 else if (((IS_ADDRESS_IN_NS(SRAM6, MemAddress))
1187 && (IS_ADDRESS_IN_NS(SRAM6, end_address))) != 0U)
1188 {
1189 mpcbb_ptr = GTZC_MPCBB6;
1190 base_address = SRAM6_BASE_NS;
1191 }
1192 else if (((IS_ADDRESS_IN_S(SRAM6, MemAddress))
1193 && (IS_ADDRESS_IN_S(SRAM6, end_address))) != 0U)
1194 {
1195 mpcbb_ptr = GTZC_MPCBB6;
1196 base_address = SRAM6_BASE_S;
1197 }
1198 #endif /* SRAM6_BASE */
1199 else
1200 {
1201 return HAL_ERROR;
1202 }
1203
1204 /* get start coordinates of the configuration */
1205 block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE;
1206 offset_reg_start = block_start / 32U;
1207 offset_bit_start = block_start % 32U;
1208
1209 for (i = 0U; i < NbBlocks; i++)
1210 {
1211 /* Indicate change done for protection attributes */
1212 do_attr_change = 0U;
1213
1214 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1215 /* secure configuration */
1216 if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_SEC) == GTZC_MPCBB_BLOCK_SEC)
1217 {
1218 SET_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1219 1UL << (offset_bit_start % 32U));
1220 do_attr_change = 1U;
1221 }
1222 else if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_NSEC) == GTZC_MPCBB_BLOCK_NSEC)
1223 {
1224 CLEAR_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1225 1UL << (offset_bit_start % 32U));
1226 do_attr_change = 1U;
1227 }
1228 else
1229 {
1230 /* nothing to do */
1231 }
1232 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1233
1234 /* privilege configuration */
1235 if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_PRIV) == GTZC_MPCBB_BLOCK_PRIV)
1236 {
1237 SET_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1238 1UL << (offset_bit_start % 32U));
1239 }
1240 else if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_NPRIV) == GTZC_MPCBB_BLOCK_NPRIV)
1241 {
1242 CLEAR_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1243 1UL << (offset_bit_start % 32U));
1244 }
1245 else
1246 {
1247 /* if no change is done for security and privilege attributes: break the loop */
1248 if (do_attr_change == 0U)
1249 {
1250 break;
1251 }
1252 }
1253
1254 offset_bit_start++;
1255 if (offset_bit_start == 32U)
1256 {
1257 offset_bit_start = 0U;
1258 offset_reg_start++;
1259 }
1260 }
1261
1262 /* an unexpected value in pMemAttributes array leads to error status */
1263 if (i != NbBlocks)
1264 {
1265 return HAL_ERROR;
1266 }
1267
1268 return HAL_OK;
1269 }
1270
1271 /**
1272 * @brief Get a MPCBB attribute configuration on the SRAM passed as parameter
1273 * for a number of blocks.
1274 * @param MemAddress MPCBB identifier, and start block to get configuration
1275 * (must be 512 Bytes aligned).
1276 * @param NbBlocks Number of blocks to get configuration.
1277 * @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
1278 * with each element will be GTZC_MPCBB_BLOCK_NSEC or GTZC_MPCBB_BLOCK_SEC,
1279 * and GTZC_MPCBB_BLOCK_NPRIV or GTZC_MPCBB_BLOCK_PRIV.
1280 * @retval HAL status.
1281 */
HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,uint32_t NbBlocks,uint32_t * pMemAttributes)1282 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,
1283 uint32_t NbBlocks,
1284 uint32_t *pMemAttributes)
1285 {
1286 GTZC_MPCBB_TypeDef *mpcbb_ptr;
1287 uint32_t base_address;
1288 uint32_t end_address;
1289 uint32_t block_start;
1290 uint32_t offset_reg_start;
1291 uint32_t offset_bit_start;
1292 uint32_t i;
1293
1294 /* firstly check that MemAddress is well 512 Bytes aligned */
1295 if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U)
1296 {
1297 return HAL_ERROR;
1298 }
1299
1300 /* check entry parameters and deduce physical base address */
1301 end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U;
1302 if ((IS_ADDRESS_IN_NS(SRAM1, MemAddress))
1303 && (IS_ADDRESS_IN_NS(SRAM1, end_address)))
1304 {
1305 mpcbb_ptr = GTZC_MPCBB1_NS;
1306 base_address = SRAM1_BASE_NS;
1307 }
1308 else if ((IS_ADDRESS_IN_S(SRAM1, MemAddress))
1309 && (IS_ADDRESS_IN_S(SRAM1, end_address)))
1310 {
1311 mpcbb_ptr = GTZC_MPCBB1_S;
1312 base_address = SRAM1_BASE_S;
1313 }
1314 else if ((IS_ADDRESS_IN_NS(SRAM2, MemAddress))
1315 && (IS_ADDRESS_IN_NS(SRAM2, end_address)))
1316 {
1317 mpcbb_ptr = GTZC_MPCBB2_NS;
1318 base_address = SRAM2_BASE_NS;
1319 }
1320 else if ((IS_ADDRESS_IN_S(SRAM2, MemAddress))
1321 && (IS_ADDRESS_IN_S(SRAM2, end_address)))
1322 {
1323 mpcbb_ptr = GTZC_MPCBB2_S;
1324 base_address = SRAM2_BASE_S;
1325 }
1326 #if defined (SRAM3_BASE)
1327 else if ((IS_ADDRESS_IN_NS(SRAM3, MemAddress))
1328 && (IS_ADDRESS_IN_NS(SRAM3, end_address)))
1329 {
1330 mpcbb_ptr = GTZC_MPCBB3_NS;
1331 base_address = SRAM3_BASE_NS;
1332 }
1333 else if ((IS_ADDRESS_IN_S(SRAM3, MemAddress))
1334 && (IS_ADDRESS_IN_S(SRAM3, end_address)))
1335 {
1336 mpcbb_ptr = GTZC_MPCBB3_S;
1337 base_address = SRAM3_BASE_S;
1338 }
1339 #endif /* SRAM3_BASE */
1340 else if ((IS_ADDRESS_IN_NS(SRAM4, MemAddress))
1341 && (IS_ADDRESS_IN_NS(SRAM4, end_address)))
1342 {
1343 mpcbb_ptr = GTZC_MPCBB4_NS;
1344 base_address = SRAM4_BASE_NS;
1345 }
1346 else if ((IS_ADDRESS_IN_S(SRAM4, MemAddress))
1347 && (IS_ADDRESS_IN_S(SRAM4, end_address)))
1348 {
1349 mpcbb_ptr = GTZC_MPCBB4_S;
1350 base_address = SRAM4_BASE_S;
1351 }
1352 #if defined (SRAM5_BASE)
1353 else if ((IS_ADDRESS_IN_NS(SRAM5, MemAddress))
1354 && (IS_ADDRESS_IN_NS(SRAM5, end_address)))
1355 {
1356 mpcbb_ptr = GTZC_MPCBB5_NS;
1357 base_address = SRAM5_BASE_NS;
1358 }
1359 else if ((IS_ADDRESS_IN_S(SRAM5, MemAddress))
1360 && (IS_ADDRESS_IN_S(SRAM5, end_address)))
1361 {
1362 mpcbb_ptr = GTZC_MPCBB5_S;
1363 base_address = SRAM5_BASE_S;
1364 }
1365 #endif /* SRAM5_BASE */
1366 #if defined (SRAM6_BASE)
1367 else if ((IS_ADDRESS_IN_NS(SRAM6, MemAddress))
1368 && (IS_ADDRESS_IN_NS(SRAM6, end_address)))
1369 {
1370 mpcbb_ptr = GTZC_MPCBB6_NS;
1371 base_address = SRAM6_BASE_NS;
1372 }
1373 else if ((IS_ADDRESS_IN_S(SRAM6, MemAddress))
1374 && (IS_ADDRESS_IN_S(SRAM6, end_address)))
1375 {
1376 mpcbb_ptr = GTZC_MPCBB6_S;
1377 base_address = SRAM6_BASE_S;
1378 }
1379 #endif /* SRAM6_BASE */
1380 else
1381 {
1382 return HAL_ERROR;
1383 }
1384
1385 /* get start coordinates of the configuration */
1386 block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE;
1387 offset_reg_start = block_start / 32U;
1388 offset_bit_start = block_start % 32U;
1389
1390 for (i = 0U; i < NbBlocks; i++)
1391 {
1392 pMemAttributes[i] = (READ_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1393 1UL << (offset_bit_start % 32U))
1394 >> (offset_bit_start % 32U)) | GTZC_ATTR_SEC_MASK;
1395 pMemAttributes[i] |= ((READ_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1396 1UL << (offset_bit_start % 32U))
1397 >> (offset_bit_start % 32U)) << 1U) | GTZC_ATTR_PRIV_MASK;
1398
1399 offset_bit_start++;
1400 if (offset_bit_start == 32U)
1401 {
1402 offset_bit_start = 0U;
1403 offset_reg_start++;
1404 }
1405 }
1406
1407 return HAL_OK;
1408 }
1409
1410 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1411 /**
1412 * @brief Lock MPCBB super-blocks on the SRAM passed as parameter.
1413 * @param MemAddress MPCBB start-address of super-block to configure
1414 * (must be 16KBytes aligned).
1415 * @param NbSuperBlocks Number of super-blocks to configure.
1416 * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements),
1417 * with for each element:
1418 * value 0 super-block is unlocked, value 1 super-block is locked
1419 * (corresponds to GTZC_MPCBB_SUPERBLOCK_UNLOCKED and
1420 * GTZC_MPCBB_SUPERBLOCK_LOCKED values).
1421 * @retval HAL status.
1422 */
HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,uint32_t NbSuperBlocks,const uint32_t * pLockAttributes)1423 HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,
1424 uint32_t NbSuperBlocks,
1425 const uint32_t *pLockAttributes)
1426 {
1427 __IO uint32_t *reg_mpcbb;
1428 uint32_t base_address;
1429 uint32_t superblock_start;
1430 uint32_t offset_bit_start;
1431 uint32_t i = 0U;
1432
1433 /* firstly check that MemAddress is well 16KBytes aligned */
1434 if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
1435 {
1436 return HAL_ERROR;
1437 }
1438
1439 /* check entry parameters */
1440 if ((IS_ADDRESS_IN(SRAM1, MemAddress))
1441 && (IS_ADDRESS_IN(SRAM1, (MemAddress
1442 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1443 - 1U))))
1444 {
1445 base_address = GTZC_BASE_ADDRESS(SRAM1);
1446 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->CFGLOCKR1;
1447 }
1448 else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
1449 && (IS_ADDRESS_IN(SRAM2, (MemAddress
1450 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1451 - 1U))))
1452 {
1453 base_address = GTZC_BASE_ADDRESS(SRAM2);
1454 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCKR1;
1455 }
1456 #if defined (SRAM3_BASE)
1457 else if ((IS_ADDRESS_IN(SRAM3, MemAddress))
1458 && (IS_ADDRESS_IN(SRAM3, (MemAddress
1459 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1460 - 1U))))
1461 {
1462 base_address = GTZC_BASE_ADDRESS(SRAM3);
1463 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB3_S->CFGLOCKR1;
1464 }
1465 #endif /* SRAM3_BASE */
1466 else if ((IS_ADDRESS_IN(SRAM4, MemAddress))
1467 && (IS_ADDRESS_IN(SRAM4, (MemAddress
1468 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1469 - 1U))))
1470 {
1471 base_address = GTZC_BASE_ADDRESS(SRAM4);
1472 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB4_S->CFGLOCKR1;
1473 }
1474 #if defined (SRAM5_BASE)
1475 else if ((IS_ADDRESS_IN(SRAM5, MemAddress))
1476 && (IS_ADDRESS_IN(SRAM5, (MemAddress
1477 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1478 - 1U))))
1479 {
1480 base_address = GTZC_BASE_ADDRESS(SRAM5);
1481 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB5_S->CFGLOCKR1;
1482 }
1483 #endif /* SRAM5_BASE */
1484 #if defined (SRAM6_BASE)
1485 else if ((IS_ADDRESS_IN(SRAM6, MemAddress))
1486 && (IS_ADDRESS_IN(SRAM6, (MemAddress
1487 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1488 - 1U))))
1489 {
1490 base_address = GTZC_BASE_ADDRESS(SRAM6);
1491 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB6_S->CFGLOCKR1;
1492 }
1493 #endif /* SRAM6_BASE */
1494 else
1495 {
1496 return HAL_ERROR;
1497 }
1498
1499 /* get start coordinates of the configuration */
1500 superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
1501 offset_bit_start = superblock_start % 32U;
1502
1503 /* First 32 super-blocks */
1504 while ((i < NbSuperBlocks) && (i < 32U) && (superblock_start < 32U))
1505 {
1506 if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_LOCKED)
1507 {
1508 SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
1509 }
1510 else if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_UNLOCKED)
1511 {
1512 CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
1513 }
1514 else
1515 {
1516 break;
1517 }
1518
1519 offset_bit_start++;
1520 i++;
1521 }
1522
1523 #if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk)
1524 if ((NbSuperBlocks > 32U) || (superblock_start >= 32U))
1525 {
1526 /* Point to second configuration lock register */
1527 reg_mpcbb++;
1528
1529 /* Remaining super-blocks */
1530 for (; i < NbSuperBlocks; i++)
1531 {
1532 if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_LOCKED)
1533 {
1534 SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
1535 }
1536 else if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_UNLOCKED)
1537 {
1538 CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
1539 }
1540 else
1541 {
1542 break;
1543 }
1544
1545 offset_bit_start++;
1546 }
1547 }
1548 #endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */
1549
1550 /* an unexpected value in pLockAttributes array leads to an error status */
1551 if (i != NbSuperBlocks)
1552 {
1553 return HAL_ERROR;
1554 }
1555
1556 return HAL_OK;
1557 }
1558
1559 /**
1560 * @brief Get MPCBB super-blocks lock configuration on the SRAM passed as parameter.
1561 * @param MemAddress MPCBB start-address of super-block to get configuration
1562 * (must be 16KBytes aligned).
1563 * @param NbSuperBlocks Number of super-blocks to get configuration.
1564 * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements),
1565 * with for each element:
1566 * value 0 super-block is unlocked, value 1 super-block is locked
1567 * (corresponds to GTZC_MPCBB_SUPERBLOCK_UNLOCKED and
1568 * GTZC_MPCBB_SUPERBLOCK_LOCKED values).
1569 * @retval HAL status.
1570 */
HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,uint32_t NbSuperBlocks,uint32_t * pLockAttributes)1571 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,
1572 uint32_t NbSuperBlocks,
1573 uint32_t *pLockAttributes)
1574 {
1575 __IO uint32_t *reg_mpcbb;
1576 uint32_t base_address;
1577 uint32_t superblock_start;
1578 uint32_t offset_bit_start;
1579 uint32_t i = 0U;
1580
1581 /* firstly check that MemAddress is well 16KBytes aligned */
1582 if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
1583 {
1584 return HAL_ERROR;
1585 }
1586
1587 /* check entry parameters */
1588 if ((IS_ADDRESS_IN(SRAM1, MemAddress))
1589 && (IS_ADDRESS_IN(SRAM1, (MemAddress
1590 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1591 - 1U))))
1592 {
1593 base_address = GTZC_BASE_ADDRESS(SRAM1);
1594 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->CFGLOCKR1;
1595 }
1596 else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
1597 && (IS_ADDRESS_IN(SRAM2, (MemAddress
1598 + (NbSuperBlocks
1599 * GTZC_MPCBB_SUPERBLOCK_SIZE)
1600 - 1U))))
1601 {
1602 base_address = GTZC_BASE_ADDRESS(SRAM2);
1603 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCKR1;
1604 }
1605 #if defined (SRAM3_BASE)
1606 else if ((IS_ADDRESS_IN(SRAM3, MemAddress))
1607 && (IS_ADDRESS_IN(SRAM3, (MemAddress
1608 + (NbSuperBlocks
1609 * GTZC_MPCBB_SUPERBLOCK_SIZE)
1610 - 1U))))
1611 {
1612 base_address = GTZC_BASE_ADDRESS(SRAM3);
1613 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB3_S->CFGLOCKR1;
1614 }
1615 #endif /* SRAM3_BASE */
1616 else if ((IS_ADDRESS_IN(SRAM4, MemAddress))
1617 && (IS_ADDRESS_IN(SRAM4, (MemAddress
1618 + (NbSuperBlocks
1619 * GTZC_MPCBB_SUPERBLOCK_SIZE)
1620 - 1U))))
1621 {
1622 base_address = GTZC_BASE_ADDRESS(SRAM4);
1623 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB4_S->CFGLOCKR1;
1624 }
1625 #if defined (SRAM5_BASE)
1626 else if ((IS_ADDRESS_IN(SRAM5, MemAddress))
1627 && (IS_ADDRESS_IN(SRAM5, (MemAddress
1628 + (NbSuperBlocks
1629 * GTZC_MPCBB_SUPERBLOCK_SIZE)
1630 - 1U))))
1631 {
1632 base_address = GTZC_BASE_ADDRESS(SRAM5);
1633 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB5_S->CFGLOCKR1;
1634 }
1635 #endif /* SRAM5_BASE */
1636
1637 #if defined (SRAM6_BASE)
1638 else if ((IS_ADDRESS_IN(SRAM6, MemAddress))
1639 && (IS_ADDRESS_IN(SRAM6, (MemAddress
1640 + (NbSuperBlocks
1641 * GTZC_MPCBB_SUPERBLOCK_SIZE)
1642 - 1U))))
1643 {
1644 base_address = GTZC_BASE_ADDRESS(SRAM6);
1645 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB6_S->CFGLOCKR1;
1646 }
1647 #endif /* SRAM6_BASE */
1648 else
1649 {
1650 return HAL_ERROR;
1651 }
1652
1653 /* Get start coordinates of the configuration */
1654 superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
1655 offset_bit_start = superblock_start % 32U;
1656
1657 while ((i < NbSuperBlocks) && (i < 32U) && (superblock_start < 32U))
1658 {
1659 pLockAttributes[i] = ((*reg_mpcbb) & (1UL << (offset_bit_start % 32U)))
1660 >> (offset_bit_start % 32U);
1661 offset_bit_start++;
1662 i++;
1663 }
1664
1665 #if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk)
1666 if ((NbSuperBlocks > 32U) || (superblock_start >= 32U))
1667 {
1668 /* Point to second configuration lock register */
1669 reg_mpcbb++;
1670
1671 /* Remaining super-blocks */
1672 for (; i < NbSuperBlocks; i++)
1673 {
1674 pLockAttributes[i] = ((*reg_mpcbb) & (1UL << (offset_bit_start % 32U)))
1675 >> (offset_bit_start % 32U);
1676 offset_bit_start++;
1677 }
1678 }
1679 #endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */
1680
1681 return HAL_OK;
1682 }
1683
1684 /**
1685 * @brief Lock a MPCBB configuration on the SRAM base address passed as parameter.
1686 * @note This functions locks the control register of the MPCBB until next reset.
1687 * @param MemBaseAddress MPCBB identifier.
1688 * @retval HAL status.
1689 */
HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress)1690 HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress)
1691 {
1692 /* check entry parameters */
1693 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
1694 {
1695 SET_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1696 }
1697 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
1698 {
1699 SET_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1700 }
1701 #if defined (SRAM3_BASE)
1702 else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
1703 {
1704 SET_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1705 }
1706 #endif /* SRAM3_BASE*/
1707 else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
1708 {
1709 SET_BIT(GTZC_MPCBB4_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1710 }
1711 #if defined (SRAM5_BASE)
1712 else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress))
1713 {
1714 SET_BIT(GTZC_MPCBB5_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1715 }
1716 #endif /* SRAM5_BASE */
1717 #if defined (SRAM6_BASE)
1718 else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress))
1719 {
1720 SET_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1721 }
1722 #endif /* SRAM6_BASE */
1723 else
1724 {
1725 return HAL_ERROR;
1726 }
1727
1728 return HAL_OK;
1729 }
1730
1731 /**
1732 * @brief Get MPCBB configuration lock state on the SRAM base address passed as parameter.
1733 * @param MemBaseAddress MPCBB identifier.
1734 * @param pLockState pointer to Lock State (GTZC_MPCBB_LOCK_OFF or GTZC_MPCBB_LOCK_ON).
1735 * @retval HAL status.
1736 */
HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,uint32_t * pLockState)1737 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,
1738 uint32_t *pLockState)
1739 {
1740 /* check entry parameters */
1741 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
1742 {
1743 *pLockState = READ_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1744 }
1745 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
1746 {
1747 *pLockState = READ_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1748 }
1749 #if defined (SRAM3_BASE)
1750 else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
1751 {
1752 *pLockState = READ_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1753 }
1754 #endif /* SRAM3_BASE */
1755 else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
1756 {
1757 *pLockState = READ_BIT(GTZC_MPCBB4_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1758 }
1759 #if defined (SRAM5_BASE)
1760 else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress))
1761 {
1762 *pLockState = READ_BIT(GTZC_MPCBB5_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1763 }
1764 #endif /* SRAM5_BASE */
1765 #if defined (SRAM6_BASE)
1766 else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress))
1767 {
1768 *pLockState = READ_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1769 }
1770 #endif /* SRAM6_BASE */
1771 else
1772 {
1773 return HAL_ERROR;
1774 }
1775
1776 return HAL_OK;
1777 }
1778
1779 /**
1780 * @}
1781 */
1782
1783 /** @defgroup GTZC_Exported_Functions_Group5 TZIC Configuration and Control functions
1784 * @brief TZIC Configuration and Control functions
1785 *
1786 @verbatim
1787 ==============================================================================
1788 ##### TZIC Configuration and Control functions #####
1789 ==============================================================================
1790 [..]
1791 This section provides functions allowing to configure and control TZIC
1792 TZIC is Trust Zone Interrupt Controller
1793 @endverbatim
1794 * @{
1795 */
1796
1797 /**
1798 * @brief Disable the interrupt associated to a single TZIC peripheral or on all peripherals.
1799 * @param PeriphId Peripheral identifier.
1800 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1801 * Use GTZC_PERIPH_ALL to select all peripherals.
1802 * @retval HAL status.
1803 */
HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId)1804 HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId)
1805 {
1806 uint32_t register_address;
1807
1808 /* check entry parameters */
1809 if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1810 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1811 && (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1812 {
1813 return HAL_ERROR;
1814 }
1815
1816 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1817 {
1818 /* same configuration is applied to all peripherals */
1819 WRITE_REG(GTZC_TZIC1->IER1, 0U);
1820 WRITE_REG(GTZC_TZIC1->IER2, 0U);
1821 WRITE_REG(GTZC_TZIC1->IER3, 0U);
1822 WRITE_REG(GTZC_TZIC1->IER4, 0U);
1823 WRITE_REG(GTZC_TZIC2->IER1, 0U);
1824 WRITE_REG(GTZC_TZIC2->IER2, 0U);
1825 }
1826 else
1827 {
1828 /* common case where only one peripheral is configured */
1829 register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->IER1)
1830 + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
1831 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1832 }
1833
1834 return HAL_OK;
1835 }
1836
1837 /**
1838 * @brief Enable the interrupt associated to a single TZIC peripheral or on all peripherals.
1839 * @param PeriphId Peripheral identifier.
1840 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1841 * Use GTZC_PERIPH_ALL to select all peripherals.
1842 * @retval HAL status.
1843 */
HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId)1844 HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId)
1845 {
1846 uint32_t register_address;
1847
1848 /* check entry parameters */
1849 if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1850 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1851 && (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1852 {
1853 return HAL_ERROR;
1854 }
1855
1856 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1857 {
1858 /* same configuration is applied to all peripherals */
1859 WRITE_REG(GTZC_TZIC1->IER1, TZIC1_IER1_ALL);
1860 WRITE_REG(GTZC_TZIC1->IER2, TZIC1_IER2_ALL);
1861 WRITE_REG(GTZC_TZIC1->IER3, TZIC1_IER3_ALL);
1862 WRITE_REG(GTZC_TZIC1->IER4, TZIC1_IER4_ALL);
1863 WRITE_REG(GTZC_TZIC2->IER1, TZIC2_IER1_ALL);
1864 WRITE_REG(GTZC_TZIC2->IER2, TZIC2_IER2_ALL);
1865 }
1866 else
1867 {
1868 /* common case where only one peripheral is configured */
1869 register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->IER1)
1870 + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
1871 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1872 }
1873
1874 return HAL_OK;
1875 }
1876
1877 /**
1878 * @brief Get TZIC flag on a single TZIC peripheral or on all peripherals.
1879 * @param PeriphId Peripheral identifier.
1880 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1881 * Use GTZC_PERIPH_ALL to select all peripherals.
1882 * @param pFlag Pointer to the flags.
1883 * If PeriphId target a single peripheral, pointer on a single element.
1884 * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array
1885 * of GTZC_TZIC_PERIPH_NUMBER elements.
1886 * Element content is either GTZC_TZIC_NO_ILA_EVENT
1887 * or GTZC_TZSC_ILA_EVENT_PENDING.
1888 * @retval HAL status
1889 */
HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId,uint32_t * pFlag)1890 HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag)
1891 {
1892 uint32_t i;
1893 uint32_t reg_value;
1894 uint32_t register_address;
1895
1896 /* check entry parameters */
1897 if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1898 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1899 && (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1900 {
1901 return HAL_ERROR;
1902 }
1903
1904 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1905 {
1906 /* special case where it is applied to all peripherals */
1907 reg_value = READ_REG(GTZC_TZIC1->SR1);
1908 for (i = 0U; i < REG_SIZE; i++)
1909 {
1910 pFlag[i] = (reg_value & (1UL << i)) >> i;
1911 }
1912
1913 reg_value = READ_REG(GTZC_TZIC1->SR2);
1914 for (i = REG_SIZE; i < (2U * REG_SIZE); i++)
1915 {
1916 pFlag[i] = (reg_value & (1UL << (i - 32U))) >> (i - 32U);
1917 }
1918
1919 reg_value = READ_REG(GTZC_TZIC1->SR3);
1920 for (i = 2U * REG_SIZE; i < (3U * REG_SIZE); i++)
1921 {
1922 pFlag[i] = (reg_value & (1UL << (i - 64U))) >> (i - 64U);
1923 }
1924
1925 reg_value = READ_REG(GTZC_TZIC1->SR4);
1926 for (i = 3U * REG_SIZE; i < (4U * REG_SIZE); i++)
1927 {
1928 pFlag[i] = (reg_value & (1UL << (i - 96U))) >> (i - 96U);
1929 }
1930
1931 reg_value = READ_REG(GTZC_TZIC2->SR1);
1932 for (i = 4U * REG_SIZE; i < (5U * REG_SIZE); i++)
1933 {
1934 pFlag[i] = (reg_value & (1UL << (i - 128U))) >> (i - 128U);
1935 }
1936
1937 reg_value = READ_REG(GTZC_TZIC2->SR2);
1938 for (i = 5U * REG_SIZE; i < GTZC_TZIC_PERIPH_NUMBER; i++)
1939 {
1940 pFlag[i] = (reg_value & (1UL << (i - 160U))) >> (i - 160U);
1941 }
1942 }
1943 else
1944 {
1945 /* common case where only one peripheral is concerned */
1946 register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->SR1)
1947 + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
1948 *pFlag = READ_BIT(*(__IO uint32_t *)register_address,
1949 1UL << GTZC_GET_PERIPH_POS(PeriphId)) >> GTZC_GET_PERIPH_POS(PeriphId);
1950 }
1951
1952 return HAL_OK;
1953 }
1954
1955 /**
1956 * @brief Clear TZIC flag on a single TZIC peripheral or on all peripherals.
1957 * @param PeriphId Peripheral identifier.
1958 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1959 * Use GTZC_PERIPH_ALL to select all peripherals.
1960 * @retval HAL status.
1961 */
HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId)1962 HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId)
1963 {
1964 uint32_t register_address;
1965
1966 /* check entry parameters */
1967 if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1968 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1969 && (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1970 {
1971 return HAL_ERROR;
1972 }
1973
1974 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1975 {
1976 /* same configuration is applied to all peripherals */
1977 WRITE_REG(GTZC_TZIC1->FCR1, TZIC1_FCR1_ALL);
1978 WRITE_REG(GTZC_TZIC1->FCR2, TZIC1_FCR2_ALL);
1979 WRITE_REG(GTZC_TZIC1->FCR3, TZIC1_FCR3_ALL);
1980 WRITE_REG(GTZC_TZIC1->FCR4, TZIC1_FCR4_ALL);
1981 WRITE_REG(GTZC_TZIC2->FCR1, TZIC2_FCR1_ALL);
1982 WRITE_REG(GTZC_TZIC2->FCR2, TZIC2_FCR2_ALL);
1983 }
1984 else
1985 {
1986 /* common case where only one peripheral is configured */
1987 register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->FCR1)
1988 + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
1989 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1990 }
1991
1992 return HAL_OK;
1993 }
1994
1995 /**
1996 * @}
1997 */
1998
1999 /** @defgroup GTZC_Exported_Functions_Group6 IRQ related functions
2000 * @brief IRQ related functions
2001 *
2002 @verbatim
2003 ==============================================================================
2004 ##### TZIC IRQ Handler and Callback functions #####
2005 ==============================================================================
2006 [..]
2007 This section provides functions allowing to treat ISR and provide user callback
2008 @endverbatim
2009 * @{
2010 */
2011
2012 /**
2013 * @brief This function handles GTZC TZIC interrupt request.
2014 * @retval None.
2015 */
HAL_GTZC_IRQHandler(void)2016 void HAL_GTZC_IRQHandler(void)
2017 {
2018 uint32_t position;
2019 uint32_t flag;
2020 uint32_t ier_itsources;
2021 uint32_t sr_flags;
2022
2023 /*********************************************************************/
2024 /****************************** TZIC1 ******************************/
2025 /*********************************************************************/
2026
2027 /* Get current IT Flags and IT sources value on 1st register of TZIC1 */
2028 ier_itsources = READ_REG(GTZC_TZIC1_S->IER1);
2029 sr_flags = READ_REG(GTZC_TZIC1_S->SR1);
2030
2031 /* Get Mask interrupt and then clear them */
2032 flag = ier_itsources & sr_flags;
2033 if (flag != 0U)
2034 {
2035 WRITE_REG(GTZC_TZIC1_S->FCR1, flag);
2036
2037 /* Loop on flag to check, which ones have been raised */
2038 position = 0U;
2039 while ((flag >> position) != 0U)
2040 {
2041 if ((flag & (1UL << position)) != 0U)
2042 {
2043 HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG1 | position);
2044 }
2045
2046 /* Position bit to be updated */
2047 position++;
2048 }
2049 }
2050
2051 /* Get current IT Flags and IT sources value on 2nd register of TZIC1 */
2052 ier_itsources = READ_REG(GTZC_TZIC1_S->IER2);
2053 sr_flags = READ_REG(GTZC_TZIC1_S->SR2);
2054
2055 /* Get Mask interrupt and then clear them */
2056 flag = ier_itsources & sr_flags;
2057 if (flag != 0U)
2058 {
2059 WRITE_REG(GTZC_TZIC1_S->FCR2, flag);
2060
2061 /* Loop on flag to check, which ones have been raised */
2062 position = 0U;
2063 while ((flag >> position) != 0U)
2064 {
2065 if ((flag & (1UL << position)) != 0U)
2066 {
2067 HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG2 | position);
2068 }
2069
2070 /* Position bit to be updated */
2071 position++;
2072 }
2073 }
2074
2075 /* Get current IT Flags and IT sources value on 3rd register of TZIC1 */
2076 ier_itsources = READ_REG(GTZC_TZIC1_S->IER3);
2077 sr_flags = READ_REG(GTZC_TZIC1_S->SR3);
2078
2079 /* Get Mask interrupt and then clear them */
2080 flag = ier_itsources & sr_flags;
2081 if (flag != 0U)
2082 {
2083 WRITE_REG(GTZC_TZIC1_S->FCR3, flag);
2084
2085 /* Loop on flag to check, which ones have been raised */
2086 position = 0U;
2087 while ((flag >> position) != 0U)
2088 {
2089 if ((flag & (1UL << position)) != 0U)
2090 {
2091 HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG3 | position);
2092 }
2093
2094 /* Position bit to be updated */
2095 position++;
2096 }
2097 }
2098
2099 /* Get current IT Flags and IT sources value on 4th register of TZIC1 */
2100 ier_itsources = READ_REG(GTZC_TZIC1_S->IER4);
2101 sr_flags = READ_REG(GTZC_TZIC1_S->SR4);
2102
2103 /* Get Mask interrupt and then clear them */
2104 flag = ier_itsources & sr_flags;
2105 if (flag != 0U)
2106 {
2107 WRITE_REG(GTZC_TZIC1_S->FCR4, flag);
2108
2109 /* Loop on flag to check, which ones have been raised */
2110 position = 0U;
2111 while ((flag >> position) != 0U)
2112 {
2113 if ((flag & (1UL << position)) != 0U)
2114 {
2115 HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG4 | position);
2116 }
2117
2118 /* Position bit to be updated */
2119 position++;
2120 }
2121 }
2122
2123 /*********************************************************************/
2124 /****************************** TZIC2 ******************************/
2125 /*********************************************************************/
2126
2127 /* Get current IT Flags and IT sources value on 1st register of TZIC2 */
2128 ier_itsources = READ_REG(GTZC_TZIC2_S->IER1);
2129 sr_flags = READ_REG(GTZC_TZIC2_S->SR1);
2130
2131 /* Get Mask interrupt and then clear them */
2132 flag = ier_itsources & sr_flags;
2133 if (flag != 0U)
2134 {
2135 WRITE_REG(GTZC_TZIC2_S->FCR1, flag);
2136
2137 /* Loop on flag to check, which ones have been raised */
2138 position = 0U;
2139 while ((flag >> position) != 0U)
2140 {
2141 if ((flag & (1UL << position)) != 0U)
2142 {
2143 HAL_GTZC_TZIC_Callback(GTZC2_PERIPH_REG1 | position);
2144 }
2145
2146 /* Position bit to be updated */
2147 position++;
2148 }
2149 }
2150
2151 /* Get current IT Flags and IT sources value on 2nd register of TZIC2 */
2152 ier_itsources = READ_REG(GTZC_TZIC2_S->IER2);
2153 sr_flags = READ_REG(GTZC_TZIC2_S->SR2);
2154
2155 /* Get Mask interrupt and then clear them */
2156 flag = ier_itsources & sr_flags;
2157 if (flag != 0U)
2158 {
2159 WRITE_REG(GTZC_TZIC2_S->FCR2, flag);
2160
2161 /* Loop on flag to check, which ones have been raised */
2162 position = 0U;
2163 while ((flag >> position) != 0U)
2164 {
2165 if ((flag & (1UL << position)) != 0U)
2166 {
2167 HAL_GTZC_TZIC_Callback(GTZC2_PERIPH_REG2 | position);
2168 }
2169
2170 /* Position bit to be updated */
2171 position++;
2172 }
2173 }
2174 }
2175
2176 /**
2177 * @brief GTZC TZIC sub-block interrupt callback.
2178 * @param PeriphId Peripheral identifier triggering the illegal access.
2179 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId
2180 * @retval None.
2181 */
HAL_GTZC_TZIC_Callback(uint32_t PeriphId)2182 __weak void HAL_GTZC_TZIC_Callback(uint32_t PeriphId)
2183 {
2184 /* Prevent unused argument(s) compilation warning */
2185 UNUSED(PeriphId);
2186
2187 /* NOTE: This function should not be modified. When the callback is needed,
2188 * the HAL_GTZC_TZIC_Callback is to be implemented in the user file
2189 */
2190 }
2191
2192 /**
2193 * @}
2194 */
2195
2196 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2197
2198 /**
2199 * @}
2200 */
2201
2202 #endif /*HAL_GTZC_MODULE_ENABLED*/
2203
2204 /**
2205 * @}
2206 */
2207
2208 /**
2209 * @}
2210 */
2211
