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Searched refs:QUADSPI_CCR_DCYC_Pos (Results 1 – 25 of 90) sorted by relevance

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/hal_stm32-3.5.0/stm32cube/stm32wbxx/drivers/src/
Dstm32wbxx_hal_qspi.c2614 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2630 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2643 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2658 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2676 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2692 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2704 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2721 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
/hal_stm32-3.5.0/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_qspi.c2533 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2549 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2562 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2577 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2595 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2611 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2623 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2640 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
/hal_stm32-3.5.0/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_hal_qspi.c2782 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2798 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2811 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2826 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2844 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2860 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2872 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2889 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
/hal_stm32-3.5.0/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_hal_qspi.c2594 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2610 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2623 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2638 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2656 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2672 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2684 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2701 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
/hal_stm32-3.5.0/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_hal_qspi.c2647 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2663 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2676 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2691 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2709 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2725 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2737 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2754 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
/hal_stm32-3.5.0/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_hal_qspi.c2707 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2723 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2736 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2751 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2769 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2785 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2797 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2814 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
/hal_stm32-3.5.0/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_hal_qspi.c2689 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2705 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2718 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2733 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2751 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2767 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2779 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
2796 … cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | in QSPI_Config()
/hal_stm32-3.5.0/stm32cube/stm32f4xx/soc/
Dstm32f423xx.h9426 #define QUADSPI_CCR_DCYC_Pos (18U) macro
9427 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
9429 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
9430 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
9431 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
9432 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
9433 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
Dstm32f412rx.h9150 #define QUADSPI_CCR_DCYC_Pos (18U) macro
9151 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
9153 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
9154 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
9155 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
9156 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
9157 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
Dstm32f412zx.h9156 #define QUADSPI_CCR_DCYC_Pos (18U) macro
9157 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
9159 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
9160 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
9161 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
9162 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
9163 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
Dstm32f412vx.h9152 #define QUADSPI_CCR_DCYC_Pos (18U) macro
9153 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
9155 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
9156 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
9157 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
9158 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
9159 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
Dstm32f413xx.h9390 #define QUADSPI_CCR_DCYC_Pos (18U) macro
9391 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
9393 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
9394 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
9395 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
9396 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
9397 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
Dstm32f446xx.h9961 #define QUADSPI_CCR_DCYC_Pos (18U) macro
9962 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
9964 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
9965 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
9966 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
9967 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
9968 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
/hal_stm32-3.5.0/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h9046 #define QUADSPI_CCR_DCYC_Pos (18U) macro
9047 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
9049 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
9050 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
9051 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
9052 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
9053 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
Dstm32f722xx.h9030 #define QUADSPI_CCR_DCYC_Pos (18U) macro
9031 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
9033 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
9034 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
9035 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
9036 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
9037 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
Dstm32f730xx.h9260 #define QUADSPI_CCR_DCYC_Pos (18U) macro
9261 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
9263 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
9264 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
9265 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
9266 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
9267 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
Dstm32f732xx.h9244 #define QUADSPI_CCR_DCYC_Pos (18U) macro
9245 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
9247 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
9248 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
9249 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
9250 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
9251 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
Dstm32f733xx.h9260 #define QUADSPI_CCR_DCYC_Pos (18U) macro
9261 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
9263 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
9264 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
9265 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
9266 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
9267 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
Dstm32f745xx.h9827 #define QUADSPI_CCR_DCYC_Pos (18U) macro
9828 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
9830 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
9831 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
9832 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
9833 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
9834 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
Dstm32f746xx.h10166 #define QUADSPI_CCR_DCYC_Pos (18U) macro
10167 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
10169 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
10170 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
10171 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
10172 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
10173 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
Dstm32f750xx.h10441 #define QUADSPI_CCR_DCYC_Pos (18U) macro
10442 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
10444 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
10445 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
10446 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
10447 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
10448 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
Dstm32f756xx.h10441 #define QUADSPI_CCR_DCYC_Pos (18U) macro
10442 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
10444 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
10445 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
10446 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
10447 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
10448 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
Dstm32f765xx.h10334 #define QUADSPI_CCR_DCYC_Pos (18U) macro
10335 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
10337 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
10338 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
10339 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
10340 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
10341 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
Dstm32f767xx.h10710 #define QUADSPI_CCR_DCYC_Pos (18U) macro
10711 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
10713 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
10714 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
10715 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
10716 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
10717 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
Dstm32f777xx.h10985 #define QUADSPI_CCR_DCYC_Pos (18U) macro
10986 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
10988 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
10989 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
10990 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
10991 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
10992 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */

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