1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL SYSTEM driver contains a set of generic APIs that can be
12 used by user:
13 (+) Some of the FLASH features need to be handled in the SYSTEM file.
14 (+) Access to DBGCMU registers
15 (+) Access to SBS registers
16 (+) Access to VREFBUF registers
17 @endverbatim
18 ******************************************************************************
19 * @attention
20 *
21 * Copyright (c) 2022 STMicroelectronics.
22 * All rights reserved.
23 *
24 * This software is licensed under terms that can be found in the LICENSE file
25 * in the root directory of this software component.
26 * If no LICENSE file comes with this software, it is provided AS-IS.
27 *
28 ******************************************************************************
29 */
30
31 /* Define to prevent recursive inclusion -------------------------------------*/
32 #ifndef STM32H5xx_LL_SYSTEM_H
33 #define STM32H5xx_LL_SYSTEM_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /* Includes ------------------------------------------------------------------*/
40 #include "stm32h5xx.h"
41
42 /** @addtogroup STM32H5xx_LL_Driver
43 * @{
44 */
45
46 #if defined (FLASH) || defined (SBS) || defined (DBGMCU) || defined (VREFBUF)
47
48 /** @defgroup SYSTEM_LL SYSTEM
49 * @{
50 */
51
52 /* Private types -------------------------------------------------------------*/
53 /* Private variables ---------------------------------------------------------*/
54
55 /* Private constants ---------------------------------------------------------*/
56 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
57 * @{
58 */
59 #define LL_SBS_HDPL_INCREMENT_VALUE 0x6AU /*!< Define used for the HDPL increment */
60 #define LL_SBS_DBG_UNLOCK (0xB4U << SBS_DBGCR_DBG_UNLOCK_Pos) /*!< Define used to unlock debug */
61 #define LL_SBS_ACCESS_PORT_UNLOCK 0xB4U /*!< Define used to unlock access port */
62 #define LL_SBS_DBG_CONFIG_LOCK 0xC3U /*!< Define used to lock debug configuration */
63 #define LL_SBS_DBG_CONFIG_UNLOCK 0xB4U /*!< Define used to unlock debug configuration */
64 #define LL_SBS_DEBUG_SEC_NSEC 0xB4U /*!< Define used to open debug for secure and non-secure */
65 #define LL_SBS_DEBUG_NSEC 0x3CU /*!< Define used to open debug for non-secure only */
66 /**
67 * @}
68 */
69
70 /* Private macros ------------------------------------------------------------*/
71
72 /* Exported types ------------------------------------------------------------*/
73 /* Exported constants --------------------------------------------------------*/
74 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
75 * @{
76 */
77
78 /** @defgroup SYSTEM_LL_EC_FASTMODEPLUS SBS FASTMODEPLUS
79 * @{
80 */
81 #define LL_SBS_FASTMODEPLUS_PB6 SBS_PMCR_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
82 #define LL_SBS_FASTMODEPLUS_PB7 SBS_PMCR_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
83 #define LL_SBS_FASTMODEPLUS_PB8 SBS_PMCR_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
84 #if defined(SBS_PMCR_PB9_FMP)
85 #define LL_SBS_FASTMODEPLUS_PB9 SBS_PMCR_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
86 #endif /* SBS_PMCR_PB9_FMP */
87 /**
88 * @}
89 */
90
91 /** @defgroup SYSTEM_LL_EC_CS1 SBS Vdd compensation cell Code selection
92 * @{
93 */
94 #define LL_SBS_VDD_CELL_CODE 0x0UL /*!< VDD I/Os code from the cell (available in the SBS_CCVALR) */
95 #define LL_SBS_VDD_REGISTER_CODE SBS_CCCSR_CS1 /*!< VDD I/Os code from the SBS compensation cell code register (SBS_CCSWCR) */
96 /**
97 * @}
98 */
99
100 /** @defgroup SYSTEM_LL_EC_CS2 SBS VddIO compensation cell Code selection
101 * @{
102 */
103 #define LL_SBS_VDDIO_CELL_CODE 0x0UL /*!< VDDIO I/Os code from the cell (available in the SBS_CCVALR)*/
104 #define LL_SBS_VDDIO_REGISTER_CODE SBS_CCCSR_CS2 /*!< VDDIO I/Os code from the SBS compensation cell code register (SBS_CCSWCR)*/
105 /**
106 * @}
107 */
108
109 #if defined(SBS_PMCR_ETH_SEL_PHY)
110 /** @defgroup SYSTEM_LL_ETHERNET_CONFIG ETHENET CONFIG
111 * @{
112 */
113 #define LL_SBS_ETH_MII 0x0UL /*!< Select the Media Independent Interface (MII) or GMII */
114 #define LL_SBS_ETH_RMII SBS_PMCR_ETH_SEL_PHY_2 /*!< Select the Reduced Media Independent Interface (RMII) */
115
116 /**
117 * @}
118 */
119 #endif /* SBS_PMCR_ETH_SEL_PHY */
120
121 /** @defgroup SYSTEM_LL_BOOSTVDD_SEL Boost VDD Selection
122 * @{
123 */
124 #define LL_SBS_BOOSTVDDSEL_VDDA 0x0UL /*!< Select VDDA as analog switch supply voltage (when BOOSTEN bit is cleared) */
125 #define LL_SBS_BOOSTVDDSEL_VDD SBS_PMCR_BOOSTVDDSEL /*!< Select VDD as analog switch supply voltage (regardless of BOOSTEN bit) */
126
127 /**
128 * @}
129 */
130
131 /** @defgroup SYSTEM_Memories_Erase_Flag_Status Memories Erase Flags Status
132 * @{
133 */
134 #define LL_SBS_MEMORIES_ERASE_MCLR_ON_GOING 0x0UL /*!< Erase after Power-on Reset of SRAM2, BKPRAM, ICACHE, DCACHE and PKA RAMs on going or cleared by SW */
135 #define LL_SBS_MEMORIES_ERASE_MCLR_ENDED SBS_MESR_MCLR /*!< Erase after Power-on Reset of SRAM2, BKPRAM, ICACHE, DCACHE and PKA RAMs done */
136 #define LL_SBS_MEMORIES_ERASE_IPMEE_ON_GOING 0x0UL /*!< Erase after Power-on Reset or Tamper detection for ICACHE and PKA RAMs on going or cleared by SW */
137 #define LL_SBS_MEMORIES_ERASE_IPMEE_ENDED SBS_MESR_IPMEE /*!< Erase after Power-on Reset or Tamper detection for ICACHE and PKA RAMs done */
138 /**
139 * @}
140 */
141
142 /** @defgroup SYSTEM_LL_EC_TIMBREAK SBS TIMER BREAK
143 * @{
144 */
145 #define LL_SBS_TIMBREAK_ECC SBS_CFGR2_ECCL /*!< Enables and locks the Flash ECC double error signal
146 with Break Input of TIM1/8/15/16/17 */
147 #define LL_SBS_TIMBREAK_PVD SBS_CFGR2_PVDL /*!< Enables and locks the PVD connection
148 with TIM1/8/15/16/17 Break Input and also the PVDE
149 and PLS bits of the Power Control Interface */
150 #define LL_SBS_TIMBREAK_SRAM_ECC SBS_CFGR2_SEL /*!< Enables and locks the SRAM ECC double error signal
151 with Break Input of TIM1/8/15/16/17 */
152 #define LL_SBS_TIMBREAK_LOCKUP SBS_CFGR2_CLL /*!< Enables and locks the LOCKUP (Hardfault) output of
153 Cortex-M33 with Break Input of TIM1/15/16/17 */
154 /**
155 * @}
156 */
157
158
159 /** @defgroup SYSTEM_LL_EPOCH_Selection EPOCH Selection
160 * @{
161 */
162 #define LL_SBS_EPOCH_SEL_SECURE 0x0UL /*!< EPOCH secure selected */
163 #define LL_SBS_EPOCH_SEL_NONSECURE SBS_EPOCHSELCR_EPOCH_SEL_0 /*!< EPOCH non secure selected */
164 #define LL_SBS_EPOCH_SEL_PUFCHECK SBS_EPOCHSELCR_EPOCH_SEL_1 /*!< EPOCH all zeros for PUF integrity check */
165
166 /**
167 * @}
168 */
169
170 /** @defgroup SYSTEM_LL_SBS_NextHDPL_Selection Next HDPL Selection
171 * @{
172 */
173 #define LL_SBS_OBKHDPL_INCR_0 0x00000000U /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */
174 #define LL_SBS_OBKHDPL_INCR_1 SBS_NEXTHDPLCR_NEXTHDPL_0 /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */
175 #define LL_SBS_OBKHDPL_INCR_2 SBS_NEXTHDPLCR_NEXTHDPL_1 /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */
176 #define LL_SBS_OBKHDPL_INCR_3 SBS_NEXTHDPLCR_NEXTHDPL /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */
177 /**
178 * @}
179 */
180
181 /** @defgroup SYSTEM_LL_SBS_HDPL_Value HDPL Value
182 * @{
183 */
184 #define LL_SBS_HDPL_VALUE_0 0x000000B4U /*!< Hide protection level 0 */
185 #define LL_SBS_HDPL_VALUE_1 0x00000051U /*!< Hide protection level 1 */
186 #define LL_SBS_HDPL_VALUE_2 0x0000008AU /*!< Hide protection level 2 */
187 #define LL_SBS_HDPL_VALUE_3 0x0000006FU /*!< Hide protection level 3 */
188 /**
189 * @}
190 */
191
192 /** @defgroup SYSTEM_LL_NS_Lock_items Lock items
193 * @brief SBS non secure items to set lock on
194 * @{
195 */
196 #define LL_SBS_MPU_NSEC SBS_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or non-secure only) */
197 #define LL_SBS_VTOR_NSEC SBS_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or non-secure only) */
198 #define LL_SBS_LOCK_ALL_NSEC (LL_SBS_MPU_NSEC | LL_SBS_VTOR_NSEC) /*!< lock all Non-secure (privileged secure or non-secure only) */
199 /**
200 * @}
201 */
202
203 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
204 /** @defgroup SYSTEM_LL_S_Lock_items SBS Lock items
205 * @brief SBS secure items to set lock on
206 * @{
207 */
208 #define LL_SBS_SAU SBS_CSLCKR_LOCKSAU /*!< SAU lock (privileged secure code only) */
209 #define LL_SBS_MPU_SEC SBS_CSLCKR_LOCKSMPU /*!< Secure MPU lock (privileged secure code only) */
210 #define LL_SBS_VTOR_AIRCR_SEC SBS_CSLCKR_LOCKSVTAIRCR /*!< VTOR_S and AIRCR lock (privileged secure code only) */
211 #define LL_SBS_LOCK_ALL_SEC (LL_SBS_SAU | LL_SBS_MPU_SEC | LL_SBS_VTOR_AIRCR_SEC) /*!< lock all secure (privileged secure only) */
212 /**
213 * @}
214 */
215
216 /** @defgroup SYSTEM_LL_EC_SECURE_ATTRIBUTES Secure attributes
217 * @note Only available when system implements security (TZEN=1)
218 * @{
219 */
220 #define LL_SBS_CLOCK_SEC SBS_SECCFGR_SBSSEC /*!< SBS clock configuration secure-only access */
221 #define LL_SBS_CLOCK_NSEC 0U /*!< SBS clock configuration secure/non-secure access */
222 #define LL_SBS_CLASSB_SEC SBS_SECCFGR_CLASSBSEC /*!< Class B configuration secure-only access */
223 #define LL_SBS_CLASSB_NSEC 0U /*!< Class B configuration secure/non-secure access */
224 #define LL_SBS_FPU_SEC SBS_SECCFGR_FPUSEC /*!< FPU configuration secure-only access */
225 #define LL_SBS_FPU_NSEC 0U /*!< FPU configuration secure/non-secure access */
226 #define LL_SBS_SMPS_SEC SBS_SECCFGR_SDCE_SEC_EN /*!< SMPS configuration secure-only access */
227 #define LL_SBS_SMPS_NSEC 0U /*!< SMPS configuration secure/non-secure access */
228 /**
229 * @}
230 */
231 #endif /* __ARM_FEATURE_CMSE */
232
233 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
234 * @{
235 */
236 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
237 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
238 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
239 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
240 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
241 /**
242 * @}
243 */
244
245 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
246 * @{
247 */
248 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/
249 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/
250 #if defined(TIM4)
251 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when the core is halted*/
252 #endif /* TIM4 */
253 #if defined(TIM5)
254 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /*!< The counter clock of TIM5 is stopped when the core is halted*/
255 #endif /* TIM5 */
256 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /*!< The counter clock of TIM6 is stopped when the core is halted*/
257 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /*!< The counter clock of TIM7 is stopped when the core is halted*/
258 #if defined(TIM12)
259 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1FZR1_DBG_TIM12_STOP /*!< The counter clock of TIM12 is stopped when the core is halted*/
260 #endif /* TIM12 */
261 #if defined(TIM13)
262 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1FZR1_DBG_TIM13_STOP /*!< The counter clock of TIM13 is stopped when the core is halted*/
263 #endif /* TIM13 */
264 #if defined(TIM14)
265 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1FZR1_DBG_TIM14_STOP /*!< The counter clock of TIM14 is stopped when the core is halted*/
266 #endif /* TIM14 */
267 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/
268 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/
269 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/
270 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/
271 #define LL_DBGMCU_APB1_GRP1_I3C1_STOP DBGMCU_APB1FZR1_DBG_I3C1_STOP /*!< The I3C1 SMBus timeout is frozen*/
272 /**
273 * @}
274 */
275
276 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
277 * @{
278 */
279 #define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/
280 /**
281 * @}
282 */
283
284 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
285 * @{
286 */
287 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted*/
288 #if defined(TIM8)
289 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP /*!< The counter clock of TIM8 is stopped when the core is halted*/
290 #endif /* TIM8 */
291 #if defined(TIM15)
292 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP /*!< The counter clock of TIM15 is stopped when the core is halted*/
293 #endif /* TIM15 */
294 #if defined(TIM16)
295 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted*/
296 #endif /* TIM16 */
297 #if defined(TIM17)
298 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted*/
299 #endif /* TIM17 */
300 /**
301 * @}
302 */
303
304 /** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP
305 * @{
306 */
307 #if defined(I2C3)
308 #define LL_DBGMCU_APB3_GRP1_I2C3_STOP DBGMCU_APB3FZR_DBG_I2C3_STOP /*!< The counter clock of I2C3 is stopped when the core is halted*/
309 #endif /* I2C3 */
310 #if defined(I2C4)
311 #define LL_DBGMCU_APB3_GRP1_I2C4_STOP DBGMCU_APB3FZR_DBG_I2C4_STOP /*!< The counter clock of I2C4 is stopped when the core is halted*/
312 #endif /* I2C4 */
313 #if defined(I3C2)
314 #define LL_DBGMCU_APB3_GRP1_I3C2_STOP DBGMCU_APB3FZR_DBG_I3C2_STOP /*!< The counter clock of I3C2 is stopped when the core is halted*/
315 #endif /* I3C2 */
316 #define LL_DBGMCU_APB3_GRP1_LPTIM1_STOP DBGMCU_APB3FZR_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
317 #if defined(LPTIM3)
318 #define LL_DBGMCU_APB3_GRP1_LPTIM3_STOP DBGMCU_APB3FZR_DBG_LPTIM3_STOP /*!< The counter clock of LPTIM3 is stopped when the core is halted*/
319 #endif /* LPTIM3 */
320 #if defined(LPTIM4)
321 #define LL_DBGMCU_APB3_GRP1_LPTIM4_STOP DBGMCU_APB3FZR_DBG_LPTIM4_STOP /*!< The counter clock of LPTIM4 is stopped when the core is halted*/
322 #endif /* LPTIM4 */
323 #if defined(LPTIM5)
324 #define LL_DBGMCU_APB3_GRP1_LPTIM5_STOP DBGMCU_APB3FZR_DBG_LPTIM5_STOP /*!< The counter clock of LPTIM5 is stopped when the core is halted*/
325 #endif /* LPTIM5 */
326 #if defined(LPTIM6)
327 #define LL_DBGMCU_APB3_GRP1_LPTIM6_STOP DBGMCU_APB3FZR_DBG_LPTIM6_STOP /*!< The counter clock of LPTIM6 is stopped when the core is halted*/
328 #endif /* LPTIM6 */
329 #define LL_DBGMCU_APB3_GRP1_RTC_STOP DBGMCU_APB3FZR_DBG_RTC_STOP /*!< The counter clock of RTC is stopped when the core is halted*/
330 /**
331 * @}
332 */
333
334
335 #if defined(VREFBUF)
336 /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
337 * @{
338 */
339 #define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
340 #define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */
341 #define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREF_OUT3) */
342 #define LL_VREFBUF_VOLTAGE_SCALE3 (VREFBUF_CSR_VRS_0 | VREFBUF_CSR_VRS_1) /*!< Voltage reference scale 3 (VREF_OUT4) */
343 /**
344 * @}
345 */
346 #endif /* VREFBUF */
347
348 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
349 * @{
350 */
351 #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH zero wait state */
352 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH one wait state */
353 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH two wait states */
354 #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH three wait states */
355 #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH four wait states */
356 #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait states */
357 #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
358 #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */
359 #define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */
360 #define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */
361 #define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */
362 #define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */
363 #define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */
364 #define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */
365 #define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */
366 #define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */
367 /**
368 * @}
369 */
370
371 /**
372 * @}
373 */
374
375 /* Exported macro ------------------------------------------------------------*/
376
377 /* Exported functions --------------------------------------------------------*/
378 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
379 * @{
380 */
381
382 /** @defgroup SYSTEM_LL_EF_SBS SBS
383 * @{
384 */
385
386 #if defined(SBS_PMCR_ETH_SEL_PHY)
387 /**
388 * @brief Select Ethernet PHY interface
389 * @rmtoll PMCR EPIS_SEL LL_SBS_SetPHYInterface
390 * @param Interface This parameter can be one of the following values:
391 * @arg @ref LL_SBS_ETH_MII
392 * @arg @ref LL_SBS_ETH_RMII
393 * @retval None
394 */
LL_SBS_SetPHYInterface(uint32_t Interface)395 __STATIC_INLINE void LL_SBS_SetPHYInterface(uint32_t Interface)
396 {
397 MODIFY_REG(SBS->PMCR, SBS_PMCR_ETH_SEL_PHY, Interface);
398 }
399
400 /**
401 * @brief Get Ethernet PHY interface
402 * @rmtoll PMCR EPIS_SEL LL_SBS_GetPHYInterface
403 * @retval Returned value can be one of the following values:
404 * @arg @ref LL_SBS_ETH_MII
405 * @arg @ref LL_SBS_ETH_RMII
406 */
LL_SBS_GetPHYInterface(void)407 __STATIC_INLINE uint32_t LL_SBS_GetPHYInterface(void)
408 {
409 return (uint32_t)(READ_BIT(SBS->PMCR, SBS_PMCR_ETH_SEL_PHY));
410 }
411 #endif /* SBS_PMCR_ETH_SEL_PHY */
412
413 /**
414 * @brief Enable I/O analog switch voltage booster.
415 * @note When voltage booster is enabled, I/O analog switches are supplied
416 * by a dedicated voltage booster, from VDD power domain. This is
417 * the recommended configuration with low VDDA voltage operation.
418 * @note The I/O analog switch voltage booster is relevant for peripherals
419 * using I/O in analog input: ADC, COMP, OPAMP.
420 * However, COMP and OPAMP inputs have a high impedance and
421 * voltage booster do not impact performance significantly.
422 * Therefore, the voltage booster is mainly intended for
423 * usage with ADC.
424 * @rmtoll PMCR BOOSTEN LL_SBS_EnableAnalogBooster
425 * @retval None
426 */
LL_SBS_EnableAnalogBooster(void)427 __STATIC_INLINE void LL_SBS_EnableAnalogBooster(void)
428 {
429 SET_BIT(SBS->PMCR, SBS_PMCR_BOOSTEN);
430 }
431
432
433 /**
434 * @brief Analog switch supply voltage selection (VDD/VDDA/booster)
435 * @rmtoll PMCR SBS_PMCR_BOOSTVDDSEL LL_SBS_AnalogSwitchSupplyVoltageSelection
436 * @param BoostVddSelection: Selects the Analog switch supply voltage (VDD/VDDA/booster)
437 * This parameter can be one of the following values:
438 * @arg LL_SBS_BOOSTVDDSEL_VDDA : Select the VDDA as analog switch supply voltage (when BOOSTEN bit is cleared).
439 * @arg LL_SBS_BOOSTVDDSEL_VDD: Select the VDD as analog switch supply voltage.
440 * @retval None
441 */
LL_SBS_AnalogSwitchSupplyVoltageSelection(uint32_t BoostVddSelection)442 __STATIC_INLINE void LL_SBS_AnalogSwitchSupplyVoltageSelection(uint32_t BoostVddSelection)
443 {
444 MODIFY_REG(SBS->PMCR, SBS_PMCR_BOOSTVDDSEL, BoostVddSelection);
445 }
446
447
448 /**
449 * @brief Disable I/O analog switch voltage booster.
450 * @note When voltage booster is enabled, I/O analog switches are supplied
451 * by a dedicated voltage booster, from VDD power domain. This is
452 * the recommended configuration with low VDDA voltage operation.
453 * @note The I/O analog switch voltage booster is relevant for peripherals
454 * using I/O in analog input: ADC, COMP, OPAMP.
455 * However, COMP and OPAMP inputs have a high impedance and
456 * voltage booster do not impact performance significantly.
457 * Therefore, the voltage booster is mainly intended for
458 * usage with ADC.
459 * @rmtoll PMCR BOOSTEN LL_SBS_DisableAnalogBooster
460 * @retval None
461 */
LL_SBS_DisableAnalogBooster(void)462 __STATIC_INLINE void LL_SBS_DisableAnalogBooster(void)
463 {
464 CLEAR_BIT(SBS->PMCR, SBS_PMCR_BOOSTEN);
465 }
466
467 /**
468 * @brief Enable the fast mode plus driving capability.
469 * @rmtoll PMCR PBx_FMP LL_SBS_EnableFastModePlus\n
470 * PMCR PBx_FMP LL_SBS_EnableFastModePlus
471 * @param ConfigFastModePlus This parameter can be a combination of the following values:
472 * @arg @ref LL_SBS_FASTMODEPLUS_PB6
473 * @arg @ref LL_SBS_FASTMODEPLUS_PB7
474 * @arg @ref LL_SBS_FASTMODEPLUS_PB8
475 * @arg @ref LL_SBS_FASTMODEPLUS_PB9
476 * @retval None
477 */
LL_SBS_EnableFastModePlus(uint32_t ConfigFastModePlus)478 __STATIC_INLINE void LL_SBS_EnableFastModePlus(uint32_t ConfigFastModePlus)
479 {
480 SET_BIT(SBS->PMCR, ConfigFastModePlus);
481 }
482
483 /**
484 * @brief Disable the fast mode plus driving capability.
485 * @rmtoll PMCR PBx_FMP LL_SBS_DisableFastModePlus\n
486 * PMCR PBx_FMP LL_SBS_DisableFastModePlus
487 * @param ConfigFastModePlus This parameter can be a combination of the following values:
488 * @arg @ref LL_SBS_FASTMODEPLUS_PB6
489 * @arg @ref LL_SBS_FASTMODEPLUS_PB7
490 * @arg @ref LL_SBS_FASTMODEPLUS_PB8
491 * @arg @ref LL_SBS_FASTMODEPLUS_PB9
492 * @retval None
493 */
LL_SBS_DisableFastModePlus(uint32_t ConfigFastModePlus)494 __STATIC_INLINE void LL_SBS_DisableFastModePlus(uint32_t ConfigFastModePlus)
495 {
496 CLEAR_BIT(SBS->PMCR, ConfigFastModePlus);
497 }
498
499 /**
500 * @brief Enable Floating Point Unit Invalid operation Interrupt
501 * @rmtoll FPUIMR FPU_IE_0 LL_SBS_EnableIT_FPU_IOC
502 * @retval None
503 */
LL_SBS_EnableIT_FPU_IOC(void)504 __STATIC_INLINE void LL_SBS_EnableIT_FPU_IOC(void)
505 {
506 SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_0);
507 }
508
509 /**
510 * @brief Enable Floating Point Unit Divide-by-zero Interrupt
511 * @rmtoll FPUIMR FPU_IE_1 LL_SBS_EnableIT_FPU_DZC
512 * @retval None
513 */
LL_SBS_EnableIT_FPU_DZC(void)514 __STATIC_INLINE void LL_SBS_EnableIT_FPU_DZC(void)
515 {
516 SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_1);
517 }
518
519 /**
520 * @brief Enable Floating Point Unit Underflow Interrupt
521 * @rmtoll FPUIMR FPU_IE_2 LL_SBS_EnableIT_FPU_UFC
522 * @retval None
523 */
LL_SBS_EnableIT_FPU_UFC(void)524 __STATIC_INLINE void LL_SBS_EnableIT_FPU_UFC(void)
525 {
526 SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_2);
527 }
528
529 /**
530 * @brief Enable Floating Point Unit Overflow Interrupt
531 * @rmtoll FPUIMR FPU_IE_3 LL_SBS_EnableIT_FPU_OFC
532 * @retval None
533 */
LL_SBS_EnableIT_FPU_OFC(void)534 __STATIC_INLINE void LL_SBS_EnableIT_FPU_OFC(void)
535 {
536 SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_3);
537 }
538
539 /**
540 * @brief Enable Floating Point Unit Input denormal Interrupt
541 * @rmtoll FPUIMR FPU_IE_4 LL_SBS_EnableIT_FPU_IDC
542 * @retval None
543 */
LL_SBS_EnableIT_FPU_IDC(void)544 __STATIC_INLINE void LL_SBS_EnableIT_FPU_IDC(void)
545 {
546 SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_4);
547 }
548
549 /**
550 * @brief Enable Floating Point Unit Inexact Interrupt
551 * @rmtoll FPUIMR FPU_IE_5 LL_SBS_EnableIT_FPU_IXC
552 * @retval None
553 */
LL_SBS_EnableIT_FPU_IXC(void)554 __STATIC_INLINE void LL_SBS_EnableIT_FPU_IXC(void)
555 {
556 SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_5);
557 }
558
559 /**
560 * @brief Disable Floating Point Unit Invalid operation Interrupt
561 * @rmtoll FPUIMR FPU_IE_0 LL_SBS_DisableIT_FPU_IOC
562 * @retval None
563 */
LL_SBS_DisableIT_FPU_IOC(void)564 __STATIC_INLINE void LL_SBS_DisableIT_FPU_IOC(void)
565 {
566 CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_0);
567 }
568
569 /**
570 * @brief Disable Floating Point Unit Divide-by-zero Interrupt
571 * @rmtoll FPUIMR FPU_IE_1 LL_SBS_DisableIT_FPU_DZC
572 * @retval None
573 */
LL_SBS_DisableIT_FPU_DZC(void)574 __STATIC_INLINE void LL_SBS_DisableIT_FPU_DZC(void)
575 {
576 CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_1);
577 }
578
579 /**
580 * @brief Disable Floating Point Unit Underflow Interrupt
581 * @rmtoll FPUIMR FPU_IE_2 LL_SBS_DisableIT_FPU_UFC
582 * @retval None
583 */
LL_SBS_DisableIT_FPU_UFC(void)584 __STATIC_INLINE void LL_SBS_DisableIT_FPU_UFC(void)
585 {
586 CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_2);
587 }
588
589 /**
590 * @brief Disable Floating Point Unit Overflow Interrupt
591 * @rmtoll FPUIMR FPU_IE_3 LL_SBS_DisableIT_FPU_OFC
592 * @retval None
593 */
LL_SBS_DisableIT_FPU_OFC(void)594 __STATIC_INLINE void LL_SBS_DisableIT_FPU_OFC(void)
595 {
596 CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_3);
597 }
598
599 /**
600 * @brief Disable Floating Point Unit Input denormal Interrupt
601 * @rmtoll FPUIMR FPU_IE_4 LL_SBS_DisableIT_FPU_IDC
602 * @retval None
603 */
LL_SBS_DisableIT_FPU_IDC(void)604 __STATIC_INLINE void LL_SBS_DisableIT_FPU_IDC(void)
605 {
606 CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_4);
607 }
608
609 /**
610 * @brief Disable Floating Point Unit Inexact Interrupt
611 * @rmtoll FPUIMR FPU_IE_5 LL_SBS_DisableIT_FPU_IXC
612 * @retval None
613 */
LL_SBS_DisableIT_FPU_IXC(void)614 __STATIC_INLINE void LL_SBS_DisableIT_FPU_IXC(void)
615 {
616 CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_5);
617 }
618
619 /**
620 * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
621 * @rmtoll FPUIMR FPU_IE_0 LL_SBS_IsEnabledIT_FPU_IOC
622 * @retval State of bit (1 or 0).
623 */
LL_SBS_IsEnabledIT_FPU_IOC(void)624 __STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_IOC(void)
625 {
626 return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_0) == SBS_FPUIMR_FPU_IE_0) ? 1UL : 0UL);
627 }
628
629 /**
630 * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
631 * @rmtoll FPUIMR FPU_IE_1 LL_SBS_IsEnabledIT_FPU_DZC
632 * @retval State of bit (1 or 0).
633 */
LL_SBS_IsEnabledIT_FPU_DZC(void)634 __STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_DZC(void)
635 {
636 return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_1) == SBS_FPUIMR_FPU_IE_1) ? 1UL : 0UL);
637 }
638
639 /**
640 * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
641 * @rmtoll FPUIMR FPU_IE_2 LL_SBS_IsEnabledIT_FPU_UFC
642 * @retval State of bit (1 or 0).
643 */
LL_SBS_IsEnabledIT_FPU_UFC(void)644 __STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_UFC(void)
645 {
646 return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_2) == SBS_FPUIMR_FPU_IE_2) ? 1UL : 0UL);
647 }
648
649 /**
650 * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
651 * @rmtoll FPUIMR FPU_IE_3 LL_SBS_IsEnabledIT_FPU_OFC
652 * @retval State of bit (1 or 0).
653 */
LL_SBS_IsEnabledIT_FPU_OFC(void)654 __STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_OFC(void)
655 {
656 return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_3) == SBS_FPUIMR_FPU_IE_3) ? 1UL : 0UL);
657 }
658
659 /**
660 * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
661 * @rmtoll FPUIMR FPU_IE_4 LL_SBS_IsEnabledIT_FPU_IDC
662 * @retval State of bit (1 or 0).
663 */
LL_SBS_IsEnabledIT_FPU_IDC(void)664 __STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_IDC(void)
665 {
666 return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_4) == SBS_FPUIMR_FPU_IE_4) ? 1UL : 0UL);
667 }
668
669 /**
670 * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
671 * @rmtoll FPUIMR FPU_IE_5 LL_SBS_IsEnabledIT_FPU_IXC
672 * @retval State of bit (1 or 0).
673 */
LL_SBS_IsEnabledIT_FPU_IXC(void)674 __STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_IXC(void)
675 {
676 return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_5) == SBS_FPUIMR_FPU_IE_5) ? 1UL : 0UL);
677 }
678
679 /**
680 * @brief Set connections to TIM1/8/15/16/17 Break inputs
681 * @rmtoll CFGR2 CLL LL_SBS_SetTIMBreakInputs\n
682 * CFGR2 SEL LL_SBS_SetTIMBreakInputs\n
683 * CFGR2 PVDL LL_SBS_SetTIMBreakInputs\n
684 * CFGR2 ECCL LL_SBS_SetTIMBreakInputs
685 * @param Break This parameter can be a combination of the following values:
686 * where non selected TIMBREAK input is disconnected.
687 * @arg @ref LL_SBS_TIMBREAK_ECC
688 * @arg @ref LL_SBS_TIMBREAK_PVD
689 * @arg @ref LL_SBS_TIMBREAK_SRAM_ECC_LOCK
690 * @arg @ref LL_SBS_TIMBREAK_LOCKUP
691 * @retval None
692 */
LL_SBS_SetTIMBreakInputs(uint32_t Break)693 __STATIC_INLINE void LL_SBS_SetTIMBreakInputs(uint32_t Break)
694 {
695 MODIFY_REG(SBS->CFGR2, SBS_CFGR2_CLL | SBS_CFGR2_SEL | SBS_CFGR2_PVDL | SBS_CFGR2_ECCL, Break);
696 }
697
698 /**
699 * @brief Get connections to TIM1/8/15/16/17 Break inputs
700 * @rmtoll CFGR2 CLL LL_SBS_GetTIMBreakInputs\n
701 * CFGR2 SEL LL_SBS_GetTIMBreakInputs\n
702 * CFGR2 PVDL LL_SBS_GetTIMBreakInputs\n
703 * CFGR2 ECCL LL_SBS_GetTIMBreakInputs
704 * @retval Returned value can be a combination of the following values:
705 * @arg @ref LL_SBS_TIMBREAK_ECC
706 * @arg @ref LL_SBS_TIMBREAK_PVD
707 * @arg @ref LL_SBS_TIMBREAK_SRAM_ECC_LOCK
708 * @arg @ref LL_SBS_TIMBREAK_LOCKUP
709 */
LL_SBS_GetTIMBreakInputs(void)710 __STATIC_INLINE uint32_t LL_SBS_GetTIMBreakInputs(void)
711 {
712 return (uint32_t)(READ_BIT(SBS->CFGR2, SBS_CFGR2_CLL | SBS_CFGR2_SEL | SBS_CFGR2_PVDL | SBS_CFGR2_ECCL));
713 }
714
715 #if defined(SBS_EPOCHSELCR_EPOCH_SEL)
716 /**
717 * @brief Select EPOCH security sent to SAES IP to encrypt/decrypt keys
718 * @rmtoll EPOCHSELCR EPOCH_SEL LL_SBS_EPOCHSelection
719 * @param Epoch_Selection: Select EPOCH security
720 * This parameter can be one of the following values:
721 * @arg LL_SBS_EPOCH_SEL_SECURE : EPOCH secure selected.
722 * @arg LL_SBS_EPOCH_SEL_NONSECURE : EPOCH non secure selected.
723 * @arg LL_SBS_EPOCH_SEL_PUFCHECK : EPOCH all zeros for PUF integrity check.
724 * @retval None
725 */
LL_SBS_EPOCHSelection(uint32_t Epoch_Selection)726 __STATIC_INLINE void LL_SBS_EPOCHSelection(uint32_t Epoch_Selection)
727 {
728 MODIFY_REG(SBS->EPOCHSELCR, SBS_EPOCHSELCR_EPOCH_SEL, (uint32_t)(Epoch_Selection));
729 }
730
731 /**
732 * @brief Get EPOCH security selection
733 * @rmtoll EPOCHSELCR EPOCH_SEL LL_SBS_GetEPOCHSelection
734 * @param none
735 * @retval Returned value can be one of the following values:
736 * @arg LL_SBS_EPOCH_SEL_SECURE : EPOCH secure selected.
737 * @arg LL_SBS_EPOCH_SEL_NONSECURE : EPOCH non secure selected.
738 * @arg LL_SBS_EPOCH_SEL_PUFCHECK : EPOCH all zeros for PUF integrity check.
739 */
LL_SBS_GetEPOCHSelection(void)740 __STATIC_INLINE uint32_t LL_SBS_GetEPOCHSelection(void)
741 {
742 return (uint32_t)(READ_BIT(SBS->EPOCHSELCR, SBS_EPOCHSELCR_EPOCH_SEL));
743 }
744 #endif /* SBS_EPOCHSELCR_EPOCH_SEL */
745
746 /**
747 * @brief Disable the NMI in case of double ECC error in FLASH Interface.
748 * @rmtoll ECCNMIR SBS_ECCNMIR_ECCNMI_MASK_EN LL_SBS_FLASH_DisableECCNMI
749 * @param none
750 * @retval None
751 */
LL_SBS_FLASH_DisableECCNMI(void)752 __STATIC_INLINE void LL_SBS_FLASH_DisableECCNMI(void)
753 {
754 SET_BIT(SBS->ECCNMIR, SBS_ECCNMIR_ECCNMI_MASK_EN);
755 }
756
757 /**
758 * @brief Enable the NMI in case of double ECC error in FLASH Interface.
759 * @rmtoll ECCNMIR SBS_ECCNMIR_ECCNMI_MASK_EN LL_SBS_FLASH_EnableECCNMI
760 * @param none
761 * @retval None
762 */
LL_SBS_FLASH_EnableECCNMI(void)763 __STATIC_INLINE void LL_SBS_FLASH_EnableECCNMI(void)
764 {
765 CLEAR_BIT(SBS->ECCNMIR, SBS_ECCNMIR_ECCNMI_MASK_EN);
766 }
767
768 /** @defgroup SBS_LL_EF_SBS_HDPL_Management HDPL Management
769 * @{
770 */
771
772 /**
773 * @brief Increment by 1 the HDPL value
774 * @rmtoll HDPLCR HDPL_INCR LL_SBS_IncrementHDPLValue
775 * @param None
776 * @retval None
777 */
LL_SBS_IncrementHDPLValue(void)778 __STATIC_INLINE void LL_SBS_IncrementHDPLValue(void)
779 {
780 MODIFY_REG(SBS->HDPLCR, SBS_HDPLCR_INCR_HDPL, LL_SBS_HDPL_INCREMENT_VALUE);
781 }
782
783 /**
784 * @brief Get the HDPL Value.
785 * @rmtoll HDPLSR HDPL LL_SBS_GetHDPLValue
786 * @param None
787 * @retval Returns the HDPL value
788 * This return value can be one of the following values:
789 * @arg LL_SBS_HDPL_VALUE_0: HDPL0
790 * @arg LL_SBS_HDPL_VALUE_1: HDPL1
791 * @arg LL_SBS_HDPL_VALUE_2: HDPL2
792 * @arg LL_SBS_HDPL_VALUE_3: HDPL3
793 */
LL_SBS_GetHDPLValue(void)794 __STATIC_INLINE uint32_t LL_SBS_GetHDPLValue(void)
795 {
796 return (uint32_t)(READ_BIT(SBS->HDPLSR, SBS_HDPLSR_HDPL));
797 }
798
799 #if defined(SBS_NEXTHDPLCR_NEXTHDPL)
800 /**
801 * @brief Set the OBK-HDPL Value.
802 * @rmtoll NEXTHDPLCR NEXTHDPL LL_SBS_SetOBKHDPL
803 * @param Set the increment to add to HDPL value to generate the OBK-HDPL.
804 * This parameter can be one of the following values:
805 * @arg LL_SBS_OBKHDPL_INCR_0 : HDPL
806 * @arg LL_SBS_OBKHDPL_INCR_1 : HDPL + 1
807 * @arg LL_SBS_OBKHDPL_INCR_2 : HDPL + 2
808 * @arg LL_SBS_OBKHDPL_INCR_3 : HDPL + 3
809 * @retval None
810 */
LL_SBS_SetOBKHDPL(uint32_t OBKHDPL_Value)811 __STATIC_INLINE void LL_SBS_SetOBKHDPL(uint32_t OBKHDPL_Value)
812 {
813 MODIFY_REG(SBS->NEXTHDPLCR, SBS_NEXTHDPLCR_NEXTHDPL, (uint32_t)(OBKHDPL_Value));
814 }
815
816 /**
817 * @brief Get the OBK-HDPL Value.
818 * @rmtoll NEXTHDPLCR NEXTHDPL LL_SBS_GetOBKHDPL
819 * @retval Returns the incremement to add to HDPL value to generate OBK-HDPL
820 * This return value can be one of the following values:
821 * @arg LL_SBS_OBKHDPL_INCR_0: HDPL
822 * @arg LL_SBS_OBKHDPL_INCR_1: HDPL + 1
823 * @arg LL_SBS_OBKHDPL_INCR_2: HDPL + 2
824 * @arg LL_SBS_OBKHDPL_INCR_3: HDPL + 3
825 */
LL_SBS_GetOBKHDPL(void)826 __STATIC_INLINE uint32_t LL_SBS_GetOBKHDPL(void)
827 {
828 return (uint32_t)(READ_BIT(SBS->NEXTHDPLCR, SBS_NEXTHDPLCR_NEXTHDPL));
829 }
830 #endif /* SBS_NEXTHDPLCR_NEXTHDPL */
831
832 /**
833 * @}
834 */
835
836 /** @defgroup SYSTEM_LL_SBS_EF_Debug_Control Debug Control
837 * @{
838 */
839
840 /**
841 * @brief Set the authenticated debug hide protection level
842 * @rmtoll SBS_DBGCR DBG_AUTH_HDPL LL_SBS_SetAuthDbgHDPL
843 * @param Level This parameter can be one of the following values:
844 * @arg @ref LL_SBS_HDPL_VALUE_1
845 * @arg @ref LL_SBS_HDPL_VALUE_2
846 * @arg @ref LL_SBS_HDPL_VALUE_3
847 * @retval None
848 */
LL_SBS_SetAuthDbgHDPL(uint32_t Level)849 __STATIC_INLINE void LL_SBS_SetAuthDbgHDPL(uint32_t Level)
850 {
851 MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_HDPL, (Level << SBS_DBGCR_DBG_AUTH_HDPL_Pos));
852 }
853
854 /**
855 * @brief Get current hide protection level
856 * @rmtoll SBS_DBGCR DBG_AUTH_HDPL LL_SBS_GetAuthDbgHDPL
857 * @retval Returned value is the hide protection level where the authenticated debug is opened:
858 * @arg @ref LL_SBS_HDPL_VALUE_1
859 * @arg @ref LL_SBS_HDPL_VALUE_2
860 * @arg @ref LL_SBS_HDPL_VALUE_3
861 */
LL_SBS_GetAuthDbgHDPL(void)862 __STATIC_INLINE uint32_t LL_SBS_GetAuthDbgHDPL(void)
863 {
864 return (uint32_t)(READ_BIT(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_HDPL) >> SBS_DBGCR_DBG_AUTH_HDPL_Pos);
865 }
866
867 #if defined(SBS_DBGCR_DBG_AUTH_SEC)
868 /**
869 * @brief Configure the authenticated debug security access.
870 * @rmtoll SBS_DBGCR DBG_AUTH_SEC LL_SBS_SetAuthDbgSec
871 * @param Control debug opening secure/non-secure or non-secure only
872 * This parameter can be one of the following values:
873 * @arg LL_SBS_DEBUG_SEC_NSEC: debug opening for secure and non-secure.
874 * @arg LL_SBS_DEBUG_NSEC: debug opening for non-secure only.
875 * @retval None
876 */
LL_SBS_SetAuthDbgSec(uint32_t Security)877 __STATIC_INLINE void LL_SBS_SetAuthDbgSec(uint32_t Security)
878 {
879 MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_SEC, (Security << SBS_DBGCR_DBG_AUTH_SEC_Pos));
880 }
881
882 /**
883 * @brief Get the current value of the hide protection level.
884 * @rmtoll SBS_DBGCR DBG_AUTH_SEC LL_SBS_GetAuthDbgSec
885 * @note This function can be only used when device state is Closed.
886 * @retval Returned value can be one of the following values:
887 * @arg SBS_DEBUG_SEC_NSEC: debug opening for secure and non-secure.
888 * @arg any other value: debug opening for non-secure only.
889 */
LL_SBS_GetAuthDbgSec(void)890 __STATIC_INLINE uint32_t LL_SBS_GetAuthDbgSec(void)
891 {
892 return ((SBS->DBGCR & SBS_DBGCR_DBG_AUTH_SEC) >> SBS_DBGCR_DBG_AUTH_SEC_Pos);
893 }
894
895 #endif /* SBS_DBGCR_DBG_AUTH_SEC */
896
897 /**
898 * @brief Unlock the debug
899 * @rmtoll SBS_DBGCR DBG_UNLOCK LL_SBS_UnlockDebug
900 * @retval None
901 */
LL_SBS_UnlockDebug(void)902 __STATIC_INLINE void LL_SBS_UnlockDebug(void)
903 {
904 MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_UNLOCK, LL_SBS_DBG_UNLOCK);
905 }
906
907 /**
908 * @brief Check if the debug is unlocked
909 * @rmtoll SBS_DBGCR DBG_UNLOCK LL_SBS_IsUnlockedDebug
910 * @retval State of bit (1 or 0).
911 */
LL_SBS_IsUnlockedDebug(void)912 __STATIC_INLINE uint32_t LL_SBS_IsUnlockedDebug(void)
913 {
914 return ((READ_BIT(SBS->DBGCR, SBS_DBGCR_DBG_UNLOCK) == LL_SBS_DBG_UNLOCK) ? 1UL : 0UL);
915 }
916
917 /**
918 * @brief Unlock the access port
919 * @rmtoll SBS_DBGCR AP_UNLOCK LL_SBS_UnlockAccessPort
920 * @retval None
921 */
LL_SBS_UnlockAccessPort(void)922 __STATIC_INLINE void LL_SBS_UnlockAccessPort(void)
923 {
924 MODIFY_REG(SBS->DBGCR, SBS_DBGCR_AP_UNLOCK, LL_SBS_ACCESS_PORT_UNLOCK);
925 }
926
927 /**
928 * @brief Check if the access port is unlocked
929 * @rmtoll SBS_DBGCR AP_UNLOCK LL_SBS_IsUnlockedAccessPort
930 * @retval State of bit (1 or 0).
931 */
LL_SBS_IsUnlockedAccessPort(void)932 __STATIC_INLINE uint32_t LL_SBS_IsUnlockedAccessPort(void)
933 {
934 return ((READ_BIT(SBS->DBGCR, SBS_DBGCR_AP_UNLOCK) == LL_SBS_ACCESS_PORT_UNLOCK) ? 1UL : 0UL);
935 }
936
937 /**
938 * @brief Lock the debug configuration
939 * @rmtoll SBS_DBGLOCKR DBGCFG_LOCK LL_SBS_LockDebugConfig
940 * @retval None
941 */
LL_SBS_LockDebugConfig(void)942 __STATIC_INLINE void LL_SBS_LockDebugConfig(void)
943 {
944 MODIFY_REG(SBS->DBGLOCKR, SBS_DBGLOCKR_DBGCFG_LOCK, LL_SBS_DBG_CONFIG_LOCK);
945 }
946
947 /**
948 * @brief Check if the debug configuration is locked
949 * @rmtoll SBS_DBGLOCKR DBGCFG_LOCK LL_SBS_IsLockedDebugConfig
950 * @retval State of bit (1 or 0).
951 */
LL_SBS_IsLockedDebugConfig(void)952 __STATIC_INLINE uint32_t LL_SBS_IsLockedDebugConfig(void)
953 {
954 return ((READ_BIT(SBS->DBGLOCKR, SBS_DBGLOCKR_DBGCFG_LOCK) != LL_SBS_DBG_CONFIG_UNLOCK) ? 1UL : 0UL);
955 }
956
957 /**
958 * @}
959 */
960
961 /** @defgroup SYSTEM_LL_SBS_EF_lock_Management lock Management
962 * @{
963 */
964
965 /**
966 * @brief Non-secure Lock of SBS item(s).
967 * @note Setting lock(s) depends on privilege mode in secure/non-secure code
968 * Lock(s) cleared only at system reset
969 * @rmtoll CNSLCKR LOCKNSVTOR LL_SBS_NonSecureLock\n
970 * CNSLCKR LOCKNSMPU LL_SBS_NonSecureLock
971 * @param Item Item(s) to set lock on.
972 * This parameter can be one of the following values :
973 * @arg LL_SBS_VTOR_NSEC : VTOR_NS register lock
974 * @arg LL_SBS_MPU_NSEC : Non-secure MPU registers lock
975 * @arg LL_SBS_LOCK_ALL_NSEC : Non-secure MPU and VTOR_NS lock
976 * @retval None
977 */
LL_SBS_NonSecureLock(uint32_t Item)978 __STATIC_INLINE void LL_SBS_NonSecureLock(uint32_t Item)
979 {
980 /* Privilege secure/non-secure locks */
981 SBS->CNSLCKR = Item;
982 }
983
984 /**
985 * @brief Get the non secure lock state of SBS items.
986 * @note Getting lock(s) depends on privilege mode in secure/non-secure code
987 * @rmtoll CNSLCKR LOCKNSVTOR LL_SBS_NonSecureLock\n
988 * CNSLCKR LOCKNSMPU LL_SBS_NonSecureLock
989 * @param none
990 * @retval the return value can be one of the following values :
991 * @arg LL_SBS_VTOR_NSEC : VTOR_NS register lock
992 * @arg LL_SBS_MPU_NSEC : Non-secure MPU registers lock
993 * @arg LL_SBS_LOCK_ALL_NSEC : VTOR_NS and Non-secure MPU registers lock
994 */
LL_SBS_GetNonSecureLock(void)995 __STATIC_INLINE uint32_t LL_SBS_GetNonSecureLock(void)
996 {
997 return (uint32_t)(READ_BIT(SBS->CNSLCKR, LL_SBS_LOCK_ALL_NSEC));
998 }
999
1000 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1001 /**
1002 * @brief Secure Lock of System item(s).
1003 * @note Setting lock(s) depends on privilege mode in secure code
1004 * Lock(s) cleared only at system reset
1005 * @rmtoll CSLCKR LOCKSVTAIRCR LL_SBS_SecureLock\n
1006 * CSLCKR LOCKSMPU LL_SBS_SecureLock\n
1007 * CSLCKR LOCKSAU LL_SBS_SecureLock
1008 * @param Item Item(s) to set lock on.
1009 * This parameter can be a combination of the following values :
1010 * @arg LL_SBS_VTOR_AIRCR_SEC : VTOR_S and AIRCR registers lock
1011 * @arg LL_SBS_MPU_SEC : Secure MPU registers lock
1012 * @arg LL_SBS_SAU : SAU registers lock
1013 * @arg LL_SBS_LOCK_ALL_SEC : VTOR_S, AIRCR, Secure MPU and SAU registers lock
1014 * @retval None
1015 */
LL_SBS_SecureLock(uint32_t Item)1016 __STATIC_INLINE void LL_SBS_SecureLock(uint32_t Item)
1017 {
1018 /* Privilege secure only locks */
1019 SBS->CSLCKR = Item;
1020 }
1021
1022 /**
1023 * @brief Get the secure lock state of System items.
1024 * @note Getting lock(s) depends on privilege mode in secure code
1025 * @rmtoll CSLCKR LOCKSVTAIRCR HAL_SBS_GetSecureLock\n
1026 * CSLCKR LOCKSMPU HAL_SBS_GetSecureLock\n
1027 * CSLCKR LOCKSAU HAL_SBS_GetSecureLock
1028 * @param none
1029 * @retval the return value is a combination of the following values :
1030 * @arg LL_SBS_VTOR_AIRCR_SEC : VTOR_S and AIRCR registers lock
1031 * @arg LL_SBS_MPU_SEC : Secure MPU registers lock
1032 * @arg LL_SBS_SAU : SAU registers lock
1033 * @arg LL_SBS_LOCK_ALL_SEC : VTOR_S, AIRCR, Secure MPU and SAU registers lock
1034 */
LL_SBS_GetSecureLock(void)1035 __STATIC_INLINE uint32_t LL_SBS_GetSecureLock(void)
1036 {
1037 return (uint32_t)(READ_BIT(SBS->CSLCKR, LL_SBS_LOCK_ALL_SEC));
1038 }
1039 #endif /* __ARM_FEATURE_CMSE && __ARM_FEATURE_CMSE == 3U */
1040
1041 /**
1042 * @}
1043 */
1044
1045 /** @defgroup SYSTEM_LL_EF_SBS_Secure_Management Secure Management
1046 * @{
1047 */
1048
1049 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1050
1051 /**
1052 * @brief Configure Secure mode
1053 * @note Only available from secure state when system implements security (TZEN=1)
1054 * @rmtoll SECCFGR SBSSEC LL_SBS_ConfigSecure\n
1055 * SECCFGR CLASSBSEC LL_SBS_ConfigSecure\n
1056 * SECCFGR FPUSEC LL_SBS_ConfigSecure\n
1057 * SECCFGR SDCE_SEC_EN LL_SBS_ConfigSecure
1058 * @param Configuration This parameter shall be the full combination
1059 * of the following values:
1060 * @arg @ref LL_SBS_CLOCK_SEC or LL_SBS_CLOCK_NSEC
1061 * @arg @ref LL_SBS_CLASSB_SEC or LL_SBS_CLASSB_NSEC
1062 * @arg @ref LL_SBS_FPU_SEC or LL_SBS_FPU_NSEC
1063 * @arg @ref LL_SBS_SMPS_SEC or LL_SBS_SMPS_NSEC
1064 * @retval None
1065 */
LL_SBS_ConfigSecure(uint32_t Configuration)1066 __STATIC_INLINE void LL_SBS_ConfigSecure(uint32_t Configuration)
1067 {
1068 WRITE_REG(SBS->SECCFGR, Configuration);
1069 }
1070
1071 /**
1072 * @brief Get Secure mode configuration
1073 * @note Only available when system implements security (TZEN=1)
1074 * @rmtoll SECCFGR SBSSEC LL_SBS_ConfigSecure\n
1075 * SECCFGR CLASSBSEC LL_SBS_ConfigSecure\n
1076 * SECCFGR FPUSEC LL_SBS_ConfigSecure\n
1077 * SECCFGR SDCE_SEC_EN LL_SBS_ConfigSecure
1078 * @retval Returned value is the combination of the following values:
1079 * @arg @ref LL_SBS_CLOCK_SEC or LL_SBS_CLOCK_NSEC
1080 * @arg @ref LL_SBS_CLASSB_SEC or LL_SBS_CLASSB_NSEC
1081 * @arg @ref LL_SBS_FPU_SEC or LL_SBS_FPU_NSEC
1082 * @arg @ref LL_SBS_SMPS_SEC or LL_SBS_SMPS_NSEC
1083 */
LL_SBS_GetConfigSecure(void)1084 __STATIC_INLINE uint32_t LL_SBS_GetConfigSecure(void)
1085 {
1086 return (uint32_t)(READ_BIT(SBS->SECCFGR, LL_SBS_CLOCK_SEC | LL_SBS_CLASSB_SEC | LL_SBS_FPU_SEC | LL_SBS_SMPS_SEC));
1087 }
1088
1089 #endif /* __ARM_FEATURE_CMSE && __ARM_FEATURE_CMSE == 3U */
1090
1091 /**
1092 * @}
1093 */
1094
1095 /**
1096 * @}
1097 */
1098
1099 /** @defgroup SYSTEM_LL_EF_COMPENSATION
1100 * @{
1101 */
1102
1103 /**
1104 * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDD
1105 * @rmtoll CCVALR PCV1 LL_SBS_GetPMOSVddCompensationValue
1106 * @retval Returned value is the PMOS compensation cell
1107 */
LL_SBS_GetPMOSVddCompensationValue(void)1108 __STATIC_INLINE uint32_t LL_SBS_GetPMOSVddCompensationValue(void)
1109 {
1110 return (uint32_t)(READ_BIT(SBS->CCVALR, SBS_CCVALR_APSRC1));
1111 }
1112
1113 /**
1114 * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDD
1115 * @rmtoll CCVALR NCV1 LL_SBS_GetNMOSVddCompensationValue
1116 * @retval Returned value is the NMOS compensation cell
1117 */
LL_SBS_GetNMOSVddCompensationValue(void)1118 __STATIC_INLINE uint32_t LL_SBS_GetNMOSVddCompensationValue(void)
1119 {
1120 return (uint32_t)(READ_BIT(SBS->CCVALR, SBS_CCVALR_ANSRC1));
1121 }
1122
1123 /**
1124 * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDDIO2
1125 * @rmtoll CCVALR PCV2 LL_SBS_GetPMOSVddIO2CompensationValue
1126 * @retval Returned value is the PMOS compensation cell
1127 */
LL_SBS_GetPMOSVddIO2CompensationValue(void)1128 __STATIC_INLINE uint32_t LL_SBS_GetPMOSVddIO2CompensationValue(void)
1129 {
1130 return (uint32_t)(READ_BIT(SBS->CCVALR, SBS_CCVALR_APSRC2));
1131 }
1132
1133 /**
1134 * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDDIO2
1135 * @rmtoll CCVALR NCV2 LL_SBS_GetNMOSVddIO2CompensationValue
1136 * @retval Returned value is the NMOS compensation cell
1137 */
LL_SBS_GetNMOSVddIO2CompensationValue(void)1138 __STATIC_INLINE uint32_t LL_SBS_GetNMOSVddIO2CompensationValue(void)
1139 {
1140 return (uint32_t)(READ_BIT(SBS->CCVALR, SBS_CCVALR_ANSRC2));
1141 }
1142
1143 /**
1144 * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDD
1145 * @rmtoll CCSWCR PCC1 LL_SBS_SetPMOSVddCompensationCode
1146 * @param PMOSCode PMOS compensation code
1147 * This code is applied to the PMOS compensation cell when the CS1 bit of the
1148 * SBS_CCCSR is set
1149 * @retval None
1150 */
LL_SBS_SetPMOSVddCompensationCode(uint32_t PMOSCode)1151 __STATIC_INLINE void LL_SBS_SetPMOSVddCompensationCode(uint32_t PMOSCode)
1152 {
1153 MODIFY_REG(SBS->CCSWCR, SBS_CCSWCR_SW_APSRC1, PMOSCode << SBS_CCSWCR_SW_APSRC1_Pos);
1154 }
1155
1156 /**
1157 * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDD
1158 * @rmtoll CCSWCR PCC1 LL_SBS_GetPMOSVddCompensationCode
1159 * @retval Returned value is the PMOS compensation cell
1160 */
LL_SBS_GetPMOSVddCompensationCode(void)1161 __STATIC_INLINE uint32_t LL_SBS_GetPMOSVddCompensationCode(void)
1162 {
1163 return (uint32_t)(READ_BIT(SBS->CCSWCR, SBS_CCSWCR_SW_APSRC1));
1164 }
1165
1166 /**
1167 * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDDIO
1168 * @rmtoll CCSWCR PCC2 LL_SBS_SetPMOSVddIOCompensationCode
1169 * @param PMOSCode PMOS compensation code
1170 * This code is applied to the PMOS compensation cell when the CS2 bit of the
1171 * SBS_CCCSR is set
1172 * @retval None
1173 */
LL_SBS_SetPMOSVddIOCompensationCode(uint32_t PMOSCode)1174 __STATIC_INLINE void LL_SBS_SetPMOSVddIOCompensationCode(uint32_t PMOSCode)
1175 {
1176 MODIFY_REG(SBS->CCSWCR, SBS_CCSWCR_SW_APSRC2, PMOSCode << SBS_CCSWCR_SW_APSRC2_Pos);
1177 }
1178
1179
1180 /**
1181 * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDDIO
1182 * @rmtoll CCSWCR PCC2 LL_SBS_GetPMOSVddIOCompensationCode
1183 * @retval Returned value is the PMOS compensation
1184 */
LL_SBS_GetPMOSVddIOCompensationCode(void)1185 __STATIC_INLINE uint32_t LL_SBS_GetPMOSVddIOCompensationCode(void)
1186 {
1187 return (uint32_t)(READ_BIT(SBS->CCSWCR, SBS_CCSWCR_SW_APSRC2));
1188 }
1189
1190 /**
1191 * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDD
1192 * @rmtoll CCSWCR PCC2 LL_SBS_SetNMOSVddCompensationCode
1193 * @param NMOSCode NMOS compensation code
1194 * This code is applied to the NMOS compensation cell when the CS2 bit of the
1195 * SBS_CCCSR is set
1196 * @retval None
1197 */
LL_SBS_SetNMOSVddCompensationCode(uint32_t NMOSCode)1198 __STATIC_INLINE void LL_SBS_SetNMOSVddCompensationCode(uint32_t NMOSCode)
1199 {
1200 MODIFY_REG(SBS->CCSWCR, SBS_CCSWCR_SW_ANSRC1, NMOSCode << SBS_CCSWCR_SW_ANSRC1_Pos);
1201 }
1202
1203 /**
1204 * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDD
1205 * @rmtoll CCSWCR NCC1 LL_SBS_GetNMOSVddCompensationCode
1206 * @retval Returned value is the Vdd compensation cell code for NMOS transistors
1207 */
LL_SBS_GetNMOSVddCompensationCode(void)1208 __STATIC_INLINE uint32_t LL_SBS_GetNMOSVddCompensationCode(void)
1209 {
1210 return (uint32_t)(READ_BIT(SBS->CCSWCR, SBS_CCSWCR_SW_ANSRC1));
1211 }
1212
1213 /**
1214 * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDDIO
1215 * @rmtoll CCSWCR NCC2 LL_SBS_SetNMOSVddIOCompensationCode
1216 * @param PMOSCode PMOS compensation cell code
1217 * This code is applied to the NMOS compensation cell when the CS2 bit of the
1218 * SBS_CCCSR is set
1219 * @retval None
1220 */
LL_SBS_SetNMOSVddIOCompensationCode(uint32_t NMOSCode)1221 __STATIC_INLINE void LL_SBS_SetNMOSVddIOCompensationCode(uint32_t NMOSCode)
1222 {
1223 MODIFY_REG(SBS->CCSWCR, SBS_CCSWCR_SW_ANSRC2, NMOSCode << SBS_CCSWCR_SW_ANSRC2_Pos);
1224 }
1225
1226
1227 /**
1228 * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDDIO
1229 * @rmtoll CCSWCR NCC2 LL_SBS_GetNMOSVddIOCompensationCode
1230 * @retval Returned value is the NMOS compensation cell code
1231 */
LL_SBS_GetNMOSVddIOCompensationCode(void)1232 __STATIC_INLINE uint32_t LL_SBS_GetNMOSVddIOCompensationCode(void)
1233 {
1234 return (uint32_t)(READ_BIT(SBS->CCSWCR, SBS_CCSWCR_SW_ANSRC2));
1235 }
1236
1237 /**
1238 * @brief Enable the Compensation Cell of GPIO supplied by VDD
1239 * @rmtoll CCCSR EN1 LL_SBS_EnableVddCompensationCell
1240 * @note The vdd compensation cell can be used only when the device supply
1241 * voltage ranges from 1.71 to 3.6 V
1242 * @retval None
1243 */
LL_SBS_EnableVddCompensationCell(void)1244 __STATIC_INLINE void LL_SBS_EnableVddCompensationCell(void)
1245 {
1246 SET_BIT(SBS->CCCSR, SBS_CCCSR_EN1);
1247 }
1248
1249 /**
1250 * @brief Enable the Compensation Cell of GPIO supplied by VDDIO
1251 * @rmtoll CCCSR EN2 LL_SBS_EnableVddIOCompensationCell
1252 * @note The Vdd I/O compensation cell can be used only when the device supply
1253 * voltage ranges from 1.08 to 3.6 V
1254 * @retval None
1255 */
LL_SBS_EnableVddIOCompensationCell(void)1256 __STATIC_INLINE void LL_SBS_EnableVddIOCompensationCell(void)
1257 {
1258 SET_BIT(SBS->CCCSR, SBS_CCCSR_EN2);
1259 }
1260
1261 /**
1262 * @brief Disable the Compensation Cell of GPIO supplied by VDD
1263 * @rmtoll CCCSR EN1 LL_SBS_DisableVddCompensationCell
1264 * @note The Vdd compensation cell can be used only when the device supply
1265 * voltage ranges from 1.71 to 3.6 V
1266 * @retval None
1267 */
LL_SBS_DisableVddCompensationCell(void)1268 __STATIC_INLINE void LL_SBS_DisableVddCompensationCell(void)
1269 {
1270 CLEAR_BIT(SBS->CCCSR, SBS_CCCSR_EN1);
1271 }
1272
1273 /**
1274 * @brief Disable the Compensation Cell of GPIO supplied by VDDIO
1275 * @rmtoll CCCSR EN2 LL_SBS_DisableVddIOCompensationCell
1276 * @note The Vdd I/O compensation cell can be used only when the device supply
1277 * voltage ranges from 1.08 to 3.6 V
1278 * @retval None
1279 */
LL_SBS_DisableVddIOCompensationCell(void)1280 __STATIC_INLINE void LL_SBS_DisableVddIOCompensationCell(void)
1281 {
1282 CLEAR_BIT(SBS->CCCSR, SBS_CCCSR_EN2);
1283 }
1284
1285 /**
1286 * @brief Check if the Compensation Cell of GPIO supplied by VDD is enable
1287 * @rmtoll CCCSR EN1 LL_SBS_IsEnabled_VddCompensationCell
1288 * @retval State of bit (1 or 0).
1289 */
LL_SBS_IsEnabled_VddCompensationCell(void)1290 __STATIC_INLINE uint32_t LL_SBS_IsEnabled_VddCompensationCell(void)
1291 {
1292 return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_EN1) == SBS_CCCSR_EN1) ? 1UL : 0UL);
1293 }
1294
1295 /**
1296 * @brief Check if the Compensation Cell of GPIO supplied by VDDIO is enable
1297 * @rmtoll CCCSR EN2 LL_SBS_IsEnabled_VddIOCompensationCell
1298 * @retval State of bit (1 or 0).
1299 */
LL_SBS_IsEnabled_VddIOCompensationCell(void)1300 __STATIC_INLINE uint32_t LL_SBS_IsEnabled_VddIOCompensationCell(void)
1301 {
1302 return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_EN2) == SBS_CCCSR_EN2) ? 1UL : 0UL);
1303 }
1304
1305 /**
1306 * @brief Get Compensation Cell ready Flag of GPIO supplied by VDD
1307 * @rmtoll CCCSR RDY1 LL_SBS_IsActiveFlag_VddCMPCR
1308 * @retval State of bit (1 or 0).
1309 */
LL_SBS_IsActiveFlag_VddCMPCR(void)1310 __STATIC_INLINE uint32_t LL_SBS_IsActiveFlag_VddCMPCR(void)
1311 {
1312 return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_RDY1) == (SBS_CCCSR_RDY1)) ? 1UL : 0UL);
1313 }
1314
1315 /**
1316 * @brief Get Compensation Cell ready Flag of GPIO supplied by VDDIO
1317 * @rmtoll CCCSR RDY1 LL_SBS_IsActiveFlag_VddIOCMPCR
1318 * @retval State of bit (1 or 0).
1319 */
LL_SBS_IsActiveFlag_VddIOCMPCR(void)1320 __STATIC_INLINE uint32_t LL_SBS_IsActiveFlag_VddIOCMPCR(void)
1321 {
1322 return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_RDY2) == (SBS_CCCSR_RDY2)) ? 1UL : 0UL);
1323 }
1324
1325
1326 /**
1327 * @brief Set the compensation cell code selection of GPIO supplied by VDD
1328 * @rmtoll CCCSR CS1 LL_SBS_SetVddCellCompensationCode
1329 * @param CompCode: Selects the code to be applied for the Vdd compensation cell
1330 * This parameter can be one of the following values:
1331 * @arg LL_SBS_VDD_CELL_CODE : Select Code from the cell (available in the SBS_CCVALR)
1332 * @arg LL_SBS_VDD_REGISTER_CODE: Select Code from the SBS compensation cell code register (SBS_CCSWCR)
1333 * @retval None
1334 */
LL_SBS_SetVddCellCompensationCode(uint32_t CompCode)1335 __STATIC_INLINE void LL_SBS_SetVddCellCompensationCode(uint32_t CompCode)
1336 {
1337 SET_BIT(SBS->CCCSR, CompCode);
1338 }
1339
1340 /**
1341 * @brief Set the compensation cell code selection of GPIO supplied by VDDIO
1342 * @rmtoll CCCSR CS2 LL_SBS_SetVddIOCellCompensationCode
1343 * @param CompCode: Selects the code to be applied for the VddIO compensation cell
1344 * This parameter can be one of the following values:
1345 * @arg LL_SBS_VDDIO_CELL_CODE : Select Code from the cell (available in the SBS_CCVALR)
1346 * @arg LL_SBS_VDDIO_REGISTER_CODE: Select Code from the SBS compensation cell code register (SBS_CCSWCR)
1347 * @retval None
1348 */
LL_SBS_SetVddIOCellCompensationCode(uint32_t CompCode)1349 __STATIC_INLINE void LL_SBS_SetVddIOCellCompensationCode(uint32_t CompCode)
1350 {
1351 SET_BIT(SBS->CCCSR, CompCode);
1352 }
1353
1354 /**
1355 * @brief Get the compensation cell code selection of GPIO supplied by VDD
1356 * @rmtoll CCCSR CS1 LL_SBS_GetVddCellCompensationCode
1357 * @retval Returned value can be one of the following values:
1358 * @arg LL_SBS_VDD_CELL_CODE : Selected Code is from the cell (available in the SBS_CCVALR)
1359 * @arg LL_SBS_VDD_REGISTER_CODE: Selected Code is from the SBS compensation cell code register (SBS_CCSWCR)
1360 */
LL_SBS_GetVddCellCompensationCode(void)1361 __STATIC_INLINE uint32_t LL_SBS_GetVddCellCompensationCode(void)
1362 {
1363 return (uint32_t)(READ_BIT(SBS->CCCSR, SBS_CCCSR_CS1));
1364 }
1365
1366 /**
1367 * @brief Get the compensation cell code selection of GPIO supplied by VDDIO
1368 * @rmtoll CCCSR CS2 LL_SBS_GetVddIOCellCompensationCode
1369 * @retval Returned value can be one of the following values:
1370 * @arg LL_SBS_VDDIO_CELL_CODE : Selected Code is from the cell (available in the SBS_CCVALR)
1371 * @arg LL_SBS_VDDIO_REGISTER_CODE: Selected Code is from the SBS compensation cell code register (SBS_CCSWCR)
1372 */
LL_SBS_GetVddIOCellCompensationCode(void)1373 __STATIC_INLINE uint32_t LL_SBS_GetVddIOCellCompensationCode(void)
1374 {
1375 return (uint32_t)(READ_BIT(SBS->CCCSR, SBS_CCCSR_CS2));
1376 }
1377
1378 /**
1379 * @}
1380 */
1381
1382 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1383 * @{
1384 */
1385
1386 /**
1387 * @brief Return the device identifier
1388 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
1389 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415)
1390 */
LL_DBGMCU_GetDeviceID(void)1391 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1392 {
1393 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1394 }
1395
1396 /**
1397 * @brief Return the device revision identifier
1398 * @note This field indicates the revision of the device.
1399 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
1400 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1401 */
LL_DBGMCU_GetRevisionID(void)1402 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1403 {
1404 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1405 }
1406
1407 /**
1408 * @brief Enable the Debug Module during STOP mode
1409 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
1410 * @retval None
1411 */
LL_DBGMCU_EnableDBGStopMode(void)1412 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1413 {
1414 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1415 }
1416
1417 /**
1418 * @brief Disable the Debug Module during STOP mode
1419 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
1420 * @retval None
1421 */
LL_DBGMCU_DisableDBGStopMode(void)1422 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1423 {
1424 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1425 }
1426
1427 /**
1428 * @brief Enable the Debug Module during STANDBY mode
1429 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
1430 * @retval None
1431 */
LL_DBGMCU_EnableDBGStandbyMode(void)1432 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1433 {
1434 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1435 }
1436
1437 /**
1438 * @brief Disable the Debug Module during STANDBY mode
1439 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
1440 * @retval None
1441 */
LL_DBGMCU_DisableDBGStandbyMode(void)1442 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1443 {
1444 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1445 }
1446
1447
1448 /**
1449 * @brief Enable the Debug Clock Trace
1450 * @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_EnableTraceClock
1451 * @retval None
1452 */
LL_DBGMCU_EnableTraceClock(void)1453 __STATIC_INLINE void LL_DBGMCU_EnableTraceClock(void)
1454 {
1455 SET_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN);
1456 }
1457
1458 /**
1459 * @brief Disable the Debug Clock Trace
1460 * @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_DisableTraceClock
1461 * @retval None
1462 */
LL_DBGMCU_DisableTraceClock(void)1463 __STATIC_INLINE void LL_DBGMCU_DisableTraceClock(void)
1464 {
1465 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN);
1466 }
1467
1468
1469 /**
1470 * @brief Check if clock trace is enabled or disabled.
1471 * @rmtoll DBGMCU_CR_TRACE_CLKEN LL_DBGMCU_IsEnabledTraceClock
1472 * @retval State of bit (1 or 0).
1473 */
LL_DBGMCU_IsEnabledTraceClock(void)1474 __STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledTraceClock(void)
1475 {
1476 return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN) == DBGMCU_CR_TRACE_CLKEN) ? 1UL : 0UL);
1477 }
1478
1479 /**
1480 * @brief Set Trace pin assignment control
1481 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
1482 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
1483 * @param PinAssignment This parameter can be one of the following values:
1484 * @arg @ref LL_DBGMCU_TRACE_NONE
1485 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1486 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1487 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1488 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1489 * @retval None
1490 */
LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)1491 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
1492 {
1493 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
1494 }
1495
1496 /**
1497 * @brief Get Trace pin assignment control
1498 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
1499 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
1500 * @retval Returned value can be one of the following values:
1501 * @arg @ref LL_DBGMCU_TRACE_NONE
1502 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1503 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1504 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1505 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1506 */
LL_DBGMCU_GetTracePinAssignment(void)1507 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
1508 {
1509 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
1510 }
1511
1512 /**
1513 * @brief Freeze APB1 peripherals (group1 peripherals)
1514 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
1515 * @param Periphs This parameter can be a combination of the following values:
1516 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1517 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1518 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
1519 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
1520 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1521 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
1522 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
1523 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
1524 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
1525 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1526 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1527 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1528 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1529 * @arg @ref LL_DBGMCU_APB1_GRP1_I3C1_STOP
1530 * @retval None
1531 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1532 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1533 {
1534 SET_BIT(DBGMCU->APB1FZR1, Periphs);
1535 }
1536
1537 /**
1538 * @brief Freeze APB1 peripherals (group2 peripherals)
1539 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
1540 * @param Periphs This parameter can be a combination of the following values:
1541 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1542 * @retval None
1543 */
LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)1544 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
1545 {
1546 SET_BIT(DBGMCU->APB1FZR2, Periphs);
1547 }
1548
1549 /**
1550 * @brief Unfreeze APB1 peripherals (group1 peripherals)
1551 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1552 * @param Periphs This parameter can be a combination of the following values:
1553 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1554 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1555 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
1556 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
1557 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1558 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
1559 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
1560 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
1561 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
1562 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1563 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1564 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1565 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1566 * @arg @ref LL_DBGMCU_APB1_GRP1_I3C1_STOP
1567 * @retval None
1568 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1569 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1570 {
1571 CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
1572 }
1573
1574 /**
1575 * @brief Unfreeze APB1 peripherals (group2 peripherals)
1576 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
1577 * @param Periphs This parameter can be a combination of the following values:
1578 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1579 * @retval None
1580 */
LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)1581 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
1582 {
1583 CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
1584 }
1585
1586 /**
1587 * @brief Freeze APB2 peripherals
1588 * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
1589 * @param Periphs This parameter can be a combination of the following values:
1590 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1591 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
1592 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1593 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1594 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1595 * @retval None
1596 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1597 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1598 {
1599 SET_BIT(DBGMCU->APB2FZR, Periphs);
1600 }
1601
1602 /**
1603 * @brief Unfreeze APB2 peripherals
1604 * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1605 * @param Periphs This parameter can be a combination of the following values:
1606 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1607 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
1608 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1609 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1610 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1611 * @retval None
1612 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1613 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1614 {
1615 CLEAR_BIT(DBGMCU->APB2FZR, Periphs);
1616 }
1617
1618 /**
1619 * @brief Freeze APB3 peripherals
1620 * @rmtoll DBGMCU_APB3FZ DBG_TIMx_STOP LL_DBGMCU_APB3_GRP1_FreezePeriph
1621 * @param Periphs This parameter can be a combination of the following values:
1622 * @arg @ref LL_DBGMCU_APB3_GRP1_I2C3_STOP
1623 * @arg @ref LL_DBGMCU_APB3_GRP1_I2C4_STOP
1624 * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM1_STOP
1625 * @arg @ref LL_DBGMCU_APB3_GRP1_RTC_STOP
1626 * @retval None
1627 */
LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)1628 __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)
1629 {
1630 SET_BIT(DBGMCU->APB3FZR, Periphs);
1631 }
1632
1633 /**
1634 * @brief Unfreeze APB3 peripherals
1635 * @rmtoll DBGMCU_APB3FZR DBG_TIMx_STOP LL_DBGMCU_APB3_GRP1_UnFreezePeriph
1636 * @param Periphs This parameter can be a combination of the following values:
1637 * @arg @ref LL_DBGMCU_APB3_GRP1_I2C3_STOP
1638 * @arg @ref LL_DBGMCU_APB3_GRP1_I2C4_STOP
1639 * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM1_STOP
1640 * @arg @ref LL_DBGMCU_APB3_GRP1_RTC_STOP
1641 * @retval None
1642 */
LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)1643 __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)
1644 {
1645 CLEAR_BIT(DBGMCU->APB3FZR, Periphs);
1646 }
1647
1648 /**
1649 * @}
1650 */
1651
1652 #if defined(VREFBUF)
1653 /** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
1654 * @{
1655 */
1656
1657 /**
1658 * @brief Enable Internal voltage reference
1659 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable
1660 * @retval None
1661 */
LL_VREFBUF_Enable(void)1662 __STATIC_INLINE void LL_VREFBUF_Enable(void)
1663 {
1664 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1665 }
1666
1667 /**
1668 * @brief Disable Internal voltage reference
1669 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable
1670 * @retval None
1671 */
LL_VREFBUF_Disable(void)1672 __STATIC_INLINE void LL_VREFBUF_Disable(void)
1673 {
1674 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1675 }
1676
1677 /**
1678 * @brief Enable high impedance (VREF+pin is high impedance)
1679 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
1680 * @retval None
1681 */
LL_VREFBUF_EnableHIZ(void)1682 __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
1683 {
1684 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1685 }
1686
1687 /**
1688 * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
1689 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
1690 * @retval None
1691 */
LL_VREFBUF_DisableHIZ(void)1692 __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
1693 {
1694 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1695 }
1696
1697 /**
1698 * @brief Set the Voltage reference scale
1699 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
1700 * @param Scale This parameter can be one of the following values:
1701 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1702 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1703 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
1704 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE3
1705 * @retval None
1706 */
LL_VREFBUF_SetVoltageScaling(uint32_t Scale)1707 __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
1708 {
1709 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
1710 }
1711
1712 /**
1713 * @brief Get the Voltage reference scale
1714 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
1715 * @retval Returned value can be one of the following values:
1716 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1717 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1718 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
1719 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE3
1720 */
LL_VREFBUF_GetVoltageScaling(void)1721 __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
1722 {
1723 return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
1724 }
1725
1726 /**
1727 * @brief Check if Voltage reference buffer is ready
1728 * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
1729 * @retval State of bit (1 or 0).
1730 */
LL_VREFBUF_IsVREFReady(void)1731 __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
1732 {
1733 return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == VREFBUF_CSR_VRR) ? 1UL : 0UL);
1734 }
1735
1736 /**
1737 * @brief Get the trimming code for VREFBUF calibration
1738 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
1739 * @retval Between 0 and 0x3F
1740 */
LL_VREFBUF_GetTrimming(void)1741 __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
1742 {
1743 return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
1744 }
1745
1746 /**
1747 * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
1748 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
1749 * @param Value Between 0 and 0x3F
1750 * @retval None
1751 */
LL_VREFBUF_SetTrimming(uint32_t Value)1752 __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
1753 {
1754 WRITE_REG(VREFBUF->CCR, Value);
1755 }
1756
1757 /**
1758 * @}
1759 */
1760 #endif /* VREFBUF */
1761
1762 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
1763 * @{
1764 */
1765 /**
1766 * @brief Set FLASH Latency
1767 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
1768 * @param Latency This parameter can be one of the following values:
1769 * @arg @ref LL_FLASH_LATENCY_0
1770 * @arg @ref LL_FLASH_LATENCY_1
1771 * @arg @ref LL_FLASH_LATENCY_2
1772 * @arg @ref LL_FLASH_LATENCY_3
1773 * @arg @ref LL_FLASH_LATENCY_4
1774 * @arg @ref LL_FLASH_LATENCY_5
1775 * @arg @ref LL_FLASH_LATENCY_6
1776 * @arg @ref LL_FLASH_LATENCY_7
1777 * @arg @ref LL_FLASH_LATENCY_8
1778 * @arg @ref LL_FLASH_LATENCY_9
1779 * @arg @ref LL_FLASH_LATENCY_10
1780 * @arg @ref LL_FLASH_LATENCY_11
1781 * @arg @ref LL_FLASH_LATENCY_12
1782 * @arg @ref LL_FLASH_LATENCY_13
1783 * @arg @ref LL_FLASH_LATENCY_14
1784 * @arg @ref LL_FLASH_LATENCY_15
1785 * @retval None
1786 */
LL_FLASH_SetLatency(uint32_t Latency)1787 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1788 {
1789 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1790 }
1791
1792 /**
1793 * @brief Get FLASH Latency
1794 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
1795 * @retval Returned value can be one of the following values:
1796 * @arg @ref LL_FLASH_LATENCY_0
1797 * @arg @ref LL_FLASH_LATENCY_1
1798 * @arg @ref LL_FLASH_LATENCY_2
1799 * @arg @ref LL_FLASH_LATENCY_3
1800 * @arg @ref LL_FLASH_LATENCY_4
1801 * @arg @ref LL_FLASH_LATENCY_5
1802 * @arg @ref LL_FLASH_LATENCY_6
1803 * @arg @ref LL_FLASH_LATENCY_7
1804 * @arg @ref LL_FLASH_LATENCY_8
1805 * @arg @ref LL_FLASH_LATENCY_9
1806 * @arg @ref LL_FLASH_LATENCY_10
1807 * @arg @ref LL_FLASH_LATENCY_11
1808 * @arg @ref LL_FLASH_LATENCY_12
1809 * @arg @ref LL_FLASH_LATENCY_13
1810 * @arg @ref LL_FLASH_LATENCY_14
1811 * @arg @ref LL_FLASH_LATENCY_15
1812 */
LL_FLASH_GetLatency(void)1813 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1814 {
1815 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1816 }
1817
1818 /**
1819 * @}
1820 */
1821
1822
1823 /** @defgroup SYSTEM_LL_EF_ERASE_MEMORIE_STATUS_CLEAR
1824 * @{
1825 */
1826
1827 /**
1828 * @brief Clear Status of End of Erase for ICACHE and PKA RAMs
1829 * @rmtoll MESR IPMEE LL_SBS_ClearEraseEndStatus
1830 * @retval None
1831 */
LL_SBS_ClearEraseEndStatus(void)1832 __STATIC_INLINE void LL_SBS_ClearEraseEndStatus(void)
1833 {
1834 WRITE_REG(SBS->MESR, SBS_MESR_IPMEE);
1835 }
1836
1837 /**
1838 * @brief Get Status of End of Erase for ICACHE and PKA RAMs
1839 * @rmtoll MESR IPMEE LL_SBS_GetEraseEndStatus
1840 * @retval Returned value can be one of the following values:
1841 * @arg LL_SBS_MEMORIES_ERASE_IPMEE_ON_GOING : Erase of ICACHE and PKA RAMs on going or flag cleared by SW
1842 * @arg LL_SBS_MEMORIES_ERASE_IPMEE_ENDED: Erase of ICACHE and PKA RAMs ended
1843 */
LL_SBS_GetEraseEndStatus(void)1844 __STATIC_INLINE uint32_t LL_SBS_GetEraseEndStatus(void)
1845 {
1846 return (uint32_t)(READ_BIT(SBS->MESR, SBS_MESR_IPMEE));
1847 }
1848
1849 /**
1850 * @brief Clear Status of End of Erase after Power-on Reset for SRAM2, BKPRAM, ICACHE, DCACHE and PKA RAMs
1851 * @rmtoll MESR MCLR LL_SBS_ClearEraseAfterResetStatus
1852 * @retval None
1853 */
LL_SBS_ClearEraseAfterResetStatus(void)1854 __STATIC_INLINE void LL_SBS_ClearEraseAfterResetStatus(void)
1855 {
1856 WRITE_REG(SBS->MESR, SBS_MESR_MCLR);
1857 }
1858
1859 /**
1860 * @brief Get Status of End of Erase after Power-on Reset for SRAM2, BKPRAM, ICACHE, DCACHE and PKA RAMs
1861 * @rmtoll MESR MCLR LL_SBS_GetEraseAfterResetStatus
1862 * @retval Returned value can be one of the following values:
1863 * @arg LL_SBS_MEMORIES_ERASE_MCLR_ON_GOING : Erase of memories on going or flag cleared by SW
1864 * @arg LL_SBS_MEMORIES_ERASE_MCLR_ENDED: Erase of memories ended
1865 */
LL_SBS_GetEraseAfterResetStatus(void)1866 __STATIC_INLINE uint32_t LL_SBS_GetEraseAfterResetStatus(void)
1867 {
1868 return (uint32_t)(READ_BIT(SBS->MESR, SBS_MESR_MCLR));
1869 }
1870 /**
1871 * @}
1872 */
1873
1874
1875 /**
1876 * @}
1877 */
1878
1879
1880 /**
1881 * @}
1882 */
1883
1884 #endif /* defined (FLASH) || defined (SBS) || defined (DBGMCU) || defined (VREFBUF) */
1885
1886 /**
1887 * @}
1888 */
1889
1890 #ifdef __cplusplus
1891 }
1892 #endif
1893
1894 #endif /* STM32h5xx_LL_SYSTEM_H */
1895
