1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_ll_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC LL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_LL_RCC_H 21 #define STM32U5xx_LL_RCC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx.h" 29 30 /** @addtogroup STM32U5xx_LL_Driver 31 * @{ 32 */ 33 34 #if defined(RCC) 35 36 /** @defgroup RCC_LL RCC 37 * @{ 38 */ 39 40 /* Private types -------------------------------------------------------------*/ 41 /* Private variables ---------------------------------------------------------*/ 42 /* Private constants ---------------------------------------------------------*/ 43 /** @defgroup RCC_LL_Private_Constants RCC Private Constants 44 * @{ 45 */ 46 /* Defines used to perform offsets*/ 47 /* Offset used to access to RCC_CCIPR1 and RCC_CCIPR2 registers */ 48 #define RCC_OFFSET_CCIPR1 0U 49 #define RCC_OFFSET_CCIPR2 0x04U 50 #define RCC_OFFSET_CCIPR3 0x08U 51 52 /* Defines used for security configuration extension */ 53 #define RCC_SECURE_MASK 0x1FFFU 54 /** 55 * @} 56 */ 57 58 /* Private macros ------------------------------------------------------------*/ 59 /* Exported types ------------------------------------------------------------*/ 60 #if defined(USE_FULL_LL_DRIVER) 61 /** @defgroup RCC_LL_Exported_Types RCC Exported Types 62 * @{ 63 */ 64 65 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure 66 * @{ 67 */ 68 69 /** 70 * @brief RCC Clocks Frequency Structure 71 */ 72 typedef struct 73 { 74 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ 75 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ 76 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ 77 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ 78 uint32_t PCLK3_Frequency; /*!< PCLK3 clock frequency */ 79 } LL_RCC_ClocksTypeDef; 80 81 /** 82 * @} 83 */ 84 85 /** 86 * @} 87 */ 88 #endif /* USE_FULL_LL_DRIVER */ 89 90 /* Exported constants --------------------------------------------------------*/ 91 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants 92 * @{ 93 */ 94 95 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation 96 * @brief Defines used to adapt values of different oscillators 97 * @note These values could be modified in the user environment according to 98 * HW set-up. 99 * @{ 100 */ 101 #if !defined (HSE_VALUE) 102 #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ 103 #endif /* HSE_VALUE */ 104 105 #if !defined (HSI_VALUE) 106 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ 107 #endif /* HSI_VALUE */ 108 109 #if !defined (LSE_VALUE) 110 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ 111 #endif /* LSE_VALUE */ 112 113 #if !defined (LSI_VALUE) 114 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ 115 #endif /* LSI_VALUE */ 116 117 #if !defined (HSI48_VALUE) 118 #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ 119 #endif /* HSI48_VALUE */ 120 121 #if !defined (EXTERNAL_SAI1_CLOCK_VALUE) 122 #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */ 123 #endif /* EXTERNAL_SAI1_CLOCK_VALUE */ 124 125 #if !defined (EXTERNAL_SAI2_CLOCK_VALUE) 126 #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz */ 127 #endif /* EXTERNAL_SAI2_CLOCK_VALUE */ 128 /** 129 * @} 130 */ 131 132 /** @defgroup RCC_LL_EC_LSIPRE LSI prescaler 133 * @{ 134 */ 135 #define LL_RCC_LSI_DIV_1 0x00000000U /*!< LSI divided by 1 */ 136 #define LL_RCC_LSI_DIV_128 RCC_BDCR_LSIPREDIV /*!< LSI divided by 128 */ 137 /** 138 * @} 139 */ 140 141 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability 142 * @{ 143 */ 144 #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */ 145 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */ 146 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */ 147 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ 148 /** 149 * @} 150 */ 151 152 /** @defgroup RCC_LL_EC_MSI_OSCILLATOR MSI clock Trimming 153 * @{ 154 */ 155 #define LL_RCC_MSI_OSCILLATOR_0 0x00000000U /*!< MSI clock trimming for ranges 0 to 3 */ 156 #define LL_RCC_MSI_OSCILLATOR_1 0x00000005U /*!< MSI clock trimming for ranges 4 to 7 */ 157 #define LL_RCC_MSI_OSCILLATOR_2 0x0000000AU /*!< MSI clock trimming for ranges 8 to 11 */ 158 #define LL_RCC_MSI_OSCILLATOR_3 0x0000000FU /*!< MSI clock trimming for ranges 12 to 15 */ 159 /** 160 * @} 161 */ 162 163 164 /** @defgroup RCC_LL_EC_MSISRANGE MSIS Clock Range 165 * @{ 166 */ 167 #define LL_RCC_MSISRANGE_0 0x00000000U /*!< MSIS = 48 MHz */ 168 #define LL_RCC_MSISRANGE_1 RCC_ICSCR1_MSISRANGE_0 /*!< MSIS = 24 MHz */ 169 #define LL_RCC_MSISRANGE_2 RCC_ICSCR1_MSISRANGE_1 /*!< MSIS = 16 MHz */ 170 #define LL_RCC_MSISRANGE_3 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1) /*!< MSIS = 12 MHz */ 171 #define LL_RCC_MSISRANGE_4 RCC_ICSCR1_MSISRANGE_2 /*!< MSIS = 4 MHz */ 172 #define LL_RCC_MSISRANGE_5 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2) /*!< MSIS = 2 MHz */ 173 #define LL_RCC_MSISRANGE_6 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSIS = 1.5 MHz */ 174 #define LL_RCC_MSISRANGE_7 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSIS = 1 MHz */ 175 #define LL_RCC_MSISRANGE_8 RCC_ICSCR1_MSISRANGE_3 /*!< MSIS = 3.072 MHz */ 176 #define LL_RCC_MSISRANGE_9 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 1.536 MHz */ 177 #define LL_RCC_MSISRANGE_10 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 1.024 MHz */ 178 #define LL_RCC_MSISRANGE_11 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 768 KHz */ 179 #define LL_RCC_MSISRANGE_12 (RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 400 KHz */ 180 #define LL_RCC_MSISRANGE_13 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 200 KHz */ 181 #define LL_RCC_MSISRANGE_14 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 150 KHz */ 182 #define LL_RCC_MSISRANGE_15 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1| RCC_ICSCR1_MSISRANGE_2 | \ 183 RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 100 KHz */ 184 /** 185 * @} 186 */ 187 188 /** @defgroup RCC_LL_EC_MSIKRANGE MSIK Clock Range 189 * @{ 190 */ 191 #define LL_RCC_MSIKRANGE_0 0x00000000U /*!< MSIK = 48 MHz */ 192 #define LL_RCC_MSIKRANGE_1 RCC_ICSCR1_MSIKRANGE_0 /*!< MSIK = 24 MHz */ 193 #define LL_RCC_MSIKRANGE_2 RCC_ICSCR1_MSIKRANGE_1 /*!< MSIK = 16 MHz */ 194 #define LL_RCC_MSIKRANGE_3 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1) /*!< MSIK = 12 MHz */ 195 #define LL_RCC_MSIKRANGE_4 RCC_ICSCR1_MSIKRANGE_2 /*!< MSIK = 4 MHz */ 196 #define LL_RCC_MSIKRANGE_5 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 2 MHz */ 197 #define LL_RCC_MSIKRANGE_6 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1.5 MHz */ 198 #define LL_RCC_MSIKRANGE_7 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1 MHz */ 199 #define LL_RCC_MSIKRANGE_8 RCC_ICSCR1_MSIKRANGE_3 /*!< MSIK = 3.072 MHz */ 200 #define LL_RCC_MSIKRANGE_9 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.536 MHz */ 201 #define LL_RCC_MSIKRANGE_10 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.024 MHz */ 202 #define LL_RCC_MSIKRANGE_11 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 768 KHz */ 203 #define LL_RCC_MSIKRANGE_12 (RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 400 KHz */ 204 #define LL_RCC_MSIKRANGE_13 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 200 KHz */ 205 #define LL_RCC_MSIKRANGE_14 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 150 KHz */ 206 #define LL_RCC_MSIKRANGE_15 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | \ 207 RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 100 KHz */ 208 /** 209 * @} 210 */ 211 212 /** @defgroup RCC_LL_EC_MSISSRANGE MSIS range after Standby mode 213 * @{ 214 */ 215 #define LL_RCC_MSISSRANGE_4 RCC_CSR_MSISSRANGE_2 /*!< MSIS = 4 MHz */ 216 #define LL_RCC_MSISSRANGE_5 (RCC_CSR_MSISSRANGE_2 | RCC_CSR_MSISSRANGE_0) /*!< MSIS = 2 MHz */ 217 #define LL_RCC_MSISSRANGE_6 (RCC_CSR_MSISSRANGE_2 | RCC_CSR_MSISSRANGE_1) /*!< MSIS = 1.5 MHz */ 218 #define LL_RCC_MSISSRANGE_7 (RCC_CSR_MSISSRANGE_0 | RCC_CSR_MSISSRANGE_2 | RCC_CSR_MSISSRANGE_1) /*!< MSIS = 1 MHz */ 219 #define LL_RCC_MSISSRANGE_8 RCC_CSR_MSISSRANGE_3 /*!< MSIS = 3.072 MHz*/ 220 /** 221 * @} 222 */ 223 224 /** @defgroup RCC_LL_EC_MSIKSRANGE MSIK range after Standby mode 225 * @{ 226 */ 227 #define LL_RCC_MSIKSRANGE_4 RCC_CSR_MSIKSRANGE_2 /*!< MSIK = 4 MHz */ 228 #define LL_RCC_MSIKSRANGE_5 (RCC_CSR_MSIKSRANGE_2 | RCC_CSR_MSIKSRANGE_0) /*!< MSIK = 2 MHz */ 229 #define LL_RCC_MSIKSRANGE_6 (RCC_CSR_MSIKSRANGE_2 | RCC_CSR_MSIKSRANGE_1) /*!< MSIK = 1.5 MHz */ 230 #define LL_RCC_MSIKSRANGE_7 (RCC_CSR_MSIKSRANGE_2 | RCC_CSR_MSIKSRANGE_1 | RCC_CSR_MSIKSRANGE_0) /*!< MSIK = 1 MHz */ 231 #define LL_RCC_MSIKSRANGE_8 RCC_CSR_MSIKSRANGE_3 /*!< MSIK = 3.072 MHz*/ 232 /** 233 * @} 234 */ 235 236 /** @defgroup RCC_LL_EC_MSIPLLMODE MSIS/MSIK Pll Mode 237 * @{ 238 */ 239 #define LL_RCC_PLLMODE_MSIS RCC_CR_MSIPLLSEL /*!< MSIS selection for Pll Mode */ 240 #define LL_RCC_PLLMODE_MSIK 0U /*!< MSIK selection for Pll Mode */ 241 /** 242 * @} 243 */ 244 245 /** @defgroup RCC_LL_EC_MSIBIASMODE MSI BIAS Mode 246 * @{ 247 */ 248 #define LL_RCC_MSIBIASMODE_SAMPLING RCC_ICSCR1_MSIBIAS /*!< Sampling mode selection for MSI*/ 249 #define LL_RCC_MSIBIASMODE_CONTINUOUS 0U /*!< Continuous mode selection for MSI*/ 250 /** 251 * @} 252 */ 253 254 /** @defgroup RCC_LL_EC_HSEEXT EXTERNAL HSE Mode 255 * @{ 256 */ 257 #define LL_RCC_HSE_ANALOG_MODE 0U /*!< HSE clock used as ANALOG clock source */ 258 #define LL_RCC_HSE_DIGITAL_MODE RCC_CR_HSEEXT /*!< HSE clock used as DIGITAL clock source */ 259 /** 260 * @} 261 */ 262 263 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection 264 * @{ 265 */ 266 #define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */ 267 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */ 268 /** 269 * @} 270 */ 271 272 273 /** @defgroup RCC_LL_EC_PLL1MBOOST_DIV EPOD prescaler 274 * @{ 275 */ 276 #define LL_RCC_PLL1MBOOST_DIV_1 0x00000000U /*!< PLL1CLK not divided */ 277 #define LL_RCC_PLL1MBOOST_DIV_2 RCC_PLL1CFGR_PLL1MBOOST_0 /*!< PLL1CLK divided by 2 */ 278 #define LL_RCC_PLL1MBOOST_DIV_4 RCC_PLL1CFGR_PLL1MBOOST_1 /*!< PLL1CLK divided by 4 */ 279 #define LL_RCC_PLL1MBOOST_DIV_6 (RCC_PLL1CFGR_PLL1MBOOST_1 | RCC_PLL1CFGR_PLL1MBOOST_0) /*!< PLL1CLK divided by 6 */ 280 #define LL_RCC_PLL1MBOOST_DIV_8 RCC_PLL1CFGR_PLL1MBOOST_2 /*!< PLL1CLK divided by 8 */ 281 #define LL_RCC_PLL1MBOOST_DIV_10 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_0) /*!< PLL1CLK divided by 10 */ 282 #define LL_RCC_PLL1MBOOST_DIV_12 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1) /*!< PLL1CLK divided by 12 */ 283 #define LL_RCC_PLL1MBOOST_DIV_14 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1 | \ 284 RCC_PLL1CFGR_PLL1MBOOST_0) /*!< PLL1CLK divided by 14 */ 285 #define LL_RCC_PLL1MBOOST_DIV_16 RCC_PLL1CFGR_PLL1MBOOST_3 /*!< PLL1CLK divided by 16 */ 286 /** 287 * @} 288 */ 289 290 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch 291 * @{ 292 */ 293 #define LL_RCC_SYS_CLKSOURCE_MSIS 0x00000000U /*!< MSIS selection as system clock */ 294 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR1_SW_0 /*!< HSI oscillator selection as system clock */ 295 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE selection as system clock */ 296 #define LL_RCC_SYS_CLKSOURCE_PLL1 (RCC_CFGR1_SW_1 | RCC_CFGR1_SW_0) /*!< PLL selection as system clock */ 297 /** 298 * @} 299 */ 300 301 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status 302 * @{ 303 */ 304 #define LL_RCC_SYS_CLKSOURCE_STATUS_MSIS 0x00000000U /*!< MSIS used as system clock */ 305 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR1_SWS_0 /*!< HSI used as system clock */ 306 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE used as system clock */ 307 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 (RCC_CFGR1_SWS_1 | RCC_CFGR1_SWS_0) /*!< PLL1 used as system clock */ 308 /** 309 * @} 310 */ 311 312 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler 313 * @{ 314 */ 315 #define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */ 316 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR2_HPRE_3 /*!< SYSCLK divided by 2 */ 317 #define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 4 */ 318 #define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_1) /*!< SYSCLK divided by 8 */ 319 #define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 16 */ 320 #define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2) /*!< SYSCLK divided by 64 */ 321 #define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 128 */ 322 #define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1) /*!< SYSCLK divided by 256 */ 323 #define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1 | \ 324 RCC_CFGR2_HPRE_0)/*!< SYSCLK divided by 512 */ 325 /** 326 * @} 327 */ 328 329 /** @defgroup RCC_LL_EC_SYSTICK_CLKSOURCE SYSTICK clock source selection 330 * @{ 331 */ 332 #define LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 0x00000000U /*!< HCLKDIV8 clock used as SYSTICK clock source */ 333 #define LL_RCC_SYSTICK_CLKSOURCE_LSI RCC_CCIPR1_SYSTICKSEL_0 /*!< LSI clock used as SYSTICK clock source */ 334 #define LL_RCC_SYSTICK_CLKSOURCE_LSE RCC_CCIPR1_SYSTICKSEL_1 /*!< LSE clock used as SYSTICK clock source */ 335 /** 336 * @} 337 */ 338 339 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) 340 * @{ 341 */ 342 #define LL_RCC_APB1_DIV_1 0x00000000U /*!< HCLK not divided */ 343 #define LL_RCC_APB1_DIV_2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */ 344 #define LL_RCC_APB1_DIV_4 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 4 */ 345 #define LL_RCC_APB1_DIV_8 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1) /*!< HCLK divided by 8 */ 346 #define LL_RCC_APB1_DIV_16 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 16 */ 347 /** 348 * @} 349 */ 350 351 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) 352 * @{ 353 */ 354 #define LL_RCC_APB2_DIV_1 0x00000000U /*!< HCLK not divided */ 355 #define LL_RCC_APB2_DIV_2 RCC_CFGR2_PPRE2_2 /*!< HCLK divided by 2 */ 356 #define LL_RCC_APB2_DIV_4 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 4 */ 357 #define LL_RCC_APB2_DIV_8 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1) /*!< HCLK divided by 8 */ 358 #define LL_RCC_APB2_DIV_16 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 16 */ 359 /** 360 * @} 361 */ 362 363 364 /** @defgroup RCC_LL_EC_APB3_DIV APB high-speed prescaler (APB3) 365 * @{ 366 */ 367 #define LL_RCC_APB3_DIV_1 0x00000000U /*!< HCLK not divided */ 368 #define LL_RCC_APB3_DIV_2 RCC_CFGR3_PPRE3_2 /*!< HCLK divided by 2 */ 369 #define LL_RCC_APB3_DIV_4 (RCC_CFGR3_PPRE3_2 | RCC_CFGR3_PPRE3_0) /*!< HCLK divided by 4 */ 370 #define LL_RCC_APB3_DIV_8 (RCC_CFGR3_PPRE3_2 | RCC_CFGR3_PPRE3_1) /*!< HCLK divided by 8 */ 371 #define LL_RCC_APB3_DIV_16 (RCC_CFGR3_PPRE3_2 | RCC_CFGR3_PPRE3_1 | RCC_CFGR3_PPRE3_0) /*!< HCLK divided by 16 */ 372 /** 373 * @} 374 */ 375 376 #if defined(RCC_CFGR2_PPRE_DPHY) 377 /** @defgroup RCC_LL_EC_DPHY_DIV DSI PHY clock prescaler (DCLK) 378 * @{ 379 */ 380 #define LL_RCC_DPHY_DIV_1 0x00000000U /*!< DCLK not divided */ 381 #define LL_RCC_DPHY_DIV_2 RCC_CFGR2_PPRE_DPHY_2 /*!< DCLK divided by 2 */ 382 #define LL_RCC_DPHY_DIV_4 (RCC_CFGR2_PPRE_DPHY_2 | RCC_CFGR2_PPRE_DPHY_0) /*!< DCLK divided by 4 */ 383 #define LL_RCC_DPHY_DIV_8 (RCC_CFGR2_PPRE_DPHY_2 | RCC_CFGR2_PPRE_DPHY_1) /*!< DCLK divided by 8 */ 384 #define LL_RCC_DPHY_DIV_16 (RCC_CFGR2_PPRE_DPHY_2 | RCC_CFGR2_PPRE_DPHY_1 | RCC_CFGR2_PPRE_DPHY_0) /*!< DCLK divided by 16 */ 385 /** 386 * @} 387 */ 388 #endif /* RCC_CFGR2_PPRE_DPHY */ 389 390 /** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection 391 * @{ 392 */ 393 #define LL_RCC_STOP_WAKEUPCLOCK_MSIS 0x00000000U /*!< MSIS selection after wake-up from STOP */ 394 #define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR1_STOPWUCK /*!< HSI selection after wake-up from STOP */ 395 /** 396 * @} 397 */ 398 399 /** @defgroup RCC_LL_EC_STOP_WAKEUPKERCLOCK Wakeup from Stop kernel clock automatic enable selection 400 * @{ 401 */ 402 #define LL_RCC_STOP_WAKEUPKERCLOCK_MSIK 0x00000000U /*!< MSIK oscillator automatically enabled when exiting Stop mode */ 403 #define LL_RCC_STOP_WAKEUPKERCLOCK_HSI RCC_CFGR1_STOPKERWUCK /*!< HSI oscillator automatically enabled when exiting Stop mode */ 404 /** 405 * @} 406 */ 407 408 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection 409 * @{ 410 */ 411 #define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */ 412 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR1_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ 413 #define LL_RCC_MCO1SOURCE_MSIS RCC_CFGR1_MCOSEL_1 /*!< MSIS selection as MCO1 source */ 414 #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_1) /*!< HSI selection as MCO1 source */ 415 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR1_MCOSEL_2 /*!< HSE selection as MCO1 source */ 416 #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_2) /*!< Main PLL selection as MCO1 source */ 417 #define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR1_MCOSEL_1 | RCC_CFGR1_MCOSEL_2) /*!< LSI selection as MCO1 source */ 418 #define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_1| RCC_CFGR1_MCOSEL_2)/*!< LSE selection as MCO1 source */ 419 #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR1_MCOSEL_3 /*!< HSI48 selection as MCO1 source */ 420 #define LL_RCC_MCO1SOURCE_MSIK (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_3) /*!< MSIK selection as MCO1 source */ 421 /** 422 * @} 423 */ 424 425 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler 426 * @{ 427 */ 428 #define LL_RCC_MCO1_DIV_1 0x00000000U /*!< MCO not divided */ 429 #define LL_RCC_MCO1_DIV_2 RCC_CFGR1_MCOPRE_0 /*!< MCO divided by 2 */ 430 #define LL_RCC_MCO1_DIV_4 RCC_CFGR1_MCOPRE_1 /*!< MCO divided by 4 */ 431 #define LL_RCC_MCO1_DIV_8 (RCC_CFGR1_MCOPRE_1 | RCC_CFGR1_MCOPRE_0) /*!< MCO divided by 8 */ 432 #define LL_RCC_MCO1_DIV_16 RCC_CFGR1_MCOPRE_2 /*!< MCO divided by 16 */ 433 /** 434 * @} 435 */ 436 437 #if defined(USE_FULL_LL_DRIVER) 438 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency 439 * @{ 440 */ 441 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ 442 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ 443 /** 444 * @} 445 */ 446 #endif /* USE_FULL_LL_DRIVER */ 447 448 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection 449 * @{ 450 */ 451 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ 452 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 453 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 454 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ 455 /** 456 * @} 457 */ 458 459 /** @defgroup RCC_LL_EC_USART_CLKSOURCE Peripheral USARTx clock source selection 460 * @{ 461 */ 462 #define LL_RCC_USART1_CLKSOURCE_PCLK2 ((RCC_OFFSET_CCIPR1 << 24U)| (RCC_CCIPR1_USART1SEL_Pos << 16U)) /*!< PCLK2 clock used as USART1 clock source */ 463 #define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART1SEL_Pos << 16U) | (RCC_CCIPR1_USART1SEL_0 >> RCC_CCIPR1_USART1SEL_Pos)) /*!< SYSCLK clock used as USART1 clock source */ 464 #define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART1SEL_Pos << 16U) | (RCC_CCIPR1_USART1SEL_1 >> RCC_CCIPR1_USART1SEL_Pos)) /*!< HSI clock used as USART1 clock source */ 465 #define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART1SEL_Pos << 16U) | (RCC_CCIPR1_USART1SEL >> RCC_CCIPR1_USART1SEL_Pos)) /*!< LSE clock used as USART1 clock source */ 466 #if defined(USART2) 467 #define LL_RCC_USART2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U)) /*!< PCLK1 clock used as USART2 clock source */ 468 #define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U) | (RCC_CCIPR1_USART2SEL_0 >> RCC_CCIPR1_USART2SEL_Pos)) /*!< SYSCLK clock used as USART2 clock source */ 469 #define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U) | (RCC_CCIPR1_USART2SEL_1 >> RCC_CCIPR1_USART2SEL_Pos)) /*!< HSI clock used as USART2 clock source */ 470 #define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U) | (RCC_CCIPR1_USART2SEL >> RCC_CCIPR1_USART2SEL_Pos)) /*!< LSE clock used as USART2 clock source */ 471 #endif /* USART2 */ 472 #define LL_RCC_USART3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U)) /*!< PCLK3 clock used as USART3 clock source */ 473 #define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U) | (RCC_CCIPR1_USART3SEL_0 >> RCC_CCIPR1_USART3SEL_Pos)) /*!< SYSCLK clock used as USART3 clock source */ 474 #define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U) | (RCC_CCIPR1_USART3SEL_1 >> RCC_CCIPR1_USART3SEL_Pos)) /*!< HSI clock used as USART3 clock source */ 475 #define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U) | (RCC_CCIPR1_USART3SEL >> RCC_CCIPR1_USART3SEL_Pos)) /*!< LSE clock used as USART3 clock source */ 476 #if defined (RCC_CCIPR2_USART6SEL) 477 #define LL_RCC_USART6_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U)) /*!< PCLK1 clock used as USART6 clock source */ 478 #define LL_RCC_USART6_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | (RCC_CCIPR2_USART6SEL_0 >> RCC_CCIPR2_USART6SEL_Pos)) /*!< SYSCLK clock used as USART6 clock source */ 479 #define LL_RCC_USART6_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | (RCC_CCIPR2_USART6SEL_1 >> RCC_CCIPR2_USART6SEL_Pos)) /*!< HSI clock used as USART6 clock source */ 480 #define LL_RCC_USART6_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | (RCC_CCIPR2_USART6SEL >> RCC_CCIPR2_USART6SEL_Pos)) /*!< LSE clock used as USART6 clock source */ 481 /* Legacy define */ 482 #define LL_RCC_USART6_CLKSOURCE_PCLK2 LL_RCC_USART6_CLKSOURCE_PCLK1 483 #endif /* RCC_CCIPR2_USART6SEL */ 484 /** 485 * @} 486 */ 487 488 /** @defgroup RCC_LL_EC_UART_CLKSOURCE Peripheral UARTx clock source selection 489 * @{ 490 */ 491 #define LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR1_UART4SEL << 16U) /*!< PCLK1 clock used as UART4 clock source */ 492 #define LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR1_UART4SEL << 16U) | RCC_CCIPR1_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */ 493 #define LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR1_UART4SEL << 16U) | RCC_CCIPR1_UART4SEL_1) /*!< HSI clock used as UART4 clock source */ 494 #define LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR1_UART4SEL << 16U) | RCC_CCIPR1_UART4SEL) /*!< LSE clock used as UART4 clock source */ 495 #define LL_RCC_UART5_CLKSOURCE_PCLK1 (RCC_CCIPR1_UART5SEL << 16U) /*!< PCLK1 clock used as UART5 clock source */ 496 #define LL_RCC_UART5_CLKSOURCE_SYSCLK ((RCC_CCIPR1_UART5SEL << 16U) | RCC_CCIPR1_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */ 497 #define LL_RCC_UART5_CLKSOURCE_HSI ((RCC_CCIPR1_UART5SEL << 16U) | RCC_CCIPR1_UART5SEL_1) /*!< HSI clock used as UART5 clock source */ 498 #define LL_RCC_UART5_CLKSOURCE_LSE ((RCC_CCIPR1_UART5SEL << 16U) | RCC_CCIPR1_UART5SEL) /*!< LSE clock used as UART5 clock source */ 499 /** 500 * @} 501 */ 502 503 /** @defgroup RCC_LL_EC_LPUART_CLKSOURCE Peripheral LPUARTx clock source selection 504 * @{ 505 */ 506 #define LL_RCC_LPUART1_CLKSOURCE_PCLK3 0x00000000U /*!< PCLK3 clock used as LPUART1 clock source */ 507 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR3_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */ 508 #define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR3_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */ 509 #define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_1) /*!< LSE clock used as LPUART1 clock source */ 510 #define LL_RCC_LPUART1_CLKSOURCE_MSIK RCC_CCIPR3_LPUART1SEL_2 /*!< MSIK clock used as LPUART1 clock source */ 511 /** 512 * @} 513 */ 514 515 /** @defgroup RCC_LL_EC_I2C_CLKSOURCE Peripheral I2Cx clock source selection 516 * @{ 517 */ 518 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */ 519 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \ 520 (RCC_CCIPR1_I2C1SEL_0 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */ 521 #define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \ 522 (RCC_CCIPR1_I2C1SEL_1 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */ 523 #define LL_RCC_I2C1_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \ 524 (RCC_CCIPR1_I2C1SEL >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< MSIK clock used as I2C1 clock source */ 525 #define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */ 526 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \ 527 (RCC_CCIPR1_I2C2SEL_0 >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */ 528 #define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \ 529 (RCC_CCIPR1_I2C2SEL_1 >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */ 530 #define LL_RCC_I2C2_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \ 531 (RCC_CCIPR1_I2C2SEL >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< MSIK clock used as I2C2 clock source */ 532 #define LL_RCC_I2C3_CLKSOURCE_PCLK3 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U)) /*!< PCLK3 clock used as I2C3 clock source */ 533 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \ 534 (RCC_CCIPR3_I2C3SEL_0 >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */ 535 #define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \ 536 (RCC_CCIPR3_I2C3SEL_1 >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */ 537 #define LL_RCC_I2C3_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \ 538 (RCC_CCIPR3_I2C3SEL >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< MSIK clock used as I2C3 clock source */ 539 #define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */ 540 #define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \ 541 (RCC_CCIPR1_I2C4SEL_0 >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */ 542 #define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \ 543 (RCC_CCIPR1_I2C4SEL_1 >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */ 544 #define LL_RCC_I2C4_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \ 545 (RCC_CCIPR1_I2C4SEL >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< MSIK clock used as I2C4 clock source */ 546 #if defined (RCC_CCIPR2_I2C5SEL) 547 #define LL_RCC_I2C5_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C5 clock source */ 548 #define LL_RCC_I2C5_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \ 549 (RCC_CCIPR2_I2C5SEL_0 >> RCC_CCIPR2_I2C5SEL_Pos)) /*!< SYSCLK clock used as I2C5 clock source */ 550 #define LL_RCC_I2C5_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \ 551 (RCC_CCIPR2_I2C5SEL_1 >> RCC_CCIPR2_I2C5SEL_Pos)) /*!< HSI clock used as I2C5 clock source */ 552 #define LL_RCC_I2C5_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \ 553 (RCC_CCIPR2_I2C5SEL >> RCC_CCIPR2_I2C5SEL_Pos)) /*!< MSIK clock used as I2C5 clock source */ 554 #endif /* RCC_CCIPR2_I2C5SEL */ 555 #if defined (RCC_CCIPR2_I2C6SEL) 556 #define LL_RCC_I2C6_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C6 clock source */ 557 #define LL_RCC_I2C6_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \ 558 (RCC_CCIPR2_I2C6SEL_0 >> RCC_CCIPR2_I2C6SEL_Pos)) /*!< SYSCLK clock used as I2C6 clock source */ 559 #define LL_RCC_I2C6_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \ 560 (RCC_CCIPR2_I2C6SEL_1 >> RCC_CCIPR2_I2C6SEL_Pos)) /*!< HSI clock used as I2C6 clock source */ 561 #define LL_RCC_I2C6_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \ 562 (RCC_CCIPR2_I2C6SEL >> RCC_CCIPR2_I2C6SEL_Pos)) /*!< MSIK clock used as I2C6 clock source */ 563 #endif /* RCC_CCIPR2_I2C6SEL */ 564 /** 565 * @} 566 */ 567 568 /** @defgroup RCC_LL_EC_SPI_CLKSOURCE Peripheral SPIx clock source selection 569 * @{ 570 */ 571 #define LL_RCC_SPI1_CLKSOURCE_PCLK2 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U)) /*!< PCLK2 clock used as SPI1 clock source */ 572 #define LL_RCC_SPI1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \ 573 (RCC_CCIPR1_SPI1SEL_0 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< SYSCLK clock used as SPI1 clock source */ 574 #define LL_RCC_SPI1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \ 575 (RCC_CCIPR1_SPI1SEL_1 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< HSI clock used as SPI1 clock source */ 576 #define LL_RCC_SPI1_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \ 577 (RCC_CCIPR1_SPI1SEL >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< MSIK clock used as SPI1 clock source */ 578 #define LL_RCC_SPI2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U)) /*!< PCLK1 clock used as SPI2 clock source */ 579 #define LL_RCC_SPI2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \ 580 (RCC_CCIPR1_SPI2SEL_0 >> RCC_CCIPR1_SPI2SEL_Pos)) /*!< SYSCLK clock used as SPI2 clock source */ 581 #define LL_RCC_SPI2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \ 582 (RCC_CCIPR1_SPI2SEL_1 >> RCC_CCIPR1_SPI2SEL_Pos)) /*!< HSI clock used as SPI2 clock source */ 583 #define LL_RCC_SPI2_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \ 584 (RCC_CCIPR1_SPI2SEL >> RCC_CCIPR1_SPI2SEL_Pos)) /*!< MSIK clock used as SPI2 clock source */ 585 #define LL_RCC_SPI3_CLKSOURCE_PCLK3 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U)) /*!< PCLK3 clock used as SPI3 clock source */ 586 #define LL_RCC_SPI3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \ 587 (RCC_CCIPR3_SPI3SEL_0 >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< SYSCLK clock used as SPI3 clock source */ 588 #define LL_RCC_SPI3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \ 589 (RCC_CCIPR3_SPI3SEL_1 >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< HSI clock used as SPI3 clock source */ 590 #define LL_RCC_SPI3_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \ 591 (RCC_CCIPR3_SPI3SEL >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< MSIK clock used as SPI3 clock source */ 592 /** 593 * @} 594 */ 595 596 /** @defgroup RCC_LL_EC_LPTIM_CLKSOURCE Peripheral LPTIMx clock source selection 597 * @{ 598 */ 599 #define LL_RCC_LPTIM1_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U)) /*!< MSIK clock used as LPTIM1 clock source */ 600 #define LL_RCC_LPTIM1_CLKSOURCE_LSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \ 601 (RCC_CCIPR3_LPTIM1SEL_0 >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LSI clock used as LPTIM1 clock source */ 602 #define LL_RCC_LPTIM1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \ 603 (RCC_CCIPR3_LPTIM1SEL_1 >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< HSI clock used as LPTIM1 clock source */ 604 #define LL_RCC_LPTIM1_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \ 605 (RCC_CCIPR3_LPTIM1SEL >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LSE clock used as LPTIM1 clock source */ 606 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U)) /*!< PCLK1 clock used as LPTIM2 clock source */ 607 #define LL_RCC_LPTIM2_CLKSOURCE_LSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \ 608 (RCC_CCIPR1_LPTIM2SEL_0 >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LSI clock used as LPTIM2 clock source */ 609 #define LL_RCC_LPTIM2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \ 610 (RCC_CCIPR1_LPTIM2SEL_1 >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< HSI clock used as LPTIM2 clock source */ 611 #define LL_RCC_LPTIM2_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \ 612 (RCC_CCIPR1_LPTIM2SEL >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LSE clock used as LPTIM2 clock source */ 613 #define LL_RCC_LPTIM34_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U)) /*!< MSIK clock used as LPTIM34 clock source*/ 614 #define LL_RCC_LPTIM34_CLKSOURCE_LSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \ 615 (RCC_CCIPR3_LPTIM34SEL_0 >> RCC_CCIPR3_LPTIM34SEL_Pos)) /*!< LSI clock used as LPTIM34 clock source */ 616 #define LL_RCC_LPTIM34_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \ 617 (RCC_CCIPR3_LPTIM34SEL_1 >> RCC_CCIPR3_LPTIM34SEL_Pos)) /*!< HSI clock used as LPTIM34 clock source */ 618 #define LL_RCC_LPTIM34_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \ 619 (RCC_CCIPR3_LPTIM34SEL >> RCC_CCIPR3_LPTIM34SEL_Pos)) /*!< LSE clock used as LPTIM34 clock source */ 620 /** 621 * @} 622 */ 623 624 /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN kernel clock source selection 625 * @{ 626 */ 627 #define LL_RCC_FDCAN_CLKSOURCE_HSE 0x00000000U /*!< HSE clock used as FDCAN kernel clock source */ 628 #define LL_RCC_FDCAN_CLKSOURCE_PLL1 RCC_CCIPR1_FDCANSEL_0 /*!< PLL1 Q clock used as FDCAN kernel clock source */ 629 #define LL_RCC_FDCAN_CLKSOURCE_PLL2 RCC_CCIPR1_FDCANSEL_1 /*!< PLL2 P clock used as FDCAN kernel clock source */ 630 /** 631 * @} 632 */ 633 634 /** @defgroup RCC_LL_EC_SAI_CLKSOURCE Peripheral SAIx clock source selection 635 * @{ 636 */ 637 #define LL_RCC_SAI1_CLKSOURCE_PLL2 (RCC_CCIPR2_SAI1SEL << 16U) /*!< PLL2 clock used as SAI1 clock source */ 638 #define LL_RCC_SAI1_CLKSOURCE_PLL3 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0) /*!< PLL3 clock used as SAI1 clock source */ 639 #define LL_RCC_SAI1_CLKSOURCE_PLL1 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< PLL1 clock used as SAI1 clock source */ 640 #define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */ 641 #define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | \ 642 RCC_CCIPR2_SAI1SEL_0)) /*!< External input clock used as SAI1 clock source */ 643 #if defined(SAI2) 644 #define LL_RCC_SAI2_CLKSOURCE_PLL2 (RCC_CCIPR2_SAI2SEL << 16U) /*!< PLL2 clock used as SAI2 clock source */ 645 #define LL_RCC_SAI2_CLKSOURCE_PLL3 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_0) /*!< PLL3 clock used as SAI2 clock source */ 646 #define LL_RCC_SAI2_CLKSOURCE_PLL1 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_1) /*!< PLL1clock used as SAI2 clock source */ 647 #define LL_RCC_SAI2_CLKSOURCE_HSI ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_2) /*!< HSI clock used as SAI2 clock source */ 648 #define LL_RCC_SAI2_CLKSOURCE_PIN ((RCC_CCIPR2_SAI2SEL << 16U) | (RCC_CCIPR2_SAI2SEL_1 | \ 649 RCC_CCIPR2_SAI2SEL_0)) /*!< External input clock used as SAI2 clock source */ 650 #endif /* SAI2 */ 651 /** 652 * @} 653 */ 654 655 /** @defgroup RCC_LL_EC_SDMMC_KERNELCLKSOURCE Peripheral SDMMC1/2 kernel clock source selection 656 * @{ 657 */ 658 #define LL_RCC_SDMMC12_KERNELCLKSOURCE_48CLK 0x00000000U /*!< 48MHz clock from internal multiplexor used as SDMMC1/2 clock source */ 659 #define LL_RCC_SDMMC12_KERNELCLKSOURCE_PLL1 RCC_CCIPR2_SDMMCSEL /*!< PLL1 "P" used as SDMMC1/2 clock source */ 660 /** 661 * @} 662 */ 663 664 /** @defgroup RCC_LL_EC_SDMMC12_CLKSOURCE Peripheral SDMMC clock source selection 665 * @{ 666 */ 667 #define LL_RCC_SDMMC12_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as SDMMC1/2 clock source */ 668 #define LL_RCC_SDMMC12_CLKSOURCE_PLL2 RCC_CCIPR1_ICLKSEL_0 /*!< PLL2 "Q" clock used as SDMMC1/2 clock source */ 669 #define LL_RCC_SDMMC12_CLKSOURCE_PLL1 RCC_CCIPR1_ICLKSEL_1 /*!< PLL1 "Q" clock used as SDMMC1/2 clock source */ 670 #define LL_RCC_SDMMC12_CLKSOURCE_MSIK RCC_CCIPR1_ICLKSEL /*!< MSIK clock used as SDMMC1/2 clock source */ 671 /** 672 * @} 673 */ 674 675 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection 676 * @{ 677 */ 678 #define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as RNG clock source */ 679 #define LL_RCC_RNG_CLKSOURCE_HSI48_DIV2 RCC_CCIPR2_RNGSEL_0 /*!< HSI48/2 clock used as RNG clock source */ 680 #define LL_RCC_RNG_CLKSOURCE_HSI RCC_CCIPR2_RNGSEL_1 /*!< HSI clock used as RNG clock source */ 681 /** 682 * @} 683 */ 684 685 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection 686 * @{ 687 */ 688 #define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB clock source */ 689 #define LL_RCC_USB_CLKSOURCE_PLL2 RCC_CCIPR1_ICLKSEL_0 /*!< PLL2 "Q" clock used as USB clock source */ 690 #define LL_RCC_USB_CLKSOURCE_PLL1 RCC_CCIPR1_ICLKSEL_1 /*!< PLL1 "Q" clock used as USB clock source */ 691 #define LL_RCC_USB_CLKSOURCE_MSIK RCC_CCIPR1_ICLKSEL /*!< MSIK clock used as USB clock source */ 692 /** 693 * @} 694 */ 695 696 /** @defgroup RCC_LL_EC_ADCDAC_CLKSOURCE Peripheral ADCx and DAC1 clock source selection 697 * @{ 698 */ 699 #define LL_RCC_ADCDAC_CLKSOURCE_HCLK 0x00000000U /*!< No clock used as ADCx/DAC1 clock source */ 700 #define LL_RCC_ADCDAC_CLKSOURCE_SYSCLK RCC_CCIPR3_ADCDACSEL_0 /*!< SYSCLK clock used as ADCx/DAC1 clock source */ 701 #define LL_RCC_ADCDAC_CLKSOURCE_PLL2 RCC_CCIPR3_ADCDACSEL_1 /*!< PLL2 clock used as ADCx/DAC1 clock source */ 702 #define LL_RCC_ADCDAC_CLKSOURCE_HSI RCC_CCIPR3_ADCDACSEL_2 /*!< HSI clock used as ADCx/DAC1 clock source */ 703 #define LL_RCC_ADCDAC_CLKSOURCE_HSE (RCC_CCIPR3_ADCDACSEL_1 | RCC_CCIPR3_ADCDACSEL_0) /*!< HSE clock used as ADCx/DAC1 clock source */ 704 #define LL_RCC_ADCDAC_CLKSOURCE_MSIK (RCC_CCIPR3_ADCDACSEL_2 | RCC_CCIPR3_ADCDACSEL_0) /*!< MSIK clock used as ADCx/DAC1 clock source */ 705 /** 706 * @} 707 */ 708 709 /** @defgroup RCC_LL_EC_DAC1_CLKSOURCE Peripheral DAC1 clock source selection 710 * @{ 711 */ 712 #define LL_RCC_DAC1_CLKSOURCE_LSE 0x00000000U /*!< LSE clock used as DAC1 clock */ 713 #define LL_RCC_DAC1_CLKSOURCE_LSI RCC_CCIPR3_DAC1SEL /*!< LSI clock used as DAC1 clock */ 714 /** 715 * @} 716 */ 717 718 /** @defgroup RCC_LL_EC_ADF1_CLKSOURCE Peripheral ADF1 clock source selection 719 * @{ 720 */ 721 #define LL_RCC_ADF1_CLKSOURCE_HCLK 0x00000000U /*!< HCLK clock used as ADF1 clock */ 722 #define LL_RCC_ADF1_CLKSOURCE_PLL1 RCC_CCIPR3_ADF1SEL_0 /*!< PLL1 clock used as ADF1 clock */ 723 #define LL_RCC_ADF1_CLKSOURCE_PLL3 RCC_CCIPR3_ADF1SEL_1 /*!< PLL3 clock used as ADF1 clock */ 724 #define LL_RCC_ADF1_CLKSOURCE_MSIK RCC_CCIPR3_ADF1SEL_2 /*!< MSIK clock used as ADF1 clock */ 725 #define LL_RCC_ADF1_CLKSOURCE_PIN (RCC_CCIPR3_ADF1SEL_1 | RCC_CCIPR3_ADF1SEL_0) /*!< PIN SAI1_EXTCLK clock used as ADF1 clock */ 726 /** 727 * @} 728 */ 729 730 /** @defgroup RCC_LL_EC_MDF1_CLKSOURCE Peripheral MDF1 clock source selection 731 * @{ 732 */ 733 #define LL_RCC_MDF1_CLKSOURCE_HCLK 0x00000000U /*!< HCLK clock used as MDF1 clock */ 734 #define LL_RCC_MDF1_CLKSOURCE_PLL1 RCC_CCIPR2_MDF1SEL_0 /*!< PLL1 clock used as MDF1 clock */ 735 #define LL_RCC_MDF1_CLKSOURCE_PLL3 RCC_CCIPR2_MDF1SEL_1 /*!< PLL3 clock used as MDF1 clock */ 736 #define LL_RCC_MDF1_CLKSOURCE_MSIK RCC_CCIPR2_MDF1SEL_2 /*!< MSIK clock used as MDF1 clock */ 737 #define LL_RCC_MDF1_CLKSOURCE_PIN (RCC_CCIPR2_MDF1SEL_1 | RCC_CCIPR2_MDF1SEL_0) /*!< PIN SAI1_EXTCLK clock used as MDF1 clock */ 738 /** 739 * @} 740 */ 741 742 /** @defgroup RCC_LL_EC_OCTOSPI_CLKSOURCE Peripheral OCTOSPI kernel clock source selection 743 * @{ 744 */ 745 #define LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock used as OctoSPI kernel clock source */ 746 #define LL_RCC_OCTOSPI_CLKSOURCE_MSIK RCC_CCIPR2_OCTOSPISEL_0 /*!< MSIK clock used as OctoSPI kernel clock source */ 747 #define LL_RCC_OCTOSPI_CLKSOURCE_PLL1 RCC_CCIPR2_OCTOSPISEL_1 /*!< PLL1 "Q" clock used as OctoSPI kernel clock source */ 748 #define LL_RCC_OCTOSPI_CLKSOURCE_PLL2 (RCC_CCIPR2_OCTOSPISEL_1|RCC_CCIPR2_OCTOSPISEL_0) /*!< PLL2 "Q" clock used as OctoSPI kernel clock source */ 749 /** 750 * @} 751 */ 752 753 #if defined (HSPI1) 754 /** @defgroup RCC_LL_EC_HSPI1_CLKSOURCE Peripheral HSPI1 kernel clock source selection 755 * @{ 756 */ 757 #define LL_RCC_HSPI_CLKSOURCE_SYSCLK (0x00000000U) 758 #define LL_RCC_HSPI_CLKSOURCE_PLL1 RCC_CCIPR2_HSPISEL_0 759 #define LL_RCC_HSPI_CLKSOURCE_PLL2 RCC_CCIPR2_HSPISEL_1 760 #define LL_RCC_HSPI_CLKSOURCE_PLL3 RCC_CCIPR2_HSPISEL 761 /** 762 * @} 763 */ 764 #endif /* HSPI1 */ 765 766 /** @defgroup RCC_LL_EC_TIM_INPUT_CAPTURE_CLOCKSource TIM Input capture clock source selection 767 * @{ 768 */ 769 #define LL_RCC_TIMIC_CLKSOURCE_NONE 0x00000000U /*!< No clock available for TIM16/TIM17 and LPTIM2 input capture */ 770 #define LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256 RCC_CCIPR1_TIMICSEL_2 /*!< HSI/256 selected for TIM16/TIM17 and LPTIM2 input capture */ 771 #define LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV1024 RCC_CCIPR1_TIMICSEL_2 /*!< MSIS/1024 selected for TIM16/TIM17 and LPTIM2 input capture */ 772 #define LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV4 (RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_1) /*!< MSIS/4 selected for TIM16/TIM17 and LPTIM2 input capture */ 773 #define LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV4 (RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_0) /*!< MSIK/4 selected for TIM16/TIM17 and LPTIM2 input capture */ 774 #define LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV1024 (RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_1 | \ 775 RCC_CCIPR1_TIMICSEL_0) /*!< MSIK/1024 selected for TIM16/TIM17 and LPTIM2 input capture */ 776 /** 777 * @} 778 */ 779 780 781 #if defined(SAES) 782 /** @defgroup RCC_LL_EC_SAES_CLKSOURCE Peripheral SAES clock source selection 783 * @{ 784 */ 785 #define LL_RCC_SAES_CLKSOURCE_SHSI 0x00000000U /*!< SHSI clock used as SAES clock source */ 786 #define LL_RCC_SAES_CLKSOURCE_SHSI_DIV2 RCC_CCIPR2_SAESSEL /*!< SHSI_DIV2 clock used as SAES clock source */ 787 /** 788 * @} 789 */ 790 #endif /* SAES */ 791 792 /** @defgroup RCC_LL_EC_USART Peripheral USARTx get clock source 793 * @{ 794 */ 795 #define LL_RCC_USART1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_USART1SEL_Pos << 16U) | \ 796 (RCC_CCIPR1_USART1SEL >> RCC_CCIPR1_USART1SEL_Pos)) /*!< USART1 Clock source selection */ 797 #if defined(USART2) 798 #define LL_RCC_USART2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_USART2SEL_Pos << 16U) | \ 799 (RCC_CCIPR1_USART2SEL >> RCC_CCIPR1_USART2SEL_Pos)) /*!< USART2 Clock source selection */ 800 #endif /* USART2 */ 801 #define LL_RCC_USART3_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_USART3SEL_Pos << 16U) | \ 802 (RCC_CCIPR1_USART3SEL >> RCC_CCIPR1_USART3SEL_Pos)) /*!< USART3 Clock source selection */ 803 #if defined (RCC_CCIPR2_USART6SEL) 804 #define LL_RCC_USART6_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | \ 805 (RCC_CCIPR2_USART6SEL >> RCC_CCIPR2_USART6SEL_Pos)) /*!< USART6 Clock source selection */ 806 #endif /* RCC_CCIPR2_USART6SEL */ 807 /** 808 * @} 809 */ 810 811 /** @defgroup RCC_LL_EC_UART Peripheral UARTx get clock source 812 * @{ 813 */ 814 #define LL_RCC_UART4_CLKSOURCE RCC_CCIPR1_UART4SEL /*!< UART4 Clock source selection */ 815 #define LL_RCC_UART5_CLKSOURCE RCC_CCIPR1_UART5SEL /*!< UART5 Clock source selection */ 816 /** 817 * @} 818 */ 819 820 /** @defgroup RCC_LL_EC_SPI Peripheral SPIx get clock source 821 * @{ 822 */ 823 #define LL_RCC_SPI1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \ 824 (RCC_CCIPR1_SPI1SEL >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< SPI1 Clock source selection */ 825 #define LL_RCC_SPI2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \ 826 (RCC_CCIPR1_SPI2SEL >> RCC_CCIPR1_SPI2SEL_Pos)) /*!< SPI2 Clock source selection */ 827 #define LL_RCC_SPI3_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \ 828 (RCC_CCIPR3_SPI3SEL >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< SPI3 Clock source selection */ 829 /** 830 * @} 831 */ 832 833 /** @defgroup RCC_LL_EC_LPUART Peripheral LPUARTx get clock source 834 * @{ 835 */ 836 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR3_LPUART1SEL /*!< LPUART1 Clock source selection */ 837 /** 838 * @} 839 */ 840 841 #if defined(DSI) 842 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection 843 * @{ 844 */ 845 #define LL_RCC_DSI_CLKSOURCE_PHY (RCC_CCIPR2_DSIHOSTSEL) 846 #define LL_RCC_DSI_CLKSOURCE_PLL3 (0x00000000U) 847 /** 848 * @} 849 */ 850 #endif /* DSI */ 851 852 #if defined(LTDC) 853 /** @defgroup RCC_LL_EC_LTDC_CLKSOURCE Peripheral LTDC clock source selection 854 * @{ 855 */ 856 #define LL_RCC_LTDC_CLKSOURCE_PLL2 (RCC_CCIPR2_LTDCSEL) 857 #define LL_RCC_LTDC_CLKSOURCE_PLL3 (0x00000000U) 858 /** 859 * @} 860 */ 861 #endif /* LTDC */ 862 863 #if defined (RCC_CCIPR2_USBPHYCSEL) 864 /** @defgroup RCC_LL_EC_USBPHY_CLKSOURCE Peripheral USBPHY clock source selection 865 * @{ 866 */ 867 #define LL_RCC_USBPHYCLKSOURCE_HSE (0x00000000U) /*!< HSE clock selected as USBPHYC clock */ 868 #define LL_RCC_USBPHYCLKSOURCE_HSE_DIV2 RCC_CCIPR2_USBPHYCSEL_1 /*!< HSE clock divided by 2 selected as USBPHYC clock */ 869 #define LL_RCC_USBPHYCLKSOURCE_PLL1 RCC_CCIPR2_USBPHYCSEL_0 /*!< PLL1 divider P selected as USBPHYC clock */ 870 #define LL_RCC_USBPHYCLKSOURCE_PLL1_DIV2 (RCC_CCIPR2_USBPHYCSEL_1 | RCC_CCIPR2_USBPHYCSEL_0) /*!< PLL1 divider P divided by 2 selected as USBPHYC clock */ 871 /** 872 * @} 873 */ 874 #endif /* RCC_CCIPR2_USBPHYCSEL */ 875 876 /** @defgroup RCC_LL_EC_I2C Peripheral I2Cx get clock source 877 * @{ 878 */ 879 #define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \ 880 (RCC_CCIPR1_I2C1SEL >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */ 881 #define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \ 882 (RCC_CCIPR1_I2C2SEL >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */ 883 #define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \ 884 (RCC_CCIPR3_I2C3SEL >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */ 885 #define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \ 886 (RCC_CCIPR1_I2C4SEL >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */ 887 #if defined (RCC_CCIPR2_I2C5SEL) 888 #define LL_RCC_I2C5_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \ 889 (RCC_CCIPR2_I2C5SEL >> RCC_CCIPR2_I2C5SEL_Pos)) /*!< I2C1 Clock source selection */ 890 #endif /* RCC_CCIPR2_I2C5SEL */ 891 #if defined (RCC_CCIPR2_I2C6SEL) 892 #define LL_RCC_I2C6_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \ 893 (RCC_CCIPR2_I2C6SEL >> RCC_CCIPR2_I2C6SEL_Pos)) /*!< I2C1 Clock source selection */ 894 #endif /* RCC_CCIPR2_I2C6SEL */ 895 /** 896 * @} 897 */ 898 899 /** @defgroup RCC_LL_EC_LPTIM Peripheral LPTIMx get clock source 900 * @{ 901 */ 902 #define LL_RCC_LPTIM1_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \ 903 (RCC_CCIPR3_LPTIM1SEL >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LPTIM1 Clock source selection */ 904 #define LL_RCC_LPTIM2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \ 905 (RCC_CCIPR1_LPTIM2SEL >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LPTIM2 Clock source selection */ 906 #define LL_RCC_LPTIM34_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \ 907 (RCC_CCIPR3_LPTIM34SEL >> RCC_CCIPR3_LPTIM34SEL_Pos)) /*!< LPTIM3 and LPTIM4 Clock source selection */ 908 /** 909 * @} 910 */ 911 912 /** @defgroup RCC_LL_EC_SAI Peripheral SAIx get clock source 913 * @{ 914 */ 915 #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL /*!< SAI1 Clock source selection */ 916 #if defined (SAI2) 917 #define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR2_SAI2SEL /*!< SAI2 Clock source selection */ 918 #endif /* SAI2 */ 919 /** 920 * @} 921 */ 922 923 /** @defgroup RCC_LL_EC_SDMMC_KERNEL Peripheral SDMMC get kernel clock source 924 * @{ 925 */ 926 #define LL_RCC_SDMMC_KERNELCLKSOURCE RCC_CCIPR2_SDMMCSEL /*!< SDMMC1/2 Kernel Clock source selection */ 927 /** 928 * @} 929 */ 930 931 /** @defgroup RCC_LL_EC_SDMMC1/2 Peripheral SDMMC get clock source 932 * @{ 933 */ 934 #define LL_RCC_SDMMC_CLKSOURCE RCC_CCIPR1_ICLKSEL /*!< SDMMC1/2 Clock source selection */ 935 /** 936 * @} 937 */ 938 939 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source 940 * @{ 941 */ 942 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR2_RNGSEL /*!< RNG Clock source selection */ 943 /** 944 * @} 945 */ 946 947 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source 948 * @{ 949 */ 950 #define LL_RCC_USB_CLKSOURCE RCC_CCIPR1_ICLKSEL /*!< USB Clock source selection */ 951 /** 952 * @} 953 */ 954 955 /** @defgroup RCC_LL_EC_ADCDAC Peripheral ADCDAC get clock source 956 * @{ 957 */ 958 #define LL_RCC_ADCDAC_CLKSOURCE RCC_CCIPR3_ADCDACSEL /*!< ADCDACs Clock source selection */ 959 /** 960 * @} 961 */ 962 963 /** @defgroup RCC_LL_EC_MDF1 Peripheral MDF1 get clock source 964 * @{ 965 */ 966 #define LL_RCC_MDF1_CLKSOURCE RCC_CCIPR2_MDF1SEL /* MDF1 Clock source selection */ 967 /** 968 * @} 969 */ 970 971 /** @defgroup RCC_LL_EC_DAC1 Peripheral DAC1 get clock source 972 * @{ 973 */ 974 #define LL_RCC_DAC1_CLKSOURCE RCC_CCIPR3_DAC1SEL /* DAC1 Clock source selection */ 975 /** 976 * @} 977 */ 978 979 /** @defgroup RCC_LL_EC_ADF1 Peripheral ADF1 get clock source 980 * @{ 981 */ 982 #define LL_RCC_ADF1_CLKSOURCE RCC_CCIPR3_ADF1SEL /*!< ADF1 Clock source selection */ 983 /** 984 * @} 985 */ 986 987 /** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get kernel clock source 988 * @{ 989 */ 990 #define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR1_FDCANSEL /*!< FDCAN Kernel Clock source selection */ 991 /** 992 * @} 993 */ 994 995 /** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source 996 * @{ 997 */ 998 #define LL_RCC_OCTOSPI_CLKSOURCE RCC_CCIPR2_OCTOSPISEL /*!< OctoSPI Clock source selection */ 999 /** 1000 * @} 1001 */ 1002 #if defined (HSPI1) 1003 /** @defgroup RCC_LL_EC_HSPI Peripheral HSPI get clock source 1004 * @{ 1005 */ 1006 #define LL_RCC_HSPI_CLKSOURCE RCC_CCIPR2_HSPISEL /*!< HSPI Clock source selection */ 1007 /** 1008 * @} 1009 */ 1010 #endif /* HSPI */ 1011 1012 #if defined(SAES) 1013 /** @defgroup RCC_LL_EC_SAES Peripheral SAES get clock source 1014 * @{ 1015 */ 1016 #define LL_RCC_SAES_CLKSOURCE RCC_CCIPR2_SAESSEL /*!< SAES Clock source selection */ 1017 /** 1018 * @} 1019 */ 1020 #endif /* SAES */ 1021 1022 #if defined(DSI) 1023 /** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source 1024 * @{ 1025 */ 1026 #define LL_RCC_DSI_CLKSOURCE RCC_CCIPR2_DSIHOSTSEL 1027 /** 1028 * @} 1029 */ 1030 #endif /* DSI */ 1031 1032 #if defined(LTDC) 1033 /** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source 1034 * @{ 1035 */ 1036 #define LL_RCC_LTDC_CLKSOURCE RCC_CCIPR2_LTDCSEL 1037 /** 1038 * @} 1039 */ 1040 #endif /* LTDC */ 1041 1042 #if defined (RCC_CCIPR2_USBPHYCSEL) 1043 /** @defgroup RCC_LL_EC_USBPHY Peripheral USBPHY get clock source 1044 * @{ 1045 */ 1046 #define LL_RCC_USBPHY_CLKSOURCE RCC_CCIPR2_USBPHYCSEL 1047 /** 1048 * @} 1049 */ 1050 #endif /* RCC_CCIPR2_USBPHYCSEL */ 1051 1052 /** @defgroup RCC_LL_EC_PLL1SOURCE PLL1 entry clock source 1053 * @{ 1054 */ 1055 #define LL_RCC_PLL1SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL1 entry clock source */ 1056 #define LL_RCC_PLL1SOURCE_MSIS RCC_PLL1CFGR_PLL1SRC_0 /*!< MSIS clock selected as main PLL1 entry clock source */ 1057 #define LL_RCC_PLL1SOURCE_HSI RCC_PLL1CFGR_PLL1SRC_1 /*!< HSI clock selected as main PLL1 entry clock source */ 1058 #define LL_RCC_PLL1SOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) /*!< HSE clock selected as main PLL1 entry clock source */ 1059 1060 #define LL_RCC_PLLSOURCE_NONE LL_RCC_PLL1SOURCE_NONE /*!< alias define for compatibility with legacy code */ 1061 #define LL_RCC_PLLSOURCE_MSIS LL_RCC_PLL1SOURCE_MSIS /*!< alias define for compatibility with legacy code */ 1062 #define LL_RCC_PLLSOURCE_HSI LL_RCC_PLL1SOURCE_HSI /*!< alias define for compatibility with legacy code */ 1063 #define LL_RCC_PLLSOURCE_HSE LL_RCC_PLL1SOURCE_HSE /*!< alias define for compatibility with legacy code */ 1064 1065 /** 1066 * @} 1067 */ 1068 1069 /** @defgroup RCC_LL_EC_PLLINPUTRANGE All PLLs input ranges 1070 * @{ 1071 */ 1072 #define LL_RCC_PLLINPUTRANGE_4_8 0x00000000U /*!< VCO input range: 4 to 8 MHz */ 1073 #define LL_RCC_PLLINPUTRANGE_8_16 RCC_PLL1CFGR_PLL1RGE /*!< VCO input range: 8 to 16 MHz */ 1074 /** 1075 * @} 1076 */ 1077 1078 /** @defgroup RCC_LL_EC_PLL2SOURCE PLL2 entry clock source 1079 * @{ 1080 */ 1081 #define LL_RCC_PLL2SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL2 entry clock source */ 1082 #define LL_RCC_PLL2SOURCE_MSIS RCC_PLL2CFGR_PLL2SRC_0 /*!< MSIS clock selected as main PLL2 entry clock source */ 1083 #define LL_RCC_PLL2SOURCE_HSI RCC_PLL2CFGR_PLL2SRC_1 /*!< HSI clock selected as main PLL2 entry clock source */ 1084 #define LL_RCC_PLL2SOURCE_HSE (RCC_PLL2CFGR_PLL2SRC_0 | RCC_PLL2CFGR_PLL2SRC_1) /*!< HSE clock selected as main PLL2 entry clock source */ 1085 /** 1086 * @} 1087 */ 1088 1089 /** @defgroup RCC_LL_EC_PLL3SOURCE PLL3 entry clock source 1090 * @{ 1091 */ 1092 #define LL_RCC_PLL3SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL3 entry clock source */ 1093 #define LL_RCC_PLL3SOURCE_MSIS RCC_PLL3CFGR_PLL3SRC_0 /*!< MSIS clock selected as main PLL3 entry clock source */ 1094 #define LL_RCC_PLL3SOURCE_HSI RCC_PLL3CFGR_PLL3SRC_1 /*!< HSI clock selected as main PLL3 entry clock source */ 1095 #define LL_RCC_PLL3SOURCE_HSE (RCC_PLL3CFGR_PLL3SRC_0 | RCC_PLL3CFGR_PLL3SRC_1) /*!< HSE clock selected as main PLL3 entry clock source */ 1096 /** 1097 * @} 1098 */ 1099 1100 /** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection 1101 * @{ 1102 */ 1103 #define LL_RCC_MSIRANGESEL_STANDBY 0U /*!< MSI Range is provided by MSISRANGE */ 1104 #define LL_RCC_MSIRANGESEL_RUN 1U /*!< MSI Range is provided by MSISRANGE */ 1105 /** 1106 * @} 1107 */ 1108 1109 /** @defgroup RCC_LL_EF_Security_Services Security Services 1110 * @note Only available when system implements security (TZEN=1) 1111 * @{ 1112 */ 1113 #define LL_RCC_ALL_NSEC 0U /*!< No security on RCC resources (default) */ 1114 #define LL_RCC_ALL_SEC RCC_SECURE_MASK /*!< Security on all RCC resources */ 1115 1116 #define LL_RCC_HSI_SEC RCC_SECCFGR_HSISEC /*!< HSI clock configuration security */ 1117 #define LL_RCC_HSI_NSEC 0U /*!< HSI clock configuration secure/non-secure access */ 1118 #define LL_RCC_HSE_SEC RCC_SECCFGR_HSESEC /*!< HSE clock configuration security */ 1119 #define LL_RCC_HSE_NSEC 0U /*!< HSE clock configuration secure/non-secure access */ 1120 #define LL_RCC_MSI_SEC RCC_SECCFGR_MSISEC /*!< MSI clock configuration security */ 1121 #define LL_RCC_MSI_NSEC 0U /*!< MSI clock configuration secure/non-secure access */ 1122 #define LL_RCC_LSE_SEC RCC_SECCFGR_LSESEC /*!< LSE clock configuration security */ 1123 #define LL_RCC_LSE_NSEC 0U /*!< LSE clock configuration secure/non-secure access */ 1124 #define LL_RCC_LSI_SEC RCC_SECCFGR_LSISEC /*!< LSI clock configuration security */ 1125 #define LL_RCC_LSI_NSEC 0U /*!< LSI clock configuration secure/non-secure access */ 1126 #define LL_RCC_SYSCLK_SEC RCC_SECCFGR_SYSCLKSEC /*!< SYSCLK clock; STOPWUCK and MCO output configuration security */ 1127 #define LL_RCC_SYSCLK_NSEC 0U /*!< SYSCLK clock; STOPWUCK and MCO output configuration secure/non-secure access */ 1128 #define LL_RCC_PRESCALERS_SEC RCC_SECCFGR_PRESCSEC /*!< AHBx/APBx prescaler configuration security */ 1129 #define LL_RCC_PRESCALERS_NSEC 0U /*!< AHBx/APBx prescaler configuration secure/non-secure access */ 1130 #define LL_RCC_PLL1_SEC RCC_SECCFGR_PLL1SEC /*!< PLL1 clock configuration security */ 1131 #define LL_RCC_PLL1_NSEC 0U /*!< main PLL1 clock configuration secure/non-secure access */ 1132 #define LL_RCC_PLL2_SEC RCC_SECCFGR_PLL2SEC /*!< PLL2 clock configuration security */ 1133 #define LL_RCC_PLL2_NSEC 0U /*!< main PLL2 clock configuration secure/non-secure access */ 1134 #define LL_RCC_PLL3_SEC RCC_SECCFGR_PLL3SEC /*!< PLL3 clock configuration security */ 1135 #define LL_RCC_PLL3_NSEC 0U /*!< main PLL3 clock configuration secure/non-secure access */ 1136 #define LL_RCC_ICLK_SEC RCC_SECCFGR_ICLKSEC /*!< ICLK clock source selection security */ 1137 #define LL_RCC_ICLK_NSEC 0U /*!< ICLK clock source selection secure/non-secure access */ 1138 #define LL_RCC_HSI48_SEC RCC_SECCFGR_HSI48SEC /*!< HSI48 clock configuration security */ 1139 #define LL_RCC_HSI48_NSEC 0U /*!< HSI48 clock configuration secure/non-secure access */ 1140 #define LL_RCC_RESET_FLAGS_SEC RCC_SECCFGR_RMVFSEC /*!< Remove reset flag security */ 1141 #define LL_RCC_RESET_FLAGS_NSEC 0U 1142 1143 #define LL_RCC_PLL_SEC LL_RCC_PLL1_NSEC /*!< alias define for compatibility with legacy code */ 1144 #define LL_RCC_PLL_NSEC LL_RCC_PLL1_NSEC /*!< alias define for compatibility with legacy code */ 1145 #define LL_RCC_CLK48M_SEC LL_RCC_ICLK_SEC /*!< alias define for compatibility with legacy code */ 1146 #define LL_RCC_CLK48M_NSEC LL_RCC_ICLK_NSEC /*!< alias define for compatibility with legacy code */ 1147 /** 1148 * @} 1149 */ 1150 1151 /** 1152 * @} 1153 */ 1154 1155 /* Exported macro ------------------------------------------------------------*/ 1156 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros 1157 * @{ 1158 */ 1159 1160 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros 1161 * @{ 1162 */ 1163 1164 /** 1165 * @brief Write a value in RCC register 1166 * @param __REG__ Register to be written 1167 * @param __VALUE__ Value to be written in the register 1168 * @retval None 1169 */ 1170 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) 1171 1172 /** 1173 * @brief Read a value in RCC register 1174 * @param __REG__ Register to be read 1175 * @retval Register value 1176 */ 1177 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) 1178 /** 1179 * @} 1180 */ 1181 1182 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies 1183 * @{ 1184 */ 1185 1186 /** 1187 * @brief Helper macro to calculate the PLL1CLK frequency on system domain 1188 * @note ex: @ref __LL_RCC_CALC_PLL1CLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (), 1189 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetR ()); 1190 * @param __INPUTFREQ__ PLL1 Input frequency (based on MSI/HSE/HSI) 1191 * @param __PLL1M__ parameter can be a value between 1 and 16 1192 * @param __PLL1N__ parameter can be a value between 4 and 512 1193 * @param __PLL1R__ parameter can be a value between 1 and 128 (Only division by 1 and even division are allowed) 1194 * @retval PLL1 clock frequency (in Hz) 1195 */ 1196 #define __LL_RCC_CALC_PLL1CLK_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1R__) ((((__INPUTFREQ__) /(__PLL1M__)) * \ 1197 (__PLL1N__)) / (__PLL1R__)) 1198 #define __LL_RCC_CALC_PLLCLK_FREQ __LL_RCC_CALC_PLL1CLK_FREQ /*!< alias for compatibility with legacy code */ 1199 1200 /** 1201 * @brief Helper macro to calculate the PLL1CLK frequency used on SAI domain 1202 * @note ex: @ref __LL_RCC_CALC_PLL1CLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (), 1203 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetP ()); 1204 * @param __INPUTFREQ__ PLL1 Input frequency (based on MSI/HSE/HSI) 1205 * @param __PLL1M__ parameter can be a value between 1 and 16 1206 * @param __PLL1N__ parameter can be a value between 4 and 512 1207 * @param __PLL1P__ parameter can be a value between 1 and 128 1208 * @retval PLL1 clock frequency (in Hz) 1209 */ 1210 #define __LL_RCC_CALC_PLL1CLK_SAI_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1P__) ((((__INPUTFREQ__) \ 1211 /(__PLL1M__)) * (__PLL1N__)) / (__PLL1P__)) 1212 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ __LL_RCC_CALC_PLL1CLK_SAI_FREQ /*!< alias for compatibility with legacy code */ 1213 1214 /** 1215 * @brief Helper macro to calculate the PLL1CLK frequency used on 48M domain 1216 * @note ex: @ref __LL_RCC_CALC_PLL1CLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (), 1217 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetQ ()); 1218 * @param __INPUTFREQ__ PLL1 Input frequency (based on MSI/HSE/HSI) 1219 * @param __PLL1M__ parameter can be a value between 1 and 16 1220 * @param __PLL1N__ parameter can be a value between 4 and 512 1221 * @param __PLL1Q__ parameter can be a value between 1 and 128 1222 * @retval PLL clock frequency (in Hz) 1223 */ 1224 #define __LL_RCC_CALC_PLL1CLK_48M_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1Q__) ((((__INPUTFREQ__) \ 1225 /(__PLL1M__)) * (__PLL1N__)) / (__PLL1Q__)) 1226 #define __LL_RCC_CALC_PLLCLK_48M_FREQ __LL_RCC_CALC_PLL1CLK_48M_FREQ /*!< alias for compatibility with legacy code */ 1227 1228 /** 1229 * @brief Helper macro to calculate the PLL2 frequency used for SAI domain 1230 * @note ex: @ref __LL_RCC_CALC_PLL2CLK_SAI_FREQ (HSE_ALUE,@ref LL_RCC_PLL2_GetDivider (), 1231 * @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetP ()); 1232 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 1233 * @param __PLL2M__ parameter can be a value between 1 and 16 1234 * @param __PLL2N__ parameter can be a value between 4 and 512 1235 * @param __PLL2P__ parameter can be a value between 1 and 128 1236 * @retval PLL2 clock frequency (in Hz) 1237 */ 1238 #define __LL_RCC_CALC_PLL2CLK_SAI_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2P__) ((((__INPUTFREQ__) \ 1239 /(__PLL2M__)) * (__PLL2N__)) / (__PLL2P__)) 1240 1241 /** 1242 * @brief Helper macro to calculate the PLL2 frequency used on 48M domain 1243 * @note ex: @ref __LL_RCC_CALC_PLL2CLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL2_GetDivider (), 1244 * @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetQ ()); 1245 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 1246 * @param __PLL2M__ parameter can be a value between 1 and 16 1247 * @param __PLL2N__ parameter can be a value between 4 and 512 1248 * @param __PLL2Q__ parameter can be a value between 1 and 128 1249 * @retval PLL2 clock frequency (in Hz) 1250 */ 1251 #define __LL_RCC_CALC_PLL2CLK_48M_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2Q__) ((((__INPUTFREQ__) \ 1252 /(__PLL2M__)) * (__PLL2N__)) / (__PLL2Q__)) 1253 1254 /** 1255 * @brief Helper macro to calculate the PLL2 frequency used on ADC domain 1256 * @note ex: @ref __LL_RCC_CALC_PLL2CLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL2_GetDivider (), 1257 * @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetR ()); 1258 * @param __INPUTFREQ__ PLL2 Input frequency (based on MSI/HSE/HSI) 1259 * @param __PLL2M__ parameter can be a value between 1 and 16 1260 * @param __PLL2N__ parameter can be a value between 4 and 512 1261 * @param __PLL2R__ parameter can be a value between 1 and 128 1262 * @retval PLL2 clock frequency (in Hz) 1263 */ 1264 #define __LL_RCC_CALC_PLL2CLK_ADC_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2R__) ((((__INPUTFREQ__) \ 1265 /(__PLL2M__)) * (__PLL2N__)) / (__PLL2R__)) 1266 1267 /** 1268 * @brief Helper macro to calculate the PLL3 frequency used for SAI domain 1269 * @note ex: @ref __LL_RCC_CALC_PLL3CLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetDivider (), 1270 * @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetP ()); 1271 * @param __INPUTFREQ__ PLL3 Input frequency (based on MSI/HSE/HSI) 1272 * @param __PLL3M__ parameter can be a value between 1 and 16 1273 * @param __PLL3N__ parameter can be a value between 4 and 512 1274 * @param __PLL3P__ parameter can be a value between 1 and 128 1275 * @retval PLL3 clock frequency (in Hz) 1276 */ 1277 #define __LL_RCC_CALC_PLL3CLK_SAI_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3P__)((((__INPUTFREQ__) \ 1278 /(__PLL3M__)) * (__PLL3N__)) / (__PLL3P__)) 1279 1280 /** 1281 * @brief Helper macro to calculate the PLL2 frequency used on 48M domain 1282 * @note ex: @ref __LL_RCC_CALC_PLL3CLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetDivider (), 1283 * @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetQ ()); 1284 * @param __INPUTFREQ__ PLL3 Input frequency (based on MSI/HSE/HSI) 1285 * @param __PLL3M__ parameter can be a value between 1 and 16 1286 * @param __PLL3N__ parameter can be a value between 4 and 512 1287 * @param __PLL3Q__ parameter can be a value between 1 and 128 1288 * @retval PLL3 clock frequency (in Hz) 1289 */ 1290 #define __LL_RCC_CALC_PLL3CLK_48M_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3Q__) ((((__INPUTFREQ__) \ 1291 /(__PLL3M__)) * (__PLL3N__)) / (__PLL3Q__)) 1292 1293 #if defined(HSPI1) || defined(LTDC) 1294 /** 1295 * @brief Helper macro to calculate the PLL3 frequency used on HSPI domain 1296 * @note ex: @ref __LL_RCC_CALC_PLL3CLK_HSPI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetDivider (), 1297 * @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetQ ()); 1298 * @param __INPUTFREQ__ PLL3 Input frequency (based on MSI/HSE/HSI) 1299 * @param __PLL3M__ parameter can be a value between 1 and 16 1300 * @param __PLL3N__ parameter can be a value between 4 and 512 1301 * @param __PLL3R__ parameter can be a value between 1 and 128 1302 * @retval PLL3 clock frequency (in Hz) 1303 */ 1304 #define __LL_RCC_CALC_PLL3CLK_HSPI_LTDC_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3R__) ((((__INPUTFREQ__) \ 1305 /(__PLL3M__)) * (__PLL3N__)) / (__PLL3R__)) 1306 /* Legacy define */ 1307 #define __LL_RCC_CALC_PLL3CLK_HSPI_FREQ __LL_RCC_CALC_PLL3CLK_HSPI_LTDC_FREQ 1308 #endif /* HSPI1 || LTDC */ 1309 1310 /** 1311 * @brief Helper macro to calculate the HCLK frequency 1312 * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK) 1313 * @param __AHBPRESCALER__ This parameter can be one of the following values: 1314 * @arg @ref LL_RCC_SYSCLK_DIV_1 1315 * @arg @ref LL_RCC_SYSCLK_DIV_2 1316 * @arg @ref LL_RCC_SYSCLK_DIV_4 1317 * @arg @ref LL_RCC_SYSCLK_DIV_8 1318 * @arg @ref LL_RCC_SYSCLK_DIV_16 1319 * @arg @ref LL_RCC_SYSCLK_DIV_64 1320 * @arg @ref LL_RCC_SYSCLK_DIV_128 1321 * @arg @ref LL_RCC_SYSCLK_DIV_256 1322 * @arg @ref LL_RCC_SYSCLK_DIV_512 1323 * @retval HCLK clock frequency (in Hz) 1324 */ 1325 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> \ 1326 AHBPrescTable[((__AHBPRESCALER__)& RCC_CFGR2_HPRE) \ 1327 >> RCC_CFGR2_HPRE_Pos]) 1328 1329 /** 1330 * @brief Helper macro to calculate the PCLK1 frequency (ABP1) 1331 * @param __HCLKFREQ__ HCLK frequency 1332 * @param __APB1PRESCALER__ This parameter can be one of the following values: 1333 * @arg @ref LL_RCC_APB1_DIV_1 1334 * @arg @ref LL_RCC_APB1_DIV_2 1335 * @arg @ref LL_RCC_APB1_DIV_4 1336 * @arg @ref LL_RCC_APB1_DIV_8 1337 * @arg @ref LL_RCC_APB1_DIV_16 1338 * @retval PCLK1 clock frequency (in Hz) 1339 */ 1340 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> \ 1341 (APBPrescTable[((__APB1PRESCALER__)& \ 1342 RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_Pos])) 1343 1344 /** 1345 * @brief Helper macro to calculate the PCLK2 frequency (ABP2) 1346 * @param __HCLKFREQ__ HCLK frequency 1347 * @param __APB2PRESCALER__ This parameter can be one of the following values: 1348 * @arg @ref LL_RCC_APB2_DIV_1 1349 * @arg @ref LL_RCC_APB2_DIV_2 1350 * @arg @ref LL_RCC_APB2_DIV_4 1351 * @arg @ref LL_RCC_APB2_DIV_8 1352 * @arg @ref LL_RCC_APB2_DIV_16 1353 * @retval PCLK2 clock frequency (in Hz) 1354 */ 1355 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >>\ 1356 APBPrescTable[(__APB2PRESCALER__) >> \ 1357 RCC_CFGR2_PPRE2_Pos]) 1358 1359 /** 1360 * @brief Helper macro to calculate the PCLK3 frequency (ABP3) 1361 * @param __HCLKFREQ__ HCLK frequency 1362 * @param __APB3PRESCALER__ This parameter can be one of the following values: 1363 * @arg @ref LL_RCC_APB3_DIV_1 1364 * @arg @ref LL_RCC_APB3_DIV_2 1365 * @arg @ref LL_RCC_APB3_DIV_4 1366 * @arg @ref LL_RCC_APB3_DIV_8 1367 * @arg @ref LL_RCC_APB3_DIV_16 1368 * @retval PCLK3 clock frequency (in Hz) 1369 */ 1370 #define __LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> \ 1371 APBPrescTable[(__APB3PRESCALER__) >> \ 1372 RCC_CFGR3_PPRE3_Pos]) 1373 1374 /** 1375 * @brief Helper macro to calculate the MSIS frequency (in Hz) 1376 * @note __MSISSEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect() 1377 * @note if __MSISSEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY, 1378 * __MSISRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby() 1379 * else by LL_RCC_MSI_GetRange() 1380 * ex: __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 1381 * (LL_RCC_MSI_IsEnabledRangeSelect()? 1382 * LL_RCC_MSI_GetRange(): 1383 * LL_RCC_MSI_GetRangeAfterStandby())) 1384 * @param __MSISSEL__ This parameter can be one of the following values: 1385 * @arg @ref LL_RCC_MSIRANGESEL_STANDBY 1386 * @arg @ref LL_RCC_MSIRANGESEL_RUN 1387 * @param __MSISRANGE__ This parameter can be one of the following values: 1388 * @arg @ref LL_RCC_MSISRANGE_0 1389 * @arg @ref LL_RCC_MSISRANGE_1 1390 * @arg @ref LL_RCC_MSISRANGE_2 1391 * @arg @ref LL_RCC_MSISRANGE_3 1392 * @arg @ref LL_RCC_MSISRANGE_4 1393 * @arg @ref LL_RCC_MSISRANGE_5 1394 * @arg @ref LL_RCC_MSISRANGE_6 1395 * @arg @ref LL_RCC_MSISRANGE_7 1396 * @arg @ref LL_RCC_MSISRANGE_8 1397 * @arg @ref LL_RCC_MSISRANGE_9 1398 * @arg @ref LL_RCC_MSISRANGE_10 1399 * @arg @ref LL_RCC_MSISRANGE_11 1400 * @arg @ref LL_RCC_MSISRANGE_12 1401 * @arg @ref LL_RCC_MSISRANGE_13 1402 * @arg @ref LL_RCC_MSISRANGE_14 1403 * @arg @ref LL_RCC_MSISRANGE_15 1404 * @retval MSI clock frequency (in Hz) 1405 */ 1406 #define __LL_RCC_CALC_MSIS_FREQ(__MSISSEL__, __MSISRANGE__) (((__MSISSEL__) == LL_RCC_MSIRANGESEL_RUN) ? \ 1407 (MSIRangeTable[((__MSISRANGE__) >> 28U) & 0x0FU]) : \ 1408 (MSIRangeTable[((__MSISRANGE__) >> 12U) & 0x0FU])) 1409 1410 1411 /** 1412 * @brief Helper macro to calculate the MSIK frequency (in Hz) 1413 * @note __MSIKSEL__ can be retrieved thanks to function LL_RCC_MSIK_IsEnabledRangeSelect() 1414 * @note if __MSIKSEL__ is equal to LL_RCC_MSIKRANGESEL_STANDBY, 1415 * __MSIKRANGE__can be retrieved by LL_RCC_MSIK_GetRangeAfterStandby() 1416 * else by LL_RCC_MSIK_GetRange() 1417 * ex: __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSIK_IsEnabledRangeSelect(), 1418 * (LL_RCC_MSIK_IsEnabledRangeSelect()? 1419 * LL_RCC_MSIK_GetRange(): 1420 * LL_RCC_MSIK_GetRangeAfterStandby())) 1421 * @param __MSIKSEL__ This parameter can be one of the following values: 1422 * @arg @ref LL_RCC_MSIRANGESEL_STANDBY 1423 * @arg @ref LL_RCC_MSIRANGESEL_RUN 1424 * @param __MSIKRANGE__ This parameter can be one of the following values: 1425 * @arg @ref LL_RCC_MSIKRANGE_0 1426 * @arg @ref LL_RCC_MSIKRANGE_1 1427 * @arg @ref LL_RCC_MSIKRANGE_2 1428 * @arg @ref LL_RCC_MSIKRANGE_3 1429 * @arg @ref LL_RCC_MSIKRANGE_4 1430 * @arg @ref LL_RCC_MSIKRANGE_5 1431 * @arg @ref LL_RCC_MSIKRANGE_6 1432 * @arg @ref LL_RCC_MSIKRANGE_7 1433 * @arg @ref LL_RCC_MSIKRANGE_8 1434 * @arg @ref LL_RCC_MSIKRANGE_9 1435 * @arg @ref LL_RCC_MSIKRANGE_10 1436 * @arg @ref LL_RCC_MSIKRANGE_11 1437 * @arg @ref LL_RCC_MSIKRANGE_12 1438 * @arg @ref LL_RCC_MSIKRANGE_13 1439 * @arg @ref LL_RCC_MSIKRANGE_14 1440 * @arg @ref LL_RCC_MSIKRANGE_15 1441 * @retval MSIK clock frequency (in Hz) 1442 */ 1443 #define __LL_RCC_CALC_MSIK_FREQ(__MSIKSEL__, __MSIKRANGE__) (((__MSIKSEL__) == LL_RCC_MSIRANGESEL_RUN) ? \ 1444 (MSIRangeTable[((__MSIKRANGE__) >> 24U) & 0x0FU]) : \ 1445 (MSIRangeTable[((__MSIKRANGE__) >> 8U) & 0x0FU])) 1446 /** 1447 * @} 1448 */ 1449 1450 /** 1451 * @} 1452 */ 1453 1454 /* Exported functions --------------------------------------------------------*/ 1455 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions 1456 * @{ 1457 */ 1458 1459 /** @defgroup RCC_LL_EF_HSE HSE 1460 * @{ 1461 */ 1462 1463 /** 1464 * @brief Enable the Clock Security System. 1465 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS 1466 * @retval None 1467 */ LL_RCC_HSE_EnableCSS(void)1468 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) 1469 { 1470 SET_BIT(RCC->CR, RCC_CR_CSSON); 1471 } 1472 1473 /** 1474 * @brief Enable HSE external oscillator (HSE Bypass) 1475 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass 1476 * @retval None 1477 */ LL_RCC_HSE_EnableBypass(void)1478 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) 1479 { 1480 SET_BIT(RCC->CR, RCC_CR_HSEBYP); 1481 } 1482 1483 /** 1484 * @brief Disable HSE external oscillator (HSE Bypass) 1485 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass 1486 * @retval None 1487 */ LL_RCC_HSE_DisableBypass(void)1488 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) 1489 { 1490 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); 1491 } 1492 1493 /** 1494 * @brief Enable HSE crystal oscillator (HSE ON) 1495 * @rmtoll CR HSEON LL_RCC_HSE_Enable 1496 * @retval None 1497 */ LL_RCC_HSE_Enable(void)1498 __STATIC_INLINE void LL_RCC_HSE_Enable(void) 1499 { 1500 SET_BIT(RCC->CR, RCC_CR_HSEON); 1501 } 1502 1503 /** 1504 * @brief Disable HSE crystal oscillator (HSE ON) 1505 * @rmtoll CR HSEON LL_RCC_HSE_Disable 1506 * @retval None 1507 */ LL_RCC_HSE_Disable(void)1508 __STATIC_INLINE void LL_RCC_HSE_Disable(void) 1509 { 1510 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); 1511 } 1512 1513 /** 1514 * @brief Check if HSE oscillator Ready 1515 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady 1516 * @retval State of bit (1 or 0). 1517 */ LL_RCC_HSE_IsReady(void)1518 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) 1519 { 1520 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL); 1521 } 1522 1523 /** 1524 * @brief Set external HSE clock mode 1525 * @note This bit can be written only if the HSE oscillator is disabled 1526 * @rmtoll CR HSEEXT LL_RCC_HSE_SetClockMode 1527 * @param HSEMode This parameter can be one of the following values: 1528 * @arg @ref LL_RCC_HSE_ANALOG_MODE 1529 * @arg @ref LL_RCC_HSE_DIGITAL_MODE 1530 * @retval None 1531 */ LL_RCC_HSE_SetClockMode(uint32_t HSEMode)1532 __STATIC_INLINE void LL_RCC_HSE_SetClockMode(uint32_t HSEMode) 1533 { 1534 MODIFY_REG(RCC->CR, RCC_CR_HSEEXT, HSEMode); 1535 } 1536 1537 /** 1538 * @brief Get External HSE clock mode 1539 * @rmtoll CR HSEEXT LL_RCC_HSE_GetClockMode 1540 * @retval Returned value can be one of the following values: 1541 * @arg @ref LL_RCC_HSE_ANALOG_MODE 1542 * @arg @ref LL_RCC_HSE_DIGITAL_MODE 1543 */ LL_RCC_HSE_GetClockMode(void)1544 __STATIC_INLINE uint32_t LL_RCC_HSE_GetClockMode(void) 1545 { 1546 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSEEXT)); 1547 } 1548 1549 /** 1550 * @} 1551 */ 1552 1553 /** @defgroup RCC_LL_EF_HSI HSI 1554 * @{ 1555 */ 1556 1557 /** 1558 * @brief Enable HSI even in stop mode 1559 * @note HSI oscillator is forced ON even in Stop mode 1560 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode 1561 * @retval None 1562 */ LL_RCC_HSI_EnableInStopMode(void)1563 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void) 1564 { 1565 SET_BIT(RCC->CR, RCC_CR_HSIKERON); 1566 } 1567 1568 /** 1569 * @brief Disable HSI in stop mode 1570 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode 1571 * @retval None 1572 */ LL_RCC_HSI_DisableInStopMode(void)1573 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) 1574 { 1575 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); 1576 } 1577 1578 /** 1579 * @brief Check if HSI is enabled in stop mode 1580 * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode 1581 * @retval State of bit (1 or 0). 1582 */ LL_RCC_HSI_IsEnabledInStopMode(void)1583 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void) 1584 { 1585 return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == RCC_CR_HSIKERON) ? 1UL : 0UL); 1586 } 1587 1588 /** 1589 * @brief Enable HSI oscillator 1590 * @rmtoll CR HSION LL_RCC_HSI_Enable 1591 * @retval None 1592 */ LL_RCC_HSI_Enable(void)1593 __STATIC_INLINE void LL_RCC_HSI_Enable(void) 1594 { 1595 SET_BIT(RCC->CR, RCC_CR_HSION); 1596 } 1597 1598 /** 1599 * @brief Disable HSI oscillator 1600 * @rmtoll CR HSION LL_RCC_HSI_Disable 1601 * @retval None 1602 */ LL_RCC_HSI_Disable(void)1603 __STATIC_INLINE void LL_RCC_HSI_Disable(void) 1604 { 1605 CLEAR_BIT(RCC->CR, RCC_CR_HSION); 1606 } 1607 1608 /** 1609 * @brief Check if HSI clock is ready 1610 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady 1611 * @retval State of bit (1 or 0). 1612 */ LL_RCC_HSI_IsReady(void)1613 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) 1614 { 1615 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL); 1616 } 1617 1618 /** 1619 * @brief Get HSI Calibration value 1620 * @note When HSITRIM is written, HSICAL is updated with the sum of 1621 * HSITRIM and the factory trim value 1622 * @rmtoll ICSCR3 HSICAL LL_RCC_HSI_GetCalibration 1623 * @retval Between Min_Data = 0 and Max_Data = 127 1624 */ LL_RCC_HSI_GetCalibration(void)1625 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) 1626 { 1627 return (uint32_t)(READ_BIT(RCC->ICSCR3, RCC_ICSCR3_HSICAL) >> RCC_ICSCR3_HSICAL_Pos); 1628 } 1629 1630 /** 1631 * @brief Set HSI Calibration trimming 1632 * @note user-programmable trimming value that is added to the HSICAL 1633 * @note Default value is 64, which, when added to the HSICAL value, 1634 * should trim the HSI to 16 MHz +/- 1 % 1635 * @rmtoll ICSCR3 HSITRIM LL_RCC_HSI_SetCalibTrimming 1636 * @param Value Between Min_Data = 0 and Max_Data = 127 1637 * @retval None 1638 */ LL_RCC_HSI_SetCalibTrimming(uint32_t Value)1639 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) 1640 { 1641 MODIFY_REG(RCC->ICSCR3, RCC_ICSCR3_HSITRIM, Value << RCC_ICSCR3_HSITRIM_Pos); 1642 } 1643 1644 /** 1645 * @brief Get HSI Calibration trimming 1646 * @rmtoll ICSC3R HSITRIM LL_RCC_HSI_GetCalibTrimming 1647 * @retval Between Min_Data = 0 and Max_Data = 127 1648 */ LL_RCC_HSI_GetCalibTrimming(void)1649 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) 1650 { 1651 return (uint32_t)(READ_BIT(RCC->ICSCR3, RCC_ICSCR3_HSITRIM) >> RCC_ICSCR3_HSITRIM_Pos); 1652 } 1653 1654 /** 1655 * @} 1656 */ 1657 1658 /** @defgroup RCC_LL_EF_HSI48 HSI48 1659 * @{ 1660 */ 1661 1662 /** 1663 * @brief Enable HSI48 1664 * @rmtoll CR HSI48ON LL_RCC_HSI48_Enable 1665 * @retval None 1666 */ LL_RCC_HSI48_Enable(void)1667 __STATIC_INLINE void LL_RCC_HSI48_Enable(void) 1668 { 1669 SET_BIT(RCC->CR, RCC_CR_HSI48ON); 1670 } 1671 1672 /** 1673 * @brief Disable HSI48 1674 * @rmtoll CR HSI48ON LL_RCC_HSI48_Disable 1675 * @retval None 1676 */ LL_RCC_HSI48_Disable(void)1677 __STATIC_INLINE void LL_RCC_HSI48_Disable(void) 1678 { 1679 CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON); 1680 } 1681 1682 /** 1683 * @brief Check if HSI48 oscillator Ready 1684 * @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady 1685 * @retval State of bit (1 or 0). 1686 */ LL_RCC_HSI48_IsReady(void)1687 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) 1688 { 1689 return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == RCC_CR_HSI48RDY) ? 1UL : 0UL); 1690 } 1691 1692 /** 1693 * @brief Get HSI48 Calibration value 1694 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration 1695 * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF 1696 */ LL_RCC_HSI48_GetCalibration(void)1697 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) 1698 { 1699 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos); 1700 } 1701 1702 /** 1703 * @} 1704 */ 1705 1706 /** @defgroup RCC_LL_EF_LSE LSE 1707 * @{ 1708 */ 1709 1710 /** 1711 * @brief Enable Low Speed External (LSE) crystal. 1712 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable 1713 * @retval None 1714 */ LL_RCC_LSE_Enable(void)1715 __STATIC_INLINE void LL_RCC_LSE_Enable(void) 1716 { 1717 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); 1718 } 1719 1720 /** 1721 * @brief Disable Low Speed External (LSE) crystal. 1722 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable 1723 * @retval None 1724 */ LL_RCC_LSE_Disable(void)1725 __STATIC_INLINE void LL_RCC_LSE_Disable(void) 1726 { 1727 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); 1728 } 1729 1730 /** 1731 * @brief Enable external clock source (LSE bypass). 1732 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass 1733 * @retval None 1734 */ LL_RCC_LSE_EnableBypass(void)1735 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) 1736 { 1737 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 1738 } 1739 1740 /** 1741 * @brief Disable external clock source (LSE bypass). 1742 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass 1743 * @retval None 1744 */ LL_RCC_LSE_DisableBypass(void)1745 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) 1746 { 1747 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 1748 } 1749 1750 /** 1751 * @brief Set LSE oscillator drive capability 1752 * @note The oscillator is in Xtal mode when it is not in bypass mode. 1753 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability 1754 * @param LSEDrive This parameter can be one of the following values: 1755 * @arg @ref LL_RCC_LSEDRIVE_LOW 1756 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW 1757 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH 1758 * @arg @ref LL_RCC_LSEDRIVE_HIGH 1759 * @retval None 1760 */ LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)1761 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) 1762 { 1763 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); 1764 } 1765 1766 /** 1767 * @brief Get LSE oscillator drive capability 1768 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability 1769 * @retval Returned value can be one of the following values: 1770 * @arg @ref LL_RCC_LSEDRIVE_LOW 1771 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW 1772 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH 1773 * @arg @ref LL_RCC_LSEDRIVE_HIGH 1774 */ LL_RCC_LSE_GetDriveCapability(void)1775 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) 1776 { 1777 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); 1778 } 1779 1780 /** 1781 * @brief Enable Clock security system on LSE. 1782 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS 1783 * @retval None 1784 */ LL_RCC_LSE_EnableCSS(void)1785 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) 1786 { 1787 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); 1788 } 1789 1790 /** 1791 * @brief Disable Clock security system on LSE. 1792 * @note Clock security system can be disabled only after a LSE 1793 * failure detection. In that case it MUST be disabled by software. 1794 * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS 1795 * @retval None 1796 */ LL_RCC_LSE_DisableCSS(void)1797 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) 1798 { 1799 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); 1800 } 1801 1802 /** 1803 * @brief Check if LSE oscillator Ready 1804 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady 1805 * @retval State of bit (1 or 0). 1806 */ LL_RCC_LSE_IsReady(void)1807 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) 1808 { 1809 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL); 1810 } 1811 1812 /** 1813 * @brief Enable LSE oscillator propagation for system clock 1814 * @rmtoll BDCR LSESYSEN LL_RCC_LSE_EnablePropagation 1815 * @retval None 1816 */ LL_RCC_LSE_EnablePropagation(void)1817 __STATIC_INLINE void LL_RCC_LSE_EnablePropagation(void) 1818 { 1819 SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); 1820 } 1821 1822 /** 1823 * @brief Check if LSESYS oscillator Ready 1824 * @rmtoll BDCR LSESYSRDY LL_RCC_LSESYS_IsReady 1825 * @retval State of bit (1 or 0). 1826 */ LL_RCC_LSESYS_IsReady(void)1827 __STATIC_INLINE uint32_t LL_RCC_LSESYS_IsReady(void) 1828 { 1829 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == RCC_BDCR_LSESYSRDY) ? 1UL : 0UL); 1830 } 1831 1832 /** 1833 * @brief Disable LSE oscillator propagation for system clock 1834 * @rmtoll BDCR LSESYSEN LL_RCC_LSE_DisablePropagation 1835 * @retval None 1836 */ LL_RCC_LSE_DisablePropagation(void)1837 __STATIC_INLINE void LL_RCC_LSE_DisablePropagation(void) 1838 { 1839 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); 1840 } 1841 1842 /** 1843 * @brief Check if LSE oscillator propagation for system clock Ready 1844 * @rmtoll BDCR LSESYSRDY LL_RCC_LSE_IsPropagationReady 1845 * @retval State of bit (1 or 0). 1846 */ LL_RCC_LSE_IsPropagationReady(void)1847 __STATIC_INLINE uint32_t LL_RCC_LSE_IsPropagationReady(void) 1848 { 1849 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == RCC_BDCR_LSESYSRDY) ? 1UL : 0UL); 1850 } 1851 1852 /** 1853 * @brief Check if CSS on LSE failure Detection 1854 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected 1855 * @retval State of bit (1 or 0). 1856 */ LL_RCC_LSE_IsCSSDetected(void)1857 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) 1858 { 1859 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == RCC_BDCR_LSECSSD) ? 1UL : 0UL); 1860 } 1861 1862 /** 1863 * @brief Enable LSE clock glitch filter. 1864 * @note The glitches on LSE can be filtred by setting the LSEGFON. 1865 * @note LSEGFON must be written when the LSE is disabled (LSEON = 0 and LSERDY = 0). 1866 * @rmtoll BDCR LSEGFON LL_RCC_LSE_EnableGlitchFilter 1867 * @retval None 1868 */ LL_RCC_LSE_EnableGlitchFilter(void)1869 __STATIC_INLINE void LL_RCC_LSE_EnableGlitchFilter(void) 1870 { 1871 SET_BIT(RCC->BDCR, RCC_BDCR_LSEGFON); 1872 } 1873 1874 /** 1875 * @brief Disable LSE clock glitch filter. 1876 * @note LSEGFON must be written when the LSE is disabled (LSEON = 0 and LSERDY = 0). 1877 * @rmtoll BDCR LSEGFON LL_RCC_LSE_DisableGlitchFilter 1878 * @retval None 1879 */ LL_RCC_LSE_DisableGlitchFilter(void)1880 __STATIC_INLINE void LL_RCC_LSE_DisableGlitchFilter(void) 1881 { 1882 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEGFON); 1883 } 1884 1885 /** 1886 * @brief Check if LSE clock glitch filter is enabled 1887 * @rmtoll BDCR LSEGFON LL_RCC_LSE_IsGlitchFilterEnabled 1888 * @retval State of bit (1 or 0). 1889 */ LL_RCC_LSE_IsGlitchFilterEnabled(void)1890 __STATIC_INLINE uint32_t LL_RCC_LSE_IsGlitchFilterEnabled(void) 1891 { 1892 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSEGFON) == RCC_BDCR_LSEGFON) ? 1UL : 0UL); 1893 } 1894 1895 /** 1896 * @} 1897 */ 1898 1899 /** @defgroup RCC_LL_EF_LSI LSI 1900 * @{ 1901 */ 1902 1903 /** 1904 * @brief Enable LSI Oscillator 1905 * @rmtoll BDCR LSION LL_RCC_LSI_Enable 1906 * @retval None 1907 */ LL_RCC_LSI_Enable(void)1908 __STATIC_INLINE void LL_RCC_LSI_Enable(void) 1909 { 1910 SET_BIT(RCC->BDCR, RCC_BDCR_LSION); 1911 } 1912 1913 /** 1914 * @brief Disable LSI Oscillator 1915 * @rmtoll BDCR LSION LL_RCC_LSI_Disable 1916 * @retval None 1917 */ LL_RCC_LSI_Disable(void)1918 __STATIC_INLINE void LL_RCC_LSI_Disable(void) 1919 { 1920 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSION); 1921 } 1922 1923 /** 1924 * @brief Check if LSI is Ready 1925 * @rmtoll BDCR LSIRDY LL_RCC_LSI_IsReady 1926 * @retval State of bit (1 or 0). 1927 */ LL_RCC_LSI_IsReady(void)1928 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) 1929 { 1930 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) == RCC_BDCR_LSIRDY) ? 1UL : 0UL); 1931 } 1932 1933 /** 1934 * @brief Set LSI prescaler 1935 * @rmtoll BDCR LSIPREDIV LL_RCC_LSI_SetPrescaler 1936 * @param LSIPrescaler This parameter can be one of the following values: 1937 * @arg @ref LL_RCC_LSI_DIV_1 1938 * @arg @ref LL_RCC_LSI_DIV_128 1939 * @retval None 1940 */ LL_RCC_LSI_SetPrescaler(uint32_t LSIPrescaler)1941 __STATIC_INLINE void LL_RCC_LSI_SetPrescaler(uint32_t LSIPrescaler) 1942 { 1943 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSIPREDIV, LSIPrescaler); 1944 } 1945 1946 /** 1947 * @brief Get LSI prescaler 1948 * @rmtoll BDCR LSIPREDIV LL_RCC_LSI_GetPrescaler 1949 * @retval Returned value can be one of the following values: 1950 * @arg @ref LL_RCC_LSI_DIV_1 1951 * @arg @ref LL_RCC_LSI_DIV_128 1952 */ LL_RCC_LSI_GetPrescaler(void)1953 __STATIC_INLINE uint32_t LL_RCC_LSI_GetPrescaler(void) 1954 { 1955 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV)); 1956 } 1957 1958 /** 1959 * @} 1960 */ 1961 1962 /** @defgroup RCC_LL_EF_MSIK MSIK 1963 * @{ 1964 */ 1965 1966 /** 1967 * @brief Enable MSIK oscillator 1968 * @rmtoll CR MSIKON LL_RCC_MSIK_Enable 1969 * @retval None 1970 */ LL_RCC_MSIK_Enable(void)1971 __STATIC_INLINE void LL_RCC_MSIK_Enable(void) 1972 { 1973 SET_BIT(RCC->CR, RCC_CR_MSIKON); 1974 } 1975 1976 /** 1977 * @brief Disable MSIK oscillator 1978 * @rmtoll CR MSIKON LL_RCC_MSIK_Disable 1979 * @retval None 1980 */ LL_RCC_MSIK_Disable(void)1981 __STATIC_INLINE void LL_RCC_MSIK_Disable(void) 1982 { 1983 CLEAR_BIT(RCC->CR, RCC_CR_MSIKON); 1984 } 1985 1986 /** 1987 * @brief Check if MSIK oscillator Ready 1988 * @rmtoll CR MSIKRDY LL_RCC_MSIK_IsReady 1989 * @retval State of bit (1 or 0). 1990 */ LL_RCC_MSIK_IsReady(void)1991 __STATIC_INLINE uint32_t LL_RCC_MSIK_IsReady(void) 1992 { 1993 return ((READ_BIT(RCC->CR, RCC_CR_MSIKRDY) == RCC_CR_MSIKRDY) ? 1UL : 0UL); 1994 } 1995 1996 /** 1997 * @} 1998 */ 1999 2000 /** @defgroup RCC_LL_EF_SHSI SHSI 2001 * @{ 2002 */ 2003 2004 /** 2005 * @brief Enable SHSI oscillator 2006 * @rmtoll CR SHSION LL_RCC_SHSI_Enable 2007 * @retval None 2008 */ LL_RCC_SHSI_Enable(void)2009 __STATIC_INLINE void LL_RCC_SHSI_Enable(void) 2010 { 2011 SET_BIT(RCC->CR, RCC_CR_SHSION); 2012 } 2013 2014 /** 2015 * @brief Disable SHSI oscillator 2016 * @rmtoll CR SHSION LL_RCC_SHSI_Disable 2017 * @retval None 2018 */ LL_RCC_SHSI_Disable(void)2019 __STATIC_INLINE void LL_RCC_SHSI_Disable(void) 2020 { 2021 CLEAR_BIT(RCC->CR, RCC_CR_SHSION); 2022 } 2023 2024 /** 2025 * @brief Check if SHSI oscillator Ready 2026 * @rmtoll CR SHSIRDY LL_RCC_SHSI_IsReady 2027 * @retval State of bit (1 or 0). 2028 */ LL_RCC_SHSI_IsReady(void)2029 __STATIC_INLINE uint32_t LL_RCC_SHSI_IsReady(void) 2030 { 2031 return ((READ_BIT(RCC->CR, RCC_CR_SHSIRDY) == RCC_CR_SHSIRDY) ? 1UL : 0UL); 2032 } 2033 /** 2034 * @} 2035 */ 2036 2037 /** 2038 * @} 2039 */ 2040 2041 /** @defgroup RCC_LL_EF_MSI MSI 2042 * @{ 2043 */ 2044 2045 /** 2046 * @brief Enable MSIS oscillator 2047 * @rmtoll CR MSISON LL_RCC_MSIS_Enable 2048 * @retval None 2049 */ LL_RCC_MSIS_Enable(void)2050 __STATIC_INLINE void LL_RCC_MSIS_Enable(void) 2051 { 2052 SET_BIT(RCC->CR, RCC_CR_MSISON); 2053 } 2054 #define LL_RCC_MSI_Enable LL_RCC_MSIS_Enable /*!< alias define for compatibility with legacy code */ 2055 2056 /** 2057 * @brief Disable MSIS oscillator 2058 * @rmtoll CR MSISON LL_RCC_MSIS_Disable 2059 * @retval None 2060 */ LL_RCC_MSIS_Disable(void)2061 __STATIC_INLINE void LL_RCC_MSIS_Disable(void) 2062 { 2063 CLEAR_BIT(RCC->CR, RCC_CR_MSISON); 2064 } 2065 #define LL_RCC_MSI_Disable LL_RCC_MSIS_Disable /*!< alias define for compatibility with legacy code */ 2066 2067 /** 2068 * @brief Check if MSIS oscillator Ready 2069 * @rmtoll CR MSISRDY LL_RCC_MSIS_IsReady 2070 * @retval State of bit (1 or 0). 2071 */ LL_RCC_MSIS_IsReady(void)2072 __STATIC_INLINE uint32_t LL_RCC_MSIS_IsReady(void) 2073 { 2074 return ((READ_BIT(RCC->CR, RCC_CR_MSISRDY) == RCC_CR_MSISRDY) ? 1UL : 0UL); 2075 } 2076 #define LL_RCC_MSI_IsReady LL_RCC_MSIS_IsReady /*!< alias define for compatibility with legacy code */ 2077 2078 /** 2079 * @brief Enable MSI PLL-mode (Hardware auto calibration with LSE) 2080 * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) 2081 * and ready (LSERDY set by hardware) 2082 * @note hardware protection to avoid enabling MSIPLLEN if LSE is not 2083 * ready 2084 * @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode 2085 * @retval None 2086 */ LL_RCC_MSI_EnablePLLMode(void)2087 __STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void) 2088 { 2089 SET_BIT(RCC->CR, RCC_CR_MSIPLLEN); 2090 } 2091 2092 /** 2093 * @brief Disable MSI-PLL mode 2094 * @note cleared by hardware when LSE is disabled (LSEON = 0) or when 2095 * the Clock Security System on LSE detects a LSE failure 2096 * @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode 2097 * @retval None 2098 */ LL_RCC_MSI_DisablePLLMode(void)2099 __STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void) 2100 { 2101 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN); 2102 } 2103 2104 /** 2105 * @brief Check if MSI-PLL mode has been enabled or not 2106 * @rmtoll CR MSIPLLEN LL_RCC_IsEnabledPLLMode 2107 * @retval State of bit (1 or 0). 2108 */ LL_RCC_IsEnabledPLLMode(void)2109 __STATIC_INLINE uint32_t LL_RCC_IsEnabledPLLMode(void) 2110 { 2111 return ((READ_BIT(RCC->CR, RCC_CR_MSIPLLEN) == RCC_CR_MSIPLLEN) ? 1UL : 0UL); 2112 } 2113 2114 /** 2115 * @brief Set clock source in PLL mode 2116 * @rmtoll CR MSIPLLSEL LL_RCC_SetMSIPLLMode 2117 * @param Source This parameter can be one of the following values: 2118 * @arg @ref LL_RCC_PLLMODE_MSIS 2119 * @arg @ref LL_RCC_PLLMODE_MSIK 2120 * @retval None 2121 */ LL_RCC_SetMSIPLLMode(uint32_t Source)2122 __STATIC_INLINE void LL_RCC_SetMSIPLLMode(uint32_t Source) 2123 { 2124 MODIFY_REG(RCC->CR, RCC_CR_MSIPLLSEL, Source); 2125 } 2126 2127 /** 2128 * @brief Get Clock source in PLL Mode 2129 * @rmtoll CR MSIPLLSEL LL_RCC_GetMSIPLLMode 2130 * @retval Returned value can be one of the following values: 2131 * @arg @ref LL_RCC_PLLMODE_MSIS 2132 * @arg @ref LL_RCC_PLLMODE_MSIK 2133 */ LL_RCC_GetMSIPLLMode(void)2134 __STATIC_INLINE uint32_t LL_RCC_GetMSIPLLMode(void) 2135 { 2136 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIPLLSEL)); 2137 } 2138 2139 /** 2140 * @brief Enable MSI fast mode 2141 * @rmtoll CR MSIPLLFAST LL_RCC_Enable_MSIPLLFAST 2142 * @note This bit is used only if PLL mode is selected. 2143 */ LL_RCC_Enable_MSIPLLFAST(void)2144 __STATIC_INLINE void LL_RCC_Enable_MSIPLLFAST(void) 2145 { 2146 SET_BIT(RCC->CR, RCC_CR_MSIPLLFAST); 2147 } 2148 2149 /** 2150 * @brief Disable MSI fast mode 2151 * @rmtoll CR MSIPLLFAST LL_RCC_Disable_MSIPLLFAST 2152 * @note This bit is used only if PLL mode is selected. 2153 */ LL_RCC_Disable_MSIPLLFAST(void)2154 __STATIC_INLINE void LL_RCC_Disable_MSIPLLFAST(void) 2155 { 2156 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLFAST); 2157 } 2158 2159 /** 2160 * @brief Check if MSI PLL Fast Mode is enable 2161 * @rmtoll CR MSIPLLFAST LL_RCC_MSI_IsEnabledMSIPLLFAST 2162 * @retval State of bit (1 or 0). 2163 */ LL_RCC_MSI_IsEnabledMSIPLLFAST(void)2164 __STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledMSIPLLFAST(void) 2165 { 2166 return ((READ_BIT(RCC->CR, RCC_CR_MSIPLLFAST) == RCC_CR_MSIPLLFAST) ? 1UL : 0UL); 2167 } 2168 2169 /** 2170 * @brief Set MSI Bias mode 2171 * @rmtoll ICSCR1 MSIBIAS LL_RCC_MSI_SetMSIBiasMode 2172 * @param BiasMode This parameter can be one of the following values: 2173 * @arg @ref LL_RCC_MSIBIASMODE_CONTINUOUS 2174 * @arg @ref LL_RCC_MSIBIASMODE_SAMPLING 2175 2176 * @retval None 2177 */ LL_RCC_MSI_SetMSIBiasMode(uint32_t BiasMode)2178 __STATIC_INLINE void LL_RCC_MSI_SetMSIBiasMode(uint32_t BiasMode) 2179 { 2180 MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS, BiasMode); 2181 } 2182 2183 /** 2184 * @brief Get MSI Bias mode 2185 * @rmtoll ICSCR1 MSIBIAS LL_RCC_MSI_GetMSIBiasMode 2186 * @retval Returned value can be one of the following values: 2187 * @arg @ref LL_RCC_MSIBIASMODE_CONTINUOUS 2188 * @arg @ref LL_RCC_MSIBIASMODE_SAMPLING 2189 2190 */ LL_RCC_MSI_GetMSIBiasMode(void)2191 __STATIC_INLINE uint32_t LL_RCC_MSI_GetMSIBiasMode(void) 2192 { 2193 return (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS)); 2194 } 2195 2196 /** 2197 * @brief Enable MSIK even in stop mode 2198 * @note MSIK oscillator is forced ON even in Stop mode 2199 * @rmtoll CR MSIKERON LL_RCC_MSIK_EnableInStopMode 2200 * @retval None 2201 */ LL_RCC_MSIK_EnableInStopMode(void)2202 __STATIC_INLINE void LL_RCC_MSIK_EnableInStopMode(void) 2203 { 2204 SET_BIT(RCC->CR, RCC_CR_MSIKERON); 2205 } 2206 2207 /** 2208 * @brief Disable MSIK in stop mode 2209 * @rmtoll CR MSIKERON LL_RCC_MSIK_DisableInStopMode 2210 * @retval None 2211 */ LL_RCC_MSIK_DisableInStopMode(void)2212 __STATIC_INLINE void LL_RCC_MSIK_DisableInStopMode(void) 2213 { 2214 CLEAR_BIT(RCC->CR, RCC_CR_MSIKERON); 2215 } 2216 2217 /** 2218 * @brief Check if MSIK is enabled in stop mode 2219 * @rmtoll CR MSIKERON LL_RCC_MSIK_IsEnabledInStopMode 2220 * @retval State of bit (1 or 0). 2221 */ LL_RCC_MSIK_IsEnabledInStopMode(void)2222 __STATIC_INLINE uint32_t LL_RCC_MSIK_IsEnabledInStopMode(void) 2223 { 2224 return ((READ_BIT(RCC->CR, RCC_CR_MSIKERON) == RCC_CR_MSIKERON) ? 1UL : 0UL); 2225 } 2226 2227 /** 2228 * @brief Enable MSI clock range selection with MSIRANGE register 2229 * @note Write 0 has no effect. After a standby or a reset 2230 * MSIRGSEL is at 0 and the MSI range value is provided by 2231 * MSISRANGE 2232 * @rmtoll ICSCR1 MSIRGSEL LL_RCC_MSI_EnableRangeSelection 2233 * @retval None 2234 */ LL_RCC_MSI_EnableRangeSelection(void)2235 __STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void) 2236 { 2237 SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); 2238 } 2239 2240 /** 2241 * @brief Check if MSI clock range is selected with MSIRANGE register 2242 * @rmtoll ICSCR1 MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect 2243 * @retval State of bit (1 or 0). 2244 */ LL_RCC_MSI_IsEnabledRangeSelect(void)2245 __STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void) 2246 { 2247 return ((READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == RCC_ICSCR1_MSIRGSEL) ? 1UL : 0UL); 2248 } 2249 2250 /** 2251 * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode. 2252 * @rmtoll ICSCR1 MSISRANGE LL_RCC_MSIS_SetRange 2253 * @param Range This parameter can be one of the following values: 2254 * @arg @ref LL_RCC_MSISRANGE_0 2255 * @arg @ref LL_RCC_MSISRANGE_1 2256 * @arg @ref LL_RCC_MSISRANGE_2 2257 * @arg @ref LL_RCC_MSISRANGE_3 2258 * @arg @ref LL_RCC_MSISRANGE_4 2259 * @arg @ref LL_RCC_MSISRANGE_5 2260 * @arg @ref LL_RCC_MSISRANGE_6 2261 * @arg @ref LL_RCC_MSISRANGE_7 2262 * @arg @ref LL_RCC_MSISRANGE_8 2263 * @arg @ref LL_RCC_MSISRANGE_9 2264 * @arg @ref LL_RCC_MSISRANGE_10 2265 * @arg @ref LL_RCC_MSISRANGE_11 2266 * @arg @ref LL_RCC_MSISRANGE_12 2267 * @arg @ref LL_RCC_MSISRANGE_13 2268 * @arg @ref LL_RCC_MSISRANGE_14 2269 * @arg @ref LL_RCC_MSISRANGE_15 2270 * @retval None 2271 */ LL_RCC_MSIS_SetRange(uint32_t Range)2272 __STATIC_INLINE void LL_RCC_MSIS_SetRange(uint32_t Range) 2273 { 2274 MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE, Range); 2275 } 2276 #define LL_RCC_MSI_SetRange LL_RCC_MSIS_SetRange /*!< alias define for compatibility with legacy code */ 2277 2278 /** 2279 * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode. 2280 * @rmtoll ICSCR1 MSISRANGE LL_RCC_MSIS_GetRange 2281 * @retval Returned value can be one of the following values: 2282 * @arg @ref LL_RCC_MSISRANGE_0 2283 * @arg @ref LL_RCC_MSISRANGE_1 2284 * @arg @ref LL_RCC_MSISRANGE_2 2285 * @arg @ref LL_RCC_MSISRANGE_3 2286 * @arg @ref LL_RCC_MSISRANGE_4 2287 * @arg @ref LL_RCC_MSISRANGE_5 2288 * @arg @ref LL_RCC_MSISRANGE_6 2289 * @arg @ref LL_RCC_MSISRANGE_7 2290 * @arg @ref LL_RCC_MSISRANGE_8 2291 * @arg @ref LL_RCC_MSISRANGE_9 2292 * @arg @ref LL_RCC_MSISRANGE_10 2293 * @arg @ref LL_RCC_MSISRANGE_11 2294 * @arg @ref LL_RCC_MSISRANGE_12 2295 * @arg @ref LL_RCC_MSISRANGE_13 2296 * @arg @ref LL_RCC_MSISRANGE_14 2297 * @arg @ref LL_RCC_MSISRANGE_15 2298 */ LL_RCC_MSIS_GetRange(void)2299 __STATIC_INLINE uint32_t LL_RCC_MSIS_GetRange(void) 2300 { 2301 return (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE)); 2302 } 2303 #define LL_RCC_MSI_GetRange LL_RCC_MSIS_GetRange /*!< alias define for compatibility with legacy code */ 2304 2305 /** 2306 * @brief Configure MSIS range used after standby 2307 * @rmtoll CSR MSISSRANGE LL_RCC_MSIS_SetRangeAfterStandby 2308 * @param Range This parameter can be one of the following values: 2309 * @arg @ref LL_RCC_MSISSRANGE_4 2310 * @arg @ref LL_RCC_MSISSRANGE_5 2311 * @arg @ref LL_RCC_MSISSRANGE_6 2312 * @arg @ref LL_RCC_MSISSRANGE_7 2313 * @arg @ref LL_RCC_MSISSRANGE_8 2314 * @retval None 2315 */ LL_RCC_MSIS_SetRangeAfterStandby(uint32_t Range)2316 __STATIC_INLINE void LL_RCC_MSIS_SetRangeAfterStandby(uint32_t Range) 2317 { 2318 MODIFY_REG(RCC->CSR, RCC_CSR_MSISSRANGE, Range); 2319 } 2320 #define LL_RCC_MSI_SetRangeAfterStandby LL_RCC_MSIS_SetRangeAfterStandby /*!< alias define for compatibility with legacy code */ 2321 2322 /** 2323 * @brief Get MSIS range used after standby 2324 * @rmtoll CSR MSISSRANGE LL_RCC_MSIS_GetRangeAfterStandby 2325 * @retval Returned value can be one of the following values: 2326 * @arg @ref LL_RCC_MSISSRANGE_4 2327 * @arg @ref LL_RCC_MSISSRANGE_5 2328 * @arg @ref LL_RCC_MSISSRANGE_6 2329 * @arg @ref LL_RCC_MSISSRANGE_7 2330 * @arg @ref LL_RCC_MSISSRANGE_8 2331 */ LL_RCC_MSIS_GetRangeAfterStandby(void)2332 __STATIC_INLINE uint32_t LL_RCC_MSIS_GetRangeAfterStandby(void) 2333 { 2334 return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISSRANGE)); 2335 } 2336 #define LL_RCC_MSI_GetRangeAfterStandby LL_RCC_MSIS_GetRangeAfterStandby /*!< alias define for compatibility with legacy code */ 2337 2338 /** 2339 * @brief Set MSI OSCILLATORx Calibration trimming 2340 * @note user-programmable trimming value that is added to the MSICALx 2341 * @rmtoll ICSCR2 MSITRIMx LL_RCC_MSI_SetCalibTrimming 2342 * @param Value Between Min_Data = 0 and Max_Data = 31 2343 * @param Oscillator This parameter can be one of the following values: 2344 * @arg @ref LL_RCC_MSI_OSCILLATOR_0 2345 * @arg @ref LL_RCC_MSI_OSCILLATOR_1 2346 * @arg @ref LL_RCC_MSI_OSCILLATOR_2 2347 * @arg @ref LL_RCC_MSI_OSCILLATOR_3 2348 * @retval None 2349 */ LL_RCC_MSI_SetCalibTrimming(uint32_t Value,uint32_t Oscillator)2350 __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value, uint32_t Oscillator) 2351 { 2352 MODIFY_REG(RCC->ICSCR2, (RCC_ICSCR2_MSITRIM0 >> Oscillator), Value << (RCC_ICSCR2_MSITRIM0_Pos - Oscillator)); 2353 } 2354 2355 /** 2356 * @brief Get MSI OSCILLATORx Calibration trimming 2357 * @rmtoll ICSCR2 MSITRIMx LL_RCC_MSI_GetCalibTrimming 2358 * @retval Between 0 and 31 2359 * @param Oscillator This parameter can be one of the following values: 2360 * @arg @ref LL_RCC_MSI_OSCILLATOR_0 2361 * @arg @ref LL_RCC_MSI_OSCILLATOR_1 2362 * @arg @ref LL_RCC_MSI_OSCILLATOR_2 2363 * @arg @ref LL_RCC_MSI_OSCILLATOR_3 2364 */ LL_RCC_MSI_GetCalibTrimming(uint32_t Oscillator)2365 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(uint32_t Oscillator) 2366 { 2367 return (uint32_t)(READ_BIT(RCC->ICSCR2, 2368 (RCC_ICSCR2_MSITRIM0 >> Oscillator)) >> (RCC_ICSCR2_MSITRIM0_Pos - Oscillator)); 2369 } 2370 2371 /** 2372 * @brief Get MSI OSCILLATORx Calibration value 2373 * @note When MSITRIMx is written, MSICALx is updated with the sum of 2374 * MSITRIMx and the factory trim value 2375 * @rmtoll ICSCR1 MSICALx LL_RCC_MSI_GetCalibration 2376 * @param Oscillator This parameter can be one of the following values: 2377 * @arg @ref LL_RCC_MSI_OSCILLATOR_0 2378 * @arg @ref LL_RCC_MSI_OSCILLATOR_1 2379 * @arg @ref LL_RCC_MSI_OSCILLATOR_2 2380 * @arg @ref LL_RCC_MSI_OSCILLATOR_3 2381 * @retval Between Min_Data = 0 and Max_Data = 31 2382 */ LL_RCC_MSI_GetCalibration(uint32_t Oscillator)2383 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(uint32_t Oscillator) 2384 { 2385 return (uint32_t)(READ_BIT(RCC->ICSCR1, (RCC_ICSCR1_MSICAL0 >> Oscillator)) >> (RCC_ICSCR1_MSICAL0_Pos - Oscillator)); 2386 } 2387 2388 /** 2389 * @} 2390 */ 2391 2392 /** @defgroup RCC_LL_EF_MSIK MSIK 2393 * @{ 2394 */ 2395 2396 /** 2397 * @brief Configure the Internal Multi Speed oscillator (MSIK) clock range in run mode. 2398 * @rmtoll ICSCR1 MSIKRANGE LL_RCC_MSIK_SetRange 2399 * @param Range This parameter can be one of the following values: 2400 * @arg @ref LL_RCC_MSIKRANGE_0 2401 * @arg @ref LL_RCC_MSIKRANGE_1 2402 * @arg @ref LL_RCC_MSIKRANGE_2 2403 * @arg @ref LL_RCC_MSIKRANGE_3 2404 * @arg @ref LL_RCC_MSIKRANGE_4 2405 * @arg @ref LL_RCC_MSIKRANGE_5 2406 * @arg @ref LL_RCC_MSIKRANGE_6 2407 * @arg @ref LL_RCC_MSIKRANGE_7 2408 * @arg @ref LL_RCC_MSIKRANGE_8 2409 * @arg @ref LL_RCC_MSIKRANGE_9 2410 * @arg @ref LL_RCC_MSIKRANGE_10 2411 * @arg @ref LL_RCC_MSIKRANGE_11 2412 * @arg @ref LL_RCC_MSIKRANGE_12 2413 * @arg @ref LL_RCC_MSIKRANGE_13 2414 * @arg @ref LL_RCC_MSIKRANGE_14 2415 * @arg @ref LL_RCC_MSIKRANGE_15 2416 * @retval None 2417 */ LL_RCC_MSIK_SetRange(uint32_t Range)2418 __STATIC_INLINE void LL_RCC_MSIK_SetRange(uint32_t Range) 2419 { 2420 MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE, Range); 2421 } 2422 2423 /** 2424 * @brief Get the Internal Multi Speed oscillator (MSIK) clock range in run mode. 2425 * @rmtoll ICSCR1 MSIKRANGE LL_RCC_MSIK_GetRange 2426 * @retval Returned value can be one of the following values: 2427 * @arg @ref LL_RCC_MSIKRANGE_0 2428 * @arg @ref LL_RCC_MSIKRANGE_1 2429 * @arg @ref LL_RCC_MSIKRANGE_2 2430 * @arg @ref LL_RCC_MSIKRANGE_3 2431 * @arg @ref LL_RCC_MSIKRANGE_4 2432 * @arg @ref LL_RCC_MSIKRANGE_5 2433 * @arg @ref LL_RCC_MSIKRANGE_6 2434 * @arg @ref LL_RCC_MSIKRANGE_7 2435 * @arg @ref LL_RCC_MSIKRANGE_8 2436 * @arg @ref LL_RCC_MSIKRANGE_9 2437 * @arg @ref LL_RCC_MSIKRANGE_10 2438 * @arg @ref LL_RCC_MSIKRANGE_11 2439 * @arg @ref LL_RCC_MSIKRANGE_12 2440 * @arg @ref LL_RCC_MSIKRANGE_13 2441 * @arg @ref LL_RCC_MSIKRANGE_14 2442 * @arg @ref LL_RCC_MSIKRANGE_15 2443 */ LL_RCC_MSIK_GetRange(void)2444 __STATIC_INLINE uint32_t LL_RCC_MSIK_GetRange(void) 2445 { 2446 return (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE)); 2447 } 2448 2449 /** 2450 * @brief Configure MSIK range used after standby 2451 * @rmtoll CSR MSIKSRANGE LL_RCC_MSIK_SetRangeAfterStandby 2452 * @param Range This parameter can be one of the following values: 2453 * @arg @ref LL_RCC_MSIKSRANGE_4 2454 * @arg @ref LL_RCC_MSIKSRANGE_5 2455 * @arg @ref LL_RCC_MSIKSRANGE_6 2456 * @arg @ref LL_RCC_MSIKSRANGE_7 2457 * @arg @ref LL_RCC_MSIKSRANGE_8 2458 * @retval None 2459 */ LL_RCC_MSIK_SetRangeAfterStandby(uint32_t Range)2460 __STATIC_INLINE void LL_RCC_MSIK_SetRangeAfterStandby(uint32_t Range) 2461 { 2462 MODIFY_REG(RCC->CSR, RCC_CSR_MSIKSRANGE, Range); 2463 } 2464 2465 /** 2466 * @brief Get MSIK range used after standby 2467 * @rmtoll CSR MSIKSRANGE LL_RCC_MSIK_GetRangeAfterStandby 2468 * @retval Returned value can be one of the following values: 2469 * @arg @ref LL_RCC_MSIKSRANGE_4 2470 * @arg @ref LL_RCC_MSIKSRANGE_5 2471 * @arg @ref LL_RCC_MSIKSRANGE_6 2472 * @arg @ref LL_RCC_MSIKSRANGE_7 2473 * @arg @ref LL_RCC_MSIKSRANGE_8 2474 */ LL_RCC_MSIK_GetRangeAfterStandby(void)2475 __STATIC_INLINE uint32_t LL_RCC_MSIK_GetRangeAfterStandby(void) 2476 { 2477 return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSIKSRANGE)); 2478 } 2479 /** 2480 * @} 2481 */ 2482 2483 /** @defgroup RCC_LL_EF_LSCO LSCO 2484 * @{ 2485 */ 2486 2487 /** 2488 * @brief Enable Low speed clock 2489 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable 2490 * @retval None 2491 */ LL_RCC_LSCO_Enable(void)2492 __STATIC_INLINE void LL_RCC_LSCO_Enable(void) 2493 { 2494 SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); 2495 } 2496 2497 /** 2498 * @brief Disable Low speed clock 2499 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable 2500 * @retval None 2501 */ LL_RCC_LSCO_Disable(void)2502 __STATIC_INLINE void LL_RCC_LSCO_Disable(void) 2503 { 2504 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); 2505 } 2506 2507 /** 2508 * @brief Configure Low speed clock selection 2509 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource 2510 * @param Source This parameter can be one of the following values: 2511 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI 2512 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE 2513 * @retval None 2514 */ LL_RCC_LSCO_SetSource(uint32_t Source)2515 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source) 2516 { 2517 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source); 2518 } 2519 2520 /** 2521 * @brief Get Low speed clock selection 2522 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource 2523 * @retval Returned value can be one of the following values: 2524 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI 2525 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE 2526 */ LL_RCC_LSCO_GetSource(void)2527 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void) 2528 { 2529 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL)); 2530 } 2531 2532 /** 2533 * @} 2534 */ 2535 2536 /** @defgroup RCC_LL_EF_System System 2537 * @{ 2538 */ 2539 2540 /** 2541 * @brief Configure the system clock source 2542 * @rmtoll CFGR1 SW LL_RCC_SetSysClkSource 2543 * @param Source This parameter can be one of the following values: 2544 * @arg @ref LL_RCC_SYS_CLKSOURCE_MSIS 2545 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI 2546 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE 2547 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1 2548 * @retval None 2549 */ LL_RCC_SetSysClkSource(uint32_t Source)2550 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) 2551 { 2552 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, Source); 2553 } 2554 2555 /** 2556 * @brief Get the system clock source 2557 * @rmtoll CFGR1 SWS LL_RCC_GetSysClkSource 2558 * @retval Returned value can be one of the following values: 2559 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSIS 2560 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI 2561 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE 2562 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 2563 */ LL_RCC_GetSysClkSource(void)2564 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) 2565 { 2566 return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_SWS)); 2567 } 2568 2569 /** 2570 * @brief Set AHB prescaler 2571 * @rmtoll CFGR2 HPRE LL_RCC_SetAHBPrescaler 2572 * @param Prescaler This parameter can be one of the following values: 2573 * @arg @ref LL_RCC_SYSCLK_DIV_1 2574 * @arg @ref LL_RCC_SYSCLK_DIV_2 2575 * @arg @ref LL_RCC_SYSCLK_DIV_4 2576 * @arg @ref LL_RCC_SYSCLK_DIV_8 2577 * @arg @ref LL_RCC_SYSCLK_DIV_16 2578 * @arg @ref LL_RCC_SYSCLK_DIV_64 2579 * @arg @ref LL_RCC_SYSCLK_DIV_128 2580 * @arg @ref LL_RCC_SYSCLK_DIV_256 2581 * @arg @ref LL_RCC_SYSCLK_DIV_512 2582 * @retval None 2583 */ LL_RCC_SetAHBPrescaler(uint32_t Prescaler)2584 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) 2585 { 2586 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, Prescaler); 2587 } 2588 2589 /** 2590 * @brief Set Systick clock source 2591 * @rmtoll CCIPR1 SYSTICKSEL LL_RCC_SetSystickClockSource 2592 * @param SystickSource This parameter can be one of the following values: 2593 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI 2594 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE 2595 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 2596 * @retval None 2597 */ LL_RCC_SetSystickClockSource(uint32_t SystickSource)2598 __STATIC_INLINE void LL_RCC_SetSystickClockSource(uint32_t SystickSource) 2599 { 2600 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, SystickSource); 2601 } 2602 2603 /** 2604 * @brief Set APB1 prescaler 2605 * @rmtoll CFGR2 PPRE1 LL_RCC_SetAPB1Prescaler 2606 * @param Prescaler This parameter can be one of the following values: 2607 * @arg @ref LL_RCC_APB1_DIV_1 2608 * @arg @ref LL_RCC_APB1_DIV_2 2609 * @arg @ref LL_RCC_APB1_DIV_4 2610 * @arg @ref LL_RCC_APB1_DIV_8 2611 * @arg @ref LL_RCC_APB1_DIV_16 2612 * @retval None 2613 */ LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)2614 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) 2615 { 2616 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, Prescaler); 2617 } 2618 2619 /** 2620 * @brief Set APB2 prescaler 2621 * @rmtoll CFGR2 PPRE2 LL_RCC_SetAPB2Prescaler 2622 * @param Prescaler This parameter can be one of the following values: 2623 * @arg @ref LL_RCC_APB2_DIV_1 2624 * @arg @ref LL_RCC_APB2_DIV_2 2625 * @arg @ref LL_RCC_APB2_DIV_4 2626 * @arg @ref LL_RCC_APB2_DIV_8 2627 * @arg @ref LL_RCC_APB2_DIV_16 2628 * @retval None 2629 */ LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)2630 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) 2631 { 2632 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, Prescaler); 2633 } 2634 2635 /** 2636 * @brief Set APB3 prescaler 2637 * @rmtoll CFGR3 PPRE3 LL_RCC_SetAPB3Prescaler 2638 * @param Prescaler This parameter can be one of the following values: 2639 * @arg @ref LL_RCC_APB3_DIV_1 2640 * @arg @ref LL_RCC_APB3_DIV_2 2641 * @arg @ref LL_RCC_APB3_DIV_4 2642 * @arg @ref LL_RCC_APB3_DIV_8 2643 * @arg @ref LL_RCC_APB3_DIV_16 2644 * @retval None 2645 */ LL_RCC_SetAPB3Prescaler(uint32_t Prescaler)2646 __STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler) 2647 { 2648 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, Prescaler); 2649 } 2650 2651 #if defined(RCC_CFGR2_PPRE_DPHY) 2652 /** 2653 * @brief Set DPHY clock prescaler 2654 * @rmtoll CFGR2 PPRE_DPHY LL_RCC_SetDPHYPrescaler 2655 * @param Prescaler This parameter can be one of the following values: 2656 * @arg @ref LL_RCC_DPHY_DIV_1 2657 * @arg @ref LL_RCC_DPHY_DIV_2 2658 * @arg @ref LL_RCC_DPHY_DIV_4 2659 * @arg @ref LL_RCC_DPHY_DIV_8 2660 * @arg @ref LL_RCC_DPHY_DIV_16 2661 * @retval None 2662 */ LL_RCC_SetDPHYPrescaler(uint32_t Prescaler)2663 __STATIC_INLINE void LL_RCC_SetDPHYPrescaler(uint32_t Prescaler) 2664 { 2665 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE_DPHY, Prescaler); 2666 } 2667 #endif /* RCC_CFGR2_PPRE_DPHY */ 2668 2669 /** 2670 * @brief Get AHB prescaler 2671 * @rmtoll CFGR2 HPRE LL_RCC_GetAHBPrescaler 2672 * @retval Returned value can be one of the following values: 2673 * @arg @ref LL_RCC_SYSCLK_DIV_1 2674 * @arg @ref LL_RCC_SYSCLK_DIV_2 2675 * @arg @ref LL_RCC_SYSCLK_DIV_4 2676 * @arg @ref LL_RCC_SYSCLK_DIV_8 2677 * @arg @ref LL_RCC_SYSCLK_DIV_16 2678 * @arg @ref LL_RCC_SYSCLK_DIV_64 2679 * @arg @ref LL_RCC_SYSCLK_DIV_128 2680 * @arg @ref LL_RCC_SYSCLK_DIV_256 2681 * @arg @ref LL_RCC_SYSCLK_DIV_512 2682 */ LL_RCC_GetAHBPrescaler(void)2683 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) 2684 { 2685 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_HPRE)); 2686 } 2687 2688 /** 2689 * @brief Get Sysctick clock source 2690 * @rmtoll CCIPR1 SYSTICKSEL LL_RCC_SetSystickClockSource 2691 * @retval Returned value can be one of the following values: 2692 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI 2693 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE 2694 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 2695 */ LL_RCC_GetSystickClockSource(void)2696 __STATIC_INLINE uint32_t LL_RCC_GetSystickClockSource(void) 2697 { 2698 return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL)); 2699 } 2700 2701 /** 2702 * @brief Get APB1 prescaler 2703 * @rmtoll CFGR2 PPRE1 LL_RCC_GetAPB1Prescaler 2704 * @retval Returned value can be one of the following values: 2705 * @arg @ref LL_RCC_APB1_DIV_1 2706 * @arg @ref LL_RCC_APB1_DIV_2 2707 * @arg @ref LL_RCC_APB1_DIV_4 2708 * @arg @ref LL_RCC_APB1_DIV_8 2709 * @arg @ref LL_RCC_APB1_DIV_16 2710 */ LL_RCC_GetAPB1Prescaler(void)2711 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) 2712 { 2713 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE1)); 2714 } 2715 2716 /** 2717 * @brief Get APB2 prescaler 2718 * @rmtoll CFGR2 PPRE2 LL_RCC_GetAPB2Prescaler 2719 * @retval Returned value can be one of the following values: 2720 * @arg @ref LL_RCC_APB2_DIV_1 2721 * @arg @ref LL_RCC_APB2_DIV_2 2722 * @arg @ref LL_RCC_APB2_DIV_4 2723 * @arg @ref LL_RCC_APB2_DIV_8 2724 * @arg @ref LL_RCC_APB2_DIV_16 2725 */ LL_RCC_GetAPB2Prescaler(void)2726 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) 2727 { 2728 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE2)); 2729 } 2730 2731 /** 2732 * @brief Get APB3 prescaler 2733 * @rmtoll CFGR3 PPRE3 LL_RCC_GetAPB2Prescaler 2734 * @retval Returned value can be one of the following values: 2735 * @arg @ref LL_RCC_APB3_DIV_1 2736 * @arg @ref LL_RCC_APB3_DIV_2 2737 * @arg @ref LL_RCC_APB3_DIV_4 2738 * @arg @ref LL_RCC_APB3_DIV_8 2739 * @arg @ref LL_RCC_APB3_DIV_16 2740 */ LL_RCC_GetAPB3Prescaler(void)2741 __STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void) 2742 { 2743 return (uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_PPRE3)); 2744 } 2745 2746 #if defined(RCC_CFGR2_PPRE_DPHY) 2747 /** 2748 * @brief Get DPHY clock prescaler 2749 * @rmtoll CFGR2 PPRE_DPHY LL_RCC_GetDPHYPrescaler 2750 * @retval Returned value can be one of the following values: 2751 * @arg @ref LL_RCC_DPHY_DIV_1 2752 * @arg @ref LL_RCC_DPHY_DIV_2 2753 * @arg @ref LL_RCC_DPHY_DIV_4 2754 * @arg @ref LL_RCC_DPHY_DIV_8 2755 * @arg @ref LL_RCC_DPHY_DIV_16 2756 */ LL_RCC_GetDPHYPrescaler(void)2757 __STATIC_INLINE uint32_t LL_RCC_GetDPHYPrescaler(void) 2758 { 2759 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE_DPHY)); 2760 } 2761 #endif /* RCC_CFGR2_PPRE_DPHY */ 2762 2763 /** 2764 * @brief Set Clock After Wake-Up From Stop mode 2765 * @rmtoll CFGR1 STOPWUCK LL_RCC_SetClkAfterWakeFromStop 2766 * @param Clock This parameter can be one of the following values: 2767 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSIS 2768 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI 2769 * @retval None 2770 */ LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)2771 __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock) 2772 { 2773 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, Clock); 2774 } 2775 2776 /** 2777 * @brief Get Clock After Wake-Up From Stop mode 2778 * @rmtoll CFGR1 STOPWUCK LL_RCC_GetClkAfterWakeFromStop 2779 * @retval Returned value can be one of the following values: 2780 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSIS 2781 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI 2782 */ LL_RCC_GetClkAfterWakeFromStop(void)2783 __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void) 2784 { 2785 return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_STOPWUCK)); 2786 } 2787 2788 /** 2789 * @brief Set Kernel Clock After Wake-Up From Stop mode 2790 * @rmtoll CFGR1 STOPKERWUCK LL_RCC_SetKerClkAfterWakeFromStop 2791 * @param Clock This parameter can be one of the following values: 2792 * @arg @ref LL_RCC_STOP_WAKEUPKERCLOCK_MSIK 2793 * @arg @ref LL_RCC_STOP_WAKEUPKERCLOCK_HSI 2794 * @retval None 2795 */ LL_RCC_SetKerClkAfterWakeFromStop(uint32_t Clock)2796 __STATIC_INLINE void LL_RCC_SetKerClkAfterWakeFromStop(uint32_t Clock) 2797 { 2798 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK, Clock); 2799 } 2800 2801 /** 2802 * @brief Get Kernel Clock After Wake-Up From Stop mode 2803 * @rmtoll CFGR1 STOPKERWUCK LL_RCC_GetKerClkAfterWakeFromStop 2804 * @retval Returned value can be one of the following values: 2805 * @arg @ref LL_RCC_STOP_WAKEUPKERCLOCK_MSIK 2806 * @arg @ref LL_RCC_STOP_WAKEUPKERCLOCK_HSI 2807 */ LL_RCC_GetKerClkAfterWakeFromStop(void)2808 __STATIC_INLINE uint32_t LL_RCC_GetKerClkAfterWakeFromStop(void) 2809 { 2810 return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK)); 2811 } 2812 2813 /** 2814 * @} 2815 */ 2816 2817 /** @defgroup RCC_LL_EF_MCO MCO 2818 * @{ 2819 */ 2820 2821 /** 2822 * @brief Configure MCOx 2823 * @rmtoll CFGR1 MCOSEL LL_RCC_ConfigMCO\n 2824 * CFGR1 MCOPRE LL_RCC_ConfigMCO 2825 * @param MCOxSource This parameter can be one of the following values: 2826 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK 2827 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK 2828 * @arg @ref LL_RCC_MCO1SOURCE_MSIS 2829 * @arg @ref LL_RCC_MCO1SOURCE_HSI 2830 * @arg @ref LL_RCC_MCO1SOURCE_HSE 2831 * @arg @ref LL_RCC_MCO1SOURCE_HSI48 2832 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK 2833 * @arg @ref LL_RCC_MCO1SOURCE_LSI 2834 * @arg @ref LL_RCC_MCO1SOURCE_LSE 2835 * @param MCOxPrescaler This parameter can be one of the following values: 2836 * @arg @ref LL_RCC_MCO1_DIV_1 2837 * @arg @ref LL_RCC_MCO1_DIV_2 2838 * @arg @ref LL_RCC_MCO1_DIV_4 2839 * @arg @ref LL_RCC_MCO1_DIV_8 2840 * @arg @ref LL_RCC_MCO1_DIV_16 2841 * @retval None 2842 */ LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)2843 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) 2844 { 2845 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE, MCOxSource | MCOxPrescaler); 2846 } 2847 2848 /** 2849 * @} 2850 */ 2851 2852 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source 2853 * @{ 2854 */ 2855 2856 /** 2857 * @brief Configure USARTx clock source 2858 * @rmtoll CCIPR1 USART1SEL LL_RCC_SetUSARTClockSource\n 2859 * CCIPR1 USART2SEL LL_RCC_SetUSARTClockSource\n 2860 * CCIPR1 USART3SEL LL_RCC_SetUSARTClockSource\n 2861 * CCIPR2 USART6SEL LL_RCC_SetUSARTClockSource 2862 * @param USARTxSource This parameter can be one of the following values: 2863 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 2864 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK 2865 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI 2866 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE 2867 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) 2868 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) 2869 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) 2870 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) 2871 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 2872 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK 2873 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI 2874 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE 2875 * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*) 2876 * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK (*) 2877 * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI (*) 2878 * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*) 2879 * 2880 * (*) Availability depends on devices. 2881 2882 * @retval None 2883 */ LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)2884 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) 2885 { 2886 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (USARTxSource >> 24U)); 2887 MODIFY_REG(*reg, 3UL << ((USARTxSource & 0x001F0000U) >> 16U), ((USARTxSource & 0x000000FFU) << \ 2888 ((USARTxSource & 0x001F0000U) >> 16U))); 2889 } 2890 2891 /** 2892 * @brief Configure UARTx clock source 2893 * @rmtoll CCIPR1 UART4SEL LL_RCC_SetUARTClockSource\n 2894 * CCIPR1 UART5SEL LL_RCC_SetUARTClockSource 2895 * @param UARTxSource This parameter can be one of the following values: 2896 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 2897 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK 2898 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI 2899 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE 2900 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 2901 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK 2902 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI 2903 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE 2904 * @retval None 2905 */ LL_RCC_SetUARTClockSource(uint32_t UARTxSource)2906 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource) 2907 { 2908 MODIFY_REG(RCC->CCIPR1, UARTxSource >> 16U, (UARTxSource & 0x0000FFFFU)); 2909 } 2910 2911 /** 2912 * @brief Configure LPUARTx clock source 2913 * @rmtoll CCIPR3 LPUART1SEL LL_RCC_SetLPUARTClockSource 2914 * @param LPUARTxSource This parameter can be one of the following values: 2915 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3 2916 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK 2917 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI 2918 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE 2919 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_MSIK 2920 * @retval None 2921 */ LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)2922 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) 2923 { 2924 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL, LPUARTxSource); 2925 } 2926 2927 /** 2928 * @brief Configure I2Cx clock source 2929 * @rmtoll CCIPR1 I2C1SEL LL_RCC_SetI2CClockSource\n 2930 * CCIPR1 I2C2SEL LL_RCC_SetI2CClockSource\n 2931 * CCIPR3 I2C3SEL LL_RCC_SetI2CClockSource\n 2932 * CCIPR1 I2C4SEL LL_RCC_SetI2CClockSource 2933 * @param I2CxSource This parameter can be one of the following values: 2934 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 2935 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK 2936 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI 2937 * @arg @ref LL_RCC_I2C1_CLKSOURCE_MSIK 2938 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 2939 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK 2940 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI 2941 * @arg @ref LL_RCC_I2C2_CLKSOURCE_MSIK 2942 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK3 2943 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK 2944 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI 2945 * @arg @ref LL_RCC_I2C3_CLKSOURCE_MSIK 2946 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 2947 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK 2948 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI 2949 * @arg @ref LL_RCC_I2C4_CLKSOURCE_MSIK 2950 * @retval None 2951 */ LL_RCC_SetI2CClockSource(uint32_t I2CxSource)2952 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) 2953 { 2954 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2CxSource >> 24U)); 2955 MODIFY_REG(*reg, 3U << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((I2CxSource & 0x000000FFU) << \ 2956 (((I2CxSource & 0x00FF0000U) >> 16U) & \ 2957 0x1FU))); 2958 } 2959 2960 /** 2961 * @brief Configure SPIx clock source 2962 * @rmtoll CCIPR1 SPI1SEL LL_RCC_SetSPIClockSource\n 2963 * CCIPR1 SPI1SEL LL_RCC_SetSPIClockSource\n 2964 * CCIPR1 SPI2SEL LL_RCC_SetSPIClockSource\n 2965 * CCIPR3 SPI3SEL LL_RCC_SetSPIClockSource 2966 * @param SPIxSource This parameter can be one of the following values: 2967 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2 2968 * @arg @ref LL_RCC_SPI1_CLKSOURCE_SYSCLK 2969 * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI 2970 * @arg @ref LL_RCC_SPI1_CLKSOURCE_MSIK 2971 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1 2972 * @arg @ref LL_RCC_SPI2_CLKSOURCE_SYSCLK 2973 * @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI 2974 * @arg @ref LL_RCC_SPI2_CLKSOURCE_MSIK 2975 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK3 2976 * @arg @ref LL_RCC_SPI3_CLKSOURCE_SYSCLK 2977 * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI 2978 * @arg @ref LL_RCC_SPI3_CLKSOURCE_MSIK 2979 * @retval None 2980 */ LL_RCC_SetSPIClockSource(uint32_t SPIxSource)2981 __STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t SPIxSource) 2982 { 2983 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIxSource >> 24U)); 2984 MODIFY_REG(*reg, 3U << (((SPIxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((SPIxSource & 0x000000FFU) << \ 2985 (((SPIxSource & 0x00FF0000U) >> 16U) & \ 2986 0x1FU))); 2987 } 2988 2989 /** 2990 * @brief Configure LPTIMx clock source 2991 * @rmtoll CCIPR1 LPTIM2SEL LL_RCC_SetLPTIMClockSource\n 2992 * CCIPR3 LPTIM2SEL LL_RCC_SetLPTIMClockSource\n 2993 * CCIPR3 LPTIM34SEL LL_RCC_SetLPTIMClockSource 2994 * @param LPTIMxSource This parameter can be one of the following values: 2995 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_MSIK 2996 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI 2997 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI 2998 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE 2999 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 3000 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI 3001 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI 3002 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE 3003 * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_MSIK 3004 * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_LSI 3005 * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_HSI 3006 * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_LSE 3007 * @retval None 3008 */ LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)3009 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) 3010 { 3011 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMxSource >> 24U)); 3012 MODIFY_REG(*reg, 3U << (((LPTIMxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((LPTIMxSource & 0x000000FFU) << \ 3013 (((LPTIMxSource & 0x00FF0000U) >> 16U) & \ 3014 0x1FU))); 3015 } 3016 3017 /** 3018 * @brief Configure FDCAN kernel clock source 3019 * @rmtoll CCIPR1 FDCANSEL LL_RCC_SetFDCANClockSource 3020 * @param FDCANxSource This parameter can be one of the following values: 3021 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE 3022 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1 3023 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2 3024 * @retval None 3025 */ LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)3026 __STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource) 3027 { 3028 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL, FDCANxSource); 3029 } 3030 3031 /** 3032 * @brief Configure SAIx clock source 3033 * @rmtoll CCIPR2 SAI1SEL LL_RCC_SetSAIClockSource\n 3034 * CCIPR2 SAI2SEL LL_RCC_SetSAIClockSource 3035 * @param SAIxSource This parameter can be one of the following values: 3036 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1 3037 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2 3038 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3 3039 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN 3040 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI 3041 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1 (*) 3042 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2 (*) 3043 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3 (*) 3044 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*) 3045 * @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI (*) 3046 * 3047 * (*) Availability depends on devices. 3048 * 3049 * @retval None 3050 */ LL_RCC_SetSAIClockSource(uint32_t SAIxSource)3051 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) 3052 { 3053 MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU)); 3054 } 3055 3056 /** 3057 * @brief Configure SDMMC1/2 kernel clock source 3058 * @rmtoll CCIPR2 SDMMCSEL LL_RCC_SetSDMMCKernelClockSource 3059 * @param SDMMCxSource This parameter can be one of the following values: 3060 * @arg @ref LL_RCC_SDMMC12_KERNELCLKSOURCE_48CLK 3061 * @arg @ref LL_RCC_SDMMC12_KERNELCLKSOURCE_PLL1 "P" 3062 * @retval None 3063 */ LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource)3064 __STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource) 3065 { 3066 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, SDMMCxSource); 3067 } 3068 3069 /** 3070 * @brief Configure SDMMC1/2 clock source 3071 * @rmtoll CCIPR1 ICLKSEL LL_RCC_SetSDMMCClockSource 3072 * @param SDMMCxSource This parameter can be one of the following values: 3073 * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_HSI48 3074 * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL1 3075 * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL2 3076 * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_MSIK 3077 * @retval None 3078 */ LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)3079 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource) 3080 { 3081 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ICLKSEL, SDMMCxSource); 3082 } 3083 3084 /** 3085 * @brief Configure RNG clock source 3086 * @rmtoll CCIPR2 RNGSEL LL_RCC_SetRNGClockSource 3087 * @param RNGxSource This parameter can be one of the following values: 3088 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 3089 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48_DIV2 3090 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI 3091 * @retval None 3092 */ LL_RCC_SetRNGClockSource(uint32_t RNGxSource)3093 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) 3094 { 3095 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_RNGSEL, RNGxSource); 3096 } 3097 3098 #if defined(RCC_CCIPR2_USBPHYCSEL) 3099 /** 3100 * @brief Configure USBPHY clock source 3101 * @rmtoll CCIPR2 USBPHYCSEL LL_RCC_SetUSBPHYClockSource 3102 * @param Source This parameter can be one of the following values: 3103 * @arg @ref LL_RCC_USBPHYCLKSOURCE_HSE 3104 * @arg @ref LL_RCC_USBPHYCLKSOURCE_HSE_DIV2 3105 * @arg @ref LL_RCC_USBPHYCLKSOURCE_PLL1 3106 * @arg @ref LL_RCC_USBPHYCLKSOURCE_PLL1_DIV2 3107 * @retval None 3108 */ LL_RCC_SetUSBPHYClockSource(uint32_t Source)3109 __STATIC_INLINE void LL_RCC_SetUSBPHYClockSource(uint32_t Source) 3110 { 3111 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBPHYCSEL, Source); 3112 } 3113 #endif /* RCC_CCIPR2_USBPHYCSEL */ 3114 3115 /** 3116 * @brief Configure USB clock source 3117 * @rmtoll CCIPR1 ICLKSEL LL_RCC_SetUSBClockSource 3118 * @param USBxSource This parameter can be one of the following values: 3119 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 3120 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1 3121 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL2 3122 * @arg @ref LL_RCC_USB_CLKSOURCE_MSIK 3123 * @retval None 3124 */ LL_RCC_SetUSBClockSource(uint32_t USBxSource)3125 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) 3126 { 3127 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ICLKSEL, USBxSource); 3128 } 3129 3130 /** 3131 * @brief Configure ADC clock source 3132 * @rmtoll CCIPR3 ADCDACSEL LL_RCC_SetADCDACClockSource 3133 * @param ADCxDAC1Source This parameter can be one of the following values: 3134 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HCLK 3135 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_SYSCLK 3136 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_PLL2 3137 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSE 3138 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSI 3139 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_MSIK 3140 * @retval None 3141 */ LL_RCC_SetADCDACClockSource(uint32_t ADCxDAC1Source)3142 __STATIC_INLINE void LL_RCC_SetADCDACClockSource(uint32_t ADCxDAC1Source) 3143 { 3144 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADCDACSEL, ADCxDAC1Source); 3145 } 3146 3147 /** 3148 * @brief Configure DAC1 clock source 3149 * @rmtoll CCIPR3 DAC1SEL LL_RCC_SetDAC1ClockSource 3150 * @param Source This parameter can be one of the following values: 3151 * @arg @ref LL_RCC_DAC1_CLKSOURCE_LSE 3152 * @arg @ref LL_RCC_DAC1_CLKSOURCE_LSI 3153 * @retval None 3154 */ LL_RCC_SetDAC1ClockSource(uint32_t Source)3155 __STATIC_INLINE void LL_RCC_SetDAC1ClockSource(uint32_t Source) 3156 { 3157 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_DAC1SEL, Source); 3158 } 3159 3160 /** 3161 * @brief Configure ADF1 clock source 3162 * @rmtoll CCIPR3 ADF1SEL LL_RCC_SetADF1ClockSource 3163 * @param Source This parameter can be one of the following values: 3164 * @arg @ref LL_RCC_ADF1_CLKSOURCE_HCLK 3165 * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL1 3166 * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL3 3167 * @arg @ref LL_RCC_ADF1_CLKSOURCE_MSIK 3168 * @arg @ref LL_RCC_ADF1_CLKSOURCE_PIN 3169 * @retval None 3170 */ LL_RCC_SetADF1ClockSource(uint32_t Source)3171 __STATIC_INLINE void LL_RCC_SetADF1ClockSource(uint32_t Source) 3172 { 3173 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADF1SEL, Source); 3174 } 3175 3176 /** 3177 * @brief Configure MDF1 clock source 3178 * @rmtoll CCIPR3 MDF1SEL LL_RCC_SetMDF1ClockSource 3179 * @param Source This parameter can be one of the following values: 3180 * @arg @ref LL_RCC_MDF1_CLKSOURCE_HCLK 3181 * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL1 3182 * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL3 3183 * @arg @ref LL_RCC_MDF1_CLKSOURCE_MSIK 3184 * @arg @ref LL_RCC_MDF1_CLKSOURCE_PIN 3185 * @retval None 3186 */ LL_RCC_SetMDF1ClockSource(uint32_t Source)3187 __STATIC_INLINE void LL_RCC_SetMDF1ClockSource(uint32_t Source) 3188 { 3189 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_MDF1SEL, Source); 3190 } 3191 3192 /** 3193 * @brief Configure OCTOSPI kernel clock source 3194 * @rmtoll CCIPR2 OSPISEL LL_RCC_SetOCTOSPIClockSource 3195 * @param Source This parameter can be one of the following values: 3196 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 3197 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSIK 3198 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL1 3199 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL2 3200 * @retval None 3201 */ LL_RCC_SetOCTOSPIClockSource(uint32_t Source)3202 __STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t Source) 3203 { 3204 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OCTOSPISEL, Source); 3205 } 3206 3207 #if defined (HSPI1) 3208 /** 3209 * @brief Configure HSPI kernel clock source 3210 * @rmtoll CCIPR2 HSPISEL LL_RCC_SetHSPIClockSource 3211 * @param Source This parameter can be one of the following values: 3212 * @arg @ref LL_RCC_HSPI_CLKSOURCE_SYSCLK 3213 * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL1 3214 * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL2 3215 * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL3 3216 * @retval None 3217 */ LL_RCC_SetHSPIClockSource(uint32_t Source)3218 __STATIC_INLINE void LL_RCC_SetHSPIClockSource(uint32_t Source) 3219 { 3220 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_HSPISEL, Source); 3221 } 3222 #endif /* HSPI1 */ 3223 3224 #if defined(SAES) 3225 /** 3226 * @brief Configure SAES clock source 3227 * @rmtoll CCIPR2 SAESSEL LL_RCC_SetSAESClockSource 3228 * @param Source This parameter can be one of the following values: 3229 * @arg @ref LL_RCC_SAES_CLKSOURCE_SHSI 3230 * @arg @ref LL_RCC_SAES_CLKSOURCE_SHSI_DIV2 3231 * @retval None 3232 */ LL_RCC_SetSAESClockSource(uint32_t Source)3233 __STATIC_INLINE void LL_RCC_SetSAESClockSource(uint32_t Source) 3234 { 3235 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAESSEL, Source); 3236 } 3237 #endif /* SAES */ 3238 3239 #if defined(DSI) 3240 /** 3241 * @brief Configure DSIx clock source 3242 * @rmtoll CCIPR2 DSISEL LL_RCC_SetDSIClockSource 3243 * @param Source This parameter can be one of the following values: 3244 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY 3245 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL3 3246 * @retval None 3247 */ LL_RCC_SetDSIClockSource(uint32_t Source)3248 __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source) 3249 { 3250 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSIHOSTSEL, Source); 3251 } 3252 #endif /* DSI */ 3253 3254 #if defined(LTDC) 3255 /** 3256 * @brief Configure LTDCx clock source 3257 * @rmtoll CCIPR2 LTDCSEL LL_RCC_SetLTDCClockSource 3258 * @param Source This parameter can be one of the following values: 3259 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL2 3260 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL3 3261 * @retval None 3262 */ LL_RCC_SetLTDCClockSource(uint32_t Source)3263 __STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t Source) 3264 { 3265 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LTDCSEL, Source); 3266 } 3267 #endif /* LTDC */ 3268 /** 3269 * @brief Get USARTx clock source 3270 * @rmtoll CCIPR1 USART1SEL LL_RCC_GetUSARTClockSource\n 3271 * CCIPR1 USART2SEL LL_RCC_GetUSARTClockSource\n 3272 * CCIPR1 USART3SEL LL_RCC_GetUSARTClockSource\n 3273 * CCIPR2 USART6SEL LL_RCC_GetUSARTClockSource 3274 * @param USARTx This parameter can be one of the following values: 3275 * @arg @ref LL_RCC_USART1_CLKSOURCE 3276 * @arg @ref LL_RCC_USART2_CLKSOURCE (*) 3277 * @arg @ref LL_RCC_USART3_CLKSOURCE 3278 * @arg @ref LL_RCC_USART6_CLKSOURCE (*) 3279 * @retval Returned value can be one of the following values: 3280 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 3281 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK 3282 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI 3283 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE 3284 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) 3285 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) 3286 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) 3287 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) 3288 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 3289 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK 3290 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI 3291 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE 3292 * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*) 3293 * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK (*) 3294 * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI (*) 3295 * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*) 3296 * 3297 * (*) Availability depends on devices. 3298 */ LL_RCC_GetUSARTClockSource(uint32_t USARTx)3299 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) 3300 { 3301 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (USARTx >> 24U)); 3302 return (uint32_t)((READ_BIT(*reg, 3UL << ((USARTx & 0x001F0000U) >> 16U)) >> \ 3303 ((USARTx & 0x001F0000U) >> 16U)) | (USARTx & 0xFFFF0000U)); 3304 } 3305 3306 /** 3307 * @brief Get UARTx clock source 3308 * @rmtoll CCIPR1 UART4SEL LL_RCC_GetUARTClockSource\n 3309 * CCIPR1 UART5SEL LL_RCC_GetUARTClockSource 3310 * @param UARTx This parameter can be one of the following values: 3311 * @arg @ref LL_RCC_UART4_CLKSOURCE 3312 * @arg @ref LL_RCC_UART5_CLKSOURCE 3313 * @retval Returned value can be one of the following values: 3314 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 3315 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK 3316 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI 3317 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE 3318 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 3319 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK 3320 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI 3321 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE 3322 */ LL_RCC_GetUARTClockSource(uint32_t UARTx)3323 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx) 3324 { 3325 return (uint32_t)(READ_BIT(RCC->CCIPR1, UARTx) | (UARTx << 16U)); 3326 } 3327 3328 /** 3329 * @brief Get LPUARTx clock source 3330 * @rmtoll CCIPR1 LPUART1SEL LL_RCC_GetLPUARTClockSource 3331 * @param LPUARTx This parameter can be one of the following values: 3332 * @arg @ref LL_RCC_LPUART1_CLKSOURCE 3333 * @retval Returned value can be one of the following values: 3334 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3 3335 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK 3336 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI 3337 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE 3338 */ LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)3339 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) 3340 { 3341 return (uint32_t)(READ_BIT(RCC->CCIPR3, LPUARTx)); 3342 } 3343 3344 /** 3345 * @brief Get I2Cx clock source 3346 * @rmtoll CCIPR1 I2C1SEL LL_RCC_GetI2CClockSource\n 3347 * CCIPR1 I2C2SEL LL_RCC_GetI2CClockSource\n 3348 * CCIPR3 I2C3SEL LL_RCC_GetI2CClockSource\n 3349 * CCIPR1 I2C4SEL LL_RCC_GetI2CClockSource 3350 * @param I2Cx This parameter can be one of the following values: 3351 * @arg @ref LL_RCC_I2C1_CLKSOURCE 3352 * @arg @ref LL_RCC_I2C2_CLKSOURCE 3353 * @arg @ref LL_RCC_I2C3_CLKSOURCE 3354 * @arg @ref LL_RCC_I2C4_CLKSOURCE 3355 * @retval Returned value can be one of the following values: 3356 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 3357 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK 3358 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI 3359 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 3360 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK 3361 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI 3362 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK3 3363 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK 3364 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI 3365 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 3366 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK 3367 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI 3368 */ LL_RCC_GetI2CClockSource(uint32_t I2Cx)3369 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) 3370 { 3371 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2Cx >> 24U)); 3372 return (uint32_t)((READ_BIT(*reg, (3UL << (((I2Cx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> \ 3373 (((I2Cx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (I2Cx & 0xFFFF0000UL)); 3374 } 3375 3376 /** 3377 * @brief Get SPIx clock source 3378 * @rmtoll CCIPR1 SPI1SEL LL_RCC_GetSPIClockSource\n 3379 * CCIPR1 SPI2SEL LL_RCC_GetSPIClockSource\n 3380 * CCIPR3 SPI3SEL LL_RCC_GetSPIClockSource 3381 * @param SPIx This parameter can be one of the following values: 3382 * @arg @ref LL_RCC_SPI1_CLKSOURCE 3383 * @arg @ref LL_RCC_SPI2_CLKSOURCE 3384 * @arg @ref LL_RCC_SPI3_CLKSOURCE 3385 * @retval Returned value can be one of the following values: 3386 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2 3387 * @arg @ref LL_RCC_SPI1_CLKSOURCE_SYSCLK 3388 * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI 3389 * @arg @ref LL_RCC_SPI1_CLKSOURCE_MSIK 3390 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1 3391 * @arg @ref LL_RCC_SPI2_CLKSOURCE_SYSCLK 3392 * @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI 3393 * @arg @ref LL_RCC_SPI2_CLKSOURCE_MSIK 3394 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK3 3395 * @arg @ref LL_RCC_SPI3_CLKSOURCE_SYSCLK 3396 * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI 3397 * @arg @ref LL_RCC_SPI3_CLKSOURCE_MSIK 3398 */ LL_RCC_GetSPIClockSource(uint32_t SPIx)3399 __STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t SPIx) 3400 { 3401 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIx >> 24U)); 3402 return (uint32_t)((READ_BIT(*reg, (3UL << (((SPIx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> \ 3403 (((SPIx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (SPIx & 0xFFFF0000UL)); 3404 } 3405 3406 /** 3407 * @brief Get LPTIMx clock source 3408 * @rmtoll CCIPR1 LPTIM2SEL LL_RCC_GetLPTIMClockSource\n 3409 * CCIPR3 LPTIM2SEL LL_RCC_GetLPTIMClockSource\n 3410 * CCIPR3 LPTIM34SEL LL_RCC_GetLPTIMClockSource 3411 * @param LPTIMx This parameter can be one of the following values: 3412 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE 3413 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE 3414 * @arg @ref LL_RCC_LPTIM34_CLKSOURCE 3415 * @retval Returned value can be one of the following values: 3416 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_MSIK 3417 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI 3418 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI 3419 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE 3420 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 3421 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI 3422 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI 3423 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE 3424 * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_MSIK 3425 * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_LSI 3426 * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_HSI 3427 * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_LSE 3428 */ LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)3429 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) 3430 { 3431 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMx >> 24U)); 3432 return (uint32_t)((READ_BIT(*reg, (3UL << (((LPTIMx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> \ 3433 (((LPTIMx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (LPTIMx & 0xFFFF0000UL)); 3434 } 3435 3436 /** 3437 * @brief Set Tim Input capture clock source 3438 * @rmtoll CCIPR1 TIMICSEL LL_RCC_SetTIMICClockSource 3439 * @param TIMICSource This parameter can be one of the following combined values: 3440 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_NONE 3441 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256 3442 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV1024 3443 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV4 3444 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV4 3445 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV1024 3446 * @note HSI, MSI and MSIK clocks without division are also available when TIMICSEL[2] is 1. 3447 * @note combination to be avoided : 3448 * LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV1024 and LL_RCC_CLKSOURCE_TIMIC_MSIK_DIV1024 3449 * LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV4 and LL_RCC_CLKSOURCE_TIMIC_MSIK_DIV4 3450 * @retval None 3451 */ LL_RCC_SetTIMICClockSource(uint32_t TIMICSource)3452 __STATIC_INLINE void LL_RCC_SetTIMICClockSource(uint32_t TIMICSource) 3453 { 3454 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL, TIMICSource); 3455 } 3456 3457 /** 3458 * @brief Get Tim Input capture clock source 3459 * @rmtoll CCIPR1 TIMICSEL LL_RCC_GetTIMICClockSource 3460 * @retval Returned value can be one of the following combined values: 3461 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_NONE 3462 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256 3463 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV1024 3464 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV4 3465 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV4 3466 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV1024 3467 */ LL_RCC_GetTIMICClockSource(void)3468 __STATIC_INLINE uint32_t LL_RCC_GetTIMICClockSource(void) 3469 { 3470 return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL)); 3471 } 3472 3473 /** 3474 * @brief Get FDCAN kernel clock source 3475 * @rmtoll CCIPR1 FDCANSEL LL_RCC_GetFDCANClockSource 3476 * @param FDCANx This parameter can be one of the following values: 3477 * @arg @ref LL_RCC_FDCAN_CLKSOURCE 3478 * @retval Returned value can be one of the following values: 3479 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE 3480 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1 3481 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2 3482 */ LL_RCC_GetFDCANClockSource(uint32_t FDCANx)3483 __STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx) 3484 { 3485 return (uint32_t)(READ_BIT(RCC->CCIPR1, FDCANx)); 3486 } 3487 3488 /** 3489 * @brief Get SAIx clock source 3490 * @rmtoll CCIPR2 SAI1SEL LL_RCC_GetSAIClockSource\n 3491 * CCIPR2 SAI2SEL LL_RCC_GetSAIClockSource 3492 * @param SAIx This parameter can be one of the following values: 3493 * @arg @ref LL_RCC_SAI1_CLKSOURCE 3494 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*) 3495 * @retval Returned value can be one of the following values: 3496 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1 3497 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2 3498 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3 3499 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN 3500 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI 3501 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1 (*) 3502 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2 (*) 3503 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3 (*) 3504 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*) 3505 * @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI (*) 3506 * 3507 * (*) Availability depends on devices. 3508 */ LL_RCC_GetSAIClockSource(uint32_t SAIx)3509 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) 3510 { 3511 return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) | (SAIx << 16U)); 3512 } 3513 3514 /** 3515 * @brief Get SDMMCx kernel clock source 3516 * @rmtoll CCIPR2 SDMMCSEL LL_RCC_GetSDMMCKernelClockSource 3517 * @param SDMMCx This parameter can be one of the following values: 3518 * @arg @ref LL_RCC_SDMMC_KERNELCLKSOURCE 3519 * @retval Returned value can be one of the following values: 3520 * @arg @ref LL_RCC_SDMMC12_KERNELCLKSOURCE_48CLK 3521 * @arg @ref LL_RCC_SDMMC12_KERNELCLKSOURCE_PLL1 "P" 3522 */ LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx)3523 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx) 3524 { 3525 return (uint32_t)(READ_BIT(RCC->CCIPR2, SDMMCx)); 3526 } 3527 3528 /** 3529 * @brief Get SDMMC1/2 clock source 3530 * @rmtoll CCIPR1 ICLKSEL LL_RCC_GetSDMMCClockSource 3531 * @param SDMMCx This parameter can be one of the following values: 3532 * @arg @ref LL_RCC_SDMMC_CLKSOURCE 3533 * @retval Returned value can be one of the following values: 3534 * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_HSI48 3535 * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL1 3536 * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL2 3537 * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_MSIK 3538 */ LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)3539 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx) 3540 { 3541 return (uint32_t)(READ_BIT(RCC->CCIPR1, SDMMCx)); 3542 } 3543 3544 /** 3545 * @brief Get RNGx clock source 3546 * @rmtoll CCIPR2 RNGSEL LL_RCC_GetRNGClockSource 3547 * @param RNGx This parameter can be one of the following values: 3548 * @arg @ref LL_RCC_RNG_CLKSOURCE 3549 * @retval Returned value can be one of the following values: 3550 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 3551 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48_DIV2 3552 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI 3553 */ LL_RCC_GetRNGClockSource(uint32_t RNGx)3554 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) 3555 { 3556 return (uint32_t)(READ_BIT(RCC->CCIPR2, RNGx)); 3557 } 3558 3559 #if defined(RCC_CCIPR2_USBPHYCSEL) 3560 /** 3561 * @brief Get USBPHYx clock source 3562 * @rmtoll CCIPR2 USBPHYCSEL LL_RCC_GetUSBPHYClockSource 3563 * @param USBPHYx This parameter can be one of the following values: 3564 * @arg @ref LL_RCC_USBPHY_CLKSOURCE 3565 * @retval Returned value can be one of the following values: 3566 * @arg @ref LL_RCC_USBPHYCLKSOURCE_HSE 3567 * @arg @ref LL_RCC_USBPHYCLKSOURCE_HSE_DIV2 3568 * @arg @ref LL_RCC_USBPHYCLKSOURCE_PLL1 3569 * @arg @ref LL_RCC_USBPHYCLKSOURCE_PLL1_DIV2 3570 */ LL_RCC_GetUSBPHYClockSource(uint32_t USBPHYx)3571 __STATIC_INLINE uint32_t LL_RCC_GetUSBPHYClockSource(uint32_t USBPHYx) 3572 { 3573 return (uint32_t)(READ_BIT(RCC->CCIPR2, USBPHYx)); 3574 } 3575 #endif /* RCC_CCIPR2_USBPHYCSEL */ 3576 3577 /** 3578 * @brief Get USBx clock source 3579 * @rmtoll CCIPR1 ICLKSEL LL_RCC_GetUSBClockSource 3580 * @param USBx This parameter can be one of the following values: 3581 * @arg @ref LL_RCC_USB_CLKSOURCE 3582 * @retval Returned value can be one of the following values: 3583 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 3584 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1 3585 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL2 3586 * @arg @ref LL_RCC_USB_CLKSOURCE_MSIK 3587 */ LL_RCC_GetUSBClockSource(uint32_t USBx)3588 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) 3589 { 3590 return (uint32_t)(READ_BIT(RCC->CCIPR1, USBx)); 3591 } 3592 3593 /** 3594 * @brief Get ADCx clock source 3595 * @rmtoll CCIPR3 ADCDACSEL LL_RCC_SetADCDACClockSource 3596 * @param ADCxDAC1 This parameter can be one of the following values: 3597 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE 3598 * @retval Returned value can be one of the following values: 3599 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HCLK 3600 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_SYSCLK 3601 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_PLL2 3602 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_MSIK 3603 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSE 3604 */ LL_RCC_GetADCDACClockSource(uint32_t ADCxDAC1)3605 __STATIC_INLINE uint32_t LL_RCC_GetADCDACClockSource(uint32_t ADCxDAC1) 3606 { 3607 return (uint32_t)(READ_BIT(RCC->CCIPR3, ADCxDAC1)); 3608 } 3609 3610 /** 3611 * @brief Get DFSDM Audio Clock Source 3612 * @rmtoll CCIPR3 ADF1SEL LL_RCC_GetADF1ClockSource 3613 * @param ADF1x This parameter can be one of the following values: 3614 * @arg @ref LL_RCC_ADF1_CLKSOURCE 3615 * @retval Returned value can be one of the following values: 3616 * @arg @ref LL_RCC_ADF1_CLKSOURCE_HCLK 3617 * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL1 3618 * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL3 3619 * @arg @ref LL_RCC_ADF1_CLKSOURCE_MSIK 3620 * @arg @ref LL_RCC_ADF1_CLKSOURCE_PIN 3621 */ LL_RCC_GetADF1ClockSource(uint32_t ADF1x)3622 __STATIC_INLINE uint32_t LL_RCC_GetADF1ClockSource(uint32_t ADF1x) 3623 { 3624 return (uint32_t)(READ_BIT(RCC->CCIPR3, ADF1x)); 3625 } 3626 3627 /** 3628 * @brief Get DAC1 Clock Source 3629 * @rmtoll CCIPR3 DAC1SEL LL_RCC_GetDAC1ClockSource 3630 * @param DAC1x This parameter can be one of the following values: 3631 * @arg @ref LL_RCC_DAC1_CLKSOURCE 3632 * @retval Returned value can be one of the following values: 3633 * @arg @ref LL_RCC_DAC1_CLKSOURCE_LSE 3634 * @arg @ref LL_RCC_DAC1_CLKSOURCE_LSI 3635 */ LL_RCC_GetDAC1ClockSource(uint32_t DAC1x)3636 __STATIC_INLINE uint32_t LL_RCC_GetDAC1ClockSource(uint32_t DAC1x) 3637 { 3638 return (uint32_t)(READ_BIT(RCC->CCIPR3, DAC1x)); 3639 } 3640 3641 /** 3642 * @brief Get MDF1 Clock Source 3643 * @rmtoll CCIPR2 MDF1SEL LL_RCC_GetMDF1ClockSource 3644 * @param MDF1x This parameter can be one of the following values: 3645 * @arg @ref LL_RCC_MDF1_CLKSOURCE 3646 * @retval Returned value can be one of the following values: 3647 * @arg @ref LL_RCC_MDF1_CLKSOURCE_HCLK 3648 * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL1 3649 * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL3 3650 * @arg @ref LL_RCC_MDF1_CLKSOURCE_MSIK 3651 * @arg @ref LL_RCC_MDF1_CLKSOURCE_PIN 3652 */ LL_RCC_GetMDF1ClockSource(uint32_t MDF1x)3653 __STATIC_INLINE uint32_t LL_RCC_GetMDF1ClockSource(uint32_t MDF1x) 3654 { 3655 return (uint32_t)(READ_BIT(RCC->CCIPR2, MDF1x)); 3656 } 3657 3658 /** 3659 * @brief Get OCTOSPI clock source 3660 * @rmtoll CCIPR2 OSPISEL LL_RCC_GetOCTOSPIClockSource 3661 * @param OCTOSPIx This parameter can be one of the following values: 3662 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE 3663 * @retval Returned value can be one of the following values: 3664 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 3665 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSIK 3666 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL1 3667 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL2 3668 */ LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx)3669 __STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx) 3670 { 3671 return (uint32_t)(READ_BIT(RCC->CCIPR2, OCTOSPIx)); 3672 } 3673 3674 #if defined (HSPI1) 3675 /** 3676 * @brief Get HSPI clock source 3677 * @rmtoll CCIPR2 HSPISEL LL_RCC_GetHSPIClockSource 3678 * @param HSPIx This parameter can be one of the following values: 3679 * @arg @ref LL_RCC_HSPI_CLKSOURCE 3680 * @retval Returned value can be one of the following values: 3681 * @arg @ref LL_RCC_HSPI_CLKSOURCE_SYSCLK 3682 * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL1 3683 * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL2 3684 * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL3 3685 */ LL_RCC_GetHSPIClockSource(uint32_t HSPIx)3686 __STATIC_INLINE uint32_t LL_RCC_GetHSPIClockSource(uint32_t HSPIx) 3687 { 3688 return (uint32_t)(READ_BIT(RCC->CCIPR2, HSPIx)); 3689 } 3690 #endif /* HSPI1 */ 3691 /** 3692 * @} 3693 */ 3694 3695 #if defined(SAES) 3696 /** 3697 * @brief Get SAES kernel clock source 3698 * @rmtoll CCIPR2 SAESSEL LL_RCC_GetSAESClockSource 3699 * @param SAESx This parameter can be one of the following values: 3700 * @arg @ref LL_RCC_SAES_CLKSOURCE 3701 * @retval Returned value can be one of the following values: 3702 * @arg @ref LL_RCC_SAES_CLKSOURCE_SHSI 3703 * @arg @ref LL_RCC_SAES_CLKSOURCE_SHSI_DIV2 3704 */ LL_RCC_GetSAESClockSource(uint32_t SAESx)3705 __STATIC_INLINE uint32_t LL_RCC_GetSAESClockSource(uint32_t SAESx) 3706 { 3707 return (uint32_t)(READ_BIT(RCC->CCIPR2, SAESx)); 3708 } 3709 #endif /* SAES */ 3710 3711 #if defined(DSI) 3712 /** 3713 * @brief Get DSI clock source 3714 * @rmtoll CCIPR2 DSISEL LL_RCC_GetDSIClockSource 3715 * @param DSIx This parameter can be one of the following values: 3716 * @arg @ref LL_RCC_DSI_CLKSOURCE 3717 * @retval Returned value can be one of the following values: 3718 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY 3719 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL3 3720 */ LL_RCC_GetDSIClockSource(uint32_t DSIx)3721 __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx) 3722 { 3723 return (uint32_t)(READ_BIT(RCC->CCIPR2, DSIx)); 3724 } 3725 #endif /* DSI */ 3726 3727 #if defined(LTDC) 3728 /** 3729 * @brief Get LTDC clock source 3730 * @rmtoll CCIPR2 LTDCSEL LL_RCC_GetLTDCClockSource 3731 * @param LTDCx This parameter can be one of the following values: 3732 * @arg @ref LL_RCC_LTDC_CLKSOURCE 3733 * @retval Returned value can be one of the following values: 3734 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL2 3735 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL3 3736 */ LL_RCC_GetLTDCClockSource(uint32_t LTDCx)3737 __STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t LTDCx) 3738 { 3739 return (uint32_t)(READ_BIT(RCC->CCIPR2, LTDCx)); 3740 } 3741 #endif /* LTDC */ 3742 3743 /** @defgroup RCC_LL_EF_RTC RTC 3744 * @{ 3745 */ 3746 3747 /** 3748 * @brief Set RTC Clock Source 3749 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless 3750 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is 3751 * set). The BDRST bit can be used to reset them. 3752 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource 3753 * @param Source This parameter can be one of the following values: 3754 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE 3755 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE 3756 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI 3757 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 3758 * @retval None 3759 */ LL_RCC_SetRTCClockSource(uint32_t Source)3760 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) 3761 { 3762 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); 3763 } 3764 3765 /** 3766 * @brief Get RTC Clock Source 3767 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource 3768 * @retval Returned value can be one of the following values: 3769 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE 3770 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE 3771 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI 3772 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 3773 */ LL_RCC_GetRTCClockSource(void)3774 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) 3775 { 3776 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); 3777 } 3778 3779 /** 3780 * @brief Enable RTC 3781 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC 3782 * @retval None 3783 */ LL_RCC_EnableRTC(void)3784 __STATIC_INLINE void LL_RCC_EnableRTC(void) 3785 { 3786 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); 3787 } 3788 3789 /** 3790 * @brief Disable RTC 3791 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC 3792 * @retval None 3793 */ LL_RCC_DisableRTC(void)3794 __STATIC_INLINE void LL_RCC_DisableRTC(void) 3795 { 3796 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); 3797 } 3798 3799 /** 3800 * @brief Check if RTC has been enabled or not 3801 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC 3802 * @retval State of bit (1 or 0). 3803 */ LL_RCC_IsEnabledRTC(void)3804 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) 3805 { 3806 return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == RCC_BDCR_RTCEN) ? 1UL : 0UL); 3807 } 3808 3809 /** 3810 * @brief Force the Backup domain reset 3811 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset 3812 * @retval None 3813 */ LL_RCC_ForceBackupDomainReset(void)3814 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) 3815 { 3816 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); 3817 } 3818 3819 /** 3820 * @brief Release the Backup domain reset 3821 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset 3822 * @retval None 3823 */ LL_RCC_ReleaseBackupDomainReset(void)3824 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) 3825 { 3826 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); 3827 } 3828 3829 /** 3830 * @} 3831 */ 3832 3833 3834 /** @defgroup RCC_LL_EF_PLL1 PLL1 3835 * @{ 3836 */ 3837 3838 /** 3839 * @brief Enable PLL1 3840 * @rmtoll CR PLL1ON LL_RCC_PLL1_Enable 3841 * @retval None 3842 */ LL_RCC_PLL1_Enable(void)3843 __STATIC_INLINE void LL_RCC_PLL1_Enable(void) 3844 { 3845 SET_BIT(RCC->CR, RCC_CR_PLL1ON); 3846 } 3847 #define LL_RCC_PLL_Enable LL_RCC_PLL1_Enable /*!< alias for compatibility with legacy code */ 3848 3849 /** 3850 * @brief Disable PLL1 3851 * @note Cannot be disabled if the PLL1 clock is used as the system clock 3852 * @rmtoll CR PLLON LL_RCC_PLL1_Disable 3853 * @retval None 3854 */ LL_RCC_PLL1_Disable(void)3855 __STATIC_INLINE void LL_RCC_PLL1_Disable(void) 3856 { 3857 CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON); 3858 } 3859 #define LL_RCC_PLL_Disable LL_RCC_PLL1_Disable /*!< alias for compatibility with legacy code */ 3860 3861 /** 3862 * @brief Check if PLL1 Ready 3863 * @rmtoll CR PLL1RDY LL_RCC_PLL1_IsReady 3864 * @retval State of bit (1 or 0). 3865 */ LL_RCC_PLL1_IsReady(void)3866 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void) 3867 { 3868 return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == RCC_CR_PLL1RDY) ? 1UL : 0UL); 3869 } 3870 #define LL_RCC_PLL_IsReady LL_RCC_PLL1_IsReady /*!< alias for compatibility with legacy code */ 3871 3872 /** 3873 * @brief Configure PLL1 used for SYSCLK Domain 3874 * @note PLL1 Source, PLLM, PLLN and PLLR can be written only when PLL1 is disabled. 3875 * @note PLLN/PLLR can be written only when PLL is disabled. 3876 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_SYS\n 3877 * PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_SYS\n 3878 * PLL1CFGR PLL1N LL_RCC_PLL1_ConfigDomain_SYS\n 3879 * PLL1CFGR PLL1R LL_RCC_PLL1_ConfigDomain_SYS 3880 * @param Source This parameter can be one of the following values: 3881 * @arg @ref LL_RCC_PLL1SOURCE_NONE 3882 * @arg @ref LL_RCC_PLL1SOURCE_MSIS 3883 * @arg @ref LL_RCC_PLL1SOURCE_HSI 3884 * @arg @ref LL_RCC_PLL1SOURCE_HSE 3885 * @param PLLM parameter can be a value between 1 and 16 3886 * @param PLLR parameter can be a value between 1 and 128 (Only division by 1 and even division are allowed) 3887 * @param PLLN parameter can be a value between 4 and 512 3888 * @retval None 3889 */ LL_RCC_PLL1_ConfigDomain_SYS(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)3890 __STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 3891 { 3892 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | \ 3893 ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos)); 3894 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1R, ((PLLN - 1UL) << \ 3895 RCC_PLL1DIVR_PLL1N_Pos) | ((PLLR - 1UL) << \ 3896 RCC_PLL1DIVR_PLL1R_Pos)); 3897 } 3898 #define LL_RCC_PLL_ConfigDomain_SYS LL_RCC_PLL1_ConfigDomain_SYS /*!< alias for compatibility with legacy code */ 3899 3900 /** 3901 * @brief Configure PLL1 used for SAI domain clock 3902 * @note PLL1 Source, PLLM, PLLN and PLLPDIV can be written only when PLL1 is disabled. 3903 * @note This can be selected for SAI1 or SAI2 3904 * @rmtoll PLLC1FGR PLL1SRC LL_RCC_PLL1_ConfigDomain_SAI\n 3905 * PLLC1FGR PLL1M LL_RCC_PLL1_ConfigDomain_SAI\n 3906 * PLLC1FGR PLL1N LL_RCC_PLL1_ConfigDomain_SAI\n 3907 * PLLC1FGR PLL1P LL_RCC_PLL1_ConfigDomain_SAI 3908 * @param Source This parameter can be one of the following values: 3909 * @arg @ref LL_RCC_PLL1SOURCE_NONE 3910 * @arg @ref LL_RCC_PLL1SOURCE_MSIS 3911 * @arg @ref LL_RCC_PLL1SOURCE_HSI 3912 * @arg @ref LL_RCC_PLL1SOURCE_HSE 3913 * @param PLLM parameter can be a value between 1 and 16 3914 * @param PLLN parameter can be a value between 4 and 512 3915 * @param PLLP parameter can be a value between 1 and 128 3916 * @retval None 3917 */ LL_RCC_PLL1_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)3918 __STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 3919 { 3920 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | \ 3921 ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos)); 3922 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1P, ((PLLN - 1UL) << \ 3923 RCC_PLL1DIVR_PLL1N_Pos) | ((PLLP - 1UL) << \ 3924 RCC_PLL1DIVR_PLL1P_Pos)); 3925 } 3926 #define LL_RCC_PLL_ConfigDomain_SAI LL_RCC_PLL1_ConfigDomain_SAI /*!< alias for compatibility with legacy code */ 3927 3928 /** 3929 * @brief Configure PLL1 used for 48Mhz domain clock 3930 * @note PLL1 Source, PLLM, PLLN and PLLQ can be written only when PLL1 is disabled. 3931 * @note This can be selected for USB, SDMMC 3932 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_48M\n 3933 * PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_48M\n 3934 * PLL1CFGR PLL1N LL_RCC_PLL1_ConfigDomain_48M\n 3935 * PLL1CFGR PLL1Q LL_RCC_PLL1_ConfigDomain_48M 3936 * @param Source This parameter can be one of the following values: 3937 * @arg @ref LL_RCC_PLL1SOURCE_NONE 3938 * @arg @ref LL_RCC_PLL1SOURCE_MSIS 3939 * @arg @ref LL_RCC_PLL1SOURCE_HSI 3940 * @arg @ref LL_RCC_PLL1SOURCE_HSE 3941 * @param PLLM parameter can be a value between 1 and 16 3942 * @param PLLN parameter can be a value between 4 and 512 3943 * @param PLLQ parameter can be a value between 1 and 128 3944 * @retval None 3945 */ LL_RCC_PLL1_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)3946 __STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) 3947 { 3948 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | \ 3949 ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos)); 3950 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1Q, ((PLLN - 1UL) << \ 3951 RCC_PLL1DIVR_PLL1N_Pos) | ((PLLQ - 1UL) << \ 3952 RCC_PLL1DIVR_PLL1Q_Pos)); 3953 } 3954 #define LL_RCC_PLL_ConfigDomain_48M LL_RCC_PLL1_ConfigDomain_48M /*!< alias for compatibility with legacy code */ 3955 3956 /** 3957 * @brief Configure PLL clock source 3958 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_SetMainSource 3959 * @param PLL1Source This parameter can be one of the following values: 3960 * @arg @ref LL_RCC_PLL1SOURCE_NONE 3961 * @arg @ref LL_RCC_PLL1SOURCE_MSIS 3962 * @arg @ref LL_RCC_PLL1SOURCE_HSI 3963 * @arg @ref LL_RCC_PLL1SOURCE_HSE 3964 * @retval None 3965 */ LL_RCC_PLL1_SetMainSource(uint32_t PLL1Source)3966 __STATIC_INLINE void LL_RCC_PLL1_SetMainSource(uint32_t PLL1Source) 3967 { 3968 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, PLL1Source); 3969 } 3970 #define LL_RCC_PLL_SetMainSource LL_RCC_PLL1_SetMainSource /*!< alias for compatibility with legacy code */ 3971 3972 /** 3973 * @brief Get the oscillator used as PLL1 clock source. 3974 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_GetMainSource 3975 * @retval Returned value can be one of the following values: 3976 * @arg @ref LL_RCC_PLL1SOURCE_NONE 3977 * @arg @ref LL_RCC_PLL1SOURCE_MSIS 3978 * @arg @ref LL_RCC_PLL1SOURCE_HSI 3979 * @arg @ref LL_RCC_PLL1SOURCE_HSE 3980 */ LL_RCC_PLL1_GetMainSource(void)3981 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetMainSource(void) 3982 { 3983 return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC)); 3984 } 3985 #define LL_RCC_PLL_GetMainSource LL_RCC_PLL1_GetMainSource /*!< alias for compatibility with legacy code */ 3986 3987 /** 3988 * @brief Set Main PLL1 multiplication factor for VCO 3989 * @rmtoll PLL1CFGR PLL1N LL_RCC_PLL1_SetN 3990 * @param PLL1N parameter can be a value between 4 and 512 3991 */ LL_RCC_PLL1_SetN(uint32_t PLL1N)3992 __STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t PLL1N) 3993 { 3994 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N, (PLL1N - 1UL) << RCC_PLL1DIVR_PLL1N_Pos); 3995 } 3996 #define LL_RCC_PLL_SetN LL_RCC_PLL1_SetN /*!< alias for compatibility with legacy code */ 3997 3998 /** 3999 * @brief Get Main PLL1 multiplication factor for VCO 4000 * @rmtoll PLL1CFGR PLL1N LL_RCC_PLL1_GetN 4001 * @retval Between 4 and 512 4002 */ LL_RCC_PLL1_GetN(void)4003 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void) 4004 { 4005 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1UL); 4006 } 4007 #define LL_RCC_PLL_GetN LL_RCC_PLL1_GetN /*!< alias for compatibility with legacy code */ 4008 4009 /** 4010 * @brief Set Main PLL1 division factor for PLL1P 4011 * @note Used for SAI1 and SAI2 clock 4012 * @rmtoll PLL1CFGR PLL1P LL_RCC_PLL1_SetP 4013 * @param PLL1P parameter can be a value between 1 and 128 4014 */ LL_RCC_PLL1_SetP(uint32_t PLL1P)4015 __STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t PLL1P) 4016 { 4017 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P, (PLL1P - 1UL) << RCC_PLL1DIVR_PLL1P_Pos); 4018 } 4019 #define LL_RCC_PLL_SetP LL_RCC_PLL1_SetP /*!< alias for compatibility with legacy code */ 4020 4021 /** 4022 * @brief Get Main PLL1 division factor for PLL1P 4023 * @note Used for SAI1 and SAI2 clock 4024 * @rmtoll PLL1CFGR PLL1P LL_RCC_PLL1_GetP 4025 * @retval Between 1 and 128 4026 */ LL_RCC_PLL1_GetP(void)4027 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void) 4028 { 4029 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1UL); 4030 } 4031 #define LL_RCC_PLL_GetP LL_RCC_PLL1_GetP /*!< alias for compatibility with legacy code */ 4032 4033 /** 4034 * @brief Set Main PLL division factor for PLLQ 4035 * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock) 4036 * @rmtoll PLLCFGR PLL1Q LL_RCC_PLL1_SetQ 4037 * @param PLL1Q parameter can be a value between 1 and 128 4038 */ LL_RCC_PLL1_SetQ(uint32_t PLL1Q)4039 __STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t PLL1Q) 4040 { 4041 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q, (PLL1Q - 1UL) << RCC_PLL1DIVR_PLL1Q_Pos); 4042 } 4043 #define LL_RCC_PLL_SetQ LL_RCC_PLL1_SetQ /*!< alias for compatibility with legacy code */ 4044 4045 /** 4046 * @brief Get Main PLL division factor for PLLQ 4047 * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock) 4048 * @rmtoll PLL1CFGR PLL1Q LL_RCC_PLL1_GetQ 4049 * @retval Between 1 and 128 4050 */ LL_RCC_PLL1_GetQ(void)4051 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void) 4052 { 4053 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1UL); 4054 } 4055 #define LL_RCC_PLL_GetQ LL_RCC_PLL1_GetQ /*!< alias for compatibility with legacy code */ 4056 4057 /** 4058 * @brief Set Main PLL division factor for PLL1R 4059 * @note Used for PLL1CLK selected for USB, SDMMC (48 MHz clock) 4060 * @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_SetR 4061 * @param PLL1R parameter can be a value between 1 and 128 (Only division by 1 and even division are allowed) 4062 */ LL_RCC_PLL1_SetR(uint32_t PLL1R)4063 __STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t PLL1R) 4064 { 4065 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R, (PLL1R - 1UL) << RCC_PLL1DIVR_PLL1R_Pos); 4066 } 4067 #define LL_RCC_PLL_SetR LL_RCC_PLL1_SetR /*!< alias for compatibility with legacy code */ 4068 4069 /** 4070 * @brief Get Main PLL1 division factor for PLL1R 4071 * @note Used for PLL1CLK (system clock) 4072 * @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_GetR 4073 * @retval Between 1 and 128 4074 */ LL_RCC_PLL1_GetR(void)4075 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void) 4076 { 4077 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1UL); 4078 } 4079 #define LL_RCC_PLL_GetR LL_RCC_PLL1_GetR /*!< alias for compatibility with legacy code */ 4080 4081 /** 4082 * @brief Set Division factor for the main PLL and other PLL 4083 * @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_SetDivider 4084 * @param PLL1M parameter can be a value between 1 and 16 4085 */ LL_RCC_PLL1_SetDivider(uint32_t PLL1M)4086 __STATIC_INLINE void LL_RCC_PLL1_SetDivider(uint32_t PLL1M) 4087 { 4088 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, (PLL1M - 1UL) << RCC_PLL1CFGR_PLL1M_Pos); 4089 } 4090 #define LL_RCC_PLL_SetDivider LL_RCC_PLL1_SetDivider /*!< alias for compatibility with legacy code */ 4091 4092 /** 4093 * @brief Get Division factor for the main PLL and other PLL 4094 * @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_GetDivider 4095 * @retval Between 1 and 16 4096 */ LL_RCC_PLL1_GetDivider(void)4097 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetDivider(void) 4098 { 4099 return (uint32_t)((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1UL); 4100 } 4101 #define LL_RCC_PLL_GetDivider LL_RCC_PLL1_GetDivider /*!< alias for compatibility with legacy code */ 4102 4103 /** 4104 * @brief Enable PLL1 output mapped on SAI domain clock 4105 * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_EnableDomain_SAI 4106 * @retval None 4107 */ LL_RCC_PLL1_EnableDomain_SAI(void)4108 __STATIC_INLINE void LL_RCC_PLL1_EnableDomain_SAI(void) 4109 { 4110 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN); 4111 } 4112 #define LL_RCC_PLL_EnableDomain_SAI LL_RCC_PLL1_EnableDomain_SAI /*!< alias for compatibility with legacy code */ 4113 4114 /** 4115 * @brief Disable PLL1 output mapped on SAI domain clock 4116 * @note Cannot be disabled if the PLL1 clock is used as the system 4117 * clock 4118 * @note In order to save power, when the PLL1CLK of the PLL1 is 4119 * not used, should be 0 4120 * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_DisableDomain_SAI 4121 * @retval None 4122 */ LL_RCC_PLL1_DisableDomain_SAI(void)4123 __STATIC_INLINE void LL_RCC_PLL1_DisableDomain_SAI(void) 4124 { 4125 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN); 4126 } 4127 #define LL_RCC_PLL_DisableDomain_SAI LL_RCC_PLL1_DisableDomain_SAI /*!< alias for compatibility with legacy code */ 4128 4129 /** 4130 * @brief Check if PLL1 output mapped on SAI domain clock is enabled 4131 * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_IsEnabledDomain_SAI 4132 * @retval State of bit (1 or 0). 4133 */ LL_RCC_PLL1_IsEnabledDomain_SAI(void)4134 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_SAI(void) 4135 { 4136 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN) == (RCC_PLL1CFGR_PLL1PEN)) ? 1UL : 0UL); 4137 } 4138 #define LL_RCC_PLL_IsEnabledDomain_SAI LL_RCC_PLL1_IsEnabledDomain_SAI /*!< alias for compatibility with legacy code */ 4139 4140 /** 4141 * @brief Enable PLL output mapped on 48MHz domain clock 4142 * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_EnableDomain_48M 4143 * @retval None 4144 */ LL_RCC_PLL1_EnableDomain_48M(void)4145 __STATIC_INLINE void LL_RCC_PLL1_EnableDomain_48M(void) 4146 { 4147 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN); 4148 } 4149 4150 /** 4151 * @brief Disable PLL1 output mapped on 48MHz domain clock 4152 * @note Cannot be disabled if the PLL clock is used as the system 4153 * clock 4154 * @note In order to save power, when the PLL1CLK of the PLL1 is 4155 * not used, should be 0 4156 * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_DisableDomain_48M 4157 * @retval None 4158 */ LL_RCC_PLL1_DisableDomain_48M(void)4159 __STATIC_INLINE void LL_RCC_PLL1_DisableDomain_48M(void) 4160 { 4161 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN); 4162 } 4163 #define LL_RCC_PLL_DisableDomain_48M LL_RCC_PLL1_DisableDomain_48M /*!< alias for compatibility with legacy code */ 4164 4165 /** 4166 * @brief Check if PLL1 output mapped on 48M domain clock is enabled 4167 * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_IsEnabledDomain_48M 4168 * @retval State of bit (1 or 0). 4169 */ LL_RCC_PLL1_IsEnabledDomain_48M(void)4170 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_48M(void) 4171 { 4172 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN) == (RCC_PLL1CFGR_PLL1QEN)) ? 1UL : 0UL); 4173 } 4174 #define LL_RCC_PLL_IsEnabledDomain_48M LL_RCC_PLL1_IsEnabledDomain_48M /*!< alias for compatibility with legacy code */ 4175 4176 /** 4177 * @brief Enable PLL1 output mapped on SYSCLK domain 4178 * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_EnableDomain_SYS 4179 * @retval None 4180 */ LL_RCC_PLL1_EnableDomain_SYS(void)4181 __STATIC_INLINE void LL_RCC_PLL1_EnableDomain_SYS(void) 4182 { 4183 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN); 4184 } 4185 #define LL_RCC_PLL_EnableDomain_SYS LL_RCC_PLL1_EnableDomain_SYS /*!< alias for compatibility with legacy code */ 4186 4187 /** 4188 * @brief Disable PLL1 output mapped on SYSCLK domain 4189 * @note Cannot be disabled if the PLL1 clock is used as the system 4190 * clock 4191 * @note In order to save power, when the PLL1CLK of the PLL1 is 4192 * not used, Main PLL1 should be 0 4193 * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_DisableDomain_SYS 4194 * @retval None 4195 */ LL_RCC_PLL1_DisableDomain_SYS(void)4196 __STATIC_INLINE void LL_RCC_PLL1_DisableDomain_SYS(void) 4197 { 4198 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN); 4199 } 4200 #define LL_RCC_PLL_DisableDomain_SYS LL_RCC_PLL1_DisableDomain_SYS /*!< alias for compatibility with legacy code */ 4201 4202 /** 4203 * @brief Check if PLL1 output mapped on SYS domain clock is enabled 4204 * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_IsEnabledDomain_SYS 4205 * @retval State of bit (1 or 0). 4206 */ LL_RCC_PLL1_IsEnabledDomain_SYS(void)4207 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_SYS(void) 4208 { 4209 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN) == (RCC_PLL1CFGR_PLL1REN)) ? 1UL : 0UL); 4210 } 4211 #define LL_RCC_PLL_IsEnabledDomain_SYS LL_RCC_PLL1_IsEnabledDomain_SYS /*!< alias for compatibility with legacy code */ 4212 4213 /** 4214 * @brief Enable PLL1 FRACN 4215 * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable 4216 * @retval None 4217 */ LL_RCC_PLL1FRACN_Enable(void)4218 __STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void) 4219 { 4220 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN); 4221 } 4222 #define LL_RCC_PLLFRACN_Enable LL_RCC_PLL1FRACN_Enable /*!< alias for compatibility with legacy code */ 4223 4224 /** 4225 * @brief Check if PLL1 FRACN is enabled 4226 * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_IsEnabled 4227 * @retval State of bit (1 or 0). 4228 */ LL_RCC_PLL1FRACN_IsEnabled(void)4229 __STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void) 4230 { 4231 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) == RCC_PLL1CFGR_PLL1FRACEN) ? 1UL : 0UL); 4232 } 4233 #define LL_RCC_PLLFRACN_IsEnabled LL_RCC_PLL1FRACN_IsEnabled /*!< alias for compatibility with legacy code */ 4234 4235 /** 4236 * @brief Disable PLL1 FRACN 4237 * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Disable 4238 * @retval None 4239 */ LL_RCC_PLL1FRACN_Disable(void)4240 __STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void) 4241 { 4242 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN); 4243 } 4244 #define LL_RCC_PLLFRACN_Disable LL_RCC_PLL1FRACN_Disable /*!< alias for compatibility with legacy code */ 4245 4246 /** 4247 * @brief Set PLL1 FRACN Coefficient 4248 * @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_SetFRACN 4249 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) 4250 */ LL_RCC_PLL1_SetFRACN(uint32_t FRACN)4251 __STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN) 4252 { 4253 MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN, FRACN << RCC_PLL1FRACR_PLL1FRACN_Pos); 4254 } 4255 #define LL_RCC_PLL_SetFRACN LL_RCC_PLL1_SetFRACN /*!< alias for compatibility with legacy code */ 4256 4257 /** 4258 * @brief Get PLL1 FRACN Coefficient 4259 * @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_GetFRACN 4260 * @retval A value between 0 and 8191 (0x1FFF) 4261 */ LL_RCC_PLL1_GetFRACN(void)4262 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void) 4263 { 4264 return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN) >> RCC_PLL1FRACR_PLL1FRACN_Pos); 4265 } 4266 #define LL_RCC_PLL_GetFRACN LL_RCC_PLL1_GetFRACN /*!< alias for compatibility with legacy code */ 4267 4268 /** 4269 * @brief Set PLL1 VCO Input Range 4270 * @note This API shall be called only when PLL1 is disabled. 4271 * @rmtoll PLL1CFGR PLL1RGE LL_RCC_PLL1_SetVCOInputRange 4272 * @param InputRange This parameter can be one of the following values: 4273 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 4274 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 4275 * @retval None 4276 */ LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)4277 __STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange) 4278 { 4279 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, InputRange); 4280 } 4281 #define LL_RCC_PLL_SetVCOInputRange LL_RCC_PLL1_SetVCOInputRange /*!< alias for compatibility with legacy code */ 4282 4283 /** 4284 * @brief Set PLL1 EPOD Prescaler booster input clock 4285 * @rmtoll PLL1CFGR PLL1MBOOST LL_RCC_SetPll1EPodPrescaler 4286 * @param BoostDiv This parameter can be one of the following values: 4287 * @arg @ref LL_RCC_PLL1MBOOST_DIV_1 4288 * @arg @ref LL_RCC_PLL1MBOOST_DIV_2 4289 * @arg @ref LL_RCC_PLL1MBOOST_DIV_4 4290 * @arg @ref LL_RCC_PLL1MBOOST_DIV_6 4291 * @arg @ref LL_RCC_PLL1MBOOST_DIV_8 4292 * @arg @ref LL_RCC_PLL1MBOOST_DIV_10 4293 * @arg @ref LL_RCC_PLL1MBOOST_DIV_12 4294 * @arg @ref LL_RCC_PLL1MBOOST_DIV_14 4295 * @arg @ref LL_RCC_PLL1MBOOST_DIV_16 4296 */ LL_RCC_SetPll1EPodPrescaler(uint32_t BoostDiv)4297 __STATIC_INLINE void LL_RCC_SetPll1EPodPrescaler(uint32_t BoostDiv) 4298 { 4299 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1MBOOST, BoostDiv); 4300 } 4301 4302 /** 4303 * @brief Get PLL1 EPOD Prescaler booster input clock 4304 * @rmtoll PLL1CFGR PLL1MBOOST LL_RCC_GetPll1EPodPrescaler 4305 * @retval Returned value can be one of the following values: 4306 * @arg @ref LL_RCC_PLL1MBOOST_DIV_1 4307 * @arg @ref LL_RCC_PLL1MBOOST_DIV_2 4308 * @arg @ref LL_RCC_PLL1MBOOST_DIV_4 4309 * @arg @ref LL_RCC_PLL1MBOOST_DIV_6 4310 * @arg @ref LL_RCC_PLL1MBOOST_DIV_8 4311 * @arg @ref LL_RCC_PLL1MBOOST_DIV_10 4312 * @arg @ref LL_RCC_PLL1MBOOST_DIV_12 4313 * @arg @ref LL_RCC_PLL1MBOOST_DIV_14 4314 * @arg @ref LL_RCC_PLL1MBOOST_DIV_16 4315 */ LL_RCC_GetPll1EPodPrescaler(void)4316 __STATIC_INLINE uint32_t LL_RCC_GetPll1EPodPrescaler(void) 4317 { 4318 return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1MBOOST)); 4319 } 4320 4321 /** 4322 * @} 4323 */ 4324 4325 /** @defgroup RCC_LL_EF_PLL2 PLL2 4326 * @{ 4327 */ 4328 4329 /** 4330 * @brief Enable PLL2 4331 * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable 4332 * @retval None 4333 */ LL_RCC_PLL2_Enable(void)4334 __STATIC_INLINE void LL_RCC_PLL2_Enable(void) 4335 { 4336 SET_BIT(RCC->CR, RCC_CR_PLL2ON); 4337 } 4338 4339 /** 4340 * @brief Disable PLL2 4341 * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable 4342 * @retval None 4343 */ LL_RCC_PLL2_Disable(void)4344 __STATIC_INLINE void LL_RCC_PLL2_Disable(void) 4345 { 4346 CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); 4347 } 4348 4349 /** 4350 * @brief Check if PLL2 Ready 4351 * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady 4352 * @retval State of bit (1 or 0). 4353 */ LL_RCC_PLL2_IsReady(void)4354 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void) 4355 { 4356 return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == RCC_CR_PLL2RDY) ? 1UL : 0UL); 4357 } 4358 4359 /** 4360 * @brief Configure PLL2 used for 48Mhz domain clock 4361 * @note PLL2 Source, PLLM, PLLN and PLLQ can be written only when PLL2 is disabled. 4362 * @note This can be selected for USB, SDMMC 4363 * @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_ConfigDomain_48M\n 4364 * PLL2CFGR PLL2M LL_RCC_PLL2_ConfigDomain_48M\n 4365 * PLL2CFGR PLL2N LL_RCC_PLL2_ConfigDomain_48M\n 4366 * PLL2CFGR PLL2Q LL_RCC_PLL2_ConfigDomain_48M 4367 * @param Source This parameter can be one of the following values: 4368 * @arg @ref LL_RCC_PLL2SOURCE_NONE 4369 * @arg @ref LL_RCC_PLL2SOURCE_MSIS 4370 * @arg @ref LL_RCC_PLL2SOURCE_HSI 4371 * @arg @ref LL_RCC_PLL2SOURCE_HSE 4372 * @param PLLM parameter can be a value between 1 and 16 4373 * @param PLLN parameter can be a value between 4 and 512 4374 * @param PLLQ parameter can be a value between 1 and 128 4375 * @retval None 4376 */ LL_RCC_PLL2_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)4377 __STATIC_INLINE void LL_RCC_PLL2_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) 4378 { 4379 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC | RCC_PLL2CFGR_PLL2M, Source | \ 4380 ((PLLM - 1UL) << RCC_PLL2CFGR_PLL2M_Pos)); 4381 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N | RCC_PLL2DIVR_PLL2Q, ((PLLN - 1UL) << \ 4382 RCC_PLL2DIVR_PLL2N_Pos) | ((PLLQ - 1UL) << \ 4383 RCC_PLL2DIVR_PLL2Q_Pos)); 4384 } 4385 4386 /** 4387 * @brief Configure PLL2 used for SAI domain clock 4388 * @note PLL1 Source, PLLM, PLLN and PLL2P can be written only when PLL1 is disabled. 4389 * @note This can be selected for SAI1 or SAI2 4390 * @rmtoll PLLC2FGR PLL2SRC LL_RCC_PLL2_ConfigDomain_SAI\n 4391 * PLLC2FGR PLL2M LL_RCC_PLL2_ConfigDomain_SAI\n 4392 * PLLC2FGR PLL2N LL_RCC_PLL2_ConfigDomain_SAI\n 4393 * PLLC2FGR PLL2P LL_RCC_PLL2_ConfigDomain_SAI 4394 * @param Source This parameter can be one of the following values: 4395 * @arg @ref LL_RCC_PLL2SOURCE_NONE 4396 * @arg @ref LL_RCC_PLL2SOURCE_MSIS 4397 * @arg @ref LL_RCC_PLL2SOURCE_HSI 4398 * @arg @ref LL_RCC_PLL2SOURCE_HSE 4399 * @param PLLM parameter can be a value between 1 and 16 4400 * @param PLLN parameter can be a value between 4 and 512 4401 * @param PLLP parameter can be a value between 1 and 128 4402 * @retval None 4403 */ LL_RCC_PLL2_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)4404 __STATIC_INLINE void LL_RCC_PLL2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 4405 { 4406 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC | RCC_PLL2CFGR_PLL2M, Source | \ 4407 ((PLLM - 1UL) << RCC_PLL2CFGR_PLL2M_Pos)); 4408 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N | RCC_PLL2DIVR_PLL2P, ((PLLN - 1UL) << \ 4409 RCC_PLL2DIVR_PLL2N_Pos) | ((PLLP - 1UL) << \ 4410 RCC_PLL2DIVR_PLL2P_Pos)); 4411 } 4412 4413 /** 4414 * @brief Configure PLL2 used for ADC domain clock 4415 * @note PLL2SRC/PLL2M/PLL2N/PLL2R can be written only when PLL2 is disabled. 4416 * @note This can be selected for ADC 4417 * @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_ConfigDomain_ADC\n 4418 * PLL2CFGR PLL2M LL_RCC_PLL2_ConfigDomain_ADC\n 4419 * PLL2CFGR PLL2N LL_RCC_PLL2_ConfigDomain_ADC\n 4420 * PLL2CFGR PLL2R LL_RCC_PLL2_ConfigDomain_ADC 4421 * @param Source This parameter can be one of the following values: 4422 * @arg @ref LL_RCC_PLL2SOURCE_NONE 4423 * @arg @ref LL_RCC_PLL2SOURCE_MSIS 4424 * @arg @ref LL_RCC_PLL2SOURCE_HSI 4425 * @arg @ref LL_RCC_PLL2SOURCE_HSE 4426 * @param PLLM parameter can be a value between 1 and 16 4427 * @param PLLR parameter can be a value between 1 and 128 4428 * @param PLLN parameter can be a value between 4 and 512 4429 * @retval None 4430 */ LL_RCC_PLL2_ConfigDomain_ADC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)4431 __STATIC_INLINE void LL_RCC_PLL2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 4432 { 4433 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC | RCC_PLL2CFGR_PLL2M, Source | \ 4434 ((PLLM - 1UL) << RCC_PLL2CFGR_PLL2M_Pos)); 4435 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N | RCC_PLL2DIVR_PLL2R, ((PLLN - 1UL) << \ 4436 RCC_PLL2DIVR_PLL2N_Pos) | ((PLLR - 1UL) << \ 4437 RCC_PLL2DIVR_PLL2R_Pos)); 4438 } 4439 4440 /** 4441 * @brief Configure PLL2 clock source 4442 * @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_SetSource 4443 * @param PLL2Source This parameter can be one of the following values: 4444 * @arg @ref LL_RCC_PLL2SOURCE_NONE 4445 * @arg @ref LL_RCC_PLL2SOURCE_MSIS 4446 * @arg @ref LL_RCC_PLL2SOURCE_HSI 4447 * @arg @ref LL_RCC_PLL2SOURCE_HSE 4448 * @retval None 4449 */ LL_RCC_PLL2_SetSource(uint32_t PLL2Source)4450 __STATIC_INLINE void LL_RCC_PLL2_SetSource(uint32_t PLL2Source) 4451 { 4452 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC, PLL2Source); 4453 } 4454 4455 /** 4456 * @brief Get the oscillator used as PLL2 clock source. 4457 * @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_GetSource 4458 * @retval Returned value can be one of the following values: 4459 * @arg @ref LL_RCC_PLL2SOURCE_NONE 4460 * @arg @ref LL_RCC_PLL2SOURCE_MSIS 4461 * @arg @ref LL_RCC_PLL2SOURCE_HSI 4462 * @arg @ref LL_RCC_PLL2SOURCE_HSE 4463 */ LL_RCC_PLL2_GetSource(void)4464 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetSource(void) 4465 { 4466 return (uint32_t)(READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC)); 4467 } 4468 4469 /** 4470 * @brief Set Main PLL2 multiplication factor for VCO 4471 * @rmtoll PLL2CFGR PLL2N LL_RCC_PLL2_SetN 4472 * @param PLL2N parameter can be a value between 4 and 512 4473 */ LL_RCC_PLL2_SetN(uint32_t PLL2N)4474 __STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t PLL2N) 4475 { 4476 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N, (PLL2N - 1UL) << RCC_PLL2DIVR_PLL2N_Pos); 4477 } 4478 4479 /** 4480 * @brief Get Main PLL2 multiplication factor for VCO 4481 * @rmtoll PLL2CFGR PLL2N LL_RCC_PLL2_GetN 4482 * @retval Between 4 and 512 4483 */ LL_RCC_PLL2_GetN(void)4484 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void) 4485 { 4486 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N) >> RCC_PLL2DIVR_PLL2N_Pos) + 1UL); 4487 } 4488 4489 4490 /** 4491 * @brief Set Main PLL2 division factor for PLL2P 4492 * @note Used for SAI1 and SAI2 clock 4493 * @rmtoll PLL2CFGR PLL2P LL_RCC_PLL2_SetP 4494 * @param PLL2P parameter can be a value between 1 and 128 4495 */ LL_RCC_PLL2_SetP(uint32_t PLL2P)4496 __STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t PLL2P) 4497 { 4498 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2P, (PLL2P - 1UL) << RCC_PLL2DIVR_PLL2P_Pos); 4499 } 4500 4501 /** 4502 * @brief Get Main PLL2 division factor for PLL2P 4503 * @note Used for SAI1 and SAI2 clock 4504 * @rmtoll PLL2CFGR PLL2P LL_RCC_PLL2_GetP 4505 * @retval Between 1 and 128 4506 */ LL_RCC_PLL2_GetP(void)4507 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void) 4508 { 4509 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + 1UL); 4510 } 4511 4512 4513 /** 4514 * @brief Set Main PLL division factor for PLLQ 4515 * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock) 4516 * @rmtoll PLLCFGR PLL2Q LL_RCC_PLL2_SetQ 4517 * @param PLL2Q parameter can be a value between 1 and 128 4518 */ LL_RCC_PLL2_SetQ(uint32_t PLL2Q)4519 __STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t PLL2Q) 4520 { 4521 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2Q, (PLL2Q - 1UL) << RCC_PLL2DIVR_PLL2Q_Pos); 4522 } 4523 4524 /** 4525 * @brief Get Main PLL division factor for PLLQ 4526 * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock) 4527 * @rmtoll PLL2CFGR PLL2Q LL_RCC_PLL2_GetQ 4528 * @retval Between 1 and 128 4529 */ LL_RCC_PLL2_GetQ(void)4530 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void) 4531 { 4532 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + 1UL); 4533 } 4534 4535 /** 4536 * @brief Set Main PLL division factor for PLLQ 4537 * @note Used for PLL2CLK selected for USB, SDMMC (48 MHz clock) 4538 * @rmtoll PLL2CFGR PLL2R LL_RCC_PLL2_SetR 4539 * @param PLL2R parameter can be a value between 1 and 128 4540 */ LL_RCC_PLL2_SetR(uint32_t PLL2R)4541 __STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t PLL2R) 4542 { 4543 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2R, (PLL2R - 1UL) << RCC_PLL2DIVR_PLL2R_Pos); 4544 } 4545 4546 /** 4547 * @brief Get Main PLL2 division factor for PLL2R 4548 * @note Used for PLL2CLK (system clock) 4549 * @rmtoll PLL2DIVR PLL2R LL_RCC_PLL2_GetR 4550 * @retval Between 1 and 128 4551 */ LL_RCC_PLL2_GetR(void)4552 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void) 4553 { 4554 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + 1UL); 4555 } 4556 4557 /** 4558 * @brief Set Division factor for the main PLL and other PLL 4559 * @rmtoll PLL2CFGR PLL2M LL_RCC_PLL2_SetDivider 4560 * @param PLL2M parameter can be a value between 1 and 16 4561 */ LL_RCC_PLL2_SetDivider(uint32_t PLL2M)4562 __STATIC_INLINE void LL_RCC_PLL2_SetDivider(uint32_t PLL2M) 4563 { 4564 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2M, (PLL2M - 1UL) << RCC_PLL2CFGR_PLL2M_Pos); 4565 } 4566 4567 /** 4568 * @brief Get Division factor for the main PLL and other PLL 4569 * @rmtoll PLL2CFGR PLL2M LL_RCC_PLL2_GetDivider 4570 * @retval Between 1 and 16 4571 */ LL_RCC_PLL2_GetDivider(void)4572 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetDivider(void) 4573 { 4574 return (uint32_t)((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1UL); 4575 } 4576 4577 /** 4578 * @brief Enable PLL2 output mapped on SAI domain clock 4579 * @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2_EnableDomain_SAI 4580 * @retval None 4581 */ LL_RCC_PLL2_EnableDomain_SAI(void)4582 __STATIC_INLINE void LL_RCC_PLL2_EnableDomain_SAI(void) 4583 { 4584 SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN); 4585 } 4586 4587 /** 4588 * @brief Disable PLL2 output mapped on SAI domain clock 4589 * @note In order to save power, when of the PLL2 is 4590 * not used, should be 0 4591 * @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2_DisableDomain_SAI 4592 * @retval None 4593 */ LL_RCC_PLL2_DisableDomain_SAI(void)4594 __STATIC_INLINE void LL_RCC_PLL2_DisableDomain_SAI(void) 4595 { 4596 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN); 4597 } 4598 4599 /** 4600 * @brief Check if PLL2 output mapped on SAI domain clock is enabled 4601 * @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2_IsEnabledDomain_SAI 4602 * @retval State of bit (1 or 0). 4603 */ LL_RCC_PLL2_IsEnabledDomain_SAI(void)4604 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledDomain_SAI(void) 4605 { 4606 return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN) == (RCC_PLL2CFGR_PLL2PEN)) ? 1UL : 0UL); 4607 } 4608 4609 /** 4610 * @brief Enable PLL2 output mapped on 48MHz domain clock 4611 * @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2_EnableDomain_48M 4612 * @retval None 4613 */ LL_RCC_PLL2_EnableDomain_48M(void)4614 __STATIC_INLINE void LL_RCC_PLL2_EnableDomain_48M(void) 4615 { 4616 SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN); 4617 } 4618 4619 /** 4620 * @brief Disable PLL2 output mapped on 48MHz domain clock 4621 * @note In order to save power, when of the PLL2 48M is 4622 * not used, should be 0 4623 * @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2_DisableDomain_48M 4624 * @retval None 4625 */ LL_RCC_PLL2_DisableDomain_48M(void)4626 __STATIC_INLINE void LL_RCC_PLL2_DisableDomain_48M(void) 4627 { 4628 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN); 4629 } 4630 4631 /** 4632 * @brief Check if PLL2 output mapped on 48M domain clock is enabled 4633 * @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2_IsEnabledDomain_48M 4634 * @retval State of bit (1 or 0). 4635 */ LL_RCC_PLL2_IsEnabledDomain_48M(void)4636 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledDomain_48M(void) 4637 { 4638 return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN) == (RCC_PLL2CFGR_PLL2QEN)) ? 1UL : 0UL); 4639 } 4640 4641 /** 4642 * @brief Enable PLL2 output mapped on ADC domain clock 4643 * @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2_EnableDomain_ADC 4644 * @retval None 4645 */ LL_RCC_PLL2_EnableDomain_ADC(void)4646 __STATIC_INLINE void LL_RCC_PLL2_EnableDomain_ADC(void) 4647 { 4648 SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN); 4649 } 4650 4651 /** 4652 * @brief Disable PLL2 output mapped on ADC domain clock 4653 * @note In order to save power, when of the PLL2 ADC is 4654 * not used, Main PLL2ADC should be 0 4655 * @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2_DisableDomain_ADC 4656 * @retval None 4657 */ LL_RCC_PLL2_DisableDomain_ADC(void)4658 __STATIC_INLINE void LL_RCC_PLL2_DisableDomain_ADC(void) 4659 { 4660 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN); 4661 } 4662 4663 /** 4664 * @brief Check if PLL2 output mapped on ADC domain clock is enabled 4665 * @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2_IsEnabledDomain_ADC 4666 * @retval State of bit (1 or 0). 4667 */ LL_RCC_PLL2_IsEnabledDomain_ADC(void)4668 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledDomain_ADC(void) 4669 { 4670 return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN) == (RCC_PLL2CFGR_PLL2REN)) ? 1UL : 0UL); 4671 } 4672 4673 /** 4674 * @brief Enable PLL2 FRACN 4675 * @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable 4676 * @retval None 4677 */ LL_RCC_PLL2FRACN_Enable(void)4678 __STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void) 4679 { 4680 SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN); 4681 } 4682 4683 /** 4684 * @brief Check if PLL2 FRACN is enabled 4685 * @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_IsEnabled 4686 * @retval State of bit (1 or 0). 4687 */ LL_RCC_PLL2FRACN_IsEnabled(void)4688 __STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void) 4689 { 4690 return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) == RCC_PLL2CFGR_PLL2FRACEN) ? 1UL : 0UL); 4691 } 4692 4693 /** 4694 * @brief Disable PLL2 FRACN 4695 * @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_Disable 4696 * @retval None 4697 */ LL_RCC_PLL2FRACN_Disable(void)4698 __STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void) 4699 { 4700 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN); 4701 } 4702 4703 /** 4704 * @brief Set PLL2 FRACN Coefficient 4705 * @rmtoll PLL2FRACR PLL2FRACN LL_RCC_PLL2_SetFRACN 4706 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) 4707 */ LL_RCC_PLL2_SetFRACN(uint32_t FRACN)4708 __STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN) 4709 { 4710 MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN, FRACN << RCC_PLL2FRACR_PLL2FRACN_Pos); 4711 } 4712 4713 /** 4714 * @brief Get PLL2 FRACN Coefficient 4715 * @rmtoll PLL2FRACR PLL2FRACN LL_RCC_PLL2_GetFRACN 4716 * @retval A value between 0 and 8191 (0x1FFF) 4717 */ LL_RCC_PLL2_GetFRACN(void)4718 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void) 4719 { 4720 return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN) >> RCC_PLL2FRACR_PLL2FRACN_Pos); 4721 } 4722 4723 /** 4724 * @brief Set PLL2 VCO Input Range 4725 * @note This API shall be called only when PLL2 is disabled. 4726 * @rmtoll PLL2CFGR PLL2RGE LL_RCC_PLL2_SetVCOInputRange 4727 * @param InputRange This parameter can be one of the following values: 4728 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 4729 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 4730 * @retval None 4731 */ LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange)4732 __STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange) 4733 { 4734 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2RGE, InputRange); 4735 } 4736 4737 /** 4738 * @} 4739 */ 4740 4741 /** @defgroup RCC_LL_EF_PLL3 PLL3 4742 * @{ 4743 */ 4744 4745 /** 4746 * @brief Enable PLL3 4747 * @rmtoll CR PLL3ON LL_RCC_PLL3_Enable 4748 * @retval None 4749 */ LL_RCC_PLL3_Enable(void)4750 __STATIC_INLINE void LL_RCC_PLL3_Enable(void) 4751 { 4752 SET_BIT(RCC->CR, RCC_CR_PLL3ON); 4753 } 4754 4755 /** 4756 * @brief Disable PLL3 4757 * @rmtoll CR PLL3ON LL_RCC_PLL3_Disable 4758 * @retval None 4759 */ LL_RCC_PLL3_Disable(void)4760 __STATIC_INLINE void LL_RCC_PLL3_Disable(void) 4761 { 4762 CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); 4763 } 4764 4765 /** 4766 * @brief Check if PLL3 Ready 4767 * @rmtoll CR PLL3RDY LL_RCC_PLL3_IsReady 4768 * @retval State of bit (1 or 0). 4769 */ LL_RCC_PLL3_IsReady(void)4770 __STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void) 4771 { 4772 return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == RCC_CR_PLL3RDY) ? 1UL : 0UL); 4773 } 4774 4775 /** 4776 * @brief Configure PLL3 used for SAI domain clock 4777 * @note PLL3SRC/PLL3M/PLL3N/PLL3PDIV can be written only when PLL3 is disabled. 4778 * @note This can be selected for SAI1 or SAI2 4779 * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_ConfigDomain_SAI\n 4780 * PLL3CFGR PLL3M LL_RCC_PLL3_ConfigDomain_SAI\n 4781 * PLL3CFGR PLL3N LL_RCC_PLL3_ConfigDomain_SAI\n 4782 * PLL3DIVR PLL3P LL_RCC_PLL3_ConfigDomain_SAI 4783 * @param Source This parameter can be one of the following values: 4784 * @arg @ref LL_RCC_PLL3SOURCE_NONE 4785 * @arg @ref LL_RCC_PLL3SOURCE_MSIS 4786 * @arg @ref LL_RCC_PLL3SOURCE_HSI 4787 * @arg @ref LL_RCC_PLL3SOURCE_HSE 4788 * @param PLLM parameter can be a value between 1 and 16 4789 * @param PLLN parameter can be a value between 4 and 512 4790 * @param PLLP parameter can be a value between 1 and 128 4791 * @retval None 4792 */ LL_RCC_PLL3_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)4793 __STATIC_INLINE void LL_RCC_PLL3_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 4794 { 4795 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC | RCC_PLL3CFGR_PLL3M, Source | \ 4796 ((PLLM - 1UL) << RCC_PLL3CFGR_PLL3M_Pos)); 4797 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N | RCC_PLL3DIVR_PLL3P, ((PLLN - 1UL) << \ 4798 RCC_PLL3DIVR_PLL3N_Pos) | ((PLLP - 1UL) << \ 4799 RCC_PLL3DIVR_PLL3P_Pos)); 4800 } 4801 4802 4803 /** 4804 * @brief Configure PLL3 used for 48Mhz domain clock 4805 * @note PLL3 Source, PLLM, PLLN and PLLQ can be written only when PLL3 is disabled. 4806 * @note This can be selected for USB, SDMMC 4807 * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_ConfigDomain_48M\n 4808 * PLL3CFGR PLL3M LL_RCC_PLL3_ConfigDomain_48M\n 4809 * PLL3CFGR PLL3N LL_RCC_PLL3_ConfigDomain_48M\n 4810 * PLL3CFGR PLL3Q LL_RCC_PLL3_ConfigDomain_48M 4811 * @param Source This parameter can be one of the following values: 4812 * @arg @ref LL_RCC_PLL3SOURCE_NONE 4813 * @arg @ref LL_RCC_PLL3SOURCE_MSIS 4814 * @arg @ref LL_RCC_PLL3SOURCE_HSI 4815 * @arg @ref LL_RCC_PLL3SOURCE_HSE 4816 * @param PLLM parameter can be a value between 1 and 16 4817 * @param PLLN parameter can be a value between 4 and 512 4818 * @param PLLQ parameter can be a value between 1 and 128 4819 * @retval None 4820 */ LL_RCC_PLL3_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)4821 __STATIC_INLINE void LL_RCC_PLL3_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) 4822 { 4823 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC | RCC_PLL3CFGR_PLL3M, Source | \ 4824 ((PLLM - 1UL) << RCC_PLL3CFGR_PLL3M_Pos)); 4825 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N | RCC_PLL3DIVR_PLL3Q, ((PLLN - 1UL) << \ 4826 RCC_PLL3DIVR_PLL3N_Pos) | ((PLLQ - 1UL) << \ 4827 RCC_PLL3DIVR_PLL3Q_Pos)); 4828 } 4829 4830 4831 #if defined(LTDC) || defined(HSPI1) 4832 4833 /** 4834 * @brief Configure PLL3 used for HSPI_LTDC domain clock 4835 * @note PLL3 Source, PLLM, PLLN and PLLR can be written only when PLL3 is disabled. 4836 * @note This can be selected for HSPI and LTDC 4837 * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_ConfigDomain_HSPI_LTDC\n 4838 * PLL3CFGR PLL3M LL_RCC_PLL3_ConfigDomain_HSPI_LTDC\n 4839 * PLL3CFGR PLL3N LL_RCC_PLL3_ConfigDomain_HSPI_LTDC\n 4840 * PLL3CFGR PLL3R LL_RCC_PLL3_ConfigDomain_HSPI_LTDC 4841 * @param Source This parameter can be one of the following values: 4842 * @arg @ref LL_RCC_PLL3SOURCE_NONE 4843 * @arg @ref LL_RCC_PLL3SOURCE_MSIS 4844 * @arg @ref LL_RCC_PLL3SOURCE_HSI 4845 * @arg @ref LL_RCC_PLL3SOURCE_HSE 4846 * @param PLLM parameter can be a value between 1 and 16 4847 * @param PLLN parameter can be a value between 4 and 512 4848 * @param PLLR parameter can be a value between 1 and 128 4849 * @retval None 4850 */ LL_RCC_PLL3_ConfigDomain_HSPI_LTDC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)4851 __STATIC_INLINE void LL_RCC_PLL3_ConfigDomain_HSPI_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 4852 { 4853 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC | RCC_PLL3CFGR_PLL3M, Source | \ 4854 ((PLLM - 1UL) << RCC_PLL3CFGR_PLL3M_Pos)); 4855 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N | RCC_PLL3DIVR_PLL3R, ((PLLN - 1UL) << \ 4856 RCC_PLL3DIVR_PLL3N_Pos) | ((PLLR - 1UL) << \ 4857 RCC_PLL3DIVR_PLL3R_Pos)); 4858 } 4859 4860 #endif /* LTDC || HSPI1 */ 4861 4862 /** 4863 * @brief Configure PLL3 clock source 4864 * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_SetSource 4865 * @param PLLSource This parameter can be one of the following values: 4866 * @arg @ref LL_RCC_PLL3SOURCE_NONE 4867 * @arg @ref LL_RCC_PLL3SOURCE_MSIS 4868 * @arg @ref LL_RCC_PLL3SOURCE_HSI 4869 * @arg @ref LL_RCC_PLL3SOURCE_HSE 4870 * @retval None 4871 */ LL_RCC_PLL3_SetSource(uint32_t PLLSource)4872 __STATIC_INLINE void LL_RCC_PLL3_SetSource(uint32_t PLLSource) 4873 { 4874 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC, PLLSource); 4875 } 4876 4877 /** 4878 * @brief Get the oscillator used as PLL3 clock source. 4879 * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_GetSource 4880 * @retval Returned value can be one of the following values: 4881 * @arg @ref LL_RCC_PLL3SOURCE_NONE 4882 * @arg @ref LL_RCC_PLL3SOURCE_MSIS 4883 * @arg @ref LL_RCC_PLL3SOURCE_HSI 4884 * @arg @ref LL_RCC_PLL3SOURCE_HSE 4885 */ LL_RCC_PLL3_GetSource(void)4886 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetSource(void) 4887 { 4888 return (uint32_t)(READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC)); 4889 } 4890 4891 /** 4892 * @brief Set Main PLL3 multiplication factor for VCO 4893 * @rmtoll PLL3CFGR PLL3N LL_RCC_PLL3_SetN 4894 * @param PLL3N parameter can be a value between 4 and 512 4895 */ LL_RCC_PLL3_SetN(uint32_t PLL3N)4896 __STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t PLL3N) 4897 { 4898 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N, (PLL3N - 1UL) << RCC_PLL3DIVR_PLL3N_Pos); 4899 } 4900 4901 /** 4902 * @brief Get Main PLL3 multiplication factor for VCO 4903 * @rmtoll PLL3CFGR PLL3N LL_RCC_PLL3_GetN 4904 * @retval Between 4 and 512 4905 */ LL_RCC_PLL3_GetN(void)4906 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void) 4907 { 4908 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N) >> RCC_PLL3DIVR_PLL3N_Pos) + 1UL); 4909 } 4910 4911 4912 /** 4913 * @brief Set Main PLL3 division factor for PLL3P 4914 * @note Used for SAI1 and SAI2 clock 4915 * @rmtoll PLL3CFGR PLL3P LL_RCC_PLL3_SetP 4916 * @param PLL3P parameter can be a value between 1 and 128 4917 */ LL_RCC_PLL3_SetP(uint32_t PLL3P)4918 __STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t PLL3P) 4919 { 4920 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3P, (PLL3P - 1UL) << RCC_PLL3DIVR_PLL3P_Pos); 4921 } 4922 4923 /** 4924 * @brief Get Main PLL3 division factor for PLL3P 4925 * @note Used for SAI1 and SAI2 clock 4926 * @rmtoll PLL3CFGR PLL3P LL_RCC_PLL3_GetP 4927 * @retval Between 1 and 128 4928 */ LL_RCC_PLL3_GetP(void)4929 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void) 4930 { 4931 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + 1UL); 4932 } 4933 4934 4935 /** 4936 * @brief Set Main PLL division factor for PLLQ 4937 * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock) 4938 * @rmtoll PLLCFGR PLL3Q LL_RCC_PLL3_SetQ 4939 * @param PLL3Q parameter can be a value between 1 and 128 4940 */ LL_RCC_PLL3_SetQ(uint32_t PLL3Q)4941 __STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t PLL3Q) 4942 { 4943 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3Q, (PLL3Q - 1UL) << RCC_PLL3DIVR_PLL3Q_Pos); 4944 } 4945 4946 /** 4947 * @brief Get Main PLL division factor for PLLQ 4948 * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock) 4949 * @rmtoll PLL3CFGR PLL3Q LL_RCC_PLL3_GetQ 4950 * @retval Between 1 and 128 4951 */ LL_RCC_PLL3_GetQ(void)4952 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void) 4953 { 4954 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + 1UL); 4955 } 4956 4957 /** 4958 * @brief Set Main PLL division factor for PLLQ 4959 * @note Used for PLL3CLK selected for USB, SDMMC (48 MHz clock) 4960 * @rmtoll PLL3CFGR PLL3R LL_RCC_PLL3_SetR 4961 * @param PLL3R parameter can be a value between 1 and 128 4962 */ LL_RCC_PLL3_SetR(uint32_t PLL3R)4963 __STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t PLL3R) 4964 { 4965 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3R, (PLL3R - 1UL) << RCC_PLL3DIVR_PLL3R_Pos); 4966 } 4967 4968 /** 4969 * @brief Get Main PLL3 division factor for PLL3R 4970 * @note Used for PLL3CLK (system clock) 4971 * @rmtoll PLL3DIVR PLL3R LL_RCC_PLL3_GetR 4972 * @retval Between 1 and 128 4973 */ LL_RCC_PLL3_GetR(void)4974 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void) 4975 { 4976 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + 1UL); 4977 } 4978 4979 /** 4980 * @brief Set Division factor for the main PLL and other PLL 4981 * @rmtoll PLL3CFGR PLL3M LL_RCC_PLL3_SetDivider 4982 * @param PLL3M parameter can be a value between 1 and 16 4983 */ LL_RCC_PLL3_SetDivider(uint32_t PLL3M)4984 __STATIC_INLINE void LL_RCC_PLL3_SetDivider(uint32_t PLL3M) 4985 { 4986 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3M, (PLL3M - 1UL) << RCC_PLL3CFGR_PLL3M_Pos); 4987 } 4988 4989 /** 4990 * @brief Get Division factor for the main PLL and other PLL 4991 * @rmtoll PLL3CFGR PLL3M LL_RCC_PLL3_GetDivider 4992 * @retval Between 1 and 16 4993 */ LL_RCC_PLL3_GetDivider(void)4994 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetDivider(void) 4995 { 4996 return (uint32_t)((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos) + 1UL); 4997 } 4998 4999 /** 5000 * @brief Enable PLL3 output mapped on SAI domain clock 5001 * @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3_EnableDomain_SAI 5002 * @retval None 5003 */ LL_RCC_PLL3_EnableDomain_SAI(void)5004 __STATIC_INLINE void LL_RCC_PLL3_EnableDomain_SAI(void) 5005 { 5006 SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN); 5007 } 5008 5009 /** 5010 * @brief Disable PLL3 output mapped on SAI domain clock 5011 * @note In order to save power, when of the PLLSAI2 is 5012 * not used, should be 0 5013 * @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3_DisableDomain_SAI 5014 * @retval None 5015 */ LL_RCC_PLL3_DisableDomain_SAI(void)5016 __STATIC_INLINE void LL_RCC_PLL3_DisableDomain_SAI(void) 5017 { 5018 CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN); 5019 } 5020 5021 /** 5022 * @brief Check if PLL3 output mapped on SAI domain clock is enabled 5023 * @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3_IsEnabledDomain_SAI 5024 * @retval State of bit (1 or 0). 5025 */ LL_RCC_PLL3_IsEnabledDomain_SAI(void)5026 __STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledDomain_SAI(void) 5027 { 5028 return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN) == (RCC_PLL3CFGR_PLL3PEN)) ? 1UL : 0UL); 5029 } 5030 5031 /** 5032 * @brief Enable PLL2 output mapped on 48MHz domain clock 5033 * @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3_EnableDomain_48M 5034 * @retval None 5035 */ LL_RCC_PLL3_EnableDomain_48M(void)5036 __STATIC_INLINE void LL_RCC_PLL3_EnableDomain_48M(void) 5037 { 5038 SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN); 5039 } 5040 5041 /** 5042 * @brief Disable PLL3 output mapped on 48MHz domain clock 5043 * @note In order to save power, when of the PLL3 is 5044 * not used, should be 0 5045 * @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3_DisableDomain_48M 5046 * @retval None 5047 */ LL_RCC_PLL3_DisableDomain_48M(void)5048 __STATIC_INLINE void LL_RCC_PLL3_DisableDomain_48M(void) 5049 { 5050 CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN); 5051 } 5052 5053 /** 5054 * @brief Check if PLL3 output mapped on 48M domain clock is enabled 5055 * @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3_IsEnabledDomain_48M 5056 * @retval State of bit (1 or 0). 5057 */ LL_RCC_PLL3_IsEnabledDomain_48M(void)5058 __STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledDomain_48M(void) 5059 { 5060 return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN) == (RCC_PLL3CFGR_PLL3QEN)) ? 1UL : 0UL); 5061 } 5062 5063 #if defined(LTDC) || defined(HSPI1) 5064 5065 /** 5066 * @brief Enable PLL3 output mapped on HSPI_LTDC domain clock 5067 * @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3_EnableDomain_HSPI_LTDC 5068 * @retval None 5069 */ LL_RCC_PLL3_EnableDomain_HSPI_LTDC(void)5070 __STATIC_INLINE void LL_RCC_PLL3_EnableDomain_HSPI_LTDC(void) 5071 { 5072 SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN); 5073 } 5074 5075 /** 5076 * @brief Disable PLL3 output mapped on HSPI_LTDC domain clock 5077 * @note In order to save power, when of the PLL3 is 5078 * not used, should be 0 5079 * @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3_DisableDomain_HSPI_LTDC 5080 * @retval None 5081 */ LL_RCC_PLL3_DisableDomain_HSPI_LTDC(void)5082 __STATIC_INLINE void LL_RCC_PLL3_DisableDomain_HSPI_LTDC(void) 5083 { 5084 CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN); 5085 } 5086 5087 /** 5088 * @brief Check if PLL3 output mapped on HSPI_LTDC domain clock is enabled 5089 * @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3_IsEnabledDomain_HSPI_LTDC 5090 * @retval State of bit (1 or 0). 5091 */ LL_RCC_PLL3_IsEnabledDomain_HSPI_LTDC(void)5092 __STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledDomain_HSPI_LTDC(void) 5093 { 5094 return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN) == (RCC_PLL3CFGR_PLL3REN)) ? 1UL : 0UL); 5095 } 5096 5097 #endif /* LTDC || HSPI1 */ 5098 5099 5100 /** 5101 * @brief Enable PLL3 FRACN 5102 * @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable 5103 * @retval None 5104 */ LL_RCC_PLL3FRACN_Enable(void)5105 __STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void) 5106 { 5107 SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN); 5108 } 5109 5110 /** 5111 * @brief Check if PLL3 FRACN is enabled 5112 * @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_IsEnabled 5113 * @retval State of bit (1 or 0). 5114 */ LL_RCC_PLL3FRACN_IsEnabled(void)5115 __STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void) 5116 { 5117 return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) == RCC_PLL3CFGR_PLL3FRACEN) ? 1UL : 0UL); 5118 } 5119 5120 /** 5121 * @brief Disable PLL3 FRACN 5122 * @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_Disable 5123 * @retval None 5124 */ LL_RCC_PLL3FRACN_Disable(void)5125 __STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void) 5126 { 5127 CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN); 5128 } 5129 5130 /** 5131 * @brief Set PLL3 FRACN Coefficient 5132 * @rmtoll PLL3FRACR PLL3FRACN LL_RCC_PLL3_SetFRACN 5133 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) 5134 */ LL_RCC_PLL3_SetFRACN(uint32_t FRACN)5135 __STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN) 5136 { 5137 MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN, FRACN << RCC_PLL3FRACR_PLL3FRACN_Pos); 5138 } 5139 5140 /** 5141 * @brief Get PLL3 FRACN Coefficient 5142 * @rmtoll PLL3FRACR PLL3FRACN LL_RCC_PLL3_GetFRACN 5143 * @retval A value between 0 and 8191 (0x1FFF) 5144 */ LL_RCC_PLL3_GetFRACN(void)5145 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void) 5146 { 5147 return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN) >> RCC_PLL3FRACR_PLL3FRACN_Pos); 5148 } 5149 5150 /** 5151 * @brief Set PLL3 VCO Input Range 5152 * @note This API shall be called only when PLL3 is disabled. 5153 * @rmtoll PLL3CFGR PLL3RGE LL_RCC_PLL3_SetVCOInputRange 5154 * @param InputRange This parameter can be one of the following values: 5155 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 5156 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 5157 * @retval None 5158 */ LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange)5159 __STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange) 5160 { 5161 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3RGE, InputRange); 5162 } 5163 5164 /** 5165 * @} 5166 */ 5167 5168 /** @defgroup RCC_LL_EF_PRIV Privileged mode 5169 * @{ 5170 */ 5171 5172 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 5173 /** 5174 * @brief Enable Secure Privileged mode 5175 * @rmtoll PRIVCFGR SPRIV LL_RCC_EnableSecPrivilegedMode 5176 * @retval None 5177 */ LL_RCC_EnableSecPrivilegedMode(void)5178 __STATIC_INLINE void LL_RCC_EnableSecPrivilegedMode(void) 5179 { 5180 SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); 5181 } 5182 5183 /** 5184 * @brief Disable Secure Privileged mode 5185 * @rmtoll PRIVCFGR SPRIV LL_RCC_DisableSecPrivilegedMode 5186 * @retval None 5187 */ LL_RCC_DisableSecPrivilegedMode(void)5188 __STATIC_INLINE void LL_RCC_DisableSecPrivilegedMode(void) 5189 { 5190 CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); 5191 } 5192 5193 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ 5194 5195 /** 5196 * @brief Check if Secure Privileged mode has been enabled or not 5197 * @rmtoll PRIVCFGR SPRIV LL_RCC_IsEnabledSecPrivilegedMode 5198 * @retval State of bit (1 or 0). 5199 */ LL_RCC_IsEnabledSecPrivilegedMode(void)5200 __STATIC_INLINE uint32_t LL_RCC_IsEnabledSecPrivilegedMode(void) 5201 { 5202 return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV) == RCC_PRIVCFGR_SPRIV) ? 1UL : 0UL); 5203 } 5204 5205 /** 5206 * @brief Enable Non Secure Privileged mode 5207 * @rmtoll PRIVCFGR NSPRIV LL_RCC_EnableNSecPrivilegedMode 5208 * @retval None 5209 */ LL_RCC_EnableNSecPrivilegedMode(void)5210 __STATIC_INLINE void LL_RCC_EnableNSecPrivilegedMode(void) 5211 { 5212 SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); 5213 } 5214 5215 /** 5216 * @brief Disable Non Secure Privileged mode 5217 * @rmtoll PRIVCFGR NSPRIV LL_RCC_DisableNSecPrivilegedMode 5218 * @retval None 5219 */ LL_RCC_DisableNSecPrivilegedMode(void)5220 __STATIC_INLINE void LL_RCC_DisableNSecPrivilegedMode(void) 5221 { 5222 CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); 5223 } 5224 5225 /** 5226 * @brief Check if Non Secure Privileged mode has been enabled or not 5227 * @rmtoll PRIVCFGR NSPRIV LL_RCC_IsEnabledNSecPrivilegedMode 5228 * @retval State of bit (1 or 0). 5229 */ LL_RCC_IsEnabledNSecPrivilegedMode(void)5230 __STATIC_INLINE uint32_t LL_RCC_IsEnabledNSecPrivilegedMode(void) 5231 { 5232 return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV) == RCC_PRIVCFGR_NSPRIV) ? 1UL : 0UL); 5233 } 5234 5235 5236 /** 5237 * @brief Enable privileged mode 5238 * @note User should use LL_RCC_EnableSecPrivilegedMode() to enable Secure privilege 5239 * User should use LL_RCC_EnableNSecPrivilegedMode() to enable Non-secure privilege 5240 * This API is kept for legacy purpose only 5241 * @rmtoll PRIVCFGR SPRIV LL_RCC_EnablePrivilegedMode 5242 * @rmtoll PRIVCFGR NSPRIV LL_RCC_EnablePrivilegedMode 5243 * @retval None 5244 */ LL_RCC_EnablePrivilegedMode(void)5245 __STATIC_INLINE void LL_RCC_EnablePrivilegedMode(void) 5246 { 5247 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 5248 SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); 5249 #else 5250 SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); 5251 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ 5252 } 5253 5254 /** 5255 * @brief Disable Privileged mode 5256 * @note User should use LL_RCC_DisableSecPrivilegedMode() to disable Secure privilege 5257 * User should use LL_RCC_DisableNSecPrivilegedMode() to disable Non-secure privilege 5258 * This API is kept for legacy purpose only 5259 * @rmtoll CR PRIV LL_RCC_DisablePrivilegedMode 5260 * @retval None 5261 */ LL_RCC_DisablePrivilegedMode(void)5262 __STATIC_INLINE void LL_RCC_DisablePrivilegedMode(void) 5263 { 5264 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 5265 CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); 5266 #else 5267 CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); 5268 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ 5269 } 5270 5271 /** 5272 * @brief Check if Privileged mode has been enabled or not 5273 * @note User should use LL_RCC_IsEnabledSecPrivilegedMode() to check Secure privilege setting 5274 * User should use LL_RCC_IsEnabledNSecPrivilegedMode() to check Non-secure privilege setting 5275 * This API is kept for legacy purpose only 5276 * @rmtoll CR PRIV LL_RCC_IsEnabledPrivilegedMode 5277 * @retval State of bit (1 or 0). 5278 */ LL_RCC_IsEnabledPrivilegedMode(void)5279 __STATIC_INLINE uint32_t LL_RCC_IsEnabledPrivilegedMode(void) 5280 { 5281 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 5282 return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV) == RCC_PRIVCFGR_SPRIV) ? 1UL : 0UL); 5283 #else 5284 return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV) == RCC_PRIVCFGR_NSPRIV) ? 1UL : 0UL); 5285 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ 5286 } 5287 5288 /** 5289 * @} 5290 */ 5291 5292 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management 5293 * @{ 5294 */ 5295 5296 /** 5297 * @brief Clear LSI ready interrupt flag 5298 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY 5299 * @retval None 5300 */ LL_RCC_ClearFlag_LSIRDY(void)5301 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) 5302 { 5303 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC); 5304 } 5305 5306 /** 5307 * @brief Clear LSE ready interrupt flag 5308 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY 5309 * @retval None 5310 */ LL_RCC_ClearFlag_LSERDY(void)5311 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) 5312 { 5313 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC); 5314 } 5315 5316 /** 5317 * @brief Clear MSI ready interrupt flag 5318 * @rmtoll CICR MSISRDYC LL_RCC_ClearFlag_MSIRDY 5319 * @retval None 5320 */ LL_RCC_ClearFlag_MSIRDY(void)5321 __STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void) 5322 { 5323 SET_BIT(RCC->CICR, RCC_CICR_MSISRDYC); 5324 } 5325 5326 /** 5327 * @brief Clear HSI ready interrupt flag 5328 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY 5329 * @retval None 5330 */ LL_RCC_ClearFlag_HSIRDY(void)5331 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) 5332 { 5333 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC); 5334 } 5335 5336 /** 5337 * @brief Clear HSE ready interrupt flag 5338 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY 5339 * @retval None 5340 */ LL_RCC_ClearFlag_HSERDY(void)5341 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) 5342 { 5343 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC); 5344 } 5345 5346 5347 /** 5348 * @brief Clear HSI48 ready interrupt flag 5349 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY 5350 * @retval None 5351 */ LL_RCC_ClearFlag_HSI48RDY(void)5352 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) 5353 { 5354 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC); 5355 } 5356 5357 /** 5358 * @brief Clear PLL1 ready interrupt flag 5359 * @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY 5360 * @retval None 5361 */ LL_RCC_ClearFlag_PLL1RDY(void)5362 __STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void) 5363 { 5364 SET_BIT(RCC->CICR, RCC_CICR_PLL1RDYC); 5365 } 5366 5367 /** 5368 * @brief Clear PLL2 ready interrupt flag 5369 * @rmtoll CICR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY 5370 * @retval None 5371 */ LL_RCC_ClearFlag_PLL2RDY(void)5372 __STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void) 5373 { 5374 SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC); 5375 } 5376 5377 /** 5378 * @brief Clear PLL3 ready interrupt flag 5379 * @rmtoll CICR PLL3RDYC LL_RCC_ClearFlag_PLL3RDY 5380 * @retval None 5381 */ LL_RCC_ClearFlag_PLL3RDY(void)5382 __STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void) 5383 { 5384 SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC); 5385 } 5386 5387 /** 5388 * @brief Clear Clock security system interrupt flag 5389 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS 5390 * @retval None 5391 */ LL_RCC_ClearFlag_HSECSS(void)5392 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) 5393 { 5394 SET_BIT(RCC->CICR, RCC_CICR_CSSC); 5395 } 5396 5397 /** 5398 * @brief Clear MSIK ready interrupt flag 5399 * @rmtoll CICR MSIKRDYC LL_RCC_ClearFlag_MSIKRDY 5400 * @retval None 5401 */ LL_RCC_ClearFlag_MSIKRDY(void)5402 __STATIC_INLINE void LL_RCC_ClearFlag_MSIKRDY(void) 5403 { 5404 SET_BIT(RCC->CICR, RCC_CICR_MSIKRDYC); 5405 } 5406 5407 /** 5408 * @brief Clear SHSI ready interrupt flag 5409 * @rmtoll CICR SHSIRDYC LL_RCC_ClearFlag_SHSIRDY 5410 * @retval None 5411 */ 5412 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LL_RCC_ClearFlag_SHSIRDY(void)5413 __STATIC_INLINE void LL_RCC_ClearFlag_SHSIRDY(void) 5414 { 5415 SET_BIT(RCC->CICR, RCC_CICR_SHSIRDYC); 5416 } 5417 #endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/ 5418 5419 5420 /** 5421 * @brief Check if LSI ready interrupt occurred or not 5422 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY 5423 * @retval State of bit (1 or 0). 5424 */ LL_RCC_IsActiveFlag_LSIRDY(void)5425 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) 5426 { 5427 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL); 5428 } 5429 5430 /** 5431 * @brief Check if LSE ready interrupt occurred or not 5432 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY 5433 * @retval State of bit (1 or 0). 5434 */ LL_RCC_IsActiveFlag_LSERDY(void)5435 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) 5436 { 5437 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL); 5438 } 5439 5440 /** 5441 * @brief Check if MSI ready interrupt occurred or not 5442 * @rmtoll CIFR MSISRDYF LL_RCC_IsActiveFlag_MSIRDY 5443 * @retval State of bit (1 or 0). 5444 */ LL_RCC_IsActiveFlag_MSIRDY(void)5445 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void) 5446 { 5447 return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSISRDYF) == RCC_CIFR_MSISRDYF) ? 1UL : 0UL); 5448 } 5449 5450 /** 5451 * @brief Check if HSI ready interrupt occurred or not 5452 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY 5453 * @retval State of bit (1 or 0). 5454 */ LL_RCC_IsActiveFlag_HSIRDY(void)5455 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) 5456 { 5457 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL); 5458 } 5459 5460 /** 5461 * @brief Check if HSE ready interrupt occurred or not 5462 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY 5463 * @retval State of bit (1 or 0). 5464 */ LL_RCC_IsActiveFlag_HSERDY(void)5465 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) 5466 { 5467 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL); 5468 } 5469 5470 /** 5471 * @brief Check if HSI48 ready interrupt occurred or not 5472 * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY 5473 * @retval State of bit (1 or 0). 5474 */ LL_RCC_IsActiveFlag_HSI48RDY(void)5475 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) 5476 { 5477 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == RCC_CIFR_HSI48RDYF) ? 1UL : 0UL); 5478 } 5479 /** 5480 * @brief Check if PLL1 ready interrupt occurred or not 5481 * @rmtoll CIFR PLL1RDYF LL_RCC_IsActiveFlag_PLL1RDY 5482 * @retval State of bit (1 or 0). 5483 */ LL_RCC_IsActiveFlag_PLL1RDY(void)5484 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void) 5485 { 5486 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL1RDYF) == RCC_CIFR_PLL1RDYF) ? 1UL : 0UL); 5487 } 5488 5489 /** 5490 * @brief Check if PLL2 ready interrupt occurred or not 5491 * @rmtoll CIFR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY 5492 * @retval State of bit (1 or 0). 5493 */ LL_RCC_IsActiveFlag_PLL2RDY(void)5494 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void) 5495 { 5496 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == RCC_CIFR_PLL2RDYF) ? 1UL : 0UL); 5497 } 5498 5499 /** 5500 * @brief Check if PLL3 ready interrupt occurred or not 5501 * @rmtoll CIFR PLL3RDYF LL_RCC_IsActiveFlag_PLL3RDY 5502 * @retval State of bit (1 or 0). 5503 */ LL_RCC_IsActiveFlag_PLL3RDY(void)5504 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void) 5505 { 5506 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == RCC_CIFR_PLL3RDYF) ? 1UL : 0UL); 5507 } 5508 5509 /** 5510 * @brief Check if Clock security system interrupt occurred or not 5511 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS 5512 * @retval State of bit (1 or 0). 5513 */ LL_RCC_IsActiveFlag_HSECSS(void)5514 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) 5515 { 5516 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == RCC_CIFR_CSSF) ? 1UL : 0UL); 5517 } 5518 5519 /** 5520 * @brief Check if Clock security system interrupt occurred or not 5521 * @rmtoll CIFR MSIKRDYF LL_RCC_IsActiveFlag_MSIKRDY 5522 * @retval State of bit (1 or 0). 5523 */ LL_RCC_IsActiveFlag_MSIKRDY(void)5524 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIKRDY(void) 5525 { 5526 return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIKRDYF) == RCC_CIFR_MSIKRDYF) ? 1UL : 0UL); 5527 } 5528 5529 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 5530 /** 5531 * @brief Check if Clock security system interrupt occurred or not 5532 * @rmtoll CIFR SHSIRDYF LL_RCC_IsActiveFlag_SHSIRDY 5533 * @retval State of bit (1 or 0). 5534 */ LL_RCC_IsActiveFlag_SHSIRDY(void)5535 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHSIRDY(void) 5536 { 5537 return ((READ_BIT(RCC->CIFR, RCC_CIFR_SHSIRDYF) == RCC_CIFR_SHSIRDYF) ? 1UL : 0UL); 5538 } 5539 #endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/ 5540 5541 /** 5542 * @brief Check if RCC flag Independent Watchdog reset is set or not. 5543 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST 5544 * @retval State of bit (1 or 0). 5545 */ LL_RCC_IsActiveFlag_IWDGRST(void)5546 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) 5547 { 5548 return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL); 5549 } 5550 5551 /** 5552 * @brief Check if RCC flag Low Power reset is set or not. 5553 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST 5554 * @retval State of bit (1 or 0). 5555 */ LL_RCC_IsActiveFlag_LPWRRST(void)5556 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) 5557 { 5558 return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL); 5559 } 5560 5561 /** 5562 * @brief Check if RCC flag is set or not. 5563 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST 5564 * @retval State of bit (1 or 0). 5565 */ LL_RCC_IsActiveFlag_OBLRST(void)5566 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) 5567 { 5568 return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL); 5569 } 5570 5571 /** 5572 * @brief Check if RCC flag Pin reset is set or not. 5573 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST 5574 * @retval State of bit (1 or 0). 5575 */ LL_RCC_IsActiveFlag_PINRST(void)5576 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) 5577 { 5578 return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL); 5579 } 5580 5581 /** 5582 * @brief Check if RCC flag Software reset is set or not. 5583 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST 5584 * @retval State of bit (1 or 0). 5585 */ LL_RCC_IsActiveFlag_SFTRST(void)5586 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) 5587 { 5588 return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL); 5589 } 5590 5591 /** 5592 * @brief Check if RCC flag Window Watchdog reset is set or not. 5593 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST 5594 * @retval State of bit (1 or 0). 5595 */ LL_RCC_IsActiveFlag_WWDGRST(void)5596 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) 5597 { 5598 return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL); 5599 } 5600 5601 /** 5602 * @brief Check if RCC flag BOR reset is set or not. 5603 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST 5604 * @retval State of bit (1 or 0). 5605 */ LL_RCC_IsActiveFlag_BORRST(void)5606 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) 5607 { 5608 return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == RCC_CSR_BORRSTF) ? 1UL : 0UL); 5609 } 5610 5611 /** 5612 * @brief Set RMVF bit to clear the reset flags. 5613 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags 5614 * @retval None 5615 */ LL_RCC_ClearResetFlags(void)5616 __STATIC_INLINE void LL_RCC_ClearResetFlags(void) 5617 { 5618 SET_BIT(RCC->CSR, RCC_CSR_RMVF); 5619 } 5620 5621 /** 5622 * @} 5623 */ 5624 5625 /** @defgroup RCC_LL_EF_IT_Management IT Management 5626 * @{ 5627 */ 5628 5629 /** 5630 * @brief Enable LSI ready interrupt 5631 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY 5632 * @retval None 5633 */ LL_RCC_EnableIT_LSIRDY(void)5634 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) 5635 { 5636 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); 5637 } 5638 5639 /** 5640 * @brief Enable LSE ready interrupt 5641 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY 5642 * @retval None 5643 */ LL_RCC_EnableIT_LSERDY(void)5644 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) 5645 { 5646 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); 5647 } 5648 5649 /** 5650 * @brief Enable MSI ready interrupt 5651 * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY 5652 * @retval None 5653 */ LL_RCC_EnableIT_MSIRDY(void)5654 __STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void) 5655 { 5656 SET_BIT(RCC->CIER, RCC_CIER_MSISRDYIE); 5657 } 5658 5659 /** 5660 * @brief Enable HSI ready interrupt 5661 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY 5662 * @retval None 5663 */ LL_RCC_EnableIT_HSIRDY(void)5664 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) 5665 { 5666 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); 5667 } 5668 5669 /** 5670 * @brief Enable HSE ready interrupt 5671 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY 5672 * @retval None 5673 */ LL_RCC_EnableIT_HSERDY(void)5674 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) 5675 { 5676 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); 5677 } 5678 5679 /** 5680 * @brief Enable HSI48 ready interrupt 5681 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY 5682 * @retval None 5683 */ LL_RCC_EnableIT_HSI48RDY(void)5684 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) 5685 { 5686 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); 5687 } 5688 5689 /** 5690 * @brief Enable PLL1 ready interrupt 5691 * @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY 5692 * @retval None 5693 */ LL_RCC_EnableIT_PLL1RDY(void)5694 __STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void) 5695 { 5696 SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE); 5697 } 5698 5699 /** 5700 * @brief Enable PLL2 ready interrupt 5701 * @rmtoll CIER PLL2RDYIE LL_RCC_EnableIT_PLL2RDY 5702 * @retval None 5703 */ LL_RCC_EnableIT_PLL2RDY(void)5704 __STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void) 5705 { 5706 SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE); 5707 } 5708 5709 /** 5710 * @brief Enable PLL3 ready interrupt 5711 * @rmtoll CIER PLL3RDYIE LL_RCC_EnableIT_PLL3RDY 5712 * @retval None 5713 */ LL_RCC_EnableIT_PLL3RDY(void)5714 __STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void) 5715 { 5716 SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE); 5717 } 5718 5719 /** 5720 * @brief Enable MSIKRDYIE ready interrupt 5721 * @rmtoll CIER MSIKRDYIE LL_RCC_EnableIT_MSIKRDY 5722 * @retval None 5723 */ LL_RCC_EnableIT_MSIKRDY(void)5724 __STATIC_INLINE void LL_RCC_EnableIT_MSIKRDY(void) 5725 { 5726 SET_BIT(RCC->CIER, RCC_CIER_MSIKRDYIE); 5727 } 5728 5729 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 5730 /** 5731 * @brief Enable SHSIRDYIE ready interrupt 5732 * @rmtoll CIER SHSIRDYIE LL_RCC_EnableIT_SHSIRDY 5733 * @retval None 5734 */ LL_RCC_EnableIT_SHSIRDY(void)5735 __STATIC_INLINE void LL_RCC_EnableIT_SHSIRDY(void) 5736 { 5737 SET_BIT(RCC->CIER, RCC_CIER_SHSIRDYIE); 5738 } 5739 #endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/ 5740 5741 /** 5742 * @brief Disable LSI ready interrupt 5743 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY 5744 * @retval None 5745 */ LL_RCC_DisableIT_LSIRDY(void)5746 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) 5747 { 5748 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); 5749 } 5750 5751 /** 5752 * @brief Disable LSE ready interrupt 5753 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY 5754 * @retval None 5755 */ LL_RCC_DisableIT_LSERDY(void)5756 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) 5757 { 5758 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); 5759 } 5760 5761 /** 5762 * @brief Disable MSI ready interrupt 5763 * @rmtoll CIER MSISRDYIE LL_RCC_DisableIT_MSIRDY 5764 * @retval None 5765 */ LL_RCC_DisableIT_MSIRDY(void)5766 __STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void) 5767 { 5768 CLEAR_BIT(RCC->CIER, RCC_CIER_MSISRDYIE); 5769 } 5770 5771 /** 5772 * @brief Disable HSI ready interrupt 5773 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY 5774 * @retval None 5775 */ LL_RCC_DisableIT_HSIRDY(void)5776 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) 5777 { 5778 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); 5779 } 5780 5781 /** 5782 * @brief Disable HSE ready interrupt 5783 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY 5784 * @retval None 5785 */ LL_RCC_DisableIT_HSERDY(void)5786 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) 5787 { 5788 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); 5789 } 5790 5791 /** 5792 * @brief Disable HSI48 ready interrupt 5793 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY 5794 * @retval None 5795 */ LL_RCC_DisableIT_HSI48RDY(void)5796 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) 5797 { 5798 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); 5799 } 5800 5801 /** 5802 * @brief Disable PLL1 ready interrupt 5803 * @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY 5804 * @retval None 5805 */ LL_RCC_DisableIT_PLL1RDY(void)5806 __STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void) 5807 { 5808 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE); 5809 } 5810 5811 /** 5812 * @brief Disable PLL2 ready interrupt 5813 * @rmtoll CIER PLL2RDYIE LL_RCC_DisableIT_PLL2RDY 5814 * @retval None 5815 */ LL_RCC_DisableIT_PLL2RDY(void)5816 __STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void) 5817 { 5818 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE); 5819 } 5820 5821 /** 5822 * @brief Disable PLL3 ready interrupt 5823 * @rmtoll CIER PLL3RDYIE LL_RCC_DisableIT_PLL3RDY 5824 * @retval None 5825 */ LL_RCC_DisableIT_PLL3RDY(void)5826 __STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void) 5827 { 5828 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE); 5829 } 5830 5831 /** 5832 * @brief Disable MSIKRDYIE ready interrupt 5833 * @rmtoll CIER MSIKRDYIE LL_RCC_DisableIT_MSIKRDY 5834 * @retval None 5835 */ LL_RCC_DisableIT_MSIKRDY(void)5836 __STATIC_INLINE void LL_RCC_DisableIT_MSIKRDY(void) 5837 { 5838 CLEAR_BIT(RCC->CIER, RCC_CIER_MSIKRDYIE); 5839 } 5840 5841 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 5842 /** 5843 * @brief Disable SHSIRDYIE ready interrupt 5844 * @rmtoll CIER SHSIRDYIE LL_RCC_DisableIT_SHSIRDY 5845 * @retval None 5846 */ LL_RCC_DisableIT_SHSIRDY(void)5847 __STATIC_INLINE void LL_RCC_DisableIT_SHSIRDY(void) 5848 { 5849 CLEAR_BIT(RCC->CIER, RCC_CIER_SHSIRDYIE); 5850 } 5851 #endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/ 5852 5853 /** 5854 * @brief Checks if LSI ready interrupt source is enabled or disabled. 5855 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY 5856 * @retval State of bit (1 or 0). 5857 */ LL_RCC_IsEnabledIT_LSIRDY(void)5858 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) 5859 { 5860 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL); 5861 } 5862 5863 /** 5864 * @brief Checks if LSE ready interrupt source is enabled or disabled. 5865 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY 5866 * @retval State of bit (1 or 0). 5867 */ LL_RCC_IsEnabledIT_LSERDY(void)5868 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) 5869 { 5870 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL); 5871 } 5872 5873 /** 5874 * @brief Checks if MSI ready interrupt source is enabled or disabled. 5875 * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY 5876 * @retval State of bit (1 or 0). 5877 */ LL_RCC_IsEnabledIT_MSIRDY(void)5878 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void) 5879 { 5880 return ((READ_BIT(RCC->CIER, RCC_CIER_MSISRDYIE) == RCC_CIER_MSISRDYIE) ? 1UL : 0UL); 5881 } 5882 5883 /** 5884 * @brief Checks if HSI ready interrupt source is enabled or disabled. 5885 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY 5886 * @retval State of bit (1 or 0). 5887 */ LL_RCC_IsEnabledIT_HSIRDY(void)5888 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) 5889 { 5890 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL); 5891 } 5892 5893 /** 5894 * @brief Checks if HSE ready interrupt source is enabled or disabled. 5895 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY 5896 * @retval State of bit (1 or 0). 5897 */ LL_RCC_IsEnabledIT_HSERDY(void)5898 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) 5899 { 5900 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL); 5901 } 5902 5903 /** 5904 * @brief Checks if HSI48 ready interrupt source is enabled or disabled. 5905 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY 5906 * @retval State of bit (1 or 0). 5907 */ LL_RCC_IsEnabledIT_HSI48RDY(void)5908 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) 5909 { 5910 return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL); 5911 } 5912 /** 5913 * @brief Checks if PLL1 ready interrupt source is enabled or disabled. 5914 * @rmtoll CIER PLL1RDYIE LL_RCC_IsEnabledIT_PLL1RDY 5915 * @retval State of bit (1 or 0). 5916 */ LL_RCC_IsEnabledIT_PLL1RDY(void)5917 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL1RDY(void) 5918 { 5919 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL); 5920 } 5921 5922 /** 5923 * @brief Checks if PLL2 ready interrupt source is enabled or disabled. 5924 * @rmtoll CIER PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY 5925 * @retval State of bit (1 or 0). 5926 */ LL_RCC_IsEnabledIT_PLL2RDY(void)5927 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void) 5928 { 5929 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE) ? 1UL : 0UL); 5930 } 5931 5932 /** 5933 * @brief Checks if PLL3 ready interrupt source is enabled or disabled. 5934 * @rmtoll CIER PLL3RDYIE LL_RCC_IsEnabledIT_PLL3RDY 5935 * @retval State of bit (1 or 0). 5936 */ LL_RCC_IsEnabledIT_PLL3RDY(void)5937 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL3RDY(void) 5938 { 5939 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE) ? 1UL : 0UL); 5940 } 5941 5942 /** 5943 * @brief Checks if MSIK ready interrupt source is enabled or disabled. 5944 * @rmtoll CIER MSIKRDYIE LL_RCC_IsEnabledIT_MSIKRDY 5945 * @retval State of bit (1 or 0). 5946 */ LL_RCC_IsEnabledIT_MSIKRDY(void)5947 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIKRDY(void) 5948 { 5949 return ((READ_BIT(RCC->CIER, RCC_CIER_MSIKRDYIE) == RCC_CIER_MSIKRDYIE) ? 1UL : 0UL); 5950 } 5951 5952 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 5953 /** 5954 * @brief Checks if SHSI ready interrupt source is enabled or disabled. 5955 * @rmtoll CIER SHSIRDYIE LL_RCC_IsEnabledIT_SHSIRDY 5956 * @retval State of bit (1 or 0). 5957 */ LL_RCC_IsEnabledIT_SHSIRDY(void)5958 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_SHSIRDY(void) 5959 { 5960 return ((READ_BIT(RCC->CIER, RCC_CIER_SHSIRDYIE) == RCC_CIER_SHSIRDYIE) ? 1UL : 0UL); 5961 } 5962 #endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/ 5963 5964 /** 5965 * @} 5966 */ 5967 5968 /** @defgroup RCC_LL_EF_Security_Services Security Services 5969 * @{ 5970 */ 5971 5972 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 5973 /** 5974 * @brief Configure RCC resources security 5975 * @note Only available from secure state when system implements security (TZEN=1) 5976 * @rmtoll SECCFGR HSISEC LL_RCC_ConfigSecure\n 5977 * SECCFGR HSESEC LL_RCC_ConfigSecure\n 5978 * SECCFGR MSISEC LL_RCC_ConfigSecure\n 5979 * SECCFGR LSISEC LL_RCC_ConfigSecure\n 5980 * SECCFGR LSESEC LL_RCC_ConfigSecure\n 5981 * SECCFGR SYSCLKSEC LL_RCC_ConfigSecure\n 5982 * SECCFGR PRESCSEC LL_RCC_ConfigSecure\n 5983 * SECCFGR PLL1SEC LL_RCC_ConfigSecure\n 5984 * SECCFGR PLL2SEC LL_RCC_ConfigSecure\n 5985 * SECCFGR PLL3SEC LL_RCC_ConfigSecure\n 5986 * SECCFGR CLK48MSEC LL_RCC_ConfigSecure\n 5987 * SECCFGR HSI48SEC LL_RCC_ConfigSecure\n 5988 * SECCFGR RMVFSEC LL_RCC_ConfigSecure 5989 * @param SecureConfig This parameter can be one or a combination of the following values: 5990 * @arg @ref LL_RCC_ALL_NSEC & LL_RCC_ALL_SEC 5991 * @arg @ref LL_RCC_HSI_SEC & LL_RCC_HSI_NSEC 5992 * @arg @ref LL_RCC_HSE_SEC & LL_RCC_HSE_NSEC 5993 * @arg @ref LL_RCC_MSI_SEC & LL_RCC_MSI_NSEC 5994 * @arg @ref LL_RCC_LSE_SEC & LL_RCC_LSE_NSEC 5995 * @arg @ref LL_RCC_LSI_SEC & LL_RCC_LSI_NSEC 5996 * @arg @ref LL_RCC_SYSCLK_SEC & LL_RCC_SYSCLK_NSEC 5997 * @arg @ref LL_RCC_PRESCALERS_SEC & LL_RCC_PRESCALERS_NSEC 5998 * @arg @ref LL_RCC_PLL1_SEC & LL_RCC_PLL1_NSEC 5999 * @arg @ref LL_RCC_PLL2_SEC & LL_RCC_PLL2_NSEC 6000 * @arg @ref LL_RCC_PLL3_SEC & LL_RCC_PLL3_NSEC 6001 * @arg @ref LL_RCC_CLK48M_SEC & LL_RCC_CLK48M_NSEC 6002 * @arg @ref LL_RCC_HSI48_SEC & LL_RCC_HSI48_NSEC 6003 * @arg @ref LL_RCC_RESET_FLAGS_SEC & LL_RCC_RESET_FLAGS_NSEC 6004 * @retval None 6005 */ LL_RCC_ConfigSecure(uint32_t SecureConfig)6006 __STATIC_INLINE void LL_RCC_ConfigSecure(uint32_t SecureConfig) 6007 { 6008 WRITE_REG(RCC->SECCFGR, SecureConfig); 6009 } 6010 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ 6011 6012 /** 6013 * @brief Get RCC resources security status 6014 * @note Only available from secure state when system implements security (TZEN=1) 6015 * @rmtoll SECCFGR HSISEC LL_RCC_GetConfigSecure\n 6016 * SECCFGR HSESEC LL_RCC_GetConfigSecure\n 6017 * SECCFGR MSISEC LL_RCC_GetConfigSecure\n 6018 * SECCFGR LSISEC LL_RCC_GetConfigSecure\n 6019 * SECCFGR LSESEC LL_RCC_GetConfigSecure\n 6020 * SECCFGR SYSCLKSEC LL_RCC_GetConfigSecure\n 6021 * SECCFGR PRESCSEC LL_RCC_GetConfigSecure\n 6022 * SECCFGR PLL1SEC LL_RCC_GetConfigSecure\n 6023 * SECCFGR PLL2SEC LL_RCC_GetConfigSecure\n 6024 * SECCFGR PLL3SEC LL_RCC_GetConfigSecure\n 6025 * SECCFGR CLK48MSEC LL_RCC_GetConfigSecure\n 6026 * SECCFGR HSI48SEC LL_RCC_GetConfigSecure\n 6027 * SECCFGR RMVFSEC LL_RCC_GetConfigSecure 6028 * @retval Returned value can be one or a combination of the following values: 6029 * @arg @ref LL_RCC_ALL_NSEC & LL_RCC_ALL_SEC 6030 * @arg @ref LL_RCC_HSI_SEC & LL_RCC_HSI_NSEC 6031 * @arg @ref LL_RCC_HSE_SEC & LL_RCC_HSE_NSEC 6032 * @arg @ref LL_RCC_MSI_SEC & LL_RCC_MSI_NSEC 6033 * @arg @ref LL_RCC_LSE_SEC & LL_RCC_LSE_NSEC 6034 * @arg @ref LL_RCC_LSI_SEC & LL_RCC_LSI_NSEC 6035 * @arg @ref LL_RCC_SYSCLK_SEC & LL_RCC_SYSCLK_NSEC 6036 * @arg @ref LL_RCC_PRESCALERS_SEC & LL_RCC_PRESCALERS_NSEC 6037 * @arg @ref LL_RCC_PLL1_SEC & LL_RCC_PLL1_NSEC 6038 * @arg @ref LL_RCC_PLL2_SEC & LL_RCC_PLL2_NSEC 6039 * @arg @ref LL_RCC_PLL3_SEC & LL_RCC_PLL3_NSEC 6040 * @arg @ref LL_RCC_CLK48M_SEC & LL_RCC_CLK48M_NSEC 6041 * @arg @ref LL_RCC_HSI48_SEC & LL_RCC_HSI48_NSEC 6042 * @arg @ref LL_RCC_RESET_FLAGS_SEC & LL_RCC_RESET_FLAGS_NSEC 6043 * @retval None 6044 */ LL_RCC_GetConfigSecure(void)6045 __STATIC_INLINE uint32_t LL_RCC_GetConfigSecure(void) 6046 { 6047 return (uint32_t)(READ_BIT(RCC->SECCFGR, RCC_SECURE_MASK)); 6048 } 6049 6050 /** 6051 * @} 6052 */ 6053 6054 #if defined(USE_FULL_LL_DRIVER) 6055 /** @defgroup RCC_LL_EF_Init De-initialization function 6056 * @{ 6057 */ 6058 ErrorStatus LL_RCC_DeInit(void); 6059 /** 6060 * @} 6061 */ 6062 6063 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions 6064 * @{ 6065 */ 6066 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); 6067 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); 6068 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource); 6069 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); 6070 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); 6071 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); 6072 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource); 6073 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); 6074 uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource); 6075 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource); 6076 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); 6077 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); 6078 uint32_t LL_RCC_GetADCDACClockFreq(uint32_t ADCxSource); 6079 uint32_t LL_RCC_GetADF1ClockFreq(uint32_t ADF1Source); 6080 uint32_t LL_RCC_GetMDF1ClockFreq(uint32_t MDF1Source); 6081 uint32_t LL_RCC_GetDAC1ClockFreq(uint32_t DAC1Source); 6082 uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource); 6083 #if defined(SAES) 6084 uint32_t LL_RCC_GetSAESClockFreq(uint32_t SAESxSource); 6085 #endif /* SAES */ 6086 uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource); 6087 #if defined(DSI) 6088 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); 6089 #endif /* DSI */ 6090 #if defined(HSPI1) 6091 uint32_t LL_RCC_GetHSPIClockFreq(uint32_t HSPIxSource); 6092 #endif /* HSPI1 */ 6093 #if defined(LTDC) 6094 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource); 6095 #endif /* defined(LTDC) */ 6096 /** 6097 * @} 6098 */ 6099 6100 #endif /* USE_FULL_LL_DRIVER */ 6101 6102 /** 6103 * @} 6104 */ 6105 6106 /** 6107 * @} 6108 */ 6109 6110 #endif /* defined(RCC) */ 6111 6112 /** 6113 * @} 6114 */ 6115 6116 #ifdef __cplusplus 6117 } 6118 #endif 6119 6120 #endif /* STM32u5xx_LL_RCC_H */ 6121 6122 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 6123