1 /*
2 * Copyright (c) 2024 EXALT Technologies.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/device.h>
8 #include <zephyr/drivers/i3c.h>
9 #include <zephyr/drivers/clock_control.h>
10 #include <zephyr/drivers/gpio.h>
11 #include <zephyr/kernel.h>
12 #include <zephyr/sys/util.h>
13 #include <zephyr/drivers/pinctrl.h>
14 #ifdef CONFIG_I3C_STM32_DMA
15 #include <zephyr/drivers/dma/dma_stm32.h>
16 #include <zephyr/drivers/dma.h>
17 #endif
18 #include <zephyr/pm/policy.h>
19 #include <zephyr/pm/device.h>
20 #include <zephyr/pm/device_runtime.h>
21 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
22 #include <zephyr/logging/log.h>
23
24 #include <stm32_ll_i3c.h>
25 #include <stm32_ll_bus.h>
26 #include <stm32_ll_rcc.h>
27 #include <stm32_ll_system.h>
28 #include <stm32_ll_cortex.h>
29
30 LOG_MODULE_REGISTER(i3c_stm32, CONFIG_I3C_LOG_LEVEL);
31
32 #define DT_DRV_COMPAT st_stm32_i3c
33
34 #define STM32_I3C_SCLH_I2C_MIN_FM_NS 600ull
35 #define STM32_I3C_SCLH_I2C_MIN_FMP_NS 260ull
36 #define STM32_I3C_SCLL_OD_MIN_FM_NS 1320ull
37 #define STM32_I3C_SCLL_OD_MIN_FMP_NS 500ull
38 #define STM32_I3C_SCLL_OD_MIN_I3C_NS 200ull
39
40 #define STM32_I3C_SCLL_PP_MIN_NS 32ull
41 #define STM32_I3C_SCLH_I3C_MIN_NS 32ull
42
43 #define STM32_I3C_TBUF_FMP_MIN_NS 500.0
44 #define STM32_I3C_TBUF_FM_MIN_NS 1300.0
45 #define STM32_I3C_TCAS_MIN_NS 38.4
46
47 #define STM32_I3C_TRANSFER_TIMEOUT K_MSEC(100)
48
49 #ifdef CONFIG_I3C_STM32_DMA
50 K_HEAP_DEFINE(stm32_i3c_fifo_heap, CONFIG_I3C_STM32_DMA_FIFO_HEAP_SIZE);
51 #endif
52
53 typedef void (*irq_config_func_t)(const struct device *port);
54
55 enum i3c_stm32_sf_state {
56 STM32_I3C_SF_DAA, /* Dynamic addressing state */
57 STM32_I3C_SF_CCC, /* First part of CCC command state*/
58 STM32_I3C_SF_CCC_P2, /* Second part of CCC command state (used for direct commands)*/
59 STM32_I3C_SF, /* Private msg state */
60 STM32_I2C_SF, /* I2C legacy msg state */
61 STM32_I3C_SF_IDLE, /* Idle bus state */
62 STM32_I3C_SF_ERR, /* Error state */
63 STM32_I3C_SF_INVAL, /* Invalid state */
64 };
65
66 enum i3c_stm32_msg_state {
67 STM32_I3C_MSG_DAA, /* Dynamic addressing state */
68 STM32_I3C_MSG_CCC, /* First part of CCC command state*/
69 STM32_I3C_MSG_CCC_P2, /* Second part of CCC command state (used for direct commands)*/
70 STM32_I3C_MSG, /* Private msg state */
71 STM32_I3C_MSG_IDLE, /* Idle bus state */
72 STM32_I3C_MSG_ERR, /* Error state */
73 STM32_I3C_MSG_INVAL, /* Invalid state */
74 };
75
76 #ifdef CONFIG_I3C_STM32_DMA
77 struct i3c_stm32_dma_stream {
78 const struct device *dma_dev;
79 uint32_t dma_channel;
80 struct dma_config dma_cfg;
81 uint8_t priority;
82 bool src_addr_increment;
83 bool dst_addr_increment;
84 int fifo_threshold;
85 struct dma_block_config blk_cfg;
86 };
87 #endif
88
89 /* Struct to hold the information about the current message on the bus */
90 struct i3c_stm32_msg {
91 uint8_t target_addr; /* Current target xfer address */
92 struct i3c_msg *i3c_msg_ptr; /* Pointer to the current private message to send on the bus */
93 struct i3c_msg *i3c_msg_ctrl_ptr; /* Pointer to the private message that will be used by the
94 * control FIFO
95 */
96 struct i3c_msg *i3c_msg_status_ptr; /* Pointer to the private message that will be used by
97 * the status FIFO
98 */
99 struct i2c_msg *i2c_msg_ptr; /* Pointer to the current legacy message to send on the bus */
100 struct i2c_msg *i2c_msg_ctrl_ptr; /* Pointer to the I2C legavy message that will be used by
101 * the control FIFO
102 */
103 size_t num_msgs; /* Number of messages */
104 size_t ctrl_msg_idx; /* Current control message index */
105 size_t status_msg_idx; /* Current status message index */
106 size_t xfer_msg_idx; /* Current transfer message index */
107 size_t xfer_offset; /* Current message transfer offset */
108 uint32_t msg_type; /* Either LL_I3C_CONTROLLER_MTYPE_PRIVATE or
109 * LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C
110 */
111 };
112
113 struct i3c_stm32_config {
114 struct i3c_driver_config drv_cfg; /* I3C driver config */
115 I3C_TypeDef *i3c; /* Pointer to I3C module base addr */
116 irq_config_func_t irq_config_func; /* IRQ config function */
117 const struct stm32_pclken *pclken; /* Pointer to peripheral clock configuration */
118 const struct pinctrl_dev_config *pcfg; /* Pointer to pin control configuration */
119 };
120
121 struct i3c_stm32_data {
122 struct i3c_driver_data drv_data; /* I3C driver data */
123 enum i3c_stm32_msg_state msg_state; /* Current I3C bus state */
124 enum i3c_stm32_sf_state sf_state; /* Current I3C status FIFO state */
125 struct i3c_ccc_payload *ccc_payload; /* Current CCC message payload */
126 struct i3c_ccc_target_payload *
127 ccc_target_payload; /* Current target addressed by 2nd part of direct CCC command */
128 struct i3c_ccc_target_payload
129 *ccc_target_payload_sf; /* Current target addressed
130 * by 2nd part of direct CCC command used by the
131 status FIFO
132 */
133 size_t ccc_target_idx; /* Current target index, used for filling C-FIFO */
134 struct k_sem device_sync_sem; /* Sync between device communication messages */
135 struct k_mutex bus_mutex; /* Sync between transfers */
136 struct i3c_stm32_msg curr_msg;
137 uint8_t target_addr; /* Current target xfer address */
138 uint8_t num_msgs; /* Number of messages to send on bus */
139 #ifdef CONFIG_I3C_STM32_DMA
140 struct i3c_stm32_dma_stream dma_rx; /* RX DMA channel config */
141 struct i3c_stm32_dma_stream dma_tx; /* TX DMA channel config */
142 struct i3c_stm32_dma_stream dma_tc; /* Control FIFO DMA channel config */
143 struct i3c_stm32_dma_stream dma_rs; /* Status FIFO DMA channel config */
144 uint32_t *status_fifo; /* Pointer to the allocated region for status FIFO words */
145 uint32_t *control_fifo; /* Pointer to the allocated region for control FIFO words */
146 size_t fifo_len; /* The size in bytes for the allocated region for each FIFO */
147 #endif
148 uint64_t pid; /* Current DAA target PID */
149 size_t daa_rx_rcv; /* Number of RX bytes received during DAA */
150 uint8_t target_id; /* Target id */
151 #ifdef CONFIG_I3C_USE_IBI
152 uint32_t ibi_payload; /* Received ibi payload */
153 uint32_t ibi_payload_size; /* Received payload size */
154 uint32_t ibi_target_addr; /* Received target dynamic address */
155 struct {
156 uint8_t addr[4]; /* List of target addresses */
157 uint8_t num_addr; /* Number of valid addresses */
158 } ibi;
159 struct k_sem ibi_lock_sem; /* Semaphore used for ibi requests */
160 bool hj_pm_lock; /* Used as flag for setting pm */
161 #endif
162 };
163 /**
164 * Determine I3C bus mode from the i2c devices on the bus.
165 *
166 * Reads the LVR of all I2C devices and returns the I3C bus
167 * Mode.
168 *
169 * @param dev_list Pointer to device list
170 *
171 * @return @see enum i3c_bus_mode.
172 */
i3c_bus_mode(const struct i3c_dev_list * dev_list)173 static enum i3c_bus_mode i3c_bus_mode(const struct i3c_dev_list *dev_list)
174 {
175 enum i3c_bus_mode mode = I3C_BUS_MODE_PURE;
176
177 for (int i = 0; i < dev_list->num_i2c; i++) {
178 switch (I3C_LVR_I2C_DEV_IDX(dev_list->i2c[i].lvr)) {
179 case I3C_LVR_I2C_DEV_IDX_0:
180 if (mode < I3C_BUS_MODE_MIXED_FAST) {
181 mode = I3C_BUS_MODE_MIXED_FAST;
182 }
183 break;
184 case I3C_LVR_I2C_DEV_IDX_1:
185 if (mode < I3C_BUS_MODE_MIXED_LIMITED) {
186 mode = I3C_BUS_MODE_MIXED_LIMITED;
187 }
188 break;
189 case I3C_LVR_I2C_DEV_IDX_2:
190 if (mode < I3C_BUS_MODE_MIXED_SLOW) {
191 mode = I3C_BUS_MODE_MIXED_SLOW;
192 }
193 break;
194 default:
195 mode = I3C_BUS_MODE_INVALID;
196 break;
197 }
198 }
199 return mode;
200 }
201
get_i3c_lvr_ic_mode(const struct i3c_dev_list * dev_list)202 static int get_i3c_lvr_ic_mode(const struct i3c_dev_list *dev_list)
203 {
204 for (int i = 0; i < dev_list->num_i2c; i++) {
205 if (I3C_LVR_I2C_DEV_IDX(dev_list->i2c[i].lvr) == I3C_LVR_I2C_DEV_IDX_0) {
206 if (I3C_LVR_I2C_MODE(dev_list->i2c[i].lvr) == I3C_LVR_I2C_FM_MODE) {
207 return I3C_LVR_I2C_FM_MODE;
208 }
209 }
210 }
211 return I3C_LVR_I2C_FM_PLUS_MODE;
212 }
213
i3c_stm32_curr_msg_is_i3c(const struct device * dev)214 static bool i3c_stm32_curr_msg_is_i3c(const struct device *dev)
215 {
216 struct i3c_stm32_data *data = dev->data;
217 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
218
219 return (curr_msg->msg_type == LL_I3C_CONTROLLER_MTYPE_PRIVATE);
220 }
221
i3c_stm32_arbitration_header_config(const struct device * dev)222 static void i3c_stm32_arbitration_header_config(const struct device *dev)
223 {
224 struct i3c_stm32_data *data = dev->data;
225 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
226 const struct i3c_stm32_config *config = dev->config;
227 I3C_TypeDef *i3c = config->i3c;
228
229 if (i3c_stm32_curr_msg_is_i3c(dev)) {
230 if (curr_msg->i3c_msg_ctrl_ptr->flags & I3C_MSG_NBCH) {
231 /* Disable arbitration header for this transaction */
232 LL_I3C_DisableArbitrationHeader(i3c);
233 } else {
234 /* Enable arbitration header for this transaction */
235 LL_I3C_EnableArbitrationHeader(i3c);
236 }
237 }
238 }
239
i3c_stm32_curr_msg_init(const struct device * dev,struct i3c_msg * i3c_msgs,struct i2c_msg * i2c_msgs,uint8_t num_msgs,uint8_t tgt_addr)240 static int i3c_stm32_curr_msg_init(const struct device *dev, struct i3c_msg *i3c_msgs,
241 struct i2c_msg *i2c_msgs, uint8_t num_msgs, uint8_t tgt_addr)
242 {
243 struct i3c_stm32_data *data = dev->data;
244 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
245
246 /* Either should be NULL */
247 __ASSERT(!(i3c_msgs == NULL && i2c_msgs == NULL), "Both i3c_msgs and i2c_msgs are NULL");
248 __ASSERT(!(i3c_msgs != NULL && i2c_msgs != NULL),
249 "Both i3c_msgs and i2c_msgs are not NULL");
250
251 curr_msg->target_addr = tgt_addr;
252 curr_msg->xfer_offset = 0;
253 curr_msg->num_msgs = num_msgs;
254 curr_msg->ctrl_msg_idx = 0;
255 curr_msg->status_msg_idx = 0;
256 curr_msg->xfer_msg_idx = 0;
257
258 /* I3C private message */
259 if (i2c_msgs == NULL) {
260 curr_msg->msg_type = LL_I3C_CONTROLLER_MTYPE_PRIVATE;
261 curr_msg->i3c_msg_ptr = i3c_msgs;
262 curr_msg->i3c_msg_ctrl_ptr = i3c_msgs;
263 curr_msg->i3c_msg_status_ptr = i3c_msgs;
264 } else {
265 /* Legacy I2C message */
266 curr_msg->msg_type = LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C;
267 curr_msg->i2c_msg_ptr = i2c_msgs;
268 curr_msg->i2c_msg_ctrl_ptr = i2c_msgs;
269 }
270
271 i3c_stm32_arbitration_header_config(dev);
272 return 0;
273 }
274
i3c_stm32_curr_msg_control_get_dir(const struct device * dev)275 static int i3c_stm32_curr_msg_control_get_dir(const struct device *dev)
276 {
277 struct i3c_stm32_data *data = dev->data;
278 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
279
280 if (i3c_stm32_curr_msg_is_i3c(dev)) {
281 return (((curr_msg->i3c_msg_ctrl_ptr->flags & I3C_MSG_RW_MASK) == I3C_MSG_READ)
282 ? LL_I3C_DIRECTION_READ
283 : LL_I3C_DIRECTION_WRITE);
284 }
285
286 return (((curr_msg->i2c_msg_ctrl_ptr->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ)
287 ? LL_I3C_DIRECTION_READ
288 : LL_I3C_DIRECTION_WRITE);
289 }
290
i3c_stm32_curr_msg_control_get_len(const struct device * dev)291 static int i3c_stm32_curr_msg_control_get_len(const struct device *dev)
292 {
293 struct i3c_stm32_data *data = dev->data;
294 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
295
296 return (i3c_stm32_curr_msg_is_i3c(dev)) ? curr_msg->i3c_msg_ctrl_ptr->len
297 : curr_msg->i2c_msg_ctrl_ptr->len;
298 }
299
i3c_stm32_curr_msg_control_get_end(const struct device * dev)300 static int i3c_stm32_curr_msg_control_get_end(const struct device *dev)
301 {
302 struct i3c_stm32_data *data = dev->data;
303 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
304
305 return ((curr_msg->ctrl_msg_idx < (curr_msg->num_msgs - 1)) ? LL_I3C_GENERATE_RESTART
306 : LL_I3C_GENERATE_STOP);
307 }
308
i3c_stm32_curr_msg_control_next(const struct device * dev)309 static int i3c_stm32_curr_msg_control_next(const struct device *dev)
310 {
311 struct i3c_stm32_data *data = dev->data;
312 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
313
314 if (curr_msg->ctrl_msg_idx >= curr_msg->num_msgs) {
315 LOG_ERR("No more messages left");
316 return -EFAULT;
317 }
318
319 if (i3c_stm32_curr_msg_is_i3c(dev)) {
320 curr_msg->i3c_msg_ctrl_ptr++;
321 } else {
322 curr_msg->i2c_msg_ctrl_ptr++;
323 }
324
325 curr_msg->ctrl_msg_idx++;
326
327 return 0;
328 }
329
i3c_stm32_curr_msg_status_update_num_xfer(const struct device * dev,size_t num_xfer)330 static int i3c_stm32_curr_msg_status_update_num_xfer(const struct device *dev, size_t num_xfer)
331 {
332 struct i3c_stm32_data *data = dev->data;
333 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
334
335 if (curr_msg->status_msg_idx >= curr_msg->num_msgs) {
336 LOG_ERR("No more messages left");
337 return -EFAULT;
338 }
339
340 /* Legacy I2C messages do not have num_xfer */
341 if (i3c_stm32_curr_msg_is_i3c(dev)) {
342 curr_msg->i3c_msg_status_ptr->num_xfer = num_xfer;
343 }
344
345 return 0;
346 }
347
i3c_stm32_curr_msg_status_next(const struct device * dev)348 static int i3c_stm32_curr_msg_status_next(const struct device *dev)
349 {
350 struct i3c_stm32_data *data = dev->data;
351 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
352
353 if (curr_msg->status_msg_idx >= curr_msg->num_msgs) {
354 LOG_ERR("No more messages left");
355 return -EFAULT;
356 }
357
358 if (i3c_stm32_curr_msg_is_i3c(dev)) {
359 curr_msg->i3c_msg_status_ptr++;
360 curr_msg->status_msg_idx++;
361 }
362
363 return 0;
364 }
365
i3c_stm32_curr_msg_xfer_get_buf(const struct device * dev,uint8_t ** buf,uint32_t * len,size_t ** offset)366 static int i3c_stm32_curr_msg_xfer_get_buf(const struct device *dev, uint8_t **buf, uint32_t *len,
367 size_t **offset)
368 {
369 struct i3c_stm32_data *data = dev->data;
370 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
371
372 if (curr_msg->xfer_msg_idx >= curr_msg->num_msgs) {
373 LOG_ERR("No more messages left");
374 return -EFAULT;
375 }
376
377 if (i3c_stm32_curr_msg_is_i3c(dev)) {
378 *buf = curr_msg->i3c_msg_ptr->buf;
379 *len = curr_msg->i3c_msg_ptr->len;
380 } else {
381 *buf = curr_msg->i2c_msg_ptr->buf;
382 *len = curr_msg->i2c_msg_ptr->len;
383 }
384
385 *offset = &curr_msg->xfer_offset;
386
387 return 0;
388 }
389
390 /* This method is only used in DMA mode */
391 #ifdef CONFIG_I3C_STM32_DMA
i3c_stm32_curr_msg_xfer_is_read(const struct device * dev)392 static bool i3c_stm32_curr_msg_xfer_is_read(const struct device *dev)
393 {
394 struct i3c_stm32_data *data = dev->data;
395 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
396
397 if (curr_msg->xfer_msg_idx >= curr_msg->num_msgs) {
398 LOG_ERR("No more messages left");
399 return false;
400 }
401
402 if (i3c_stm32_curr_msg_is_i3c(dev)) {
403 return ((curr_msg->i3c_msg_ptr->flags & I3C_MSG_RW_MASK) == I3C_MSG_READ);
404 }
405
406 return ((curr_msg->i2c_msg_ptr->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ);
407 }
408 #endif /* CONFIG_I3C_STM32_DMA */
409
i3c_stm32_curr_msg_xfer_next(const struct device * dev)410 static int i3c_stm32_curr_msg_xfer_next(const struct device *dev)
411 {
412 struct i3c_stm32_data *data = dev->data;
413 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
414
415 if (curr_msg->xfer_msg_idx >= curr_msg->num_msgs) {
416 LOG_ERR("No more messages left");
417 return -EFAULT;
418 }
419
420 if (i3c_stm32_curr_msg_is_i3c(dev)) {
421 curr_msg->i3c_msg_ptr++;
422 } else {
423 curr_msg->i2c_msg_ptr++;
424 }
425
426 curr_msg->xfer_msg_idx++;
427 curr_msg->xfer_offset = 0;
428
429 return 0;
430 }
431
432 /* Activates the device I3C pinctrl and CLK */
i3c_stm32_activate(const struct device * dev)433 static int i3c_stm32_activate(const struct device *dev)
434 {
435 int ret;
436 struct i3c_stm32_config *config = (struct i3c_stm32_config *)dev->config;
437 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
438
439 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
440 if (ret < 0) {
441 return ret;
442 }
443
444 if (clock_control_on(clk, (clock_control_subsys_t)&config->pclken[0]) != 0) {
445 return -EIO;
446 }
447 return 0;
448 }
449
i3c_stm32_calc_scll_od_sclh_i2c(const struct device * dev,uint32_t i2c_bus_freq,uint32_t i3c_clock,uint8_t * scll_od,uint8_t * sclh_i2c)450 static int i3c_stm32_calc_scll_od_sclh_i2c(const struct device *dev, uint32_t i2c_bus_freq,
451 uint32_t i3c_clock, uint8_t *scll_od, uint8_t *sclh_i2c)
452 {
453 const struct i3c_stm32_config *config = dev->config;
454
455 if (i2c_bus_freq != 0) {
456 if (i2c_bus_freq > 400000) {
457 /* I2C bus is FM+ */
458 *scll_od = DIV_ROUND_UP(STM32_I3C_SCLL_OD_MIN_FMP_NS * i3c_clock,
459 1000000000ull) -
460 1;
461 *sclh_i2c = DIV_ROUND_UP(i3c_clock, i2c_bus_freq) - *scll_od - 2;
462 if (*sclh_i2c <
463 DIV_ROUND_UP(STM32_I3C_SCLH_I2C_MIN_FMP_NS * i3c_clock, 1000000000ull) -
464 1) {
465 LOG_ERR("Cannot find a combination of SCLL_OD and SCLH_I2C at "
466 "current I3C clock "
467 "frequency for FM+ I2C bus");
468 return -EINVAL;
469 }
470 } else {
471 /* I2C bus is FM */
472 *scll_od = DIV_ROUND_UP(STM32_I3C_SCLL_OD_MIN_FM_NS * i3c_clock,
473 1000000000ull) -
474 1;
475 *sclh_i2c = DIV_ROUND_UP(i3c_clock, i2c_bus_freq) - *scll_od - 2;
476 }
477
478 if (*sclh_i2c <
479 DIV_ROUND_UP(STM32_I3C_SCLH_I2C_MIN_FM_NS * i3c_clock, 1000000000ull) - 1) {
480 LOG_ERR("Cannot find a combination of SCLL_OD and SCLH_I2C at current I3C "
481 "clock "
482 "frequency for FM I2C bus");
483 return -EINVAL;
484 }
485 } else {
486 if (config->drv_cfg.dev_list.num_i2c > 0) {
487 enum i3c_bus_mode mode = i3c_bus_mode(&config->drv_cfg.dev_list);
488
489 if (mode == I3C_BUS_MODE_MIXED_FAST) {
490 if (get_i3c_lvr_ic_mode(&config->drv_cfg.dev_list) ==
491 I3C_LVR_I2C_FM_MODE) {
492 /* I2C bus is FM */
493 i2c_bus_freq = 400000;
494 *scll_od = DIV_ROUND_UP(STM32_I3C_SCLL_OD_MIN_FM_NS *
495 i3c_clock,
496 1000000000ull) -
497 1;
498 *sclh_i2c = DIV_ROUND_UP(i3c_clock, i2c_bus_freq) -
499 *scll_od - 2;
500 } else {
501 /* I2C bus is FM+ */
502 i2c_bus_freq = 1000000;
503 *scll_od = DIV_ROUND_UP(STM32_I3C_SCLL_OD_MIN_FMP_NS *
504 i3c_clock,
505 1000000000ull) -
506 1;
507 *sclh_i2c = DIV_ROUND_UP(i3c_clock, i2c_bus_freq) -
508 *scll_od - 2;
509 if (*sclh_i2c <
510 DIV_ROUND_UP(STM32_I3C_SCLH_I2C_MIN_FMP_NS * i3c_clock,
511 1000000000ull) -
512 1) {
513 LOG_ERR("Cannot find a combination of SCLL_OD and "
514 "SCLH_I2C at current I3C clock "
515 "frequency for FM+ I2C bus");
516 return -EINVAL;
517 }
518 }
519
520 if (*sclh_i2c <
521 DIV_ROUND_UP(STM32_I3C_SCLH_I2C_MIN_FM_NS * i3c_clock,
522 1000000000ull) -
523 1) {
524 LOG_ERR("Cannot find a combination of SCLL_OD and SCLH_I2C "
525 "at current I3C clock "
526 "frequency for FM I2C bus");
527 return -EINVAL;
528 }
529 } else {
530 return -EINVAL;
531 }
532 } else {
533 /* Assume no I2C devices on the bus */
534 *scll_od = DIV_ROUND_UP(STM32_I3C_SCLL_OD_MIN_I3C_NS * i3c_clock,
535 1000000000ull) -
536 1;
537 *sclh_i2c = 0;
538 }
539 }
540
541 LOG_DBG("TimingReg0: SCLL_OD = %d, SCLH_I2C = %d", *scll_od, *sclh_i2c);
542 return 0;
543 }
544
i3c_stm32_calc_scll_pp_sclh_i3c(uint32_t i3c_bus_freq,uint32_t i3c_clock,uint8_t * scll_pp,uint8_t * sclh_i3c)545 static int i3c_stm32_calc_scll_pp_sclh_i3c(uint32_t i3c_bus_freq, uint32_t i3c_clock,
546 uint8_t *scll_pp, uint8_t *sclh_i3c)
547 {
548 *sclh_i3c = DIV_ROUND_UP(STM32_I3C_SCLH_I3C_MIN_NS * i3c_clock, 1000000000ull) - 1;
549 *scll_pp = DIV_ROUND_UP(i3c_clock, i3c_bus_freq) - *sclh_i3c - 2;
550
551 if (*scll_pp < DIV_ROUND_UP(STM32_I3C_SCLL_PP_MIN_NS * i3c_clock, 1000000000ull) - 1) {
552 LOG_ERR("Cannot find a combination of SCLL_PP and SCLH_I3C at current I3C clock "
553 "frequency for specified I3C bus speed");
554 return -EINVAL;
555 }
556
557 LOG_DBG("TimingReg0: SCLL_PP = %d, SCLH_I3C = %d", *scll_pp, *sclh_i3c);
558 return 0;
559 }
560
i3c_stm32_config_clk_wave(const struct device * dev)561 static int i3c_stm32_config_clk_wave(const struct device *dev)
562 {
563 const struct i3c_stm32_config *cfg = dev->config;
564 struct i3c_stm32_data *data = dev->data;
565 const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
566 I3C_TypeDef *i3c = cfg->i3c;
567 uint32_t i3c_clock = 0;
568 uint32_t i2c_bus_freq = data->drv_data.ctrl_config.scl.i2c;
569 uint32_t i3c_bus_freq = data->drv_data.ctrl_config.scl.i3c;
570
571 if (clock_control_get_rate(clk, (clock_control_subsys_t)&cfg->pclken[0], &i3c_clock) < 0) {
572 LOG_ERR("Failed call clock_control_get_rate(pclken[0])");
573 return -EIO;
574 }
575
576 uint8_t scll_od = 0;
577 uint8_t sclh_i2c = 0;
578 uint8_t scll_pp = 0;
579 uint8_t sclh_i3c = 0;
580 uint32_t clk_wave = 0;
581 int ret;
582
583 LOG_DBG("I3C Clock = %u, I2C Bus Freq = %u, I3C Bus Freq = %u", i3c_clock, i2c_bus_freq,
584 i3c_bus_freq);
585
586 ret = i3c_stm32_calc_scll_od_sclh_i2c(dev, i2c_bus_freq, i3c_clock, &scll_od, &sclh_i2c);
587 if (ret != 0) {
588 LOG_ERR("Cannot calculate the timing for TimingReg0, err=%d", ret);
589 return ret;
590 }
591
592 ret = i3c_stm32_calc_scll_pp_sclh_i3c(i3c_bus_freq, i3c_clock, &scll_pp, &sclh_i3c);
593 if (ret != 0) {
594 LOG_ERR("Cannot calculate the timing for TimingReg0, err=%d", ret);
595 return ret;
596 }
597
598 clk_wave = ((uint32_t)sclh_i2c << 24) | ((uint32_t)scll_od << 16) |
599 ((uint32_t)sclh_i3c << 8) | (scll_pp);
600
601 LOG_DBG("TimigReg0 = 0x%08x", clk_wave);
602
603 LL_I3C_ConfigClockWaveForm(i3c, clk_wave);
604
605 return 0;
606 }
607 /**
608 * @brief Get current configuration of the I3C hardware.
609 *
610 * @param[in] dev Pointer to controller device driver instance.
611 * @param[in] type Type of configuration.
612 * @param[in,out] config Pointer to the configuration parameters.
613 *
614 * @retval 0 If successful.
615 * @retval -EIO General Input/Output errors.
616 * @retval -ENOSYS If not implemented.
617 */
i3c_stm32_config_get(const struct device * dev,enum i3c_config_type type,void * config)618 static int i3c_stm32_config_get(const struct device *dev, enum i3c_config_type type, void *config)
619 {
620 struct i3c_stm32_data *data = dev->data;
621
622 if ((type != I3C_CONFIG_CONTROLLER) || (config == NULL)) {
623 return -EINVAL;
624 }
625
626 (void)memcpy(config, &data->drv_data.ctrl_config, sizeof(data->drv_data.ctrl_config));
627
628 return 0;
629 }
630
i3c_stm32_config_ctrl_bus_char(const struct device * dev)631 static int i3c_stm32_config_ctrl_bus_char(const struct device *dev)
632 {
633 const struct i3c_stm32_config *config = dev->config;
634 struct i3c_stm32_data *data = dev->data;
635 const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
636 I3C_TypeDef *i3c = config->i3c;
637 uint32_t i3c_clock = 0;
638 uint32_t i2c_bus_freq = data->drv_data.ctrl_config.scl.i2c;
639
640 uint8_t free_timing = 0;
641 uint8_t aval = 0;
642
643 if (clock_control_get_rate(clk, (clock_control_subsys_t)&config->pclken[0], &i3c_clock) <
644 0) {
645 LOG_ERR("Failed call clock_control_get_rate(pclken[0])");
646 return -EIO;
647 }
648
649 /* Satisfying I3C start timing min timing will statisfy the rest of the conditions */
650
651 if (i2c_bus_freq != 0) {
652 if (i2c_bus_freq > 400000) {
653 /* Mixed bus with I2C FM+ device */
654 free_timing = (uint8_t)ceil(
655 (STM32_I3C_TBUF_FMP_MIN_NS * i3c_clock / 1e9 - 0.5) / 2);
656 } else {
657 /* Mixed bus with I2C FM device */
658 free_timing = (uint8_t)ceil(
659 (STM32_I3C_TBUF_FM_MIN_NS * i3c_clock / 1e9 - 0.5) / 2);
660 }
661 } else {
662 if (config->drv_cfg.dev_list.num_i2c > 0) {
663 enum i3c_bus_mode mode = i3c_bus_mode(&config->drv_cfg.dev_list);
664
665 if (mode == I3C_BUS_MODE_MIXED_FAST) {
666 if (get_i3c_lvr_ic_mode(&config->drv_cfg.dev_list) ==
667 I3C_LVR_I2C_FM_MODE) {
668 /* Mixed bus with I2C FM device */
669 free_timing = (uint8_t)ceil(
670 (STM32_I3C_TBUF_FM_MIN_NS * i3c_clock / 1e9 - 0.5) /
671 2);
672 } else {
673 /* Mixed bus with I2C FM+ device */
674 free_timing = (uint8_t)ceil(
675 (STM32_I3C_TBUF_FMP_MIN_NS * i3c_clock / 1e9 -
676 0.5) /
677 2);
678 }
679 } else {
680 return -EINVAL;
681 }
682 } else {
683 /* Pure I3C bus */
684 free_timing =
685 (uint8_t)ceil((STM32_I3C_TCAS_MIN_NS * i3c_clock / 1e9 - 0.5) / 2);
686 }
687 }
688
689 aval = DIV_ROUND_UP(1000ull * i3c_clock, 1000000000ull) - 1;
690
691 LL_I3C_SetFreeTiming(i3c, free_timing);
692 LL_I3C_SetAvalTiming(i3c, aval);
693 LL_I3C_SetDataHoldTime(i3c, LL_I3C_SDA_HOLD_TIME_1_5);
694
695 LOG_DBG("TimingReg1 = 0x%08x", LL_I3C_GetCtrlBusCharacteristic(i3c));
696
697 return 0;
698 }
699
700 /* Configures the I3C module in controller mode */
i3c_stm32_configure(const struct device * dev,enum i3c_config_type type,void * cfg)701 static int i3c_stm32_configure(const struct device *dev, enum i3c_config_type type, void *cfg)
702 {
703 int ret;
704
705 if (type == I3C_CONFIG_TARGET || type == I3C_CONFIG_CUSTOM) {
706 return -ENOTSUP;
707 }
708
709 struct i3c_stm32_data *data = dev->data;
710 struct i3c_config_controller *ctrl_cfg = cfg;
711
712 if ((ctrl_cfg->scl.i2c == 0U) || (ctrl_cfg->scl.i3c == 0U)) {
713 return -EINVAL;
714 }
715
716 data->drv_data.ctrl_config.scl.i3c = ctrl_cfg->scl.i3c;
717 data->drv_data.ctrl_config.scl.i2c = ctrl_cfg->scl.i2c;
718
719 ret = i3c_stm32_activate(dev);
720 if (ret != 0) {
721 LOG_ERR("Clock and GPIO could not be initialized for the I3C module, err=%d", ret);
722 return ret;
723 }
724
725 ret = i3c_stm32_config_clk_wave(dev);
726 if (ret != 0) {
727 LOG_ERR("TimigReg0 timing could not be calculated, err=%d", ret);
728 return ret;
729 }
730
731 ret = i3c_stm32_config_ctrl_bus_char(dev);
732 if (ret != 0) {
733 LOG_ERR("TimingReg1 timing could not be calculated, err=%d", ret);
734 return ret;
735 }
736
737 return 0;
738 }
739
i3c_stm32_i2c_configure(const struct device * dev,uint32_t config)740 static int i3c_stm32_i2c_configure(const struct device *dev, uint32_t config)
741 {
742 struct i3c_stm32_data *data = dev->data;
743 struct i3c_config_controller *ctrl_config = &data->drv_data.ctrl_config;
744
745 switch (I2C_SPEED_GET(config)) {
746 case I2C_SPEED_FAST:
747 ctrl_config->scl.i2c = 400000;
748 break;
749 case I2C_SPEED_FAST_PLUS:
750 ctrl_config->scl.i2c = 1000000;
751 break;
752 default:
753 return -EINVAL;
754 }
755
756 return 0;
757 }
758
759 /**
760 * @brief Find a registered I3C target device.
761 *
762 * This returns the I3C device descriptor of the I3C device
763 * matching the incoming @p id.
764 *
765 * @param dev Pointer to controller device driver instance.
766 * @param id Pointer to I3C device ID.
767 *
768 * @return @see i3c_device_find.
769 */
i3c_stm32_device_find(const struct device * dev,const struct i3c_device_id * id)770 static struct i3c_device_desc *i3c_stm32_device_find(const struct device *dev,
771 const struct i3c_device_id *id)
772 {
773 const struct i3c_stm32_config *config = dev->config;
774
775 return i3c_dev_list_find(&config->drv_cfg.dev_list, id);
776 }
777
778 #ifdef CONFIG_I3C_STM32_DMA
779
i3c_stm32_end_dma_requests(const struct device * dev)780 static void i3c_stm32_end_dma_requests(const struct device *dev)
781 {
782 const struct i3c_stm32_config *config = dev->config;
783 I3C_TypeDef *i3c = config->i3c;
784
785 LL_I3C_EnableIT_TXFNF(i3c);
786 LL_I3C_EnableIT_RXFNE(i3c);
787 LL_I3C_EnableIT_CFNF(i3c);
788 LL_I3C_EnableIT_SFNE(i3c);
789
790 LL_I3C_DisableDMAReq_TX(i3c);
791 LL_I3C_DisableDMAReq_RX(i3c);
792 LL_I3C_DisableDMAReq_Control(i3c);
793 LL_I3C_DisableDMAReq_Status(i3c);
794 }
795
i3c_stm32_prepare_dma_requests(const struct device * dev)796 static void i3c_stm32_prepare_dma_requests(const struct device *dev)
797 {
798 const struct i3c_stm32_config *config = dev->config;
799 I3C_TypeDef *i3c = config->i3c;
800
801 LL_I3C_DisableIT_TXFNF(i3c);
802 LL_I3C_DisableIT_RXFNE(i3c);
803 LL_I3C_DisableIT_CFNF(i3c);
804 LL_I3C_DisableIT_SFNE(i3c);
805
806 LL_I3C_EnableDMAReq_TX(i3c);
807 LL_I3C_EnableDMAReq_RX(i3c);
808 LL_I3C_EnableDMAReq_Control(i3c);
809 LL_I3C_EnableDMAReq_Status(i3c);
810 }
811
812 #endif /* CONFIG_I3C_STM32_DMA */
813
i3c_stm32_flush_all_fifo(const struct device * dev)814 static void i3c_stm32_flush_all_fifo(const struct device *dev)
815 {
816 const struct i3c_stm32_config *config = dev->config;
817 I3C_TypeDef *i3c = config->i3c;
818
819 LL_I3C_RequestTxFIFOFlush(i3c);
820 LL_I3C_RequestRxFIFOFlush(i3c);
821 LL_I3C_RequestControlFIFOFlush(i3c);
822 LL_I3C_RequestStatusFIFOFlush(i3c);
823 }
824
i3c_stm32_log_err_type(const struct device * dev)825 static void i3c_stm32_log_err_type(const struct device *dev)
826 {
827 const struct i3c_stm32_config *config = dev->config;
828 I3C_TypeDef *i3c = config->i3c;
829
830 if (LL_I3C_IsActiveFlag_ANACK(i3c)) {
831 LOG_ERR("Address NACK");
832 }
833
834 if (LL_I3C_IsActiveFlag_COVR(i3c)) {
835 LOG_ERR("Control/Status FIFO underrun/overrun");
836 }
837
838 if (LL_I3C_IsActiveFlag_DOVR(i3c)) {
839 LOG_ERR("TX/RX FIFO underrun/overrun");
840 }
841
842 if (LL_I3C_IsActiveFlag_DNACK(i3c)) {
843 LOG_ERR("Data NACK by target");
844 }
845
846 if (LL_I3C_IsActiveFlag_PERR(i3c)) {
847 switch (LL_I3C_GetMessageErrorCode(i3c)) {
848 case LL_I3C_CONTROLLER_ERROR_CE0:
849 LOG_ERR("Illegally formatted CCC detected");
850 break;
851 case LL_I3C_CONTROLLER_ERROR_CE1:
852 LOG_ERR("Data on bus is not as expected");
853 break;
854 case LL_I3C_CONTROLLER_ERROR_CE2:
855 LOG_ERR("No response to broadcast address");
856 break;
857 default:
858 LOG_ERR("Unsupported error detected");
859 break;
860 }
861 }
862 }
863
i3c_stm32_clear_err(const struct device * dev,bool is_i2c_xfer)864 static void i3c_stm32_clear_err(const struct device *dev, bool is_i2c_xfer)
865 {
866 struct i3c_stm32_data *data = dev->data;
867 const struct i3c_stm32_config *config = dev->config;
868 I3C_TypeDef *i3c = config->i3c;
869
870 i3c_stm32_flush_all_fifo(dev);
871
872 /* Re-enable arbirtation header after exiting from error caused by legacy I2C msg */
873 if (is_i2c_xfer) {
874 LL_I3C_EnableArbitrationHeader(i3c);
875 }
876
877 #ifdef CONFIG_I3C_STM32_DMA
878 i3c_stm32_end_dma_requests(dev);
879
880 k_heap_free(&stm32_i3c_fifo_heap, data->status_fifo);
881 k_heap_free(&stm32_i3c_fifo_heap, data->control_fifo);
882 #endif
883
884 data->msg_state = STM32_I3C_MSG_IDLE;
885 data->sf_state = STM32_I3C_SF_IDLE;
886
887 k_mutex_unlock(&data->bus_mutex);
888 }
889
890 /**
891 * @brief Fills the I3C TX FIFO from a given buffer
892 *
893 * @param buf The buffer to fill the TX FIFO from
894 * @param len The total buffer length
895 * @param offset Pointer to the offset from the beginning of buffer which will be incremented by the
896 * number of bytes sent to the TX FIFO
897 *
898 * @return Returns true if last byte was sent (TXLAST flag was set)
899 */
i3c_stm32_fill_tx_fifo(const struct device * dev,uint8_t * buf,size_t len,size_t * offset)900 static bool i3c_stm32_fill_tx_fifo(const struct device *dev, uint8_t *buf, size_t len,
901 size_t *offset)
902 {
903 const struct i3c_stm32_config *config = dev->config;
904 I3C_TypeDef *i3c = config->i3c;
905 bool is_last = false;
906
907 if (*offset >= len) {
908 return 0;
909 }
910
911 while (LL_I3C_IsActiveFlag_TXFNF(i3c)) {
912 if (LL_I3C_IsActiveFlag_TXLAST(i3c)) {
913 is_last = true;
914 }
915
916 if (*offset < len) {
917 LL_I3C_TransmitData8(i3c, buf[(*offset)++]);
918 }
919
920 if (is_last) {
921 return is_last;
922 }
923 }
924
925 return is_last;
926 }
927
928 /**
929 * @brief Drains the I3C RX FIFO from a given buffer
930 *
931 * @param buf The buffer to drain the RX FIFO to
932 * @param len The total buffer length
933 * @param offset Pointer to the offset from the beginning of buffer which will be incremented by the
934 * number of bytes drained from the RX FIFO
935 *
936 * @return Returns true if last byte was received (RXLAST flag was set)
937 */
i3c_stm32_drain_rx_fifo(const struct device * dev,uint8_t * buf,uint32_t len,size_t * offset)938 static bool i3c_stm32_drain_rx_fifo(const struct device *dev, uint8_t *buf, uint32_t len,
939 size_t *offset)
940 {
941 const struct i3c_stm32_config *config = dev->config;
942 I3C_TypeDef *i3c = config->i3c;
943 bool is_last = false;
944
945 if (*offset >= len) {
946 return 0;
947 }
948
949 while (LL_I3C_IsActiveFlag_RXFNE(i3c)) {
950 if (LL_I3C_IsActiveFlag_RXLAST(i3c)) {
951 is_last = true;
952 }
953
954 if (*offset < len) {
955 buf[(*offset)++] = LL_I3C_ReceiveData8(i3c);
956 }
957
958 if (is_last) {
959 return is_last;
960 }
961 }
962
963 return is_last;
964 }
965
966 /* Handles broadcast/direct CCCs except for ENTDAA */
i3c_stm32_do_ccc(const struct device * dev,struct i3c_ccc_payload * payload)967 static int i3c_stm32_do_ccc(const struct device *dev, struct i3c_ccc_payload *payload)
968 {
969 const struct i3c_stm32_config *config = dev->config;
970 struct i3c_stm32_data *data = dev->data;
971 I3C_TypeDef *i3c = config->i3c;
972
973 __ASSERT(dev != NULL, "I3C Device is NULL.");
974 __ASSERT(payload != NULL, "I3C Payload is NULL.");
975
976 if (payload->ccc.id == I3C_CCC_ENTDAA) {
977 return -EINVAL;
978 }
979
980 /* Check if payload has targets when sending a direct CCC */
981 if (!i3c_ccc_is_payload_broadcast(payload) &&
982 (payload->targets.payloads == NULL || payload->targets.num_targets == 0)) {
983 return -EINVAL;
984 }
985
986 if (payload->ccc.data_len > 0 && payload->ccc.data == NULL) {
987 return -EINVAL;
988 }
989
990 k_mutex_lock(&data->bus_mutex, K_FOREVER);
991
992 /* Disable Status FIFO and enable the RXTGTEND interrupt flag to detected early read
993 * termination from target during read CCC commands
994 */
995 LL_I3C_DisableStatusFIFO(i3c);
996 LL_I3C_EnableIT_RXTGTEND(i3c);
997
998 (void)pm_device_runtime_get(dev);
999
1000 /* Prevent the clocks to be stopped during the transaction */
1001 pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
1002
1003 /* Mark current transfer as CCC */
1004 data->msg_state = STM32_I3C_MSG_CCC;
1005 data->ccc_payload = payload;
1006 data->ccc_target_idx = 0;
1007 data->ccc_target_payload = payload->targets.payloads;
1008
1009 payload->ccc.num_xfer = 0;
1010
1011 for (size_t i = 0; i < payload->targets.num_targets; i++) {
1012 payload->targets.payloads[i].num_xfer = 0;
1013 }
1014
1015 /* Start CCC transfer */
1016 LL_I3C_ControllerHandleCCC(i3c, payload->ccc.id, payload->ccc.data_len,
1017 (i3c_ccc_is_payload_broadcast(payload)
1018 ? LL_I3C_GENERATE_STOP
1019 : LL_I3C_GENERATE_RESTART));
1020
1021 /* Wait for CCC to complete */
1022 if (k_sem_take(&data->device_sync_sem, STM32_I3C_TRANSFER_TIMEOUT) != 0) {
1023 LL_I3C_DisableIT_RXTGTEND(i3c);
1024 LL_I3C_EnableStatusFIFO(i3c);
1025 i3c_stm32_clear_err(dev, false);
1026 return -ETIMEDOUT;
1027 }
1028
1029 if (data->msg_state == STM32_I3C_MSG_ERR) {
1030 LL_I3C_DisableIT_RXTGTEND(i3c);
1031 LL_I3C_EnableStatusFIFO(i3c);
1032 i3c_stm32_clear_err(dev, false);
1033 return -EIO;
1034 }
1035
1036 LL_I3C_DisableIT_RXTGTEND(i3c);
1037 LL_I3C_EnableStatusFIFO(i3c);
1038 k_mutex_unlock(&data->bus_mutex);
1039
1040 return 0;
1041 }
1042
1043 /* Handles the ENTDAA CCC */
i3c_stm32_do_daa(const struct device * dev)1044 static int i3c_stm32_do_daa(const struct device *dev)
1045 {
1046 const struct i3c_stm32_config *config = dev->config;
1047 struct i3c_stm32_data *data = dev->data;
1048 I3C_TypeDef *i3c = config->i3c;
1049
1050 k_mutex_lock(&data->bus_mutex, K_FOREVER);
1051
1052 (void)pm_device_runtime_get(dev);
1053
1054 /* Prevent the clocks to be stopped during the transaction */
1055 pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
1056
1057 /* Mark current transfer as DAA */
1058 data->msg_state = STM32_I3C_MSG_DAA;
1059
1060 /* Disable TXFNF interrupt, the RXFNE interrupt will enable it once all PID bytes are
1061 * received
1062 */
1063 LL_I3C_DisableIT_TXFNF(i3c);
1064
1065 /* Start DAA */
1066 LL_I3C_ControllerHandleCCC(i3c, I3C_CCC_ENTDAA, 0, LL_I3C_GENERATE_STOP);
1067
1068 /* Wait for DAA to finish */
1069 if (k_sem_take(&data->device_sync_sem, STM32_I3C_TRANSFER_TIMEOUT) != 0) {
1070 return -ETIMEDOUT;
1071 }
1072
1073 if (data->msg_state == STM32_I3C_MSG_ERR) {
1074 i3c_stm32_clear_err(dev, false);
1075 /* Enable TXFNF interrupt in case an error occurred before it was enabled by RXFNE
1076 */
1077 LL_I3C_EnableIT_TXFNF(i3c);
1078 return -EIO;
1079 }
1080
1081 k_mutex_unlock(&data->bus_mutex);
1082
1083 return 0;
1084 }
1085
1086 #ifdef CONFIG_I3C_STM32_DMA
1087
i3c_stm32_dma_msg_control_fifo_config(const struct device * dev)1088 static int i3c_stm32_dma_msg_control_fifo_config(const struct device *dev)
1089 {
1090 struct i3c_stm32_data *data = dev->data;
1091 int ret;
1092
1093 data->dma_tc.blk_cfg.source_address = (uint32_t)data->control_fifo;
1094 data->dma_tc.blk_cfg.block_size = data->fifo_len;
1095
1096 ret = dma_config(data->dma_tc.dma_dev, data->dma_tc.dma_channel, &data->dma_tc.dma_cfg);
1097
1098 if (ret != 0) {
1099 LOG_ERR("Control DMA config error, err=%d", ret);
1100 return -EINVAL;
1101 }
1102
1103 if (dma_start(data->dma_tc.dma_dev, data->dma_tc.dma_channel)) {
1104 LOG_ERR("Control DMA start failed");
1105 return -EFAULT;
1106 }
1107
1108 return 0;
1109 }
1110
i3c_stm32_dma_msg_status_fifo_config(const struct device * dev)1111 static int i3c_stm32_dma_msg_status_fifo_config(const struct device *dev)
1112 {
1113 struct i3c_stm32_data *data = dev->data;
1114 int ret;
1115
1116 data->dma_rs.blk_cfg.dest_address = (uint32_t)data->status_fifo;
1117 data->dma_rs.blk_cfg.block_size = data->fifo_len;
1118
1119 ret = dma_config(data->dma_rs.dma_dev, data->dma_rs.dma_channel, &data->dma_rs.dma_cfg);
1120
1121 if (ret != 0) {
1122 LOG_ERR("Status DMA config error, err=%d", ret);
1123 return -EINVAL;
1124 }
1125
1126 if (dma_start(data->dma_rs.dma_dev, data->dma_rs.dma_channel)) {
1127 LOG_ERR("Status DMA start failed");
1128 return -EFAULT;
1129 }
1130
1131 return 0;
1132 }
1133
i3c_stm32_dma_msg_config(const struct device * dev,uint32_t buf_addr,size_t buf_len)1134 static int i3c_stm32_dma_msg_config(const struct device *dev, uint32_t buf_addr, size_t buf_len)
1135 {
1136 struct i3c_stm32_dma_stream *dma_stream;
1137 struct i3c_stm32_data *data = dev->data;
1138 int ret;
1139
1140 if (i3c_stm32_curr_msg_xfer_is_read(dev)) {
1141 dma_stream = &(data->dma_rx);
1142 dma_stream->blk_cfg.dest_address = buf_addr;
1143 } else {
1144 dma_stream = &(data->dma_tx);
1145 dma_stream->blk_cfg.source_address = buf_addr;
1146 }
1147
1148 i3c_stm32_arbitration_header_config(dev);
1149
1150 dma_stream->blk_cfg.block_size = buf_len;
1151 ret = dma_config(dma_stream->dma_dev, dma_stream->dma_channel, &dma_stream->dma_cfg);
1152
1153 if (ret != 0) {
1154 LOG_ERR("TX/RX DMA config error, err=%d", ret);
1155 return -EINVAL;
1156 }
1157
1158 if (dma_start(dma_stream->dma_dev, dma_stream->dma_channel)) {
1159 LOG_ERR("TX/RX DMA start failed");
1160 return -EFAULT;
1161 }
1162 return 0;
1163 }
1164 #endif
1165
i3c_stm32_transfer_begin(const struct device * dev)1166 static int i3c_stm32_transfer_begin(const struct device *dev)
1167 {
1168 struct i3c_stm32_data *data = dev->data;
1169 const struct i3c_stm32_config *config = dev->config;
1170 I3C_TypeDef *i3c = config->i3c;
1171
1172 data->msg_state = STM32_I3C_MSG;
1173 data->sf_state = STM32_I3C_SF;
1174
1175 (void)pm_device_runtime_get(dev);
1176
1177 /* Prevent the clocks to be stopped during the transaction */
1178 pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
1179
1180 #ifdef CONFIG_I3C_STM32_DMA
1181 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
1182
1183 data->fifo_len = curr_msg->num_msgs * sizeof(uint32_t);
1184 data->control_fifo = k_heap_alloc(&stm32_i3c_fifo_heap, data->fifo_len, K_FOREVER);
1185 data->status_fifo = k_heap_alloc(&stm32_i3c_fifo_heap, data->fifo_len, K_FOREVER);
1186 int ret;
1187
1188 /* Prepare all control words for all messages on the transfer */
1189 for (size_t i = 0; i < curr_msg->num_msgs; i++) {
1190 WRITE_REG(data->control_fifo[i],
1191 ((curr_msg->target_addr << I3C_CR_ADD_Pos) |
1192 i3c_stm32_curr_msg_control_get_len(dev) |
1193 i3c_stm32_curr_msg_control_get_dir(dev) | curr_msg->msg_type |
1194 i3c_stm32_curr_msg_control_get_end(dev)) &
1195 (I3C_CR_ADD | I3C_CR_DCNT | I3C_CR_RNW | I3C_CR_MTYPE |
1196 I3C_CR_MEND));
1197
1198 i3c_stm32_curr_msg_control_next(dev);
1199 }
1200
1201 /* Configure DMA for the first message only, DMA callback will take care of the rest */
1202 uint8_t *buf = NULL;
1203 size_t *offset = 0;
1204 uint32_t len = 0;
1205
1206 i3c_stm32_curr_msg_xfer_get_buf(dev, &buf, &len, &offset);
1207
1208 ret = i3c_stm32_dma_msg_config(dev, (uint32_t)buf, len);
1209 if (ret != 0) {
1210 return ret;
1211 }
1212
1213 ret = i3c_stm32_dma_msg_control_fifo_config(dev);
1214 if (ret != 0) {
1215 return ret;
1216 }
1217
1218 ret = i3c_stm32_dma_msg_status_fifo_config(dev);
1219 if (ret != 0) {
1220 return ret;
1221 }
1222
1223 i3c_stm32_prepare_dma_requests(dev);
1224 #endif
1225
1226 /* Begin transmission */
1227 LL_I3C_RequestTransfer(i3c);
1228
1229 /* Wait for whole transfer to complete */
1230 if (k_sem_take(&data->device_sync_sem, STM32_I3C_TRANSFER_TIMEOUT) != 0) {
1231 return -ETIMEDOUT;
1232 }
1233
1234 if (data->msg_state == STM32_I3C_MSG_ERR) {
1235 return -EIO;
1236 }
1237
1238 return 0;
1239 }
1240
1241 /* Handles the controller private read/write transfers */
i3c_stm32_i3c_transfer(const struct device * dev,struct i3c_device_desc * target,struct i3c_msg * msgs,uint8_t num_msgs)1242 static int i3c_stm32_i3c_transfer(const struct device *dev, struct i3c_device_desc *target,
1243 struct i3c_msg *msgs, uint8_t num_msgs)
1244 {
1245 struct i3c_stm32_data *data = dev->data;
1246 int ret;
1247
1248 /* Verify all messages */
1249 for (size_t i = 0; i < num_msgs; i++) {
1250 if (msgs[i].buf == NULL) {
1251 return -EINVAL;
1252 }
1253 if ((msgs[i].flags & I3C_MSG_HDR) && (msgs[i].hdr_mode != 0)) {
1254 return -ENOTSUP;
1255 }
1256 }
1257
1258 k_mutex_lock(&data->bus_mutex, K_FOREVER);
1259 ret = i3c_stm32_curr_msg_init(dev, msgs, NULL, num_msgs, target->dynamic_addr);
1260 if (ret != 0) {
1261 i3c_stm32_clear_err(dev, false);
1262 LOG_ERR("Failed to initialize transfer messages, err=%d", ret);
1263 return ret;
1264 }
1265
1266 ret = i3c_stm32_transfer_begin(dev);
1267 if (ret != 0) {
1268 i3c_stm32_clear_err(dev, false);
1269 LOG_ERR("Failed to transfer messages, err=%d", ret);
1270 return ret;
1271 }
1272
1273 #ifdef CONFIG_I3C_STM32_DMA
1274 /* Fill the num_xfer for each message from the status FIFO */
1275 for (size_t i = 0; i < num_msgs; i++) {
1276 msgs[i].num_xfer = READ_BIT(data->status_fifo[i], I3C_SR_XDCNT);
1277 }
1278
1279 k_heap_free(&stm32_i3c_fifo_heap, data->control_fifo);
1280 k_heap_free(&stm32_i3c_fifo_heap, data->status_fifo);
1281
1282 i3c_stm32_end_dma_requests(dev);
1283 #endif
1284
1285 k_mutex_unlock(&data->bus_mutex);
1286
1287 return 0;
1288 }
1289
i3c_stm32_i2c_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t addr)1290 static int i3c_stm32_i2c_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
1291 uint16_t addr)
1292 {
1293 struct i3c_stm32_data *data = dev->data;
1294 const struct i3c_stm32_config *config = dev->config;
1295 I3C_TypeDef *i3c = config->i3c;
1296 int ret;
1297
1298 /* Verify all messages */
1299 for (size_t i = 0; i < num_msgs; i++) {
1300 if (msgs[i].buf == NULL) {
1301 return -EINVAL;
1302 }
1303 if (msgs[i].flags & I2C_MSG_ADDR_10_BITS) {
1304 LOG_ERR("10-bit addressing mode is not supported");
1305 return -ENOTSUP;
1306 }
1307 }
1308
1309 k_mutex_lock(&data->bus_mutex, K_FOREVER);
1310
1311 /* Disable arbitration header for all I2C messages in case no I3C devices exist on bus */
1312 LL_I3C_DisableArbitrationHeader(i3c);
1313
1314 ret = i3c_stm32_curr_msg_init(dev, NULL, msgs, num_msgs, addr);
1315 if (ret != 0) {
1316 i3c_stm32_clear_err(dev, false);
1317 LOG_ERR("Failed to initialize transfer messages, err=%d", ret);
1318 return ret;
1319 }
1320
1321 ret = i3c_stm32_transfer_begin(dev);
1322 if (ret != 0) {
1323 i3c_stm32_clear_err(dev, false);
1324 LOG_ERR("Failed to transfer messages, err=%d", ret);
1325 return ret;
1326 }
1327
1328 LL_I3C_EnableArbitrationHeader(i3c);
1329
1330 #ifdef CONFIG_I3C_STM32_DMA
1331 k_heap_free(&stm32_i3c_fifo_heap, data->control_fifo);
1332 k_heap_free(&stm32_i3c_fifo_heap, data->status_fifo);
1333
1334 i3c_stm32_end_dma_requests(dev);
1335 #endif
1336
1337 k_mutex_unlock(&data->bus_mutex);
1338
1339 return 0;
1340 }
1341
1342 #ifdef CONFIG_PM_DEVICE
i3c_stm32_suspend(const struct device * dev)1343 static int i3c_stm32_suspend(const struct device *dev)
1344 {
1345 int ret;
1346 const struct i3c_stm32_config *cfg = dev->config;
1347 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
1348
1349 /* Disable device clock. */
1350 ret = clock_control_off(clk, (clock_control_subsys_t)&cfg->pclken[0]);
1351 if (ret < 0) {
1352 LOG_ERR("failure disabling I3C clock");
1353 return ret;
1354 }
1355
1356 /* Move pins to sleep state */
1357 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_SLEEP);
1358 if (ret == -ENOENT) {
1359 /* Warn but don't block suspend */
1360 LOG_WRN("I3C pinctrl sleep state not available");
1361 } else if (ret < 0) {
1362 return ret;
1363 }
1364
1365 return 0;
1366 }
1367
i3c_stm32_pm_action(const struct device * dev,enum pm_device_action action)1368 static int i3c_stm32_pm_action(const struct device *dev, enum pm_device_action action)
1369 {
1370 int err;
1371
1372 switch (action) {
1373 case PM_DEVICE_ACTION_RESUME:
1374 err = i3c_stm32_activate(dev);
1375 break;
1376 case PM_DEVICE_ACTION_SUSPEND:
1377 err = i3c_stm32_suspend(dev);
1378 break;
1379 default:
1380 return -ENOTSUP;
1381 }
1382
1383 return err;
1384 }
1385 #endif
1386
1387 #ifdef CONFIG_I3C_STM32_DMA
i3c_stm32_dma_stream_config(const struct device * dev,struct i3c_stm32_dma_stream * dma_stream,uint64_t src_addr,uint64_t dst_addr)1388 static int i3c_stm32_dma_stream_config(const struct device *dev,
1389 struct i3c_stm32_dma_stream *dma_stream, uint64_t src_addr,
1390 uint64_t dst_addr)
1391 {
1392 if (dma_stream->dma_dev != NULL) {
1393 if (!device_is_ready(dma_stream->dma_dev)) {
1394 return -ENODEV;
1395 }
1396 }
1397
1398 memset(&dma_stream->blk_cfg, 0, sizeof(dma_stream->blk_cfg));
1399
1400 dma_stream->blk_cfg.source_address = src_addr;
1401
1402 dma_stream->blk_cfg.dest_address = dst_addr;
1403
1404 if (dma_stream->src_addr_increment) {
1405 dma_stream->blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT;
1406 } else {
1407 dma_stream->blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
1408 }
1409
1410 if (dma_stream->dst_addr_increment) {
1411 dma_stream->blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT;
1412 } else {
1413 dma_stream->blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
1414 }
1415
1416 dma_stream->blk_cfg.source_reload_en = 0;
1417 dma_stream->blk_cfg.dest_reload_en = 0;
1418 dma_stream->blk_cfg.fifo_mode_control = dma_stream->fifo_threshold;
1419
1420 dma_stream->dma_cfg.head_block = &dma_stream->blk_cfg;
1421 dma_stream->dma_cfg.user_data = (void *)dev;
1422
1423 return 0;
1424 }
1425
1426 /* Initializes the I3C DMA */
i3c_stm32_init_dma(const struct device * dev)1427 static int i3c_stm32_init_dma(const struct device *dev)
1428 {
1429 struct i3c_stm32_data *data = dev->data;
1430 int err;
1431 const struct i3c_stm32_config *config = dev->config;
1432 I3C_TypeDef *i3c = config->i3c;
1433
1434 /*Configure DMA RX */
1435 err = i3c_stm32_dma_stream_config(
1436 dev, &data->dma_rx, LL_I3C_DMA_GetRegAddr(i3c, LL_I3C_DMA_REG_DATA_RECEIVE_BYTE),
1437 0);
1438 if (err != 0) {
1439 return err;
1440 }
1441
1442 /*Configure DMA RS */
1443 err = i3c_stm32_dma_stream_config(dev, &data->dma_rs,
1444 LL_I3C_DMA_GetRegAddr(i3c, LL_I3C_DMA_REG_STATUS), 0);
1445 if (err != 0) {
1446 return err;
1447 }
1448
1449 /*Configure DMA TX */
1450 err = i3c_stm32_dma_stream_config(
1451 dev, &data->dma_tx, 0,
1452 LL_I3C_DMA_GetRegAddr(i3c, LL_I3C_DMA_REG_DATA_TRANSMIT_BYTE));
1453 if (err != 0) {
1454 return err;
1455 }
1456
1457 /*Configure DMA TC */
1458 err = i3c_stm32_dma_stream_config(dev, &data->dma_tc, 0,
1459 LL_I3C_DMA_GetRegAddr(i3c, LL_I3C_DMA_REG_CONTROL));
1460 if (err != 0) {
1461 return err;
1462 }
1463
1464 return err;
1465 }
1466 #endif
1467
i3c_stm32_controller_init(const struct device * dev)1468 static void i3c_stm32_controller_init(const struct device *dev)
1469 {
1470 struct i3c_stm32_data *data = dev->data;
1471 const struct i3c_stm32_config *config = dev->config;
1472 I3C_TypeDef *i3c = config->i3c;
1473
1474 /* Configure FIFO */
1475 LL_I3C_SetRxFIFOThreshold(i3c, LL_I3C_RXFIFO_THRESHOLD_1_4);
1476 LL_I3C_SetTxFIFOThreshold(i3c, LL_I3C_TXFIFO_THRESHOLD_1_4);
1477 LL_I3C_EnableControlFIFO(i3c);
1478 LL_I3C_EnableStatusFIFO(i3c);
1479
1480 /* I3C Initialization */
1481 LL_I3C_SetMode(i3c, LL_I3C_MODE_CONTROLLER);
1482 LL_I3C_SetStallTime(i3c, 0x00);
1483 LL_I3C_DisableStallACK(i3c);
1484 LL_I3C_DisableStallParityCCC(i3c);
1485 LL_I3C_DisableStallParityData(i3c);
1486 LL_I3C_DisableStallTbit(i3c);
1487 LL_I3C_DisableHighKeeperSDA(i3c);
1488 LL_I3C_SetControllerActivityState(i3c, LL_I3C_OWN_ACTIVITY_STATE_0);
1489
1490 LL_I3C_Enable(i3c);
1491
1492 LL_I3C_EnableIT_FC(i3c);
1493 LL_I3C_EnableIT_CFNF(i3c);
1494 LL_I3C_EnableIT_SFNE(i3c);
1495 LL_I3C_EnableIT_RXFNE(i3c);
1496 LL_I3C_EnableIT_TXFNF(i3c);
1497 LL_I3C_EnableIT_ERR(i3c);
1498 LL_I3C_EnableIT_WKP(i3c);
1499
1500 #ifdef CONFIG_I3C_USE_IBI
1501 LL_I3C_EnableIT_IBI(i3c);
1502 LL_I3C_EnableIT_HJ(i3c);
1503 #endif
1504
1505 /* Bus will be idle initially */
1506 data->msg_state = STM32_I3C_MSG_IDLE;
1507 data->sf_state = STM32_I3C_SF_IDLE;
1508 data->target_id = 0;
1509 #ifdef CONFIG_I3C_USE_IBI
1510 data->ibi_payload = 0;
1511 data->ibi_payload_size = 0;
1512 data->ibi_target_addr = 0;
1513 #endif
1514 }
1515
1516 /* Initializes the I3C device and I3C bus */
i3c_stm32_init(const struct device * dev)1517 static int i3c_stm32_init(const struct device *dev)
1518 {
1519 const struct i3c_stm32_config *config = dev->config;
1520 struct i3c_stm32_data *data = dev->data;
1521 I3C_TypeDef *i3c = config->i3c;
1522 int ret;
1523
1524 #ifdef CONFIG_I3C_STM32_DMA
1525 ret = i3c_stm32_init_dma(dev);
1526
1527 if (ret != 0) {
1528 LOG_ERR("Failed to init I3C DMA, err=%d", ret);
1529 return ret;
1530 }
1531 #endif
1532
1533 k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT);
1534
1535 /* initialize mutex used when multiple transfers
1536 * are taking place to guarantee that each one is
1537 * atomic and has exclusive access to the I3C bus.
1538 */
1539 k_mutex_init(&data->bus_mutex);
1540
1541 /* initialize semaphore used when multiple ibi requests are taking place */
1542 #ifdef CONFIG_I3C_USE_IBI
1543 k_sem_init(&data->ibi_lock_sem, 1, 1);
1544 #endif
1545 ret = i3c_addr_slots_init(dev);
1546 if (ret != 0) {
1547 LOG_ERR("Addr slots init fail, err=%d", ret);
1548 return ret;
1549 }
1550
1551 config->irq_config_func(dev);
1552 i3c_stm32_configure(dev, I3C_CONFIG_CONTROLLER, &data->drv_data.ctrl_config);
1553 i3c_stm32_controller_init(dev);
1554
1555 /* Perform bus initialization only if there are devices that already exist on the bus */
1556 if (config->drv_cfg.dev_list.num_i3c > 0) {
1557 ret = i3c_bus_init(dev, &config->drv_cfg.dev_list);
1558 if (ret != 0) {
1559 LOG_ERR("Failed to do i3c bus init, err=%d", ret);
1560 return ret;
1561 }
1562 }
1563
1564 #ifdef CONFIG_I3C_USE_IBI
1565 LL_I3C_EnableHJAck(i3c);
1566 hj_pm_lock = true;
1567 (void)pm_device_runtime_get(dev);
1568 pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
1569 #endif
1570
1571 return 0;
1572 }
1573
i3c_stm32_event_isr_tx(const struct device * dev)1574 static void i3c_stm32_event_isr_tx(const struct device *dev)
1575 {
1576 const struct i3c_stm32_config *config = dev->config;
1577 struct i3c_stm32_data *data = dev->data;
1578 I3C_TypeDef *i3c = config->i3c;
1579
1580 switch (data->msg_state) {
1581 case STM32_I3C_MSG: {
1582 uint8_t *buf = NULL;
1583 size_t *offset = NULL;
1584 uint32_t len = 0;
1585
1586 i3c_stm32_curr_msg_xfer_get_buf(dev, &buf, &len, &offset);
1587
1588 if (i3c_stm32_fill_tx_fifo(dev, buf, len, offset)) {
1589 i3c_stm32_curr_msg_xfer_next(dev);
1590 }
1591
1592 break;
1593 }
1594 case STM32_I3C_MSG_DAA: {
1595 struct i3c_device_desc *target;
1596 uint8_t bcr;
1597 uint8_t dcr;
1598 uint8_t dyn_addr = 0;
1599 int ret;
1600
1601 bcr = (data->pid >> 8) & 0xFF;
1602 dcr = data->pid & 0xFF;
1603 data->pid >>= 16;
1604
1605 /* Find the device in the device list */
1606 ret = i3c_dev_list_daa_addr_helper(&data->drv_data.attached_dev.addr_slots,
1607 &config->drv_cfg.dev_list, data->pid, false,
1608 false, &target, &dyn_addr);
1609 if (ret != 0) {
1610 /* TODO: figure out what is the correct sequence to exit form this error
1611 * It is expected that a TX overrun error to occur which triggers err isr
1612 */
1613 LOG_ERR("No dynamic address could be assigned to target");
1614
1615 return;
1616 }
1617
1618 /* Put the new dynamic address in TX FIFO for transmission */
1619 LL_I3C_TransmitData8(i3c, dyn_addr);
1620
1621 if (target != NULL) {
1622 /* Update target descriptor */
1623 target->dynamic_addr = dyn_addr;
1624 target->bcr = bcr;
1625 target->dcr = dcr;
1626 }
1627
1628 /* Mark the address as used */
1629 i3c_addr_slots_mark_i3c(&data->drv_data.attached_dev.addr_slots, dyn_addr);
1630
1631 /* Mark the static address as free */
1632 if ((target != NULL) && (target->static_addr != 0) &&
1633 (dyn_addr != target->static_addr)) {
1634 i3c_addr_slots_mark_free(&data->drv_data.attached_dev.addr_slots, dyn_addr);
1635 }
1636
1637 break;
1638 }
1639 case STM32_I3C_MSG_CCC: {
1640 struct i3c_ccc_payload *payload = data->ccc_payload;
1641
1642 if (payload->ccc.num_xfer < payload->ccc.data_len) {
1643 LL_I3C_TransmitData8(i3c, payload->ccc.data[payload->ccc.num_xfer++]);
1644 }
1645 break;
1646 }
1647 case STM32_I3C_MSG_CCC_P2: {
1648 struct i3c_ccc_target_payload *target = data->ccc_target_payload;
1649
1650 if (target->num_xfer < target->data_len) {
1651 LL_I3C_TransmitData8(i3c, target->data[target->num_xfer++]);
1652
1653 /* After sending all bytes for current target, move on to the next target */
1654 if (target->num_xfer == target->data_len) {
1655 data->ccc_target_payload++;
1656 }
1657 }
1658 break;
1659 }
1660 default:
1661 break;
1662 }
1663 }
1664
i3c_stm32_event_isr_rx(const struct device * dev)1665 static void i3c_stm32_event_isr_rx(const struct device *dev)
1666 {
1667 const struct i3c_stm32_config *config = dev->config;
1668 struct i3c_stm32_data *data = dev->data;
1669 I3C_TypeDef *i3c = config->i3c;
1670
1671 switch (data->msg_state) {
1672 case STM32_I3C_MSG: {
1673 uint8_t *buf = NULL;
1674 size_t *offset = NULL;
1675 uint32_t len = 0;
1676
1677 i3c_stm32_curr_msg_xfer_get_buf(dev, &buf, &len, &offset);
1678 if (i3c_stm32_drain_rx_fifo(dev, buf, len, offset)) {
1679 i3c_stm32_curr_msg_xfer_next(dev);
1680 }
1681
1682 break;
1683 }
1684 case STM32_I3C_MSG_DAA: {
1685 data->pid <<= 8;
1686 data->pid |= LL_I3C_ReceiveData8(i3c);
1687
1688 data->daa_rx_rcv++;
1689
1690 /* After receiving 8 PID bytes from DAA, enable TXFNF interrupt to send the dynamic
1691 * address
1692 */
1693 if (data->daa_rx_rcv == 8) {
1694 LL_I3C_EnableIT_TXFNF(i3c);
1695 data->daa_rx_rcv = 0;
1696 }
1697 break;
1698 }
1699 case STM32_I3C_MSG_CCC_P2: {
1700 struct i3c_ccc_target_payload *target = data->ccc_target_payload;
1701
1702 if (target->num_xfer < target->data_len) {
1703 target->data[target->num_xfer++] = LL_I3C_ReceiveData8(i3c);
1704
1705 /* After receiving all bytes for current target, move on to the next target
1706 */
1707 if (target->num_xfer == target->data_len) {
1708 data->ccc_target_payload++;
1709 }
1710 }
1711 break;
1712 }
1713 default:
1714 break;
1715 }
1716 }
1717
i3c_stm32_event_isr_cf(const struct device * dev)1718 static void i3c_stm32_event_isr_cf(const struct device *dev)
1719 {
1720 const struct i3c_stm32_config *config = dev->config;
1721 struct i3c_stm32_data *data = dev->data;
1722 struct i3c_stm32_msg *curr_msg = &data->curr_msg;
1723 I3C_TypeDef *i3c = config->i3c;
1724
1725 switch (data->msg_state) {
1726 case STM32_I3C_MSG: {
1727 LL_I3C_ControllerHandleMessage(
1728 i3c, curr_msg->target_addr, i3c_stm32_curr_msg_control_get_len(dev),
1729 i3c_stm32_curr_msg_control_get_dir(dev), curr_msg->msg_type,
1730 i3c_stm32_curr_msg_control_get_end(dev));
1731
1732 i3c_stm32_curr_msg_control_next(dev);
1733 break;
1734 }
1735 case STM32_I3C_MSG_CCC:
1736 case STM32_I3C_MSG_CCC_P2: {
1737 struct i3c_ccc_payload *payload = data->ccc_payload;
1738 struct i3c_ccc_target_payload *target;
1739
1740 if (data->ccc_target_idx < payload->targets.num_targets) {
1741 target = &payload->targets.payloads[data->ccc_target_idx++];
1742
1743 LL_I3C_ControllerHandleMessage(
1744 i3c, target->addr, target->data_len,
1745 target->rnw ? LL_I3C_DIRECTION_READ : LL_I3C_DIRECTION_WRITE,
1746 LL_I3C_CONTROLLER_MTYPE_DIRECT,
1747 (data->ccc_target_idx == payload->targets.num_targets)
1748 ? LL_I3C_GENERATE_STOP
1749 : LL_I3C_GENERATE_RESTART);
1750
1751 /* Change state to second part of CCC communication */
1752 if (data->msg_state == STM32_I3C_MSG_CCC) {
1753 data->msg_state = STM32_I3C_MSG_CCC_P2;
1754 }
1755 }
1756 break;
1757 }
1758 default:
1759 break;
1760 }
1761 }
1762
1763 /* Handles the I3C event ISR */
i3c_stm32_event_isr(void * arg)1764 static void i3c_stm32_event_isr(void *arg)
1765 {
1766 const struct device *dev = (const struct device *)arg;
1767
1768 const struct i3c_stm32_config *config = dev->config;
1769 struct i3c_stm32_data *data = dev->data;
1770 I3C_TypeDef *i3c = config->i3c;
1771
1772 /* TX FIFO not full handler */
1773 if (LL_I3C_IsActiveFlag_TXFNF(i3c) && LL_I3C_IsEnabledIT_TXFNF(i3c)) {
1774 i3c_stm32_event_isr_tx(dev);
1775 }
1776
1777 /* RX FIFO not empty handler */
1778 if (LL_I3C_IsActiveFlag_RXFNE(i3c) && LL_I3C_IsEnabledIT_RXFNE(i3c)) {
1779 i3c_stm32_event_isr_rx(dev);
1780 }
1781
1782 /* Control FIFO not full handler */
1783 if (LL_I3C_IsActiveFlag_CFNF(i3c) && LL_I3C_IsEnabledIT_CFNF(i3c)) {
1784 i3c_stm32_event_isr_cf(dev);
1785 }
1786
1787 /* Status FIFO not empty handler */
1788 if (LL_I3C_IsActiveFlag_SFNE(i3c) && LL_I3C_IsEnabledIT_SFNE(i3c)) {
1789
1790 if (data->msg_state == STM32_I3C_MSG) {
1791 size_t num_xfer = LL_I3C_GetXferDataCount(i3c);
1792
1793 i3c_stm32_curr_msg_status_update_num_xfer(dev, num_xfer);
1794 i3c_stm32_curr_msg_status_next(dev);
1795 } else {
1796 /* Read and discard the status FIFO word since it will not be used */
1797 uint32_t status_reg = i3c->SR;
1798
1799 ARG_UNUSED(status_reg);
1800 }
1801 }
1802
1803 /* Target read early termination flag (only used during CCC commands)*/
1804 if (LL_I3C_IsActiveFlag_RXTGTEND(i3c) && LL_I3C_IsEnabledIT_RXTGTEND(i3c)) {
1805 /* A target ended a read request early during a CCC command, move the ptr to the
1806 * next target
1807 */
1808 data->ccc_target_payload++;
1809 LL_I3C_ClearFlag_RXTGTEND(i3c);
1810 }
1811
1812 /* Frame complete handler */
1813 if (LL_I3C_IsActiveFlag_FC(i3c) && LL_I3C_IsEnabledIT_FC(i3c)) {
1814 LL_I3C_ClearFlag_FC(i3c);
1815 k_sem_give(&data->device_sync_sem);
1816
1817 (void)pm_device_runtime_put(dev);
1818 pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
1819
1820 /* Mark bus as idle after each frame complete */
1821 data->msg_state = STM32_I3C_MSG_IDLE;
1822 }
1823
1824 #ifdef CONFIG_I3C_USE_IBI
1825
1826 k_sem_take(&data->ibi_lock_sem, K_FOREVER);
1827
1828 if (LL_I3C_IsActiveFlag_IBI(i3c)) {
1829 /* Clear frame complete flag */
1830 LL_I3C_ClearFlag_IBI(i3c);
1831 data->ibi_payload = LL_I3C_GetIBIPayload(i3c);
1832 data->ibi_payload_size = LL_I3C_GetNbIBIAddData(i3c);
1833 data->ibi_target_addr = LL_I3C_GetIBITargetAddr(i3c);
1834 if ((data->ibi_payload == 0) && (data->ibi_payload_size == 0) &&
1835 (data->ibi_target_addr == 0)) {
1836 LOG_ERR("Invalid Payload\n");
1837 } else {
1838 LOG_INF("IBI done, payload received :%d,%d,%d\n", data->ibi_payload,
1839 data->ibi_payload_size, data->ibi_target_addr);
1840 if ((data->ibi_payload != 0) && (data->ibi_payload_size != 0)) {
1841 struct i3c_device_desc *target;
1842
1843 target = i3c_dev_list_i3c_addr_find(dev, data->ibi_target_addr);
1844
1845 if (target != NULL) {
1846 if (i3c_ibi_work_enqueue_target_irq(
1847 target, (uint8_t *)&data->ibi_payload,
1848 data->ibi_payload_size) != 0) {
1849 LOG_ERR("Error enqueue IBI IRQ work");
1850 }
1851 } else {
1852 LOG_ERR("IBI from unknown device addr 0x%x",
1853 data->ibi_target_addr);
1854 }
1855 }
1856 }
1857 }
1858
1859 if (LL_I3C_IsActiveFlag_HJ(i3c)) {
1860 int ret;
1861
1862 LL_I3C_ClearFlag_HJ(i3c);
1863
1864 ret = i3c_ibi_work_enqueue_hotjoin(dev);
1865 if (ret != 0) {
1866 LOG_ERR("IBI Failed to enqueue hotjoin work");
1867 }
1868 }
1869
1870 k_sem_give(&data->ibi_lock_sem);
1871
1872 #endif
1873
1874 if (LL_I3C_IsActiveFlag_WKP(i3c)) {
1875 LL_I3C_ClearFlag_WKP(i3c);
1876 }
1877 }
1878
1879 /* Handles the I3C error ISR */
i3c_stm32_error_isr(void * arg)1880 static void i3c_stm32_error_isr(void *arg)
1881 {
1882 const struct device *dev = (const struct device *)arg;
1883
1884 const struct i3c_stm32_config *config = dev->config;
1885 struct i3c_stm32_data *data = dev->data;
1886 I3C_TypeDef *i3c = config->i3c;
1887
1888 i3c_stm32_log_err_type(dev);
1889
1890 LL_I3C_ClearFlag_ERR(i3c);
1891
1892 data->msg_state = STM32_I3C_MSG_ERR;
1893
1894 k_sem_give(&data->device_sync_sem);
1895
1896 (void)pm_device_runtime_put(dev);
1897 pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
1898 }
1899
1900 #ifdef CONFIG_I3C_USE_IBI
1901
i3c_stm32_ibi_hj_response(const struct device * dev,bool ack)1902 int i3c_stm32_ibi_hj_response(const struct device *dev, bool ack)
1903 {
1904 const struct i3c_stm32_config *config = dev->config;
1905 I3C_TypeDef *i3c = config->i3c;
1906
1907 if (ack) {
1908 /*
1909 * This prevents pm_device_runtime from being called multiple times
1910 * with redunant calls
1911 */
1912 if (!hj_pm_lock) {
1913 hj_pm_lock = true;
1914 (void)pm_device_runtime_get(dev);
1915 pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
1916 }
1917 LL_I3C_EnableHJAck(i3c);
1918 } else {
1919 LL_I3C_DisableHJAck(i3c);
1920 if (hj_pm_lock) {
1921 hj_pm_lock = false;
1922 (void)pm_device_runtime_put(dev);
1923 pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
1924 }
1925 }
1926
1927 return 0;
1928 }
1929
i3c_stm32_ibi_enable(const struct device * dev,struct i3c_device_desc * target)1930 int i3c_stm32_ibi_enable(const struct device *dev, struct i3c_device_desc *target)
1931 {
1932 int ret = 0;
1933 uint8_t idx;
1934 I3C_TypeDef *i3c;
1935 struct i3c_ccc_events i3c_events;
1936 struct i3c_stm32_data *data = dev->data;
1937 const struct i3c_stm32_config *config = dev->config;
1938
1939 i3c = config->i3c;
1940 if (!i3c_device_is_ibi_capable(target)) {
1941 return -EINVAL;
1942 }
1943
1944 if (data->ibi.num_addr >= ARRAY_SIZE(data->ibi.addr)) {
1945 /* No more free entries in the IBI table */
1946 LOG_ERR("%s: no more free space in the IBI table", __func__);
1947 return -ENOMEM;
1948 }
1949
1950 for (idx = 0; idx < ARRAY_SIZE(data->ibi.addr); idx++) {
1951 if (data->ibi.addr[idx] == target->dynamic_addr) {
1952 LOG_ERR("%s: selected target is already in the list", __func__);
1953 return -EINVAL;
1954 }
1955 }
1956
1957 if (data->ibi.num_addr > 0) {
1958 for (idx = 0; idx < ARRAY_SIZE(data->ibi.addr); idx++) {
1959 if (data->ibi.addr[idx] == 0U) {
1960 break;
1961 }
1962 }
1963
1964 if (idx >= ARRAY_SIZE(data->ibi.addr)) {
1965 LOG_ERR("Cannot support more IBIs");
1966 return -ENOTSUP;
1967 }
1968
1969 } else {
1970 idx = 0;
1971 }
1972
1973 data->ibi.addr[idx] = target->dynamic_addr;
1974 data->ibi.num_addr += 1U;
1975
1976 if (data->ibi.num_addr == 1U) {
1977 (void)pm_device_runtime_get(dev);
1978 }
1979
1980 /* Tell target to enable IBI */
1981 i3c_events.events = I3C_CCC_EVT_INTR;
1982 ret = i3c_ccc_do_events_set(target, true, &i3c_events);
1983 if (ret != 0) {
1984 LOG_ERR("Error sending IBI ENEC for 0x%02x (%d)", target->dynamic_addr, ret);
1985 }
1986
1987 /* Set I3C bus devices configuration */
1988 LL_I3C_ConfigDeviceCapabilities(i3c, (idx + 1), target->dynamic_addr,
1989 LL_I3C_IBI_CAPABILITY,
1990 i3c_ibi_has_payload(target) ? LL_I3C_IBI_DATA_ENABLE
1991 : LL_I3C_IBI_DATA_DISABLE,
1992 LL_I3C_CR_NO_CAPABILITY);
1993
1994 return ret;
1995 }
1996
i3c_stm32_ibi_disable(const struct device * dev,struct i3c_device_desc * target)1997 int i3c_stm32_ibi_disable(const struct device *dev, struct i3c_device_desc *target)
1998 {
1999 int ret = 0;
2000 uint8_t idx;
2001 I3C_TypeDef *i3c;
2002 struct i3c_ccc_events i3c_events;
2003 struct i3c_stm32_data *data = dev->data;
2004 const struct i3c_stm32_config *config = dev->config;
2005
2006 i3c = config->i3c;
2007 if (!i3c_device_is_ibi_capable(target)) {
2008 return -EINVAL;
2009 }
2010
2011 for (idx = 0; idx < ARRAY_SIZE(data->ibi.addr); idx++) {
2012 if (target->dynamic_addr == data->ibi.addr[idx]) {
2013 break;
2014 }
2015 }
2016
2017 if (idx == ARRAY_SIZE(data->ibi.addr)) {
2018 LOG_ERR("%s: target is not in list of registered addresses", __func__);
2019 return -ENODEV;
2020 }
2021
2022 data->ibi.addr[idx] = 0U;
2023 data->ibi.num_addr -= 1U;
2024
2025 if (data->ibi.num_addr == 0U) {
2026 (void)pm_device_runtime_put(dev);
2027 }
2028
2029 /* Tell target to disable IBI */
2030 i3c_events.events = I3C_CCC_EVT_INTR;
2031 ret = i3c_ccc_do_events_set(target, false, &i3c_events);
2032 if (ret != 0) {
2033 LOG_ERR("Error sending IBI DISEC for 0x%02x (%d)", target->dynamic_addr, ret);
2034 }
2035
2036 /* Set I3C bus devices configuration */
2037 LL_I3C_ConfigDeviceCapabilities(i3c, (idx + 1), target->dynamic_addr,
2038 LL_I3C_IBI_NO_CAPABILITY,
2039 LL_I3C_IBI_DATA_DISABLE,
2040 LL_I3C_CR_NO_CAPABILITY);
2041
2042 return ret;
2043 }
2044
2045 #endif /* CONFIG_I3C_USE_IBI */
2046
2047 #ifdef CONFIG_I3C_STM32_DMA
i3c_stm32_tx_rx_msg_config(const struct device * dma_dev,void * user_data,uint32_t channel,int status)2048 static void i3c_stm32_tx_rx_msg_config(const struct device *dma_dev, void *user_data,
2049 uint32_t channel, int status)
2050 {
2051 const struct device *dev = (const struct device *)user_data;
2052
2053 if (i3c_stm32_curr_msg_xfer_next(dev) != 0) {
2054 /* No more messages to transmit/receive */
2055 return;
2056 }
2057
2058 uint8_t *buf = NULL;
2059 size_t *offset = 0;
2060 uint32_t len = 0;
2061
2062 i3c_stm32_curr_msg_xfer_get_buf(dev, &buf, &len, &offset);
2063 i3c_stm32_dma_msg_config(dev, (uint32_t)buf, len);
2064 }
2065
i3c_stm32_dma_tx_cb(const struct device * dma_dev,void * user_data,uint32_t channel,int status)2066 static void i3c_stm32_dma_tx_cb(const struct device *dma_dev, void *user_data, uint32_t channel,
2067 int status)
2068 {
2069 i3c_stm32_tx_rx_msg_config(dma_dev, user_data, channel, status);
2070 }
2071
i3c_stm32_dma_rx_cb(const struct device * dma_dev,void * user_data,uint32_t channel,int status)2072 static void i3c_stm32_dma_rx_cb(const struct device *dma_dev, void *user_data, uint32_t channel,
2073 int status)
2074 {
2075 i3c_stm32_tx_rx_msg_config(dma_dev, user_data, channel, status);
2076 }
2077
i3c_stm32_dma_tc_cb(const struct device * dma_dev,void * user_data,uint32_t channel,int status)2078 static void i3c_stm32_dma_tc_cb(const struct device *dma_dev, void *user_data, uint32_t channel,
2079 int status)
2080 {
2081 }
2082
i3c_stm32_dma_rs_cb(const struct device * dma_dev,void * user_data,uint32_t channel,int status)2083 static void i3c_stm32_dma_rs_cb(const struct device *dma_dev, void *user_data, uint32_t channel,
2084 int status)
2085 {
2086 }
2087
2088 #endif
2089
2090 static DEVICE_API(i3c, i3c_stm32_driver_api) = {
2091 .i2c_api.configure = i3c_stm32_i2c_configure,
2092 .i2c_api.transfer = i3c_stm32_i2c_transfer,
2093 #ifdef CONFIG_I2C_RTIO
2094 .i2c_api.iodev_submit = i2c_iodev_submit_fallback,
2095 #endif
2096 .configure = i3c_stm32_configure,
2097 .config_get = i3c_stm32_config_get,
2098 .i3c_device_find = i3c_stm32_device_find,
2099 .i3c_xfers = i3c_stm32_i3c_transfer,
2100 .do_daa = i3c_stm32_do_daa,
2101 .do_ccc = i3c_stm32_do_ccc,
2102 #ifdef CONFIG_I3C_USE_IBI
2103 .ibi_hj_response = i3c_stm32_ibi_hj_response,
2104 .ibi_enable = i3c_stm32_ibi_enable,
2105 .ibi_disable = i3c_stm32_ibi_disable,
2106 #endif
2107 #ifdef CONFIG_I3C_RTIO
2108 .iodev_submit = i3c_iodev_submit_fallback,
2109 #endif
2110 };
2111
2112 #ifdef CONFIG_I3C_STM32_DMA
2113 #define STM32_I3C_DMA_CHANNEL_INIT(index, dir, dir_cap, src_dev, dest_dev) \
2114 .dma_dev = DEVICE_DT_GET(STM32_DMA_CTLR(index, dir)), \
2115 .dma_channel = DT_INST_DMAS_CELL_BY_NAME(index, dir, channel), \
2116 .dma_cfg = \
2117 { \
2118 .dma_slot = STM32_DMA_SLOT(index, dir, slot), \
2119 .channel_direction = \
2120 STM32_DMA_CONFIG_DIRECTION(STM32_DMA_CHANNEL_CONFIG(index, dir)), \
2121 .channel_priority = \
2122 STM32_DMA_CONFIG_PRIORITY(STM32_DMA_CHANNEL_CONFIG(index, dir)), \
2123 .source_data_size = STM32_DMA_CONFIG_##src_dev##_DATA_SIZE( \
2124 STM32_DMA_CHANNEL_CONFIG(index, dir)), \
2125 .dest_data_size = STM32_DMA_CONFIG_##dest_dev##_DATA_SIZE( \
2126 STM32_DMA_CHANNEL_CONFIG(index, dir)), \
2127 .source_burst_length = 1, /* SINGLE transfer */ \
2128 .dest_burst_length = 1, \
2129 .block_count = 1, \
2130 .dma_callback = i3c_stm32_dma_##dir##_cb, \
2131 }, \
2132 .src_addr_increment = \
2133 STM32_DMA_CONFIG_##src_dev##_ADDR_INC(STM32_DMA_CHANNEL_CONFIG(index, dir)), \
2134 .dst_addr_increment = \
2135 STM32_DMA_CONFIG_##dest_dev##_ADDR_INC(STM32_DMA_CHANNEL_CONFIG(index, dir)), \
2136 .fifo_threshold = STM32_DMA_FEATURES_FIFO_THRESHOLD(STM32_DMA_FEATURES(index, dir)),
2137
2138 #endif
2139
2140 #ifdef CONFIG_I3C_STM32_DMA
2141 #define STM32_I3C_DMA_CHANNEL(index, dir, DIR, src, dest) \
2142 .dma_##dir = {COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \
2143 (STM32_I3C_DMA_CHANNEL_INIT(index, dir, DIR, src, dest)), \
2144 (NULL))},
2145
2146 #else
2147 #define STM32_I3C_DMA_CHANNEL(index, dir, DIR, src, dest)
2148 #endif
2149
2150 #define STM32_I3C_IRQ_CONNECT_AND_ENABLE(index) \
2151 do { \
2152 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, event, irq), \
2153 DT_INST_IRQ_BY_NAME(index, event, priority), i3c_stm32_event_isr, \
2154 DEVICE_DT_INST_GET(index), 0); \
2155 irq_enable(DT_INST_IRQ_BY_NAME(index, event, irq)); \
2156 \
2157 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, error, irq), \
2158 DT_INST_IRQ_BY_NAME(index, error, priority), i3c_stm32_error_isr, \
2159 DEVICE_DT_INST_GET(index), 0); \
2160 irq_enable(DT_INST_IRQ_BY_NAME(index, error, irq)); \
2161 } while (false)
2162
2163 #define STM32_I3C_IRQ_HANDLER_DECL(index) \
2164 static void i3c_stm32_irq_config_func_##index(const struct device *dev)
2165
2166 #define STM32_I3C_IRQ_HANDLER_FUNCTION(index) .irq_config_func = i3c_stm32_irq_config_func_##index,
2167
2168 #define STM32_I3C_IRQ_HANDLER(index) \
2169 static void i3c_stm32_irq_config_func_##index(const struct device *dev) \
2170 { \
2171 STM32_I3C_IRQ_CONNECT_AND_ENABLE(index); \
2172 }
2173
2174 #define I3C_STM32_INIT(index) \
2175 STM32_I3C_IRQ_HANDLER_DECL(index); \
2176 \
2177 static const struct stm32_pclken pclken_##index[] = STM32_DT_INST_CLOCKS(index); \
2178 PINCTRL_DT_INST_DEFINE(index); \
2179 static struct i3c_device_desc i3c_stm32_dev_arr_##index[] = \
2180 I3C_DEVICE_ARRAY_DT_INST(index); \
2181 static struct i3c_i2c_device_desc i3c_i2c_stm32_dev_arr_##index[] = \
2182 I3C_I2C_DEVICE_ARRAY_DT_INST(index); \
2183 \
2184 static const struct i3c_stm32_config i3c_stm32_cfg_##index = { \
2185 .i3c = (I3C_TypeDef *)DT_INST_REG_ADDR(index), \
2186 STM32_I3C_IRQ_HANDLER_FUNCTION(index).pclken = pclken_##index, \
2187 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
2188 .drv_cfg.dev_list.i3c = i3c_stm32_dev_arr_##index, \
2189 .drv_cfg.dev_list.num_i3c = ARRAY_SIZE(i3c_stm32_dev_arr_##index), \
2190 .drv_cfg.dev_list.i2c = i3c_i2c_stm32_dev_arr_##index, \
2191 .drv_cfg.dev_list.num_i2c = ARRAY_SIZE(i3c_i2c_stm32_dev_arr_##index), \
2192 }; \
2193 \
2194 static struct i3c_stm32_data i3c_stm32_data_##index = { \
2195 .drv_data.ctrl_config.scl.i2c = DT_INST_PROP_OR(index, i2c_scl_hz, 0), \
2196 .drv_data.ctrl_config.scl.i3c = DT_INST_PROP_OR(index, i3c_scl_hz, 0), \
2197 STM32_I3C_DMA_CHANNEL(index, rx, RX, PERIPHERAL, MEMORY) \
2198 STM32_I3C_DMA_CHANNEL(index, tx, TX, MEMORY, PERIPHERAL) \
2199 STM32_I3C_DMA_CHANNEL(index, tc, TC, MEMORY, PERIPHERAL) \
2200 STM32_I3C_DMA_CHANNEL(index, rs, RS, PERIPHERAL, MEMORY)}; \
2201 \
2202 PM_DEVICE_DT_INST_DEFINE(index, i3c_stm32_pm_action); \
2203 \
2204 DEVICE_DT_INST_DEFINE(index, &i3c_stm32_init, PM_DEVICE_DT_INST_GET(index), \
2205 &i3c_stm32_data_##index, &i3c_stm32_cfg_##index, POST_KERNEL, \
2206 CONFIG_I3C_CONTROLLER_INIT_PRIORITY, &i3c_stm32_driver_api); \
2207 \
2208 STM32_I3C_IRQ_HANDLER(index)
2209
2210 DT_INST_FOREACH_STATUS_OKAY(I3C_STM32_INIT)
2211
