1  /**
2    ******************************************************************************
3    * @file    stm32f4xx_ll_fmpi2c.h
4    * @author  MCD Application Team
5    * @brief   Header file of FMPI2C LL module.
6    ******************************************************************************
7    * @attention
8    *
9    * Copyright (c) 2016 STMicroelectronics.
10    * All rights reserved.
11    *
12    * This software is licensed under terms that can be found in the LICENSE file
13    * in the root directory of this software component.
14    * If no LICENSE file comes with this software, it is provided AS-IS.
15    *
16    ******************************************************************************
17    */
18  
19  /* Define to prevent recursive inclusion -------------------------------------*/
20  #ifndef STM32F4xx_LL_FMPI2C_H
21  #define STM32F4xx_LL_FMPI2C_H
22  
23  #ifdef __cplusplus
24  extern "C" {
25  #endif
26  
27  #if defined(FMPI2C_CR1_PE)
28  /* Includes ------------------------------------------------------------------*/
29  #include "stm32f4xx.h"
30  
31  /** @addtogroup STM32F4xx_LL_Driver
32    * @{
33    */
34  
35  #if defined (FMPI2C1)
36  
37  /** @defgroup FMPI2C_LL FMPI2C
38    * @{
39    */
40  
41  /* Private types -------------------------------------------------------------*/
42  /* Private variables ---------------------------------------------------------*/
43  
44  /* Private constants ---------------------------------------------------------*/
45  /** @defgroup FMPI2C_LL_Private_Constants FMPI2C Private Constants
46    * @{
47    */
48  /**
49    * @}
50    */
51  
52  /* Private macros ------------------------------------------------------------*/
53  #if defined(USE_FULL_LL_DRIVER)
54  /** @defgroup FMPI2C_LL_Private_Macros FMPI2C Private Macros
55    * @{
56    */
57  /**
58    * @}
59    */
60  #endif /*USE_FULL_LL_DRIVER*/
61  
62  /* Exported types ------------------------------------------------------------*/
63  #if defined(USE_FULL_LL_DRIVER)
64  /** @defgroup FMPI2C_LL_ES_INIT FMPI2C Exported Init structure
65    * @{
66    */
67  typedef struct
68  {
69    uint32_t PeripheralMode;      /*!< Specifies the peripheral mode.
70                                       This parameter can be a value of @ref FMPI2C_LL_EC_PERIPHERAL_MODE.
71  
72                                       This feature can be modified afterwards using unitary function
73                                       @ref LL_FMPI2C_SetMode(). */
74  
75    uint32_t Timing;              /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
76                                       This parameter must be set by referring to the STM32CubeMX Tool and
77                                       the helper macro @ref __LL_FMPI2C_CONVERT_TIMINGS().
78  
79                                       This feature can be modified afterwards using unitary function
80                                       @ref LL_FMPI2C_SetTiming(). */
81  
82    uint32_t AnalogFilter;        /*!< Enables or disables analog noise filter.
83                                       This parameter can be a value of @ref FMPI2C_LL_EC_ANALOGFILTER_SELECTION.
84  
85                                       This feature can be modified afterwards using unitary functions
86                                       @ref LL_FMPI2C_EnableAnalogFilter() or LL_FMPI2C_DisableAnalogFilter(). */
87  
88    uint32_t DigitalFilter;       /*!< Configures the digital noise filter.
89                                       This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
90  
91                                       This feature can be modified afterwards using unitary function
92                                       @ref LL_FMPI2C_SetDigitalFilter(). */
93  
94    uint32_t OwnAddress1;         /*!< Specifies the device own address 1.
95                                       This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
96  
97                                       This feature can be modified afterwards using unitary function
98                                       @ref LL_FMPI2C_SetOwnAddress1(). */
99  
100    uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
101                                       match code or next received byte.
102                                       This parameter can be a value of @ref FMPI2C_LL_EC_I2C_ACKNOWLEDGE.
103  
104                                       This feature can be modified afterwards using unitary function
105                                       @ref LL_FMPI2C_AcknowledgeNextData(). */
106  
107    uint32_t OwnAddrSize;         /*!< Specifies the device own address 1 size (7-bit or 10-bit).
108                                       This parameter can be a value of @ref FMPI2C_LL_EC_OWNADDRESS1.
109  
110                                       This feature can be modified afterwards using unitary function
111                                       @ref LL_FMPI2C_SetOwnAddress1(). */
112  } LL_FMPI2C_InitTypeDef;
113  /**
114    * @}
115    */
116  #endif /*USE_FULL_LL_DRIVER*/
117  
118  /* Exported constants --------------------------------------------------------*/
119  /** @defgroup FMPI2C_LL_Exported_Constants FMPI2C Exported Constants
120    * @{
121    */
122  
123  /** @defgroup FMPI2C_LL_EC_CLEAR_FLAG Clear Flags Defines
124    * @brief    Flags defines which can be used with LL_FMPI2C_WriteReg function
125    * @{
126    */
127  #define LL_FMPI2C_ICR_ADDRCF                   FMPI2C_ICR_ADDRCF          /*!< Address Matched flag   */
128  #define LL_FMPI2C_ICR_NACKCF                   FMPI2C_ICR_NACKCF          /*!< Not Acknowledge flag   */
129  #define LL_FMPI2C_ICR_STOPCF                   FMPI2C_ICR_STOPCF          /*!< Stop detection flag    */
130  #define LL_FMPI2C_ICR_BERRCF                   FMPI2C_ICR_BERRCF          /*!< Bus error flag         */
131  #define LL_FMPI2C_ICR_ARLOCF                   FMPI2C_ICR_ARLOCF          /*!< Arbitration Lost flag  */
132  #define LL_FMPI2C_ICR_OVRCF                    FMPI2C_ICR_OVRCF           /*!< Overrun/Underrun flag  */
133  #define LL_FMPI2C_ICR_PECCF                    FMPI2C_ICR_PECCF           /*!< PEC error flag         */
134  #define LL_FMPI2C_ICR_TIMOUTCF                 FMPI2C_ICR_TIMOUTCF        /*!< Timeout detection flag */
135  #define LL_FMPI2C_ICR_ALERTCF                  FMPI2C_ICR_ALERTCF         /*!< Alert flag             */
136  /**
137    * @}
138    */
139  
140  /** @defgroup FMPI2C_LL_EC_GET_FLAG Get Flags Defines
141    * @brief    Flags defines which can be used with LL_FMPI2C_ReadReg function
142    * @{
143    */
144  #define LL_FMPI2C_ISR_TXE                      FMPI2C_ISR_TXE             /*!< Transmit data register empty        */
145  #define LL_FMPI2C_ISR_TXIS                     FMPI2C_ISR_TXIS            /*!< Transmit interrupt status           */
146  #define LL_FMPI2C_ISR_RXNE                     FMPI2C_ISR_RXNE            /*!< Receive data register not empty     */
147  #define LL_FMPI2C_ISR_ADDR                     FMPI2C_ISR_ADDR            /*!< Address matched (slave mode)        */
148  #define LL_FMPI2C_ISR_NACKF                    FMPI2C_ISR_NACKF           /*!< Not Acknowledge received flag       */
149  #define LL_FMPI2C_ISR_STOPF                    FMPI2C_ISR_STOPF           /*!< Stop detection flag                 */
150  #define LL_FMPI2C_ISR_TC                       FMPI2C_ISR_TC              /*!< Transfer Complete (master mode)     */
151  #define LL_FMPI2C_ISR_TCR                      FMPI2C_ISR_TCR             /*!< Transfer Complete Reload            */
152  #define LL_FMPI2C_ISR_BERR                     FMPI2C_ISR_BERR            /*!< Bus error                           */
153  #define LL_FMPI2C_ISR_ARLO                     FMPI2C_ISR_ARLO            /*!< Arbitration lost                    */
154  #define LL_FMPI2C_ISR_OVR                      FMPI2C_ISR_OVR             /*!< Overrun/Underrun (slave mode)       */
155  #define LL_FMPI2C_ISR_PECERR                   FMPI2C_ISR_PECERR          /*!< PEC Error in reception (SMBus mode) */
156  #define LL_FMPI2C_ISR_TIMEOUT                  FMPI2C_ISR_TIMEOUT         /*!< Timeout detection flag (SMBus mode) */
157  #define LL_FMPI2C_ISR_ALERT                    FMPI2C_ISR_ALERT           /*!< SMBus alert (SMBus mode)            */
158  #define LL_FMPI2C_ISR_BUSY                     FMPI2C_ISR_BUSY            /*!< Bus busy                            */
159  /**
160    * @}
161    */
162  
163  /** @defgroup FMPI2C_LL_EC_IT IT Defines
164    * @brief    IT defines which can be used with LL_FMPI2C_ReadReg and  LL_FMPI2C_WriteReg functions
165    * @{
166    */
167  #define LL_FMPI2C_CR1_TXIE                     FMPI2C_CR1_TXIE            /*!< TX Interrupt enable                         */
168  #define LL_FMPI2C_CR1_RXIE                     FMPI2C_CR1_RXIE            /*!< RX Interrupt enable                         */
169  #define LL_FMPI2C_CR1_ADDRIE                   FMPI2C_CR1_ADDRIE          /*!< Address match Interrupt enable (slave only) */
170  #define LL_FMPI2C_CR1_NACKIE                   FMPI2C_CR1_NACKIE          /*!< Not acknowledge received Interrupt enable   */
171  #define LL_FMPI2C_CR1_STOPIE                   FMPI2C_CR1_STOPIE          /*!< STOP detection Interrupt enable             */
172  #define LL_FMPI2C_CR1_TCIE                     FMPI2C_CR1_TCIE            /*!< Transfer Complete interrupt enable          */
173  #define LL_FMPI2C_CR1_ERRIE                    FMPI2C_CR1_ERRIE           /*!< Error interrupts enable                     */
174  /**
175    * @}
176    */
177  
178  /** @defgroup FMPI2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
179    * @{
180    */
181  #define LL_FMPI2C_MODE_I2C                    0x00000000U              /*!< FMPI2C Master or Slave mode                 */
182  #define LL_FMPI2C_MODE_SMBUS_HOST             FMPI2C_CR1_SMBHEN           /*!< SMBus Host address acknowledge           */
183  #define LL_FMPI2C_MODE_SMBUS_DEVICE           0x00000000U              /*!< SMBus Device default mode
184                                                                           (Default address not acknowledge)        */
185  #define LL_FMPI2C_MODE_SMBUS_DEVICE_ARP       FMPI2C_CR1_SMBDEN           /*!< SMBus Device Default address acknowledge */
186  /**
187    * @}
188    */
189  
190  /** @defgroup FMPI2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
191    * @{
192    */
193  #define LL_FMPI2C_ANALOGFILTER_ENABLE          0x00000000U             /*!< Analog filter is enabled.  */
194  #define LL_FMPI2C_ANALOGFILTER_DISABLE         FMPI2C_CR1_ANFOFF          /*!< Analog filter is disabled. */
195  /**
196    * @}
197    */
198  
199  /** @defgroup FMPI2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
200    * @{
201    */
202  #define LL_FMPI2C_ADDRESSING_MODE_7BIT         0x00000000U              /*!< Master operates in 7-bit addressing mode. */
203  #define LL_FMPI2C_ADDRESSING_MODE_10BIT        FMPI2C_CR2_ADD10            /*!< Master operates in 10-bit addressing mode.*/
204  /**
205    * @}
206    */
207  
208  /** @defgroup FMPI2C_LL_EC_OWNADDRESS1 Own Address 1 Length
209    * @{
210    */
211  #define LL_FMPI2C_OWNADDRESS1_7BIT             0x00000000U             /*!< Own address 1 is a 7-bit address. */
212  #define LL_FMPI2C_OWNADDRESS1_10BIT            FMPI2C_OAR1_OA1MODE        /*!< Own address 1 is a 10-bit address.*/
213  /**
214    * @}
215    */
216  
217  /** @defgroup FMPI2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
218    * @{
219    */
220  #define LL_FMPI2C_OWNADDRESS2_NOMASK           FMPI2C_OAR2_OA2NOMASK      /*!< Own Address2 No mask.                 */
221  #define LL_FMPI2C_OWNADDRESS2_MASK01           FMPI2C_OAR2_OA2MASK01      /*!< Only Address2 bits[7:2] are compared. */
222  #define LL_FMPI2C_OWNADDRESS2_MASK02           FMPI2C_OAR2_OA2MASK02      /*!< Only Address2 bits[7:3] are compared. */
223  #define LL_FMPI2C_OWNADDRESS2_MASK03           FMPI2C_OAR2_OA2MASK03      /*!< Only Address2 bits[7:4] are compared. */
224  #define LL_FMPI2C_OWNADDRESS2_MASK04           FMPI2C_OAR2_OA2MASK04      /*!< Only Address2 bits[7:5] are compared. */
225  #define LL_FMPI2C_OWNADDRESS2_MASK05           FMPI2C_OAR2_OA2MASK05      /*!< Only Address2 bits[7:6] are compared. */
226  #define LL_FMPI2C_OWNADDRESS2_MASK06           FMPI2C_OAR2_OA2MASK06      /*!< Only Address2 bits[7] are compared.   */
227  #define LL_FMPI2C_OWNADDRESS2_MASK07           FMPI2C_OAR2_OA2MASK07      /*!< No comparison is done.
228                                                                           All Address2 are acknowledged.        */
229  /**
230    * @}
231    */
232  
233  /** @defgroup FMPI2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
234    * @{
235    */
236  #define LL_FMPI2C_ACK                          0x00000000U              /*!< ACK is sent after current received byte. */
237  #define LL_FMPI2C_NACK                         FMPI2C_CR2_NACK             /*!< NACK is sent after current received byte.*/
238  /**
239    * @}
240    */
241  
242  /** @defgroup FMPI2C_LL_EC_ADDRSLAVE Slave Address Length
243    * @{
244    */
245  #define LL_FMPI2C_ADDRSLAVE_7BIT               0x00000000U              /*!< Slave Address in 7-bit. */
246  #define LL_FMPI2C_ADDRSLAVE_10BIT              FMPI2C_CR2_ADD10            /*!< Slave Address in 10-bit.*/
247  /**
248    * @}
249    */
250  
251  /** @defgroup FMPI2C_LL_EC_REQUEST Transfer Request Direction
252    * @{
253    */
254  #define LL_FMPI2C_REQUEST_WRITE                0x00000000U              /*!< Master request a write transfer. */
255  #define LL_FMPI2C_REQUEST_READ                 FMPI2C_CR2_RD_WRN           /*!< Master request a read transfer.  */
256  /**
257    * @}
258    */
259  
260  /** @defgroup FMPI2C_LL_EC_MODE Transfer End Mode
261    * @{
262    */
263  #define LL_FMPI2C_MODE_RELOAD                  FMPI2C_CR2_RELOAD           /*!< Enable FMPI2C Reload mode.     */
264  #define LL_FMPI2C_MODE_AUTOEND                 FMPI2C_CR2_AUTOEND          /*!< Enable FMPI2C Automatic end mode
265                                                                            with no HW PEC comparison.  */
266  #define LL_FMPI2C_MODE_SOFTEND                 0x00000000U              /*!< Enable FMPI2C Software end mode
267                                                                            with no HW PEC comparison.  */
268  #define LL_FMPI2C_MODE_SMBUS_RELOAD            LL_FMPI2C_MODE_RELOAD       /*!< Enable FMPSMBUS Automatic end mode
269                                                                            with HW PEC comparison.     */
270  #define LL_FMPI2C_MODE_SMBUS_AUTOEND_NO_PEC    LL_FMPI2C_MODE_AUTOEND      /*!< Enable FMPSMBUS Automatic end mode
271                                                                            with HW PEC comparison.     */
272  #define LL_FMPI2C_MODE_SMBUS_SOFTEND_NO_PEC    LL_FMPI2C_MODE_SOFTEND      /*!< Enable FMPSMBUS Software end mode
273                                                                            with HW PEC comparison.     */
274  #define LL_FMPI2C_MODE_SMBUS_AUTOEND_WITH_PEC  (uint32_t)(LL_FMPI2C_MODE_AUTOEND | FMPI2C_CR2_PECBYTE)
275  /*!< Enable FMPSMBUS Automatic end mode with HW PEC comparison.   */
276  #define LL_FMPI2C_MODE_SMBUS_SOFTEND_WITH_PEC  (uint32_t)(LL_FMPI2C_MODE_SOFTEND | FMPI2C_CR2_PECBYTE)
277  /*!< Enable FMPSMBUS Software end mode with HW PEC comparison.    */
278  /**
279    * @}
280    */
281  
282  /** @defgroup FMPI2C_LL_EC_GENERATE Start And Stop Generation
283    * @{
284    */
285  #define LL_FMPI2C_GENERATE_NOSTARTSTOP         0x00000000U
286  /*!< Don't Generate Stop and Start condition. */
287  #define LL_FMPI2C_GENERATE_STOP                (uint32_t)(0x80000000U | FMPI2C_CR2_STOP)
288  /*!< Generate Stop condition (Size should be set to 0).      */
289  #define LL_FMPI2C_GENERATE_START_READ          (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN)
290  /*!< Generate Start for read request. */
291  #define LL_FMPI2C_GENERATE_START_WRITE         (uint32_t)(0x80000000U | FMPI2C_CR2_START)
292  /*!< Generate Start for write request. */
293  #define LL_FMPI2C_GENERATE_RESTART_7BIT_READ   (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN)
294  /*!< Generate Restart for read request, slave 7Bit address.  */
295  #define LL_FMPI2C_GENERATE_RESTART_7BIT_WRITE  (uint32_t)(0x80000000U | FMPI2C_CR2_START)
296  /*!< Generate Restart for write request, slave 7Bit address. */
297  #define LL_FMPI2C_GENERATE_RESTART_10BIT_READ  (uint32_t)(0x80000000U | FMPI2C_CR2_START | \
298                                                         FMPI2C_CR2_RD_WRN | FMPI2C_CR2_HEAD10R)
299  /*!< Generate Restart for read request, slave 10Bit address. */
300  #define LL_FMPI2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START)
301  /*!< Generate Restart for write request, slave 10Bit address.*/
302  /**
303    * @}
304    */
305  
306  /** @defgroup FMPI2C_LL_EC_DIRECTION Read Write Direction
307    * @{
308    */
309  #define LL_FMPI2C_DIRECTION_WRITE              0x00000000U              /*!< Write transfer request by master,
310                                                                            slave enters receiver mode.  */
311  #define LL_FMPI2C_DIRECTION_READ               FMPI2C_ISR_DIR              /*!< Read transfer request by master,
312                                                                            slave enters transmitter mode.*/
313  /**
314    * @}
315    */
316  
317  /** @defgroup FMPI2C_LL_EC_DMA_REG_DATA DMA Register Data
318    * @{
319    */
320  #define LL_FMPI2C_DMA_REG_DATA_TRANSMIT        0x00000000U              /*!< Get address of data register used for
321                                                                            transmission */
322  #define LL_FMPI2C_DMA_REG_DATA_RECEIVE         0x00000001U              /*!< Get address of data register used for
323                                                                            reception */
324  /**
325    * @}
326    */
327  
328  /** @defgroup FMPI2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
329    * @{
330    */
331  #define LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SCL_LOW      0x00000000U          /*!< TimeoutA is used to detect
332                                                                            SCL low level timeout.              */
333  #define LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH FMPI2C_TIMEOUTR_TIDLE   /*!< TimeoutA is used to detect
334                                                                            both SCL and SDA high level timeout.*/
335  /**
336    * @}
337    */
338  
339  /** @defgroup FMPI2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
340    * @{
341    */
342  #define LL_FMPI2C_FMPSMBUS_TIMEOUTA               FMPI2C_TIMEOUTR_TIMOUTEN                 /*!< TimeoutA enable bit          */
343  #define LL_FMPI2C_FMPSMBUS_TIMEOUTB               FMPI2C_TIMEOUTR_TEXTEN                   /*!< TimeoutB (extended clock)
344                                                                                         enable bit                   */
345  #define LL_FMPI2C_FMPSMBUS_ALL_TIMEOUT            (uint32_t)(FMPI2C_TIMEOUTR_TIMOUTEN | \
346                                                         FMPI2C_TIMEOUTR_TEXTEN)       /*!< TimeoutA and TimeoutB
347  (extended clock) enable bits */
348  /**
349    * @}
350    */
351  
352  /**
353    * @}
354    */
355  
356  /* Exported macro ------------------------------------------------------------*/
357  /** @defgroup FMPI2C_LL_Exported_Macros FMPI2C Exported Macros
358    * @{
359    */
360  
361  /** @defgroup FMPI2C_LL_EM_WRITE_READ Common Write and read registers Macros
362    * @{
363    */
364  
365  /**
366    * @brief  Write a value in FMPI2C register
367    * @param  __INSTANCE__ FMPI2C Instance
368    * @param  __REG__ Register to be written
369    * @param  __VALUE__ Value to be written in the register
370    * @retval None
371    */
372  #define LL_FMPI2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
373  
374  /**
375    * @brief  Read a value in FMPI2C register
376    * @param  __INSTANCE__ FMPI2C Instance
377    * @param  __REG__ Register to be read
378    * @retval Register value
379    */
380  #define LL_FMPI2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
381  /**
382    * @}
383    */
384  
385  /** @defgroup FMPI2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
386    * @{
387    */
388  /**
389    * @brief  Configure the SDA setup, hold time and the SCL high, low period.
390    * @param  __PRESCALER__ This parameter must be a value between  Min_Data=0 and Max_Data=0xF.
391    * @param  __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
392                             (tscldel = (SCLDEL+1)xtpresc)
393    * @param  __HOLD_TIME__  This parameter must be a value between Min_Data=0 and Max_Data=0xF.
394                             (tsdadel = SDADELxtpresc)
395    * @param  __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
396                              (tsclh = (SCLH+1)xtpresc)
397    * @param  __SCLL_PERIOD__ This parameter must be a value between  Min_Data=0 and Max_Data=0xFF.
398                              (tscll = (SCLL+1)xtpresc)
399    * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
400    */
401  #define __LL_FMPI2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
402    ((((uint32_t)(__PRESCALER__)    << FMPI2C_TIMINGR_PRESC_Pos)  & FMPI2C_TIMINGR_PRESC)   | \
403     (((uint32_t)(__SETUP_TIME__)   << FMPI2C_TIMINGR_SCLDEL_Pos) & FMPI2C_TIMINGR_SCLDEL)  | \
404     (((uint32_t)(__HOLD_TIME__)    << FMPI2C_TIMINGR_SDADEL_Pos) & FMPI2C_TIMINGR_SDADEL)  | \
405     (((uint32_t)(__SCLH_PERIOD__)  << FMPI2C_TIMINGR_SCLH_Pos)   & FMPI2C_TIMINGR_SCLH)    | \
406     (((uint32_t)(__SCLL_PERIOD__)  << FMPI2C_TIMINGR_SCLL_Pos)   & FMPI2C_TIMINGR_SCLL))
407  /**
408    * @}
409    */
410  
411  /**
412    * @}
413    */
414  
415  /* Exported functions --------------------------------------------------------*/
416  /** @defgroup FMPI2C_LL_Exported_Functions FMPI2C Exported Functions
417    * @{
418    */
419  
420  /** @defgroup FMPI2C_LL_EF_Configuration Configuration
421    * @{
422    */
423  
424  /**
425    * @brief  Enable FMPI2C peripheral (PE = 1).
426    * @rmtoll CR1          PE            LL_FMPI2C_Enable
427    * @param  FMPI2Cx FMPI2C Instance.
428    * @retval None
429    */
LL_FMPI2C_Enable(FMPI2C_TypeDef * FMPI2Cx)430  __STATIC_INLINE void LL_FMPI2C_Enable(FMPI2C_TypeDef *FMPI2Cx)
431  {
432    SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PE);
433  }
434  
435  /**
436    * @brief  Disable FMPI2C peripheral (PE = 0).
437    * @note   When PE = 0, the FMPI2C SCL and SDA lines are released.
438    *         Internal state machines and status bits are put back to their reset value.
439    *         When cleared, PE must be kept low for at least 3 APB clock cycles.
440    * @rmtoll CR1          PE            LL_FMPI2C_Disable
441    * @param  FMPI2Cx FMPI2C Instance.
442    * @retval None
443    */
LL_FMPI2C_Disable(FMPI2C_TypeDef * FMPI2Cx)444  __STATIC_INLINE void LL_FMPI2C_Disable(FMPI2C_TypeDef *FMPI2Cx)
445  {
446    CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PE);
447  }
448  
449  /**
450    * @brief  Check if the FMPI2C peripheral is enabled or disabled.
451    * @rmtoll CR1          PE            LL_FMPI2C_IsEnabled
452    * @param  FMPI2Cx FMPI2C Instance.
453    * @retval State of bit (1 or 0).
454    */
LL_FMPI2C_IsEnabled(FMPI2C_TypeDef * FMPI2Cx)455  __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabled(FMPI2C_TypeDef *FMPI2Cx)
456  {
457    return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PE) == (FMPI2C_CR1_PE)) ? 1UL : 0UL);
458  }
459  
460  /**
461    * @brief  Configure Noise Filters (Analog and Digital).
462    * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
463    *         The filters can only be programmed when the FMPI2C is disabled (PE = 0).
464    * @rmtoll CR1          ANFOFF        LL_FMPI2C_ConfigFilters\n
465    *         CR1          DNF           LL_FMPI2C_ConfigFilters
466    * @param  FMPI2Cx FMPI2C Instance.
467    * @param  AnalogFilter This parameter can be one of the following values:
468    *         @arg @ref LL_FMPI2C_ANALOGFILTER_ENABLE
469    *         @arg @ref LL_FMPI2C_ANALOGFILTER_DISABLE
470    * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
471                            and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*tfmpi2cclk).
472    *         This parameter is used to configure the digital noise filter on SDA and SCL input.
473    *         The digital filter will filter spikes with a length of up to DNF[3:0]*tfmpi2cclk.
474    * @retval None
475    */
LL_FMPI2C_ConfigFilters(FMPI2C_TypeDef * FMPI2Cx,uint32_t AnalogFilter,uint32_t DigitalFilter)476  __STATIC_INLINE void LL_FMPI2C_ConfigFilters(FMPI2C_TypeDef *FMPI2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
477  {
478    MODIFY_REG(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF | FMPI2C_CR1_DNF, AnalogFilter | (DigitalFilter << FMPI2C_CR1_DNF_Pos));
479  }
480  
481  /**
482    * @brief  Configure Digital Noise Filter.
483    * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
484    *         This filter can only be programmed when the FMPI2C is disabled (PE = 0).
485    * @rmtoll CR1          DNF           LL_FMPI2C_SetDigitalFilter
486    * @param  FMPI2Cx FMPI2C Instance.
487    * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
488                            and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*tfmpi2cclk).
489    *         This parameter is used to configure the digital noise filter on SDA and SCL input.
490    *         The digital filter will filter spikes with a length of up to DNF[3:0]*tfmpi2cclk.
491    * @retval None
492    */
LL_FMPI2C_SetDigitalFilter(FMPI2C_TypeDef * FMPI2Cx,uint32_t DigitalFilter)493  __STATIC_INLINE void LL_FMPI2C_SetDigitalFilter(FMPI2C_TypeDef *FMPI2Cx, uint32_t DigitalFilter)
494  {
495    MODIFY_REG(FMPI2Cx->CR1, FMPI2C_CR1_DNF, DigitalFilter << FMPI2C_CR1_DNF_Pos);
496  }
497  
498  /**
499    * @brief  Get the current Digital Noise Filter configuration.
500    * @rmtoll CR1          DNF           LL_FMPI2C_GetDigitalFilter
501    * @param  FMPI2Cx FMPI2C Instance.
502    * @retval Value between Min_Data=0x0 and Max_Data=0xF
503    */
LL_FMPI2C_GetDigitalFilter(FMPI2C_TypeDef * FMPI2Cx)504  __STATIC_INLINE uint32_t LL_FMPI2C_GetDigitalFilter(FMPI2C_TypeDef *FMPI2Cx)
505  {
506    return (uint32_t)(READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_DNF) >> FMPI2C_CR1_DNF_Pos);
507  }
508  
509  /**
510    * @brief  Enable Analog Noise Filter.
511    * @note   This filter can only be programmed when the FMPI2C is disabled (PE = 0).
512    * @rmtoll CR1          ANFOFF        LL_FMPI2C_EnableAnalogFilter
513    * @param  FMPI2Cx FMPI2C Instance.
514    * @retval None
515    */
LL_FMPI2C_EnableAnalogFilter(FMPI2C_TypeDef * FMPI2Cx)516  __STATIC_INLINE void LL_FMPI2C_EnableAnalogFilter(FMPI2C_TypeDef *FMPI2Cx)
517  {
518    CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF);
519  }
520  
521  /**
522    * @brief  Disable Analog Noise Filter.
523    * @note   This filter can only be programmed when the FMPI2C is disabled (PE = 0).
524    * @rmtoll CR1          ANFOFF        LL_FMPI2C_DisableAnalogFilter
525    * @param  FMPI2Cx FMPI2C Instance.
526    * @retval None
527    */
LL_FMPI2C_DisableAnalogFilter(FMPI2C_TypeDef * FMPI2Cx)528  __STATIC_INLINE void LL_FMPI2C_DisableAnalogFilter(FMPI2C_TypeDef *FMPI2Cx)
529  {
530    SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF);
531  }
532  
533  /**
534    * @brief  Check if Analog Noise Filter is enabled or disabled.
535    * @rmtoll CR1          ANFOFF        LL_FMPI2C_IsEnabledAnalogFilter
536    * @param  FMPI2Cx FMPI2C Instance.
537    * @retval State of bit (1 or 0).
538    */
LL_FMPI2C_IsEnabledAnalogFilter(FMPI2C_TypeDef * FMPI2Cx)539  __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAnalogFilter(FMPI2C_TypeDef *FMPI2Cx)
540  {
541    return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF) != (FMPI2C_CR1_ANFOFF)) ? 1UL : 0UL);
542  }
543  
544  /**
545    * @brief  Enable DMA transmission requests.
546    * @rmtoll CR1          TXDMAEN       LL_FMPI2C_EnableDMAReq_TX
547    * @param  FMPI2Cx FMPI2C Instance.
548    * @retval None
549    */
LL_FMPI2C_EnableDMAReq_TX(FMPI2C_TypeDef * FMPI2Cx)550  __STATIC_INLINE void LL_FMPI2C_EnableDMAReq_TX(FMPI2C_TypeDef *FMPI2Cx)
551  {
552    SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXDMAEN);
553  }
554  
555  /**
556    * @brief  Disable DMA transmission requests.
557    * @rmtoll CR1          TXDMAEN       LL_FMPI2C_DisableDMAReq_TX
558    * @param  FMPI2Cx FMPI2C Instance.
559    * @retval None
560    */
LL_FMPI2C_DisableDMAReq_TX(FMPI2C_TypeDef * FMPI2Cx)561  __STATIC_INLINE void LL_FMPI2C_DisableDMAReq_TX(FMPI2C_TypeDef *FMPI2Cx)
562  {
563    CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXDMAEN);
564  }
565  
566  /**
567    * @brief  Check if DMA transmission requests are enabled or disabled.
568    * @rmtoll CR1          TXDMAEN       LL_FMPI2C_IsEnabledDMAReq_TX
569    * @param  FMPI2Cx FMPI2C Instance.
570    * @retval State of bit (1 or 0).
571    */
LL_FMPI2C_IsEnabledDMAReq_TX(FMPI2C_TypeDef * FMPI2Cx)572  __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledDMAReq_TX(FMPI2C_TypeDef *FMPI2Cx)
573  {
574    return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXDMAEN) == (FMPI2C_CR1_TXDMAEN)) ? 1UL : 0UL);
575  }
576  
577  /**
578    * @brief  Enable DMA reception requests.
579    * @rmtoll CR1          RXDMAEN       LL_FMPI2C_EnableDMAReq_RX
580    * @param  FMPI2Cx FMPI2C Instance.
581    * @retval None
582    */
LL_FMPI2C_EnableDMAReq_RX(FMPI2C_TypeDef * FMPI2Cx)583  __STATIC_INLINE void LL_FMPI2C_EnableDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx)
584  {
585    SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXDMAEN);
586  }
587  
588  /**
589    * @brief  Disable DMA reception requests.
590    * @rmtoll CR1          RXDMAEN       LL_FMPI2C_DisableDMAReq_RX
591    * @param  FMPI2Cx FMPI2C Instance.
592    * @retval None
593    */
LL_FMPI2C_DisableDMAReq_RX(FMPI2C_TypeDef * FMPI2Cx)594  __STATIC_INLINE void LL_FMPI2C_DisableDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx)
595  {
596    CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXDMAEN);
597  }
598  
599  /**
600    * @brief  Check if DMA reception requests are enabled or disabled.
601    * @rmtoll CR1          RXDMAEN       LL_FMPI2C_IsEnabledDMAReq_RX
602    * @param  FMPI2Cx FMPI2C Instance.
603    * @retval State of bit (1 or 0).
604    */
LL_FMPI2C_IsEnabledDMAReq_RX(FMPI2C_TypeDef * FMPI2Cx)605  __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx)
606  {
607    return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXDMAEN) == (FMPI2C_CR1_RXDMAEN)) ? 1UL : 0UL);
608  }
609  
610  /**
611    * @brief  Get the data register address used for DMA transfer
612    * @rmtoll TXDR         TXDATA        LL_FMPI2C_DMA_GetRegAddr\n
613    *         RXDR         RXDATA        LL_FMPI2C_DMA_GetRegAddr
614    * @param  FMPI2Cx FMPI2C Instance
615    * @param  Direction This parameter can be one of the following values:
616    *         @arg @ref LL_FMPI2C_DMA_REG_DATA_TRANSMIT
617    *         @arg @ref LL_FMPI2C_DMA_REG_DATA_RECEIVE
618    * @retval Address of data register
619    */
LL_FMPI2C_DMA_GetRegAddr(FMPI2C_TypeDef * FMPI2Cx,uint32_t Direction)620  __STATIC_INLINE uint32_t LL_FMPI2C_DMA_GetRegAddr(FMPI2C_TypeDef *FMPI2Cx, uint32_t Direction)
621  {
622    uint32_t data_reg_addr;
623  
624    if (Direction == LL_FMPI2C_DMA_REG_DATA_TRANSMIT)
625    {
626      /* return address of TXDR register */
627      data_reg_addr = (uint32_t) &(FMPI2Cx->TXDR);
628    }
629    else
630    {
631      /* return address of RXDR register */
632      data_reg_addr = (uint32_t) &(FMPI2Cx->RXDR);
633    }
634  
635    return data_reg_addr;
636  }
637  
638  /**
639    * @brief  Enable Clock stretching.
640    * @note   This bit can only be programmed when the FMPI2C is disabled (PE = 0).
641    * @rmtoll CR1          NOSTRETCH     LL_FMPI2C_EnableClockStretching
642    * @param  FMPI2Cx FMPI2C Instance.
643    * @retval None
644    */
LL_FMPI2C_EnableClockStretching(FMPI2C_TypeDef * FMPI2Cx)645  __STATIC_INLINE void LL_FMPI2C_EnableClockStretching(FMPI2C_TypeDef *FMPI2Cx)
646  {
647    CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NOSTRETCH);
648  }
649  
650  /**
651    * @brief  Disable Clock stretching.
652    * @note   This bit can only be programmed when the FMPI2C is disabled (PE = 0).
653    * @rmtoll CR1          NOSTRETCH     LL_FMPI2C_DisableClockStretching
654    * @param  FMPI2Cx FMPI2C Instance.
655    * @retval None
656    */
LL_FMPI2C_DisableClockStretching(FMPI2C_TypeDef * FMPI2Cx)657  __STATIC_INLINE void LL_FMPI2C_DisableClockStretching(FMPI2C_TypeDef *FMPI2Cx)
658  {
659    SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NOSTRETCH);
660  }
661  
662  /**
663    * @brief  Check if Clock stretching is enabled or disabled.
664    * @rmtoll CR1          NOSTRETCH     LL_FMPI2C_IsEnabledClockStretching
665    * @param  FMPI2Cx FMPI2C Instance.
666    * @retval State of bit (1 or 0).
667    */
LL_FMPI2C_IsEnabledClockStretching(FMPI2C_TypeDef * FMPI2Cx)668  __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledClockStretching(FMPI2C_TypeDef *FMPI2Cx)
669  {
670    return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NOSTRETCH) != (FMPI2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
671  }
672  
673  /**
674    * @brief  Enable hardware byte control in slave mode.
675    * @rmtoll CR1          SBC           LL_FMPI2C_EnableSlaveByteControl
676    * @param  FMPI2Cx FMPI2C Instance.
677    * @retval None
678    */
LL_FMPI2C_EnableSlaveByteControl(FMPI2C_TypeDef * FMPI2Cx)679  __STATIC_INLINE void LL_FMPI2C_EnableSlaveByteControl(FMPI2C_TypeDef *FMPI2Cx)
680  {
681    SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SBC);
682  }
683  
684  /**
685    * @brief  Disable hardware byte control in slave mode.
686    * @rmtoll CR1          SBC           LL_FMPI2C_DisableSlaveByteControl
687    * @param  FMPI2Cx FMPI2C Instance.
688    * @retval None
689    */
LL_FMPI2C_DisableSlaveByteControl(FMPI2C_TypeDef * FMPI2Cx)690  __STATIC_INLINE void LL_FMPI2C_DisableSlaveByteControl(FMPI2C_TypeDef *FMPI2Cx)
691  {
692    CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SBC);
693  }
694  
695  /**
696    * @brief  Check if hardware byte control in slave mode is enabled or disabled.
697    * @rmtoll CR1          SBC           LL_FMPI2C_IsEnabledSlaveByteControl
698    * @param  FMPI2Cx FMPI2C Instance.
699    * @retval State of bit (1 or 0).
700    */
LL_FMPI2C_IsEnabledSlaveByteControl(FMPI2C_TypeDef * FMPI2Cx)701  __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSlaveByteControl(FMPI2C_TypeDef *FMPI2Cx)
702  {
703    return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SBC) == (FMPI2C_CR1_SBC)) ? 1UL : 0UL);
704  }
705  
706  /**
707    * @brief  Enable General Call.
708    * @note   When enabled the Address 0x00 is ACKed.
709    * @rmtoll CR1          GCEN          LL_FMPI2C_EnableGeneralCall
710    * @param  FMPI2Cx FMPI2C Instance.
711    * @retval None
712    */
LL_FMPI2C_EnableGeneralCall(FMPI2C_TypeDef * FMPI2Cx)713  __STATIC_INLINE void LL_FMPI2C_EnableGeneralCall(FMPI2C_TypeDef *FMPI2Cx)
714  {
715    SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_GCEN);
716  }
717  
718  /**
719    * @brief  Disable General Call.
720    * @note   When disabled the Address 0x00 is NACKed.
721    * @rmtoll CR1          GCEN          LL_FMPI2C_DisableGeneralCall
722    * @param  FMPI2Cx FMPI2C Instance.
723    * @retval None
724    */
LL_FMPI2C_DisableGeneralCall(FMPI2C_TypeDef * FMPI2Cx)725  __STATIC_INLINE void LL_FMPI2C_DisableGeneralCall(FMPI2C_TypeDef *FMPI2Cx)
726  {
727    CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_GCEN);
728  }
729  
730  /**
731    * @brief  Check if General Call is enabled or disabled.
732    * @rmtoll CR1          GCEN          LL_FMPI2C_IsEnabledGeneralCall
733    * @param  FMPI2Cx FMPI2C Instance.
734    * @retval State of bit (1 or 0).
735    */
LL_FMPI2C_IsEnabledGeneralCall(FMPI2C_TypeDef * FMPI2Cx)736  __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledGeneralCall(FMPI2C_TypeDef *FMPI2Cx)
737  {
738    return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_GCEN) == (FMPI2C_CR1_GCEN)) ? 1UL : 0UL);
739  }
740  
741  /**
742    * @brief  Configure the Master to operate in 7-bit or 10-bit addressing mode.
743    * @note   Changing this bit is not allowed, when the START bit is set.
744    * @rmtoll CR2          ADD10         LL_FMPI2C_SetMasterAddressingMode
745    * @param  FMPI2Cx FMPI2C Instance.
746    * @param  AddressingMode This parameter can be one of the following values:
747    *         @arg @ref LL_FMPI2C_ADDRESSING_MODE_7BIT
748    *         @arg @ref LL_FMPI2C_ADDRESSING_MODE_10BIT
749    * @retval None
750    */
LL_FMPI2C_SetMasterAddressingMode(FMPI2C_TypeDef * FMPI2Cx,uint32_t AddressingMode)751  __STATIC_INLINE void LL_FMPI2C_SetMasterAddressingMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t AddressingMode)
752  {
753    MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_ADD10, AddressingMode);
754  }
755  
756  /**
757    * @brief  Get the Master addressing mode.
758    * @rmtoll CR2          ADD10         LL_FMPI2C_GetMasterAddressingMode
759    * @param  FMPI2Cx FMPI2C Instance.
760    * @retval Returned value can be one of the following values:
761    *         @arg @ref LL_FMPI2C_ADDRESSING_MODE_7BIT
762    *         @arg @ref LL_FMPI2C_ADDRESSING_MODE_10BIT
763    */
LL_FMPI2C_GetMasterAddressingMode(FMPI2C_TypeDef * FMPI2Cx)764  __STATIC_INLINE uint32_t LL_FMPI2C_GetMasterAddressingMode(FMPI2C_TypeDef *FMPI2Cx)
765  {
766    return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_ADD10));
767  }
768  
769  /**
770    * @brief  Set the Own Address1.
771    * @rmtoll OAR1         OA1           LL_FMPI2C_SetOwnAddress1\n
772    *         OAR1         OA1MODE       LL_FMPI2C_SetOwnAddress1
773    * @param  FMPI2Cx FMPI2C Instance.
774    * @param  OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
775    * @param  OwnAddrSize This parameter can be one of the following values:
776    *         @arg @ref LL_FMPI2C_OWNADDRESS1_7BIT
777    *         @arg @ref LL_FMPI2C_OWNADDRESS1_10BIT
778    * @retval None
779    */
LL_FMPI2C_SetOwnAddress1(FMPI2C_TypeDef * FMPI2Cx,uint32_t OwnAddress1,uint32_t OwnAddrSize)780  __STATIC_INLINE void LL_FMPI2C_SetOwnAddress1(FMPI2C_TypeDef *FMPI2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
781  {
782    MODIFY_REG(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1 | FMPI2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
783  }
784  
785  /**
786    * @brief  Enable acknowledge on Own Address1 match address.
787    * @rmtoll OAR1         OA1EN         LL_FMPI2C_EnableOwnAddress1
788    * @param  FMPI2Cx FMPI2C Instance.
789    * @retval None
790    */
LL_FMPI2C_EnableOwnAddress1(FMPI2C_TypeDef * FMPI2Cx)791  __STATIC_INLINE void LL_FMPI2C_EnableOwnAddress1(FMPI2C_TypeDef *FMPI2Cx)
792  {
793    SET_BIT(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1EN);
794  }
795  
796  /**
797    * @brief  Disable acknowledge on Own Address1 match address.
798    * @rmtoll OAR1         OA1EN         LL_FMPI2C_DisableOwnAddress1
799    * @param  FMPI2Cx FMPI2C Instance.
800    * @retval None
801    */
LL_FMPI2C_DisableOwnAddress1(FMPI2C_TypeDef * FMPI2Cx)802  __STATIC_INLINE void LL_FMPI2C_DisableOwnAddress1(FMPI2C_TypeDef *FMPI2Cx)
803  {
804    CLEAR_BIT(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1EN);
805  }
806  
807  /**
808    * @brief  Check if Own Address1 acknowledge is enabled or disabled.
809    * @rmtoll OAR1         OA1EN         LL_FMPI2C_IsEnabledOwnAddress1
810    * @param  FMPI2Cx FMPI2C Instance.
811    * @retval State of bit (1 or 0).
812    */
LL_FMPI2C_IsEnabledOwnAddress1(FMPI2C_TypeDef * FMPI2Cx)813  __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledOwnAddress1(FMPI2C_TypeDef *FMPI2Cx)
814  {
815    return ((READ_BIT(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1EN) == (FMPI2C_OAR1_OA1EN)) ? 1UL : 0UL);
816  }
817  
818  /**
819    * @brief  Set the 7bits Own Address2.
820    * @note   This action has no effect if own address2 is enabled.
821    * @rmtoll OAR2         OA2           LL_FMPI2C_SetOwnAddress2\n
822    *         OAR2         OA2MSK        LL_FMPI2C_SetOwnAddress2
823    * @param  FMPI2Cx FMPI2C Instance.
824    * @param  OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
825    * @param  OwnAddrMask This parameter can be one of the following values:
826    *         @arg @ref LL_FMPI2C_OWNADDRESS2_NOMASK
827    *         @arg @ref LL_FMPI2C_OWNADDRESS2_MASK01
828    *         @arg @ref LL_FMPI2C_OWNADDRESS2_MASK02
829    *         @arg @ref LL_FMPI2C_OWNADDRESS2_MASK03
830    *         @arg @ref LL_FMPI2C_OWNADDRESS2_MASK04
831    *         @arg @ref LL_FMPI2C_OWNADDRESS2_MASK05
832    *         @arg @ref LL_FMPI2C_OWNADDRESS2_MASK06
833    *         @arg @ref LL_FMPI2C_OWNADDRESS2_MASK07
834    * @retval None
835    */
LL_FMPI2C_SetOwnAddress2(FMPI2C_TypeDef * FMPI2Cx,uint32_t OwnAddress2,uint32_t OwnAddrMask)836  __STATIC_INLINE void LL_FMPI2C_SetOwnAddress2(FMPI2C_TypeDef *FMPI2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
837  {
838    MODIFY_REG(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2 | FMPI2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
839  }
840  
841  /**
842    * @brief  Enable acknowledge on Own Address2 match address.
843    * @rmtoll OAR2         OA2EN         LL_FMPI2C_EnableOwnAddress2
844    * @param  FMPI2Cx FMPI2C Instance.
845    * @retval None
846    */
LL_FMPI2C_EnableOwnAddress2(FMPI2C_TypeDef * FMPI2Cx)847  __STATIC_INLINE void LL_FMPI2C_EnableOwnAddress2(FMPI2C_TypeDef *FMPI2Cx)
848  {
849    SET_BIT(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2EN);
850  }
851  
852  /**
853    * @brief  Disable  acknowledge on Own Address2 match address.
854    * @rmtoll OAR2         OA2EN         LL_FMPI2C_DisableOwnAddress2
855    * @param  FMPI2Cx FMPI2C Instance.
856    * @retval None
857    */
LL_FMPI2C_DisableOwnAddress2(FMPI2C_TypeDef * FMPI2Cx)858  __STATIC_INLINE void LL_FMPI2C_DisableOwnAddress2(FMPI2C_TypeDef *FMPI2Cx)
859  {
860    CLEAR_BIT(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2EN);
861  }
862  
863  /**
864    * @brief  Check if Own Address1 acknowledge is enabled or disabled.
865    * @rmtoll OAR2         OA2EN         LL_FMPI2C_IsEnabledOwnAddress2
866    * @param  FMPI2Cx FMPI2C Instance.
867    * @retval State of bit (1 or 0).
868    */
LL_FMPI2C_IsEnabledOwnAddress2(FMPI2C_TypeDef * FMPI2Cx)869  __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledOwnAddress2(FMPI2C_TypeDef *FMPI2Cx)
870  {
871    return ((READ_BIT(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2EN) == (FMPI2C_OAR2_OA2EN)) ? 1UL : 0UL);
872  }
873  
874  /**
875    * @brief  Configure the SDA setup, hold time and the SCL high, low period.
876    * @note   This bit can only be programmed when the FMPI2C is disabled (PE = 0).
877    * @rmtoll TIMINGR      TIMINGR       LL_FMPI2C_SetTiming
878    * @param  FMPI2Cx FMPI2C Instance.
879    * @param  Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
880    * @note   This parameter is computed with the STM32CubeMX Tool.
881    * @retval None
882    */
LL_FMPI2C_SetTiming(FMPI2C_TypeDef * FMPI2Cx,uint32_t Timing)883  __STATIC_INLINE void LL_FMPI2C_SetTiming(FMPI2C_TypeDef *FMPI2Cx, uint32_t Timing)
884  {
885    WRITE_REG(FMPI2Cx->TIMINGR, Timing);
886  }
887  
888  /**
889    * @brief  Get the Timing Prescaler setting.
890    * @rmtoll TIMINGR      PRESC         LL_FMPI2C_GetTimingPrescaler
891    * @param  FMPI2Cx FMPI2C Instance.
892    * @retval Value between Min_Data=0x0 and Max_Data=0xF
893    */
LL_FMPI2C_GetTimingPrescaler(FMPI2C_TypeDef * FMPI2Cx)894  __STATIC_INLINE uint32_t LL_FMPI2C_GetTimingPrescaler(FMPI2C_TypeDef *FMPI2Cx)
895  {
896    return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_PRESC) >> FMPI2C_TIMINGR_PRESC_Pos);
897  }
898  
899  /**
900    * @brief  Get the SCL low period setting.
901    * @rmtoll TIMINGR      SCLL          LL_FMPI2C_GetClockLowPeriod
902    * @param  FMPI2Cx FMPI2C Instance.
903    * @retval Value between Min_Data=0x00 and Max_Data=0xFF
904    */
LL_FMPI2C_GetClockLowPeriod(FMPI2C_TypeDef * FMPI2Cx)905  __STATIC_INLINE uint32_t LL_FMPI2C_GetClockLowPeriod(FMPI2C_TypeDef *FMPI2Cx)
906  {
907    return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLL) >> FMPI2C_TIMINGR_SCLL_Pos);
908  }
909  
910  /**
911    * @brief  Get the SCL high period setting.
912    * @rmtoll TIMINGR      SCLH          LL_FMPI2C_GetClockHighPeriod
913    * @param  FMPI2Cx FMPI2C Instance.
914    * @retval Value between Min_Data=0x00 and Max_Data=0xFF
915    */
LL_FMPI2C_GetClockHighPeriod(FMPI2C_TypeDef * FMPI2Cx)916  __STATIC_INLINE uint32_t LL_FMPI2C_GetClockHighPeriod(FMPI2C_TypeDef *FMPI2Cx)
917  {
918    return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLH) >> FMPI2C_TIMINGR_SCLH_Pos);
919  }
920  
921  /**
922    * @brief  Get the SDA hold time.
923    * @rmtoll TIMINGR      SDADEL        LL_FMPI2C_GetDataHoldTime
924    * @param  FMPI2Cx FMPI2C Instance.
925    * @retval Value between Min_Data=0x0 and Max_Data=0xF
926    */
LL_FMPI2C_GetDataHoldTime(FMPI2C_TypeDef * FMPI2Cx)927  __STATIC_INLINE uint32_t LL_FMPI2C_GetDataHoldTime(FMPI2C_TypeDef *FMPI2Cx)
928  {
929    return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SDADEL) >> FMPI2C_TIMINGR_SDADEL_Pos);
930  }
931  
932  /**
933    * @brief  Get the SDA setup time.
934    * @rmtoll TIMINGR      SCLDEL        LL_FMPI2C_GetDataSetupTime
935    * @param  FMPI2Cx FMPI2C Instance.
936    * @retval Value between Min_Data=0x0 and Max_Data=0xF
937    */
LL_FMPI2C_GetDataSetupTime(FMPI2C_TypeDef * FMPI2Cx)938  __STATIC_INLINE uint32_t LL_FMPI2C_GetDataSetupTime(FMPI2C_TypeDef *FMPI2Cx)
939  {
940    return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLDEL) >> FMPI2C_TIMINGR_SCLDEL_Pos);
941  }
942  
943  /**
944    * @brief  Configure peripheral mode.
945    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
946    *         SMBus feature is supported by the FMPI2Cx Instance.
947    * @rmtoll CR1          SMBHEN        LL_FMPI2C_SetMode\n
948    *         CR1          SMBDEN        LL_FMPI2C_SetMode
949    * @param  FMPI2Cx FMPI2C Instance.
950    * @param  PeripheralMode This parameter can be one of the following values:
951    *         @arg @ref LL_FMPI2C_MODE_I2C
952    *         @arg @ref LL_FMPI2C_MODE_SMBUS_HOST
953    *         @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE
954    *         @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE_ARP
955    * @retval None
956    */
LL_FMPI2C_SetMode(FMPI2C_TypeDef * FMPI2Cx,uint32_t PeripheralMode)957  __STATIC_INLINE void LL_FMPI2C_SetMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t PeripheralMode)
958  {
959    MODIFY_REG(FMPI2Cx->CR1, FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN, PeripheralMode);
960  }
961  
962  /**
963    * @brief  Get peripheral mode.
964    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
965    *         SMBus feature is supported by the FMPI2Cx Instance.
966    * @rmtoll CR1          SMBHEN        LL_FMPI2C_GetMode\n
967    *         CR1          SMBDEN        LL_FMPI2C_GetMode
968    * @param  FMPI2Cx FMPI2C Instance.
969    * @retval Returned value can be one of the following values:
970    *         @arg @ref LL_FMPI2C_MODE_I2C
971    *         @arg @ref LL_FMPI2C_MODE_SMBUS_HOST
972    *         @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE
973    *         @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE_ARP
974    */
LL_FMPI2C_GetMode(FMPI2C_TypeDef * FMPI2Cx)975  __STATIC_INLINE uint32_t LL_FMPI2C_GetMode(FMPI2C_TypeDef *FMPI2Cx)
976  {
977    return (uint32_t)(READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN));
978  }
979  
980  /**
981    * @brief  Enable SMBus alert (Host or Device mode)
982    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
983    *         SMBus feature is supported by the FMPI2Cx Instance.
984    * @note   SMBus Device mode:
985    *         - SMBus Alert pin is drived low and
986    *           Alert Response Address Header acknowledge is enabled.
987    *         SMBus Host mode:
988    *         - SMBus Alert pin management is supported.
989    * @rmtoll CR1          ALERTEN       LL_FMPI2C_EnableSMBusAlert
990    * @param  FMPI2Cx FMPI2C Instance.
991    * @retval None
992    */
LL_FMPI2C_EnableSMBusAlert(FMPI2C_TypeDef * FMPI2Cx)993  __STATIC_INLINE void LL_FMPI2C_EnableSMBusAlert(FMPI2C_TypeDef *FMPI2Cx)
994  {
995    SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ALERTEN);
996  }
997  
998  /**
999    * @brief  Disable SMBus alert (Host or Device mode)
1000    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1001    *         SMBus feature is supported by the FMPI2Cx Instance.
1002    * @note   SMBus Device mode:
1003    *         - SMBus Alert pin is not drived (can be used as a standard GPIO) and
1004    *           Alert Response Address Header acknowledge is disabled.
1005    *         SMBus Host mode:
1006    *         - SMBus Alert pin management is not supported.
1007    * @rmtoll CR1          ALERTEN       LL_FMPI2C_DisableSMBusAlert
1008    * @param  FMPI2Cx FMPI2C Instance.
1009    * @retval None
1010    */
LL_FMPI2C_DisableSMBusAlert(FMPI2C_TypeDef * FMPI2Cx)1011  __STATIC_INLINE void LL_FMPI2C_DisableSMBusAlert(FMPI2C_TypeDef *FMPI2Cx)
1012  {
1013    CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ALERTEN);
1014  }
1015  
1016  /**
1017    * @brief  Check if SMBus alert (Host or Device mode) is enabled or disabled.
1018    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1019    *         SMBus feature is supported by the FMPI2Cx Instance.
1020    * @rmtoll CR1          ALERTEN       LL_FMPI2C_IsEnabledSMBusAlert
1021    * @param  FMPI2Cx FMPI2C Instance.
1022    * @retval State of bit (1 or 0).
1023    */
LL_FMPI2C_IsEnabledSMBusAlert(FMPI2C_TypeDef * FMPI2Cx)1024  __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusAlert(FMPI2C_TypeDef *FMPI2Cx)
1025  {
1026    return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ALERTEN) == (FMPI2C_CR1_ALERTEN)) ? 1UL : 0UL);
1027  }
1028  
1029  /**
1030    * @brief  Enable SMBus Packet Error Calculation (PEC).
1031    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1032    *         SMBus feature is supported by the FMPI2Cx Instance.
1033    * @rmtoll CR1          PECEN         LL_FMPI2C_EnableSMBusPEC
1034    * @param  FMPI2Cx FMPI2C Instance.
1035    * @retval None
1036    */
LL_FMPI2C_EnableSMBusPEC(FMPI2C_TypeDef * FMPI2Cx)1037  __STATIC_INLINE void LL_FMPI2C_EnableSMBusPEC(FMPI2C_TypeDef *FMPI2Cx)
1038  {
1039    SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PECEN);
1040  }
1041  
1042  /**
1043    * @brief  Disable SMBus Packet Error Calculation (PEC).
1044    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1045    *         SMBus feature is supported by the FMPI2Cx Instance.
1046    * @rmtoll CR1          PECEN         LL_FMPI2C_DisableSMBusPEC
1047    * @param  FMPI2Cx FMPI2C Instance.
1048    * @retval None
1049    */
LL_FMPI2C_DisableSMBusPEC(FMPI2C_TypeDef * FMPI2Cx)1050  __STATIC_INLINE void LL_FMPI2C_DisableSMBusPEC(FMPI2C_TypeDef *FMPI2Cx)
1051  {
1052    CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PECEN);
1053  }
1054  
1055  /**
1056    * @brief  Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
1057    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1058    *         SMBus feature is supported by the FMPI2Cx Instance.
1059    * @rmtoll CR1          PECEN         LL_FMPI2C_IsEnabledSMBusPEC
1060    * @param  FMPI2Cx FMPI2C Instance.
1061    * @retval State of bit (1 or 0).
1062    */
LL_FMPI2C_IsEnabledSMBusPEC(FMPI2C_TypeDef * FMPI2Cx)1063  __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPEC(FMPI2C_TypeDef *FMPI2Cx)
1064  {
1065    return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PECEN) == (FMPI2C_CR1_PECEN)) ? 1UL : 0UL);
1066  }
1067  
1068  /**
1069    * @brief  Configure the SMBus Clock Timeout.
1070    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1071    *         SMBus feature is supported by the FMPI2Cx Instance.
1072    * @note   This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
1073    * @rmtoll TIMEOUTR     TIMEOUTA      LL_FMPI2C_ConfigSMBusTimeout\n
1074    *         TIMEOUTR     TIDLE         LL_FMPI2C_ConfigSMBusTimeout\n
1075    *         TIMEOUTR     TIMEOUTB      LL_FMPI2C_ConfigSMBusTimeout
1076    * @param  FMPI2Cx FMPI2C Instance.
1077    * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
1078    * @param  TimeoutAMode This parameter can be one of the following values:
1079    *         @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SCL_LOW
1080    *         @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1081    * @param  TimeoutB
1082    * @retval None
1083    */
LL_FMPI2C_ConfigSMBusTimeout(FMPI2C_TypeDef * FMPI2Cx,uint32_t TimeoutA,uint32_t TimeoutAMode,uint32_t TimeoutB)1084  __STATIC_INLINE void LL_FMPI2C_ConfigSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
1085                                                 uint32_t TimeoutB)
1086  {
1087    MODIFY_REG(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTA | FMPI2C_TIMEOUTR_TIDLE | FMPI2C_TIMEOUTR_TIMEOUTB,
1088               TimeoutA | TimeoutAMode | (TimeoutB << FMPI2C_TIMEOUTR_TIMEOUTB_Pos));
1089  }
1090  
1091  /**
1092    * @brief  Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
1093    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1094    *         SMBus feature is supported by the FMPI2Cx Instance.
1095    * @note   These bits can only be programmed when TimeoutA is disabled.
1096    * @rmtoll TIMEOUTR     TIMEOUTA      LL_FMPI2C_SetSMBusTimeoutA
1097    * @param  FMPI2Cx FMPI2C Instance.
1098    * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
1099    * @retval None
1100    */
LL_FMPI2C_SetSMBusTimeoutA(FMPI2C_TypeDef * FMPI2Cx,uint32_t TimeoutA)1101  __STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutA(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutA)
1102  {
1103    WRITE_REG(FMPI2Cx->TIMEOUTR, TimeoutA);
1104  }
1105  
1106  /**
1107    * @brief  Get the SMBus Clock TimeoutA setting.
1108    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1109    *         SMBus feature is supported by the FMPI2Cx Instance.
1110    * @rmtoll TIMEOUTR     TIMEOUTA      LL_FMPI2C_GetSMBusTimeoutA
1111    * @param  FMPI2Cx FMPI2C Instance.
1112    * @retval Value between Min_Data=0 and Max_Data=0xFFF
1113    */
LL_FMPI2C_GetSMBusTimeoutA(FMPI2C_TypeDef * FMPI2Cx)1114  __STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutA(FMPI2C_TypeDef *FMPI2Cx)
1115  {
1116    return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTA));
1117  }
1118  
1119  /**
1120    * @brief  Set the SMBus Clock TimeoutA mode.
1121    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1122    *         SMBus feature is supported by the FMPI2Cx Instance.
1123    * @note   This bit can only be programmed when TimeoutA is disabled.
1124    * @rmtoll TIMEOUTR     TIDLE         LL_FMPI2C_SetSMBusTimeoutAMode
1125    * @param  FMPI2Cx FMPI2C Instance.
1126    * @param  TimeoutAMode This parameter can be one of the following values:
1127    *         @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SCL_LOW
1128    *         @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1129    * @retval None
1130    */
LL_FMPI2C_SetSMBusTimeoutAMode(FMPI2C_TypeDef * FMPI2Cx,uint32_t TimeoutAMode)1131  __STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutAMode)
1132  {
1133    WRITE_REG(FMPI2Cx->TIMEOUTR, TimeoutAMode);
1134  }
1135  
1136  /**
1137    * @brief  Get the SMBus Clock TimeoutA mode.
1138    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1139    *         SMBus feature is supported by the FMPI2Cx Instance.
1140    * @rmtoll TIMEOUTR     TIDLE         LL_FMPI2C_GetSMBusTimeoutAMode
1141    * @param  FMPI2Cx FMPI2C Instance.
1142    * @retval Returned value can be one of the following values:
1143    *         @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SCL_LOW
1144    *         @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1145    */
LL_FMPI2C_GetSMBusTimeoutAMode(FMPI2C_TypeDef * FMPI2Cx)1146  __STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx)
1147  {
1148    return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIDLE));
1149  }
1150  
1151  /**
1152    * @brief  Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
1153    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1154    *         SMBus feature is supported by the FMPI2Cx Instance.
1155    * @note   These bits can only be programmed when TimeoutB is disabled.
1156    * @rmtoll TIMEOUTR     TIMEOUTB      LL_FMPI2C_SetSMBusTimeoutB
1157    * @param  FMPI2Cx FMPI2C Instance.
1158    * @param  TimeoutB This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
1159    * @retval None
1160    */
LL_FMPI2C_SetSMBusTimeoutB(FMPI2C_TypeDef * FMPI2Cx,uint32_t TimeoutB)1161  __STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutB(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutB)
1162  {
1163    WRITE_REG(FMPI2Cx->TIMEOUTR, TimeoutB << FMPI2C_TIMEOUTR_TIMEOUTB_Pos);
1164  }
1165  
1166  /**
1167    * @brief  Get the SMBus Extended Cumulative Clock TimeoutB setting.
1168    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1169    *         SMBus feature is supported by the FMPI2Cx Instance.
1170    * @rmtoll TIMEOUTR     TIMEOUTB      LL_FMPI2C_GetSMBusTimeoutB
1171    * @param  FMPI2Cx FMPI2C Instance.
1172    * @retval Value between Min_Data=0 and Max_Data=0xFFF
1173    */
LL_FMPI2C_GetSMBusTimeoutB(FMPI2C_TypeDef * FMPI2Cx)1174  __STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutB(FMPI2C_TypeDef *FMPI2Cx)
1175  {
1176    return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTB) >> FMPI2C_TIMEOUTR_TIMEOUTB_Pos);
1177  }
1178  
1179  /**
1180    * @brief  Enable the SMBus Clock Timeout.
1181    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1182    *         SMBus feature is supported by the FMPI2Cx Instance.
1183    * @rmtoll TIMEOUTR     TIMOUTEN      LL_FMPI2C_EnableSMBusTimeout\n
1184    *         TIMEOUTR     TEXTEN        LL_FMPI2C_EnableSMBusTimeout
1185    * @param  FMPI2Cx FMPI2C Instance.
1186    * @param  ClockTimeout This parameter can be one of the following values:
1187    *         @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA
1188    *         @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTB
1189    *         @arg @ref LL_FMPI2C_FMPSMBUS_ALL_TIMEOUT
1190    * @retval None
1191    */
LL_FMPI2C_EnableSMBusTimeout(FMPI2C_TypeDef * FMPI2Cx,uint32_t ClockTimeout)1192  __STATIC_INLINE void LL_FMPI2C_EnableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout)
1193  {
1194    SET_BIT(FMPI2Cx->TIMEOUTR, ClockTimeout);
1195  }
1196  
1197  /**
1198    * @brief  Disable the SMBus Clock Timeout.
1199    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1200    *         SMBus feature is supported by the FMPI2Cx Instance.
1201    * @rmtoll TIMEOUTR     TIMOUTEN      LL_FMPI2C_DisableSMBusTimeout\n
1202    *         TIMEOUTR     TEXTEN        LL_FMPI2C_DisableSMBusTimeout
1203    * @param  FMPI2Cx FMPI2C Instance.
1204    * @param  ClockTimeout This parameter can be one of the following values:
1205    *         @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA
1206    *         @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTB
1207    *         @arg @ref LL_FMPI2C_FMPSMBUS_ALL_TIMEOUT
1208    * @retval None
1209    */
LL_FMPI2C_DisableSMBusTimeout(FMPI2C_TypeDef * FMPI2Cx,uint32_t ClockTimeout)1210  __STATIC_INLINE void LL_FMPI2C_DisableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout)
1211  {
1212    CLEAR_BIT(FMPI2Cx->TIMEOUTR, ClockTimeout);
1213  }
1214  
1215  /**
1216    * @brief  Check if the SMBus Clock Timeout is enabled or disabled.
1217    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1218    *         SMBus feature is supported by the FMPI2Cx Instance.
1219    * @rmtoll TIMEOUTR     TIMOUTEN      LL_FMPI2C_IsEnabledSMBusTimeout\n
1220    *         TIMEOUTR     TEXTEN        LL_FMPI2C_IsEnabledSMBusTimeout
1221    * @param  FMPI2Cx FMPI2C Instance.
1222    * @param  ClockTimeout This parameter can be one of the following values:
1223    *         @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA
1224    *         @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTB
1225    *         @arg @ref LL_FMPI2C_FMPSMBUS_ALL_TIMEOUT
1226    * @retval State of bit (1 or 0).
1227    */
LL_FMPI2C_IsEnabledSMBusTimeout(FMPI2C_TypeDef * FMPI2Cx,uint32_t ClockTimeout)1228  __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout)
1229  {
1230    return ((READ_BIT(FMPI2Cx->TIMEOUTR, (FMPI2C_TIMEOUTR_TIMOUTEN | FMPI2C_TIMEOUTR_TEXTEN)) == \
1231             (ClockTimeout)) ? 1UL : 0UL);
1232  }
1233  
1234  /**
1235    * @}
1236    */
1237  
1238  /** @defgroup FMPI2C_LL_EF_IT_Management IT_Management
1239    * @{
1240    */
1241  
1242  /**
1243    * @brief  Enable TXIS interrupt.
1244    * @rmtoll CR1          TXIE          LL_FMPI2C_EnableIT_TX
1245    * @param  FMPI2Cx FMPI2C Instance.
1246    * @retval None
1247    */
LL_FMPI2C_EnableIT_TX(FMPI2C_TypeDef * FMPI2Cx)1248  __STATIC_INLINE void LL_FMPI2C_EnableIT_TX(FMPI2C_TypeDef *FMPI2Cx)
1249  {
1250    SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXIE);
1251  }
1252  
1253  /**
1254    * @brief  Disable TXIS interrupt.
1255    * @rmtoll CR1          TXIE          LL_FMPI2C_DisableIT_TX
1256    * @param  FMPI2Cx FMPI2C Instance.
1257    * @retval None
1258    */
LL_FMPI2C_DisableIT_TX(FMPI2C_TypeDef * FMPI2Cx)1259  __STATIC_INLINE void LL_FMPI2C_DisableIT_TX(FMPI2C_TypeDef *FMPI2Cx)
1260  {
1261    CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXIE);
1262  }
1263  
1264  /**
1265    * @brief  Check if the TXIS Interrupt is enabled or disabled.
1266    * @rmtoll CR1          TXIE          LL_FMPI2C_IsEnabledIT_TX
1267    * @param  FMPI2Cx FMPI2C Instance.
1268    * @retval State of bit (1 or 0).
1269    */
LL_FMPI2C_IsEnabledIT_TX(FMPI2C_TypeDef * FMPI2Cx)1270  __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_TX(FMPI2C_TypeDef *FMPI2Cx)
1271  {
1272    return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXIE) == (FMPI2C_CR1_TXIE)) ? 1UL : 0UL);
1273  }
1274  
1275  /**
1276    * @brief  Enable RXNE interrupt.
1277    * @rmtoll CR1          RXIE          LL_FMPI2C_EnableIT_RX
1278    * @param  FMPI2Cx FMPI2C Instance.
1279    * @retval None
1280    */
LL_FMPI2C_EnableIT_RX(FMPI2C_TypeDef * FMPI2Cx)1281  __STATIC_INLINE void LL_FMPI2C_EnableIT_RX(FMPI2C_TypeDef *FMPI2Cx)
1282  {
1283    SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXIE);
1284  }
1285  
1286  /**
1287    * @brief  Disable RXNE interrupt.
1288    * @rmtoll CR1          RXIE          LL_FMPI2C_DisableIT_RX
1289    * @param  FMPI2Cx FMPI2C Instance.
1290    * @retval None
1291    */
LL_FMPI2C_DisableIT_RX(FMPI2C_TypeDef * FMPI2Cx)1292  __STATIC_INLINE void LL_FMPI2C_DisableIT_RX(FMPI2C_TypeDef *FMPI2Cx)
1293  {
1294    CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXIE);
1295  }
1296  
1297  /**
1298    * @brief  Check if the RXNE Interrupt is enabled or disabled.
1299    * @rmtoll CR1          RXIE          LL_FMPI2C_IsEnabledIT_RX
1300    * @param  FMPI2Cx FMPI2C Instance.
1301    * @retval State of bit (1 or 0).
1302    */
LL_FMPI2C_IsEnabledIT_RX(FMPI2C_TypeDef * FMPI2Cx)1303  __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_RX(FMPI2C_TypeDef *FMPI2Cx)
1304  {
1305    return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXIE) == (FMPI2C_CR1_RXIE)) ? 1UL : 0UL);
1306  }
1307  
1308  /**
1309    * @brief  Enable Address match interrupt (slave mode only).
1310    * @rmtoll CR1          ADDRIE        LL_FMPI2C_EnableIT_ADDR
1311    * @param  FMPI2Cx FMPI2C Instance.
1312    * @retval None
1313    */
LL_FMPI2C_EnableIT_ADDR(FMPI2C_TypeDef * FMPI2Cx)1314  __STATIC_INLINE void LL_FMPI2C_EnableIT_ADDR(FMPI2C_TypeDef *FMPI2Cx)
1315  {
1316    SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ADDRIE);
1317  }
1318  
1319  /**
1320    * @brief  Disable Address match interrupt (slave mode only).
1321    * @rmtoll CR1          ADDRIE        LL_FMPI2C_DisableIT_ADDR
1322    * @param  FMPI2Cx FMPI2C Instance.
1323    * @retval None
1324    */
LL_FMPI2C_DisableIT_ADDR(FMPI2C_TypeDef * FMPI2Cx)1325  __STATIC_INLINE void LL_FMPI2C_DisableIT_ADDR(FMPI2C_TypeDef *FMPI2Cx)
1326  {
1327    CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ADDRIE);
1328  }
1329  
1330  /**
1331    * @brief  Check if Address match interrupt is enabled or disabled.
1332    * @rmtoll CR1          ADDRIE        LL_FMPI2C_IsEnabledIT_ADDR
1333    * @param  FMPI2Cx FMPI2C Instance.
1334    * @retval State of bit (1 or 0).
1335    */
LL_FMPI2C_IsEnabledIT_ADDR(FMPI2C_TypeDef * FMPI2Cx)1336  __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_ADDR(FMPI2C_TypeDef *FMPI2Cx)
1337  {
1338    return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ADDRIE) == (FMPI2C_CR1_ADDRIE)) ? 1UL : 0UL);
1339  }
1340  
1341  /**
1342    * @brief  Enable Not acknowledge received interrupt.
1343    * @rmtoll CR1          NACKIE        LL_FMPI2C_EnableIT_NACK
1344    * @param  FMPI2Cx FMPI2C Instance.
1345    * @retval None
1346    */
LL_FMPI2C_EnableIT_NACK(FMPI2C_TypeDef * FMPI2Cx)1347  __STATIC_INLINE void LL_FMPI2C_EnableIT_NACK(FMPI2C_TypeDef *FMPI2Cx)
1348  {
1349    SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NACKIE);
1350  }
1351  
1352  /**
1353    * @brief  Disable Not acknowledge received interrupt.
1354    * @rmtoll CR1          NACKIE        LL_FMPI2C_DisableIT_NACK
1355    * @param  FMPI2Cx FMPI2C Instance.
1356    * @retval None
1357    */
LL_FMPI2C_DisableIT_NACK(FMPI2C_TypeDef * FMPI2Cx)1358  __STATIC_INLINE void LL_FMPI2C_DisableIT_NACK(FMPI2C_TypeDef *FMPI2Cx)
1359  {
1360    CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NACKIE);
1361  }
1362  
1363  /**
1364    * @brief  Check if Not acknowledge received interrupt is enabled or disabled.
1365    * @rmtoll CR1          NACKIE        LL_FMPI2C_IsEnabledIT_NACK
1366    * @param  FMPI2Cx FMPI2C Instance.
1367    * @retval State of bit (1 or 0).
1368    */
LL_FMPI2C_IsEnabledIT_NACK(FMPI2C_TypeDef * FMPI2Cx)1369  __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_NACK(FMPI2C_TypeDef *FMPI2Cx)
1370  {
1371    return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NACKIE) == (FMPI2C_CR1_NACKIE)) ? 1UL : 0UL);
1372  }
1373  
1374  /**
1375    * @brief  Enable STOP detection interrupt.
1376    * @rmtoll CR1          STOPIE        LL_FMPI2C_EnableIT_STOP
1377    * @param  FMPI2Cx FMPI2C Instance.
1378    * @retval None
1379    */
LL_FMPI2C_EnableIT_STOP(FMPI2C_TypeDef * FMPI2Cx)1380  __STATIC_INLINE void LL_FMPI2C_EnableIT_STOP(FMPI2C_TypeDef *FMPI2Cx)
1381  {
1382    SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_STOPIE);
1383  }
1384  
1385  /**
1386    * @brief  Disable STOP detection interrupt.
1387    * @rmtoll CR1          STOPIE        LL_FMPI2C_DisableIT_STOP
1388    * @param  FMPI2Cx FMPI2C Instance.
1389    * @retval None
1390    */
LL_FMPI2C_DisableIT_STOP(FMPI2C_TypeDef * FMPI2Cx)1391  __STATIC_INLINE void LL_FMPI2C_DisableIT_STOP(FMPI2C_TypeDef *FMPI2Cx)
1392  {
1393    CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_STOPIE);
1394  }
1395  
1396  /**
1397    * @brief  Check if STOP detection interrupt is enabled or disabled.
1398    * @rmtoll CR1          STOPIE        LL_FMPI2C_IsEnabledIT_STOP
1399    * @param  FMPI2Cx FMPI2C Instance.
1400    * @retval State of bit (1 or 0).
1401    */
LL_FMPI2C_IsEnabledIT_STOP(FMPI2C_TypeDef * FMPI2Cx)1402  __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_STOP(FMPI2C_TypeDef *FMPI2Cx)
1403  {
1404    return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_STOPIE) == (FMPI2C_CR1_STOPIE)) ? 1UL : 0UL);
1405  }
1406  
1407  /**
1408    * @brief  Enable Transfer Complete interrupt.
1409    * @note   Any of these events will generate interrupt :
1410    *         Transfer Complete (TC)
1411    *         Transfer Complete Reload (TCR)
1412    * @rmtoll CR1          TCIE          LL_FMPI2C_EnableIT_TC
1413    * @param  FMPI2Cx FMPI2C Instance.
1414    * @retval None
1415    */
LL_FMPI2C_EnableIT_TC(FMPI2C_TypeDef * FMPI2Cx)1416  __STATIC_INLINE void LL_FMPI2C_EnableIT_TC(FMPI2C_TypeDef *FMPI2Cx)
1417  {
1418    SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TCIE);
1419  }
1420  
1421  /**
1422    * @brief  Disable Transfer Complete interrupt.
1423    * @note   Any of these events will generate interrupt :
1424    *         Transfer Complete (TC)
1425    *         Transfer Complete Reload (TCR)
1426    * @rmtoll CR1          TCIE          LL_FMPI2C_DisableIT_TC
1427    * @param  FMPI2Cx FMPI2C Instance.
1428    * @retval None
1429    */
LL_FMPI2C_DisableIT_TC(FMPI2C_TypeDef * FMPI2Cx)1430  __STATIC_INLINE void LL_FMPI2C_DisableIT_TC(FMPI2C_TypeDef *FMPI2Cx)
1431  {
1432    CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TCIE);
1433  }
1434  
1435  /**
1436    * @brief  Check if Transfer Complete interrupt is enabled or disabled.
1437    * @rmtoll CR1          TCIE          LL_FMPI2C_IsEnabledIT_TC
1438    * @param  FMPI2Cx FMPI2C Instance.
1439    * @retval State of bit (1 or 0).
1440    */
LL_FMPI2C_IsEnabledIT_TC(FMPI2C_TypeDef * FMPI2Cx)1441  __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_TC(FMPI2C_TypeDef *FMPI2Cx)
1442  {
1443    return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TCIE) == (FMPI2C_CR1_TCIE)) ? 1UL : 0UL);
1444  }
1445  
1446  /**
1447    * @brief  Enable Error interrupts.
1448    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1449    *         SMBus feature is supported by the FMPI2Cx Instance.
1450    * @note   Any of these errors will generate interrupt :
1451    *         Arbitration Loss (ARLO)
1452    *         Bus Error detection (BERR)
1453    *         Overrun/Underrun (OVR)
1454    *         SMBus Timeout detection (TIMEOUT)
1455    *         SMBus PEC error detection (PECERR)
1456    *         SMBus Alert pin event detection (ALERT)
1457    * @rmtoll CR1          ERRIE         LL_FMPI2C_EnableIT_ERR
1458    * @param  FMPI2Cx FMPI2C Instance.
1459    * @retval None
1460    */
LL_FMPI2C_EnableIT_ERR(FMPI2C_TypeDef * FMPI2Cx)1461  __STATIC_INLINE void LL_FMPI2C_EnableIT_ERR(FMPI2C_TypeDef *FMPI2Cx)
1462  {
1463    SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ERRIE);
1464  }
1465  
1466  /**
1467    * @brief  Disable Error interrupts.
1468    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1469    *         SMBus feature is supported by the FMPI2Cx Instance.
1470    * @note   Any of these errors will generate interrupt :
1471    *         Arbitration Loss (ARLO)
1472    *         Bus Error detection (BERR)
1473    *         Overrun/Underrun (OVR)
1474    *         SMBus Timeout detection (TIMEOUT)
1475    *         SMBus PEC error detection (PECERR)
1476    *         SMBus Alert pin event detection (ALERT)
1477    * @rmtoll CR1          ERRIE         LL_FMPI2C_DisableIT_ERR
1478    * @param  FMPI2Cx FMPI2C Instance.
1479    * @retval None
1480    */
LL_FMPI2C_DisableIT_ERR(FMPI2C_TypeDef * FMPI2Cx)1481  __STATIC_INLINE void LL_FMPI2C_DisableIT_ERR(FMPI2C_TypeDef *FMPI2Cx)
1482  {
1483    CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ERRIE);
1484  }
1485  
1486  /**
1487    * @brief  Check if Error interrupts are enabled or disabled.
1488    * @rmtoll CR1          ERRIE         LL_FMPI2C_IsEnabledIT_ERR
1489    * @param  FMPI2Cx FMPI2C Instance.
1490    * @retval State of bit (1 or 0).
1491    */
LL_FMPI2C_IsEnabledIT_ERR(FMPI2C_TypeDef * FMPI2Cx)1492  __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_ERR(FMPI2C_TypeDef *FMPI2Cx)
1493  {
1494    return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ERRIE) == (FMPI2C_CR1_ERRIE)) ? 1UL : 0UL);
1495  }
1496  
1497  /**
1498    * @}
1499    */
1500  
1501  /** @defgroup FMPI2C_LL_EF_FLAG_management FLAG_management
1502    * @{
1503    */
1504  
1505  /**
1506    * @brief  Indicate the status of Transmit data register empty flag.
1507    * @note   RESET: When next data is written in Transmit data register.
1508    *         SET: When Transmit data register is empty.
1509    * @rmtoll ISR          TXE           LL_FMPI2C_IsActiveFlag_TXE
1510    * @param  FMPI2Cx FMPI2C Instance.
1511    * @retval State of bit (1 or 0).
1512    */
LL_FMPI2C_IsActiveFlag_TXE(FMPI2C_TypeDef * FMPI2Cx)1513  __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXE(FMPI2C_TypeDef *FMPI2Cx)
1514  {
1515    return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TXE) == (FMPI2C_ISR_TXE)) ? 1UL : 0UL);
1516  }
1517  
1518  /**
1519    * @brief  Indicate the status of Transmit interrupt flag.
1520    * @note   RESET: When next data is written in Transmit data register.
1521    *         SET: When Transmit data register is empty.
1522    * @rmtoll ISR          TXIS          LL_FMPI2C_IsActiveFlag_TXIS
1523    * @param  FMPI2Cx FMPI2C Instance.
1524    * @retval State of bit (1 or 0).
1525    */
LL_FMPI2C_IsActiveFlag_TXIS(FMPI2C_TypeDef * FMPI2Cx)1526  __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXIS(FMPI2C_TypeDef *FMPI2Cx)
1527  {
1528    return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TXIS) == (FMPI2C_ISR_TXIS)) ? 1UL : 0UL);
1529  }
1530  
1531  /**
1532    * @brief  Indicate the status of Receive data register not empty flag.
1533    * @note   RESET: When Receive data register is read.
1534    *         SET: When the received data is copied in Receive data register.
1535    * @rmtoll ISR          RXNE          LL_FMPI2C_IsActiveFlag_RXNE
1536    * @param  FMPI2Cx FMPI2C Instance.
1537    * @retval State of bit (1 or 0).
1538    */
LL_FMPI2C_IsActiveFlag_RXNE(FMPI2C_TypeDef * FMPI2Cx)1539  __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_RXNE(FMPI2C_TypeDef *FMPI2Cx)
1540  {
1541    return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_RXNE) == (FMPI2C_ISR_RXNE)) ? 1UL : 0UL);
1542  }
1543  
1544  /**
1545    * @brief  Indicate the status of Address matched flag (slave mode).
1546    * @note   RESET: Clear default value.
1547    *         SET: When the received slave address matched with one of the enabled slave address.
1548    * @rmtoll ISR          ADDR          LL_FMPI2C_IsActiveFlag_ADDR
1549    * @param  FMPI2Cx FMPI2C Instance.
1550    * @retval State of bit (1 or 0).
1551    */
LL_FMPI2C_IsActiveFlag_ADDR(FMPI2C_TypeDef * FMPI2Cx)1552  __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ADDR(FMPI2C_TypeDef *FMPI2Cx)
1553  {
1554    return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ADDR) == (FMPI2C_ISR_ADDR)) ? 1UL : 0UL);
1555  }
1556  
1557  /**
1558    * @brief  Indicate the status of Not Acknowledge received flag.
1559    * @note   RESET: Clear default value.
1560    *         SET: When a NACK is received after a byte transmission.
1561    * @rmtoll ISR          NACKF         LL_FMPI2C_IsActiveFlag_NACK
1562    * @param  FMPI2Cx FMPI2C Instance.
1563    * @retval State of bit (1 or 0).
1564    */
LL_FMPI2C_IsActiveFlag_NACK(FMPI2C_TypeDef * FMPI2Cx)1565  __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_NACK(FMPI2C_TypeDef *FMPI2Cx)
1566  {
1567    return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_NACKF) == (FMPI2C_ISR_NACKF)) ? 1UL : 0UL);
1568  }
1569  
1570  /**
1571    * @brief  Indicate the status of Stop detection flag.
1572    * @note   RESET: Clear default value.
1573    *         SET: When a Stop condition is detected.
1574    * @rmtoll ISR          STOPF         LL_FMPI2C_IsActiveFlag_STOP
1575    * @param  FMPI2Cx FMPI2C Instance.
1576    * @retval State of bit (1 or 0).
1577    */
LL_FMPI2C_IsActiveFlag_STOP(FMPI2C_TypeDef * FMPI2Cx)1578  __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_STOP(FMPI2C_TypeDef *FMPI2Cx)
1579  {
1580    return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_STOPF) == (FMPI2C_ISR_STOPF)) ? 1UL : 0UL);
1581  }
1582  
1583  /**
1584    * @brief  Indicate the status of Transfer complete flag (master mode).
1585    * @note   RESET: Clear default value.
1586    *         SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
1587    * @rmtoll ISR          TC            LL_FMPI2C_IsActiveFlag_TC
1588    * @param  FMPI2Cx FMPI2C Instance.
1589    * @retval State of bit (1 or 0).
1590    */
LL_FMPI2C_IsActiveFlag_TC(FMPI2C_TypeDef * FMPI2Cx)1591  __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TC(FMPI2C_TypeDef *FMPI2Cx)
1592  {
1593    return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TC) == (FMPI2C_ISR_TC)) ? 1UL : 0UL);
1594  }
1595  
1596  /**
1597    * @brief  Indicate the status of Transfer complete flag (master mode).
1598    * @note   RESET: Clear default value.
1599    *         SET: When RELOAD=1 and NBYTES date have been transferred.
1600    * @rmtoll ISR          TCR           LL_FMPI2C_IsActiveFlag_TCR
1601    * @param  FMPI2Cx FMPI2C Instance.
1602    * @retval State of bit (1 or 0).
1603    */
LL_FMPI2C_IsActiveFlag_TCR(FMPI2C_TypeDef * FMPI2Cx)1604  __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TCR(FMPI2C_TypeDef *FMPI2Cx)
1605  {
1606    return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TCR) == (FMPI2C_ISR_TCR)) ? 1UL : 0UL);
1607  }
1608  
1609  /**
1610    * @brief  Indicate the status of Bus error flag.
1611    * @note   RESET: Clear default value.
1612    *         SET: When a misplaced Start or Stop condition is detected.
1613    * @rmtoll ISR          BERR          LL_FMPI2C_IsActiveFlag_BERR
1614    * @param  FMPI2Cx FMPI2C Instance.
1615    * @retval State of bit (1 or 0).
1616    */
LL_FMPI2C_IsActiveFlag_BERR(FMPI2C_TypeDef * FMPI2Cx)1617  __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_BERR(FMPI2C_TypeDef *FMPI2Cx)
1618  {
1619    return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_BERR) == (FMPI2C_ISR_BERR)) ? 1UL : 0UL);
1620  }
1621  
1622  /**
1623    * @brief  Indicate the status of Arbitration lost flag.
1624    * @note   RESET: Clear default value.
1625    *         SET: When arbitration lost.
1626    * @rmtoll ISR          ARLO          LL_FMPI2C_IsActiveFlag_ARLO
1627    * @param  FMPI2Cx FMPI2C Instance.
1628    * @retval State of bit (1 or 0).
1629    */
LL_FMPI2C_IsActiveFlag_ARLO(FMPI2C_TypeDef * FMPI2Cx)1630  __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ARLO(FMPI2C_TypeDef *FMPI2Cx)
1631  {
1632    return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ARLO) == (FMPI2C_ISR_ARLO)) ? 1UL : 0UL);
1633  }
1634  
1635  /**
1636    * @brief  Indicate the status of Overrun/Underrun flag (slave mode).
1637    * @note   RESET: Clear default value.
1638    *         SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
1639    * @rmtoll ISR          OVR           LL_FMPI2C_IsActiveFlag_OVR
1640    * @param  FMPI2Cx FMPI2C Instance.
1641    * @retval State of bit (1 or 0).
1642    */
LL_FMPI2C_IsActiveFlag_OVR(FMPI2C_TypeDef * FMPI2Cx)1643  __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_OVR(FMPI2C_TypeDef *FMPI2Cx)
1644  {
1645    return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_OVR) == (FMPI2C_ISR_OVR)) ? 1UL : 0UL);
1646  }
1647  
1648  /**
1649    * @brief  Indicate the status of SMBus PEC error flag in reception.
1650    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1651    *         SMBus feature is supported by the FMPI2Cx Instance.
1652    * @note   RESET: Clear default value.
1653    *         SET: When the received PEC does not match with the PEC register content.
1654    * @rmtoll ISR          PECERR        LL_FMPI2C_IsActiveSMBusFlag_PECERR
1655    * @param  FMPI2Cx FMPI2C Instance.
1656    * @retval State of bit (1 or 0).
1657    */
LL_FMPI2C_IsActiveSMBusFlag_PECERR(FMPI2C_TypeDef * FMPI2Cx)1658  __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_PECERR(FMPI2C_TypeDef *FMPI2Cx)
1659  {
1660    return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_PECERR) == (FMPI2C_ISR_PECERR)) ? 1UL : 0UL);
1661  }
1662  
1663  /**
1664    * @brief  Indicate the status of SMBus Timeout detection flag.
1665    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1666    *         SMBus feature is supported by the FMPI2Cx Instance.
1667    * @note   RESET: Clear default value.
1668    *         SET: When a timeout or extended clock timeout occurs.
1669    * @rmtoll ISR          TIMEOUT       LL_FMPI2C_IsActiveSMBusFlag_TIMEOUT
1670    * @param  FMPI2Cx FMPI2C Instance.
1671    * @retval State of bit (1 or 0).
1672    */
LL_FMPI2C_IsActiveSMBusFlag_TIMEOUT(FMPI2C_TypeDef * FMPI2Cx)1673  __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_TIMEOUT(FMPI2C_TypeDef *FMPI2Cx)
1674  {
1675    return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TIMEOUT) == (FMPI2C_ISR_TIMEOUT)) ? 1UL : 0UL);
1676  }
1677  
1678  /**
1679    * @brief  Indicate the status of SMBus alert flag.
1680    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1681    *         SMBus feature is supported by the FMPI2Cx Instance.
1682    * @note   RESET: Clear default value.
1683    *         SET: When SMBus host configuration, SMBus alert enabled and
1684    *              a falling edge event occurs on SMBA pin.
1685    * @rmtoll ISR          ALERT         LL_FMPI2C_IsActiveSMBusFlag_ALERT
1686    * @param  FMPI2Cx FMPI2C Instance.
1687    * @retval State of bit (1 or 0).
1688    */
LL_FMPI2C_IsActiveSMBusFlag_ALERT(FMPI2C_TypeDef * FMPI2Cx)1689  __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_ALERT(FMPI2C_TypeDef *FMPI2Cx)
1690  {
1691    return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ALERT) == (FMPI2C_ISR_ALERT)) ? 1UL : 0UL);
1692  }
1693  
1694  /**
1695    * @brief  Indicate the status of Bus Busy flag.
1696    * @note   RESET: Clear default value.
1697    *         SET: When a Start condition is detected.
1698    * @rmtoll ISR          BUSY          LL_FMPI2C_IsActiveFlag_BUSY
1699    * @param  FMPI2Cx FMPI2C Instance.
1700    * @retval State of bit (1 or 0).
1701    */
LL_FMPI2C_IsActiveFlag_BUSY(FMPI2C_TypeDef * FMPI2Cx)1702  __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_BUSY(FMPI2C_TypeDef *FMPI2Cx)
1703  {
1704    return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_BUSY) == (FMPI2C_ISR_BUSY)) ? 1UL : 0UL);
1705  }
1706  
1707  /**
1708    * @brief  Clear Address Matched flag.
1709    * @rmtoll ICR          ADDRCF        LL_FMPI2C_ClearFlag_ADDR
1710    * @param  FMPI2Cx FMPI2C Instance.
1711    * @retval None
1712    */
LL_FMPI2C_ClearFlag_ADDR(FMPI2C_TypeDef * FMPI2Cx)1713  __STATIC_INLINE void LL_FMPI2C_ClearFlag_ADDR(FMPI2C_TypeDef *FMPI2Cx)
1714  {
1715    SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_ADDRCF);
1716  }
1717  
1718  /**
1719    * @brief  Clear Not Acknowledge flag.
1720    * @rmtoll ICR          NACKCF        LL_FMPI2C_ClearFlag_NACK
1721    * @param  FMPI2Cx FMPI2C Instance.
1722    * @retval None
1723    */
LL_FMPI2C_ClearFlag_NACK(FMPI2C_TypeDef * FMPI2Cx)1724  __STATIC_INLINE void LL_FMPI2C_ClearFlag_NACK(FMPI2C_TypeDef *FMPI2Cx)
1725  {
1726    SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_NACKCF);
1727  }
1728  
1729  /**
1730    * @brief  Clear Stop detection flag.
1731    * @rmtoll ICR          STOPCF        LL_FMPI2C_ClearFlag_STOP
1732    * @param  FMPI2Cx FMPI2C Instance.
1733    * @retval None
1734    */
LL_FMPI2C_ClearFlag_STOP(FMPI2C_TypeDef * FMPI2Cx)1735  __STATIC_INLINE void LL_FMPI2C_ClearFlag_STOP(FMPI2C_TypeDef *FMPI2Cx)
1736  {
1737    SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_STOPCF);
1738  }
1739  
1740  /**
1741    * @brief  Clear Transmit data register empty flag (TXE).
1742    * @note   This bit can be clear by software in order to flush the transmit data register (TXDR).
1743    * @rmtoll ISR          TXE           LL_FMPI2C_ClearFlag_TXE
1744    * @param  FMPI2Cx FMPI2C Instance.
1745    * @retval None
1746    */
LL_FMPI2C_ClearFlag_TXE(FMPI2C_TypeDef * FMPI2Cx)1747  __STATIC_INLINE void LL_FMPI2C_ClearFlag_TXE(FMPI2C_TypeDef *FMPI2Cx)
1748  {
1749    WRITE_REG(FMPI2Cx->ISR, FMPI2C_ISR_TXE);
1750  }
1751  
1752  /**
1753    * @brief  Clear Bus error flag.
1754    * @rmtoll ICR          BERRCF        LL_FMPI2C_ClearFlag_BERR
1755    * @param  FMPI2Cx FMPI2C Instance.
1756    * @retval None
1757    */
LL_FMPI2C_ClearFlag_BERR(FMPI2C_TypeDef * FMPI2Cx)1758  __STATIC_INLINE void LL_FMPI2C_ClearFlag_BERR(FMPI2C_TypeDef *FMPI2Cx)
1759  {
1760    SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_BERRCF);
1761  }
1762  
1763  /**
1764    * @brief  Clear Arbitration lost flag.
1765    * @rmtoll ICR          ARLOCF        LL_FMPI2C_ClearFlag_ARLO
1766    * @param  FMPI2Cx FMPI2C Instance.
1767    * @retval None
1768    */
LL_FMPI2C_ClearFlag_ARLO(FMPI2C_TypeDef * FMPI2Cx)1769  __STATIC_INLINE void LL_FMPI2C_ClearFlag_ARLO(FMPI2C_TypeDef *FMPI2Cx)
1770  {
1771    SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_ARLOCF);
1772  }
1773  
1774  /**
1775    * @brief  Clear Overrun/Underrun flag.
1776    * @rmtoll ICR          OVRCF         LL_FMPI2C_ClearFlag_OVR
1777    * @param  FMPI2Cx FMPI2C Instance.
1778    * @retval None
1779    */
LL_FMPI2C_ClearFlag_OVR(FMPI2C_TypeDef * FMPI2Cx)1780  __STATIC_INLINE void LL_FMPI2C_ClearFlag_OVR(FMPI2C_TypeDef *FMPI2Cx)
1781  {
1782    SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_OVRCF);
1783  }
1784  
1785  /**
1786    * @brief  Clear SMBus PEC error flag.
1787    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1788    *         SMBus feature is supported by the FMPI2Cx Instance.
1789    * @rmtoll ICR          PECCF         LL_FMPI2C_ClearSMBusFlag_PECERR
1790    * @param  FMPI2Cx FMPI2C Instance.
1791    * @retval None
1792    */
LL_FMPI2C_ClearSMBusFlag_PECERR(FMPI2C_TypeDef * FMPI2Cx)1793  __STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_PECERR(FMPI2C_TypeDef *FMPI2Cx)
1794  {
1795    SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_PECCF);
1796  }
1797  
1798  /**
1799    * @brief  Clear SMBus Timeout detection flag.
1800    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1801    *         SMBus feature is supported by the FMPI2Cx Instance.
1802    * @rmtoll ICR          TIMOUTCF      LL_FMPI2C_ClearSMBusFlag_TIMEOUT
1803    * @param  FMPI2Cx FMPI2C Instance.
1804    * @retval None
1805    */
LL_FMPI2C_ClearSMBusFlag_TIMEOUT(FMPI2C_TypeDef * FMPI2Cx)1806  __STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_TIMEOUT(FMPI2C_TypeDef *FMPI2Cx)
1807  {
1808    SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_TIMOUTCF);
1809  }
1810  
1811  /**
1812    * @brief  Clear SMBus Alert flag.
1813    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
1814    *         SMBus feature is supported by the FMPI2Cx Instance.
1815    * @rmtoll ICR          ALERTCF       LL_FMPI2C_ClearSMBusFlag_ALERT
1816    * @param  FMPI2Cx FMPI2C Instance.
1817    * @retval None
1818    */
LL_FMPI2C_ClearSMBusFlag_ALERT(FMPI2C_TypeDef * FMPI2Cx)1819  __STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_ALERT(FMPI2C_TypeDef *FMPI2Cx)
1820  {
1821    SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_ALERTCF);
1822  }
1823  
1824  /**
1825    * @}
1826    */
1827  
1828  /** @defgroup FMPI2C_LL_EF_Data_Management Data_Management
1829    * @{
1830    */
1831  
1832  /**
1833    * @brief  Enable automatic STOP condition generation (master mode).
1834    * @note   Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
1835    *         This bit has no effect in slave mode or when RELOAD bit is set.
1836    * @rmtoll CR2          AUTOEND       LL_FMPI2C_EnableAutoEndMode
1837    * @param  FMPI2Cx FMPI2C Instance.
1838    * @retval None
1839    */
LL_FMPI2C_EnableAutoEndMode(FMPI2C_TypeDef * FMPI2Cx)1840  __STATIC_INLINE void LL_FMPI2C_EnableAutoEndMode(FMPI2C_TypeDef *FMPI2Cx)
1841  {
1842    SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_AUTOEND);
1843  }
1844  
1845  /**
1846    * @brief  Disable automatic STOP condition generation (master mode).
1847    * @note   Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
1848    * @rmtoll CR2          AUTOEND       LL_FMPI2C_DisableAutoEndMode
1849    * @param  FMPI2Cx FMPI2C Instance.
1850    * @retval None
1851    */
LL_FMPI2C_DisableAutoEndMode(FMPI2C_TypeDef * FMPI2Cx)1852  __STATIC_INLINE void LL_FMPI2C_DisableAutoEndMode(FMPI2C_TypeDef *FMPI2Cx)
1853  {
1854    CLEAR_BIT(FMPI2Cx->CR2, FMPI2C_CR2_AUTOEND);
1855  }
1856  
1857  /**
1858    * @brief  Check if automatic STOP condition is enabled or disabled.
1859    * @rmtoll CR2          AUTOEND       LL_FMPI2C_IsEnabledAutoEndMode
1860    * @param  FMPI2Cx FMPI2C Instance.
1861    * @retval State of bit (1 or 0).
1862    */
LL_FMPI2C_IsEnabledAutoEndMode(FMPI2C_TypeDef * FMPI2Cx)1863  __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAutoEndMode(FMPI2C_TypeDef *FMPI2Cx)
1864  {
1865    return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_AUTOEND) == (FMPI2C_CR2_AUTOEND)) ? 1UL : 0UL);
1866  }
1867  
1868  /**
1869    * @brief  Enable reload mode (master mode).
1870    * @note   The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
1871    * @rmtoll CR2          RELOAD       LL_FMPI2C_EnableReloadMode
1872    * @param  FMPI2Cx FMPI2C Instance.
1873    * @retval None
1874    */
LL_FMPI2C_EnableReloadMode(FMPI2C_TypeDef * FMPI2Cx)1875  __STATIC_INLINE void LL_FMPI2C_EnableReloadMode(FMPI2C_TypeDef *FMPI2Cx)
1876  {
1877    SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RELOAD);
1878  }
1879  
1880  /**
1881    * @brief  Disable reload mode (master mode).
1882    * @note   The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
1883    * @rmtoll CR2          RELOAD       LL_FMPI2C_DisableReloadMode
1884    * @param  FMPI2Cx FMPI2C Instance.
1885    * @retval None
1886    */
LL_FMPI2C_DisableReloadMode(FMPI2C_TypeDef * FMPI2Cx)1887  __STATIC_INLINE void LL_FMPI2C_DisableReloadMode(FMPI2C_TypeDef *FMPI2Cx)
1888  {
1889    CLEAR_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RELOAD);
1890  }
1891  
1892  /**
1893    * @brief  Check if reload mode is enabled or disabled.
1894    * @rmtoll CR2          RELOAD       LL_FMPI2C_IsEnabledReloadMode
1895    * @param  FMPI2Cx FMPI2C Instance.
1896    * @retval State of bit (1 or 0).
1897    */
LL_FMPI2C_IsEnabledReloadMode(FMPI2C_TypeDef * FMPI2Cx)1898  __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledReloadMode(FMPI2C_TypeDef *FMPI2Cx)
1899  {
1900    return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RELOAD) == (FMPI2C_CR2_RELOAD)) ? 1UL : 0UL);
1901  }
1902  
1903  /**
1904    * @brief  Configure the number of bytes for transfer.
1905    * @note   Changing these bits when START bit is set is not allowed.
1906    * @rmtoll CR2          NBYTES           LL_FMPI2C_SetTransferSize
1907    * @param  FMPI2Cx FMPI2C Instance.
1908    * @param  TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
1909    * @retval None
1910    */
LL_FMPI2C_SetTransferSize(FMPI2C_TypeDef * FMPI2Cx,uint32_t TransferSize)1911  __STATIC_INLINE void LL_FMPI2C_SetTransferSize(FMPI2C_TypeDef *FMPI2Cx, uint32_t TransferSize)
1912  {
1913    MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_NBYTES, TransferSize << FMPI2C_CR2_NBYTES_Pos);
1914  }
1915  
1916  /**
1917    * @brief  Get the number of bytes configured for transfer.
1918    * @rmtoll CR2          NBYTES           LL_FMPI2C_GetTransferSize
1919    * @param  FMPI2Cx FMPI2C Instance.
1920    * @retval Value between Min_Data=0x0 and Max_Data=0xFF
1921    */
LL_FMPI2C_GetTransferSize(FMPI2C_TypeDef * FMPI2Cx)1922  __STATIC_INLINE uint32_t LL_FMPI2C_GetTransferSize(FMPI2C_TypeDef *FMPI2Cx)
1923  {
1924    return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_NBYTES) >> FMPI2C_CR2_NBYTES_Pos);
1925  }
1926  
1927  /**
1928    * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
1929              or next received byte.
1930    * @note   Usage in Slave mode only.
1931    * @rmtoll CR2          NACK          LL_FMPI2C_AcknowledgeNextData
1932    * @param  FMPI2Cx FMPI2C Instance.
1933    * @param  TypeAcknowledge This parameter can be one of the following values:
1934    *         @arg @ref LL_FMPI2C_ACK
1935    *         @arg @ref LL_FMPI2C_NACK
1936    * @retval None
1937    */
LL_FMPI2C_AcknowledgeNextData(FMPI2C_TypeDef * FMPI2Cx,uint32_t TypeAcknowledge)1938  __STATIC_INLINE void LL_FMPI2C_AcknowledgeNextData(FMPI2C_TypeDef *FMPI2Cx, uint32_t TypeAcknowledge)
1939  {
1940    MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_NACK, TypeAcknowledge);
1941  }
1942  
1943  /**
1944    * @brief  Generate a START or RESTART condition
1945    * @note   The START bit can be set even if bus is BUSY or FMPI2C is in slave mode.
1946    *         This action has no effect when RELOAD is set.
1947    * @rmtoll CR2          START           LL_FMPI2C_GenerateStartCondition
1948    * @param  FMPI2Cx FMPI2C Instance.
1949    * @retval None
1950    */
LL_FMPI2C_GenerateStartCondition(FMPI2C_TypeDef * FMPI2Cx)1951  __STATIC_INLINE void LL_FMPI2C_GenerateStartCondition(FMPI2C_TypeDef *FMPI2Cx)
1952  {
1953    SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_START);
1954  }
1955  
1956  /**
1957    * @brief  Generate a STOP condition after the current byte transfer (master mode).
1958    * @rmtoll CR2          STOP          LL_FMPI2C_GenerateStopCondition
1959    * @param  FMPI2Cx FMPI2C Instance.
1960    * @retval None
1961    */
LL_FMPI2C_GenerateStopCondition(FMPI2C_TypeDef * FMPI2Cx)1962  __STATIC_INLINE void LL_FMPI2C_GenerateStopCondition(FMPI2C_TypeDef *FMPI2Cx)
1963  {
1964    SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_STOP);
1965  }
1966  
1967  /**
1968    * @brief  Enable automatic RESTART Read request condition for 10bit address header (master mode).
1969    * @note   The master sends the complete 10bit slave address read sequence :
1970    *         Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
1971              in Read direction.
1972    * @rmtoll CR2          HEAD10R       LL_FMPI2C_EnableAuto10BitRead
1973    * @param  FMPI2Cx FMPI2C Instance.
1974    * @retval None
1975    */
LL_FMPI2C_EnableAuto10BitRead(FMPI2C_TypeDef * FMPI2Cx)1976  __STATIC_INLINE void LL_FMPI2C_EnableAuto10BitRead(FMPI2C_TypeDef *FMPI2Cx)
1977  {
1978    CLEAR_BIT(FMPI2Cx->CR2, FMPI2C_CR2_HEAD10R);
1979  }
1980  
1981  /**
1982    * @brief  Disable automatic RESTART Read request condition for 10bit address header (master mode).
1983    * @note   The master only sends the first 7 bits of 10bit address in Read direction.
1984    * @rmtoll CR2          HEAD10R       LL_FMPI2C_DisableAuto10BitRead
1985    * @param  FMPI2Cx FMPI2C Instance.
1986    * @retval None
1987    */
LL_FMPI2C_DisableAuto10BitRead(FMPI2C_TypeDef * FMPI2Cx)1988  __STATIC_INLINE void LL_FMPI2C_DisableAuto10BitRead(FMPI2C_TypeDef *FMPI2Cx)
1989  {
1990    SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_HEAD10R);
1991  }
1992  
1993  /**
1994    * @brief  Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
1995    * @rmtoll CR2          HEAD10R       LL_FMPI2C_IsEnabledAuto10BitRead
1996    * @param  FMPI2Cx FMPI2C Instance.
1997    * @retval State of bit (1 or 0).
1998    */
LL_FMPI2C_IsEnabledAuto10BitRead(FMPI2C_TypeDef * FMPI2Cx)1999  __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAuto10BitRead(FMPI2C_TypeDef *FMPI2Cx)
2000  {
2001    return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_HEAD10R) != (FMPI2C_CR2_HEAD10R)) ? 1UL : 0UL);
2002  }
2003  
2004  /**
2005    * @brief  Configure the transfer direction (master mode).
2006    * @note   Changing these bits when START bit is set is not allowed.
2007    * @rmtoll CR2          RD_WRN           LL_FMPI2C_SetTransferRequest
2008    * @param  FMPI2Cx FMPI2C Instance.
2009    * @param  TransferRequest This parameter can be one of the following values:
2010    *         @arg @ref LL_FMPI2C_REQUEST_WRITE
2011    *         @arg @ref LL_FMPI2C_REQUEST_READ
2012    * @retval None
2013    */
LL_FMPI2C_SetTransferRequest(FMPI2C_TypeDef * FMPI2Cx,uint32_t TransferRequest)2014  __STATIC_INLINE void LL_FMPI2C_SetTransferRequest(FMPI2C_TypeDef *FMPI2Cx, uint32_t TransferRequest)
2015  {
2016    MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_RD_WRN, TransferRequest);
2017  }
2018  
2019  /**
2020    * @brief  Get the transfer direction requested (master mode).
2021    * @rmtoll CR2          RD_WRN           LL_FMPI2C_GetTransferRequest
2022    * @param  FMPI2Cx FMPI2C Instance.
2023    * @retval Returned value can be one of the following values:
2024    *         @arg @ref LL_FMPI2C_REQUEST_WRITE
2025    *         @arg @ref LL_FMPI2C_REQUEST_READ
2026    */
LL_FMPI2C_GetTransferRequest(FMPI2C_TypeDef * FMPI2Cx)2027  __STATIC_INLINE uint32_t LL_FMPI2C_GetTransferRequest(FMPI2C_TypeDef *FMPI2Cx)
2028  {
2029    return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RD_WRN));
2030  }
2031  
2032  /**
2033    * @brief  Configure the slave address for transfer (master mode).
2034    * @note   Changing these bits when START bit is set is not allowed.
2035    * @rmtoll CR2          SADD           LL_FMPI2C_SetSlaveAddr
2036    * @param  FMPI2Cx FMPI2C Instance.
2037    * @param  SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
2038    * @retval None
2039    */
LL_FMPI2C_SetSlaveAddr(FMPI2C_TypeDef * FMPI2Cx,uint32_t SlaveAddr)2040  __STATIC_INLINE void LL_FMPI2C_SetSlaveAddr(FMPI2C_TypeDef *FMPI2Cx, uint32_t SlaveAddr)
2041  {
2042    MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_SADD, SlaveAddr);
2043  }
2044  
2045  /**
2046    * @brief  Get the slave address programmed for transfer.
2047    * @rmtoll CR2          SADD           LL_FMPI2C_GetSlaveAddr
2048    * @param  FMPI2Cx FMPI2C Instance.
2049    * @retval Value between Min_Data=0x0 and Max_Data=0x3F
2050    */
LL_FMPI2C_GetSlaveAddr(FMPI2C_TypeDef * FMPI2Cx)2051  __STATIC_INLINE uint32_t LL_FMPI2C_GetSlaveAddr(FMPI2C_TypeDef *FMPI2Cx)
2052  {
2053    return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_SADD));
2054  }
2055  
2056  /**
2057    * @brief  Handles FMPI2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
2058    * @rmtoll CR2          SADD          LL_FMPI2C_HandleTransfer\n
2059    *         CR2          ADD10         LL_FMPI2C_HandleTransfer\n
2060    *         CR2          RD_WRN        LL_FMPI2C_HandleTransfer\n
2061    *         CR2          START         LL_FMPI2C_HandleTransfer\n
2062    *         CR2          STOP          LL_FMPI2C_HandleTransfer\n
2063    *         CR2          RELOAD        LL_FMPI2C_HandleTransfer\n
2064    *         CR2          NBYTES        LL_FMPI2C_HandleTransfer\n
2065    *         CR2          AUTOEND       LL_FMPI2C_HandleTransfer\n
2066    *         CR2          HEAD10R       LL_FMPI2C_HandleTransfer
2067    * @param  FMPI2Cx FMPI2C Instance.
2068    * @param  SlaveAddr Specifies the slave address to be programmed.
2069    * @param  SlaveAddrSize This parameter can be one of the following values:
2070    *         @arg @ref LL_FMPI2C_ADDRSLAVE_7BIT
2071    *         @arg @ref LL_FMPI2C_ADDRSLAVE_10BIT
2072    * @param  TransferSize Specifies the number of bytes to be programmed.
2073    *                       This parameter must be a value between Min_Data=0 and Max_Data=255.
2074    * @param  EndMode This parameter can be one of the following values:
2075    *         @arg @ref LL_FMPI2C_MODE_RELOAD
2076    *         @arg @ref LL_FMPI2C_MODE_AUTOEND
2077    *         @arg @ref LL_FMPI2C_MODE_SOFTEND
2078    *         @arg @ref LL_FMPI2C_MODE_SMBUS_RELOAD
2079    *         @arg @ref LL_FMPI2C_MODE_SMBUS_AUTOEND_NO_PEC
2080    *         @arg @ref LL_FMPI2C_MODE_SMBUS_SOFTEND_NO_PEC
2081    *         @arg @ref LL_FMPI2C_MODE_SMBUS_AUTOEND_WITH_PEC
2082    *         @arg @ref LL_FMPI2C_MODE_SMBUS_SOFTEND_WITH_PEC
2083    * @param  Request This parameter can be one of the following values:
2084    *         @arg @ref LL_FMPI2C_GENERATE_NOSTARTSTOP
2085    *         @arg @ref LL_FMPI2C_GENERATE_STOP
2086    *         @arg @ref LL_FMPI2C_GENERATE_START_READ
2087    *         @arg @ref LL_FMPI2C_GENERATE_START_WRITE
2088    *         @arg @ref LL_FMPI2C_GENERATE_RESTART_7BIT_READ
2089    *         @arg @ref LL_FMPI2C_GENERATE_RESTART_7BIT_WRITE
2090    *         @arg @ref LL_FMPI2C_GENERATE_RESTART_10BIT_READ
2091    *         @arg @ref LL_FMPI2C_GENERATE_RESTART_10BIT_WRITE
2092    * @retval None
2093    */
LL_FMPI2C_HandleTransfer(FMPI2C_TypeDef * FMPI2Cx,uint32_t SlaveAddr,uint32_t SlaveAddrSize,uint32_t TransferSize,uint32_t EndMode,uint32_t Request)2094  __STATIC_INLINE void LL_FMPI2C_HandleTransfer(FMPI2C_TypeDef *FMPI2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
2095                                             uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
2096  {
2097    MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_SADD | FMPI2C_CR2_ADD10 |
2098               (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - FMPI2C_CR2_RD_WRN_Pos))) |
2099               FMPI2C_CR2_START | FMPI2C_CR2_STOP | FMPI2C_CR2_RELOAD |
2100               FMPI2C_CR2_NBYTES | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_HEAD10R,
2101               SlaveAddr | SlaveAddrSize | (TransferSize << FMPI2C_CR2_NBYTES_Pos) | EndMode | Request);
2102  }
2103  
2104  /**
2105    * @brief  Indicate the value of transfer direction (slave mode).
2106    * @note   RESET: Write transfer, Slave enters in receiver mode.
2107    *         SET: Read transfer, Slave enters in transmitter mode.
2108    * @rmtoll ISR          DIR           LL_FMPI2C_GetTransferDirection
2109    * @param  FMPI2Cx FMPI2C Instance.
2110    * @retval Returned value can be one of the following values:
2111    *         @arg @ref LL_FMPI2C_DIRECTION_WRITE
2112    *         @arg @ref LL_FMPI2C_DIRECTION_READ
2113    */
LL_FMPI2C_GetTransferDirection(FMPI2C_TypeDef * FMPI2Cx)2114  __STATIC_INLINE uint32_t LL_FMPI2C_GetTransferDirection(FMPI2C_TypeDef *FMPI2Cx)
2115  {
2116    return (uint32_t)(READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_DIR));
2117  }
2118  
2119  /**
2120    * @brief  Return the slave matched address.
2121    * @rmtoll ISR          ADDCODE       LL_FMPI2C_GetAddressMatchCode
2122    * @param  FMPI2Cx FMPI2C Instance.
2123    * @retval Value between Min_Data=0x00 and Max_Data=0x3F
2124    */
LL_FMPI2C_GetAddressMatchCode(FMPI2C_TypeDef * FMPI2Cx)2125  __STATIC_INLINE uint32_t LL_FMPI2C_GetAddressMatchCode(FMPI2C_TypeDef *FMPI2Cx)
2126  {
2127    return (uint32_t)(READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ADDCODE) >> FMPI2C_ISR_ADDCODE_Pos << 1);
2128  }
2129  
2130  /**
2131    * @brief  Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
2132    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
2133    *         SMBus feature is supported by the FMPI2Cx Instance.
2134    * @note   This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
2135              or an Address Matched is received.
2136    *         This bit has no effect when RELOAD bit is set.
2137    *         This bit has no effect in device mode when SBC bit is not set.
2138    * @rmtoll CR2          PECBYTE       LL_FMPI2C_EnableSMBusPECCompare
2139    * @param  FMPI2Cx FMPI2C Instance.
2140    * @retval None
2141    */
LL_FMPI2C_EnableSMBusPECCompare(FMPI2C_TypeDef * FMPI2Cx)2142  __STATIC_INLINE void LL_FMPI2C_EnableSMBusPECCompare(FMPI2C_TypeDef *FMPI2Cx)
2143  {
2144    SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_PECBYTE);
2145  }
2146  
2147  /**
2148    * @brief  Check if the SMBus Packet Error byte internal comparison is requested or not.
2149    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
2150    *         SMBus feature is supported by the FMPI2Cx Instance.
2151    * @rmtoll CR2          PECBYTE       LL_FMPI2C_IsEnabledSMBusPECCompare
2152    * @param  FMPI2Cx FMPI2C Instance.
2153    * @retval State of bit (1 or 0).
2154    */
LL_FMPI2C_IsEnabledSMBusPECCompare(FMPI2C_TypeDef * FMPI2Cx)2155  __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPECCompare(FMPI2C_TypeDef *FMPI2Cx)
2156  {
2157    return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_PECBYTE) == (FMPI2C_CR2_PECBYTE)) ? 1UL : 0UL);
2158  }
2159  
2160  /**
2161    * @brief  Get the SMBus Packet Error byte calculated.
2162    * @note   The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not
2163    *         SMBus feature is supported by the FMPI2Cx Instance.
2164    * @rmtoll PECR         PEC           LL_FMPI2C_GetSMBusPEC
2165    * @param  FMPI2Cx FMPI2C Instance.
2166    * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2167    */
LL_FMPI2C_GetSMBusPEC(FMPI2C_TypeDef * FMPI2Cx)2168  __STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusPEC(FMPI2C_TypeDef *FMPI2Cx)
2169  {
2170    return (uint32_t)(READ_BIT(FMPI2Cx->PECR, FMPI2C_PECR_PEC));
2171  }
2172  
2173  /**
2174    * @brief  Read Receive Data register.
2175    * @rmtoll RXDR         RXDATA        LL_FMPI2C_ReceiveData8
2176    * @param  FMPI2Cx FMPI2C Instance.
2177    * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2178    */
LL_FMPI2C_ReceiveData8(FMPI2C_TypeDef * FMPI2Cx)2179  __STATIC_INLINE uint8_t LL_FMPI2C_ReceiveData8(FMPI2C_TypeDef *FMPI2Cx)
2180  {
2181    return (uint8_t)(READ_BIT(FMPI2Cx->RXDR, FMPI2C_RXDR_RXDATA));
2182  }
2183  
2184  /**
2185    * @brief  Write in Transmit Data Register .
2186    * @rmtoll TXDR         TXDATA        LL_FMPI2C_TransmitData8
2187    * @param  FMPI2Cx FMPI2C Instance.
2188    * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
2189    * @retval None
2190    */
LL_FMPI2C_TransmitData8(FMPI2C_TypeDef * FMPI2Cx,uint8_t Data)2191  __STATIC_INLINE void LL_FMPI2C_TransmitData8(FMPI2C_TypeDef *FMPI2Cx, uint8_t Data)
2192  {
2193    WRITE_REG(FMPI2Cx->TXDR, Data);
2194  }
2195  
2196  /**
2197    * @}
2198    */
2199  
2200  #if defined(USE_FULL_LL_DRIVER)
2201  /** @defgroup FMPI2C_LL_EF_Init Initialization and de-initialization functions
2202    * @{
2203    */
2204  
2205  ErrorStatus LL_FMPI2C_Init(FMPI2C_TypeDef *FMPI2Cx, LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct);
2206  ErrorStatus LL_FMPI2C_DeInit(FMPI2C_TypeDef *FMPI2Cx);
2207  void LL_FMPI2C_StructInit(LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct);
2208  
2209  
2210  /**
2211    * @}
2212    */
2213  #endif /* USE_FULL_LL_DRIVER */
2214  
2215  /**
2216    * @}
2217    */
2218  
2219  /**
2220    * @}
2221    */
2222  
2223  #endif /* FMPI2C1 */
2224  
2225  /**
2226    * @}
2227    */
2228  
2229  #endif /* FMPI2C_CR1_PE */
2230  #ifdef __cplusplus
2231  }
2232  #endif
2233  
2234  #endif /* STM32F4xx_LL_FMPI2C_H */
2235