1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F3xx_LL_DAC_H
21 #define __STM32F3xx_LL_DAC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f3xx.h"
29
30 /** @addtogroup STM32F3xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DAC1) || defined (DAC2)
35
36 /** @defgroup DAC_LL DAC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
45 * @{
46 */
47
48 /* Internal masks for DAC channels definition */
49 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
50 /* - channel bits position into register CR */
51 /* - channel bits position into register SWTRIG */
52 /* - channel register offset of data holding register DHRx */
53 /* - channel register offset of data output register DORx */
54 #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
55 #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
56 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
57
58 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
59 #if defined(DAC_CHANNEL2_SUPPORT)
60 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
61 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
62 #else
63 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
64 #endif /* DAC_CHANNEL2_SUPPORT */
65
66 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
67 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
68 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
69 #if defined(DAC_CHANNEL2_SUPPORT)
70 #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
71 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
72 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
73 #endif /* DAC_CHANNEL2_SUPPORT */
74 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
75 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
76 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
77 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
78
79 #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
80 #if defined(DAC_CHANNEL2_SUPPORT)
81 #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
82 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
83 #else
84 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
85 #endif /* DAC_CHANNEL2_SUPPORT */
86
87 /* DAC registers bits positions */
88 #if defined(DAC_CHANNEL2_SUPPORT)
89 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
90 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
91 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
92 #endif /* DAC_CHANNEL2_SUPPORT */
93
94 /* Miscellaneous data */
95 #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
96
97 /**
98 * @}
99 */
100
101
102 /* Private macros ------------------------------------------------------------*/
103 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
104 * @{
105 */
106
107 /**
108 * @brief Driver macro reserved for internal use: isolate bits with the
109 * selected mask and shift them to the register LSB
110 * (shift mask on register position bit 0).
111 * @param __BITS__ Bits in register 32 bits
112 * @param __MASK__ Mask in register 32 bits
113 * @retval Bits in register 32 bits
114 */
115 #define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
116 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
117
118 /**
119 * @brief Driver macro reserved for internal use: set a pointer to
120 * a register from a register basis from which an offset
121 * is applied.
122 * @param __REG__ Register basis from which the offset is applied.
123 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
124 * @retval Pointer to register address
125 */
126 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
127 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
128
129 /**
130 * @}
131 */
132
133
134 /* Exported types ------------------------------------------------------------*/
135 #if defined(USE_FULL_LL_DRIVER)
136 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
137 * @{
138 */
139
140 /**
141 * @brief Structure definition of some features of DAC instance.
142 */
143 typedef struct
144 {
145 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
146 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
147
148 This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
149
150 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
151 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
152
153 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
154
155 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
156 If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
157 If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
158 @note If waveform automatic generation mode is disabled, this parameter is discarded.
159
160 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
161
162 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
163 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
164
165 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
166
167 } LL_DAC_InitTypeDef;
168
169 /**
170 * @}
171 */
172 #endif /* USE_FULL_LL_DRIVER */
173
174 /* Exported constants --------------------------------------------------------*/
175 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
176 * @{
177 */
178
179 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
180 * @brief Flags defines which can be used with LL_DAC_ReadReg function
181 * @{
182 */
183 /* DAC channel 1 flags */
184 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
185
186 #if defined(DAC_CHANNEL2_SUPPORT)
187 /* DAC channel 2 flags */
188 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
189 #endif /* DAC_CHANNEL2_SUPPORT */
190 /**
191 * @}
192 */
193
194 /** @defgroup DAC_LL_EC_IT DAC interruptions
195 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
196 * @{
197 */
198 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
199 #if defined(DAC_CHANNEL2_SUPPORT)
200 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
201 #endif /* DAC_CHANNEL2_SUPPORT */
202 /**
203 * @}
204 */
205
206 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
207 * @{
208 */
209 #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
210 #if defined(DAC_CHANNEL2_SUPPORT)
211 #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
212 #endif /* DAC_CHANNEL2_SUPPORT */
213 /**
214 * @}
215 */
216
217 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
218 * @{
219 */
220 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
221 #if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
222 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
223 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM3_TRGO for TIM3 selection. */
224 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
225 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
226 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
227 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
228 #define LL_DAC_TRIG_EXT_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM3_TRGO) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM8_TRGO for TIM8 selection. */
229 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
230
231 #elif defined(STM32F303x8) || defined(STM32F328xx)
232 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
233 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
234 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
235 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
236 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
237 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
238
239 #elif defined(STM32F302xE) || defined(STM32F302xC) || defined(STM32F302x8)
240 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
241 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
242 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
243 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
244 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 ) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
245 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
246
247 #elif defined(STM32F301x8) || defined(STM32F318xx)
248 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
249 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
250 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
251 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
252
253 #elif defined(STM32F373xC) || defined(STM32F378xx)
254 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
255 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
256 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
257 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
258 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
259 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
260 #define LL_DAC_TRIG_EXT_TIM18_TRGO (LL_DAC_TRIG_EXT_TIM5_TRGO) /*!< DAC channel conversion trigger from external IP: TIM18 TRGO. */
261 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
262
263 #elif defined(STM32F334x8)
264 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
265 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM3_TRGO for TIM3 selection. */
266 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
267 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
268 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG3_REMAP_TIM15_TRGO for TIM15 selection. */
269 #define LL_DAC_TRIGGER_HRTIM1_DACTRG1 (LL_DAC_TRIG_EXT_TIM15_TRGO) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG1. Available only on DAC instance: DAC1. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG3_REMAP_HRTIM1_DAC1_TRIG1 for HRTIM1 TRIG1 selection. */
270 #define LL_DAC_TRIGGER_HRTIM1_DACTRG2 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG2. Available only on DAC instance: DAC2. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG5_REMAP_HRTIM1_DAC1_TRIG2 for HRTIM1 TRIG2 selection. */
271 #define LL_DAC_TRIGGER_HRTIM1_DACTRG3 (LL_DAC_TRIGGER_HRTIM1_DACTRG2) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG3. */
272 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
273
274 #endif
275 /**
276 * @}
277 */
278
279 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
280 * @{
281 */
282 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
283 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
284 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
285 /**
286 * @}
287 */
288
289 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
290 * @{
291 */
292 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
293 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
294 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
295 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
296 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
297 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
298 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
299 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
300 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
301 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
302 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
303 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
304 /**
305 * @}
306 */
307
308 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
309 * @{
310 */
311 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
312 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
313 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
314 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
315 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
316 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
317 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
318 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
319 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
320 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
321 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
322 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
323 /**
324 * @}
325 */
326
327 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
328 * @{
329 */
330 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
331 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
332
333 #if defined(DAC_CR_OUTEN1) || defined(DAC_CR_OUTEN2)
334 #define LL_DAC_OUTPUT_SWITCH_DISABLE (LL_DAC_OUTPUT_BUFFER_ENABLE) /*!< Feature specific to STM32F303x6/8 and STM32F328: On DAC1 channel 2, output buffer is replaced by a switch to connect DAC channel output to pin PA5. On DAC2 channel 1, output buffer is replaced by a switch to connect DAC channel output to pin PA6. Selection of switch disabled: DAC channel output not connected to GPIO. */
335 #define LL_DAC_OUTPUT_SWITCH_ENABLE (LL_DAC_OUTPUT_BUFFER_DISABLE) /*!< Feature specific to STM32F303x6/8 and STM32F328: On DAC1 channel 2, output buffer is replaced by a switch to connect DAC channel output to pin PA5. On DAC2 channel 1, output buffer is replaced by a switch to connect DAC channel output to pin PA6. */
336 #endif
337 /**
338 * @}
339 */
340
341
342 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
343 * @{
344 */
345 #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
346 #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
347 /**
348 * @}
349 */
350
351 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
352 * @{
353 */
354 /* List of DAC registers intended to be used (most commonly) with */
355 /* DMA transfer. */
356 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
357 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
358 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
359 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */
360 /**
361 * @}
362 */
363
364 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
365 * @note Only DAC IP HW delays are defined in DAC LL driver driver,
366 * not timeout values.
367 * For details on delays values, refer to descriptions in source code
368 * above each literal definition.
369 * @{
370 */
371
372 /* Delay for DAC channel voltage settling time from DAC channel startup */
373 /* (transition from disable to enable). */
374 /* Note: DAC channel startup time depends on board application environment: */
375 /* impedance connected to DAC channel output. */
376 /* The delay below is specified under conditions: */
377 /* - voltage maximum transition (lowest to highest value) */
378 /* - until voltage reaches final value +-1LSB */
379 /* - DAC channel output buffer enabled */
380 /* - load impedance of 5kOhm (min), 50pF (max) */
381 /* Literal set to maximum value (refer to device datasheet, */
382 /* parameter "tWAKEUP"). */
383 /* Unit: us */
384 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
385
386 /* Delay for DAC channel voltage settling time. */
387 /* Note: DAC channel startup time depends on board application environment: */
388 /* impedance connected to DAC channel output. */
389 /* The delay below is specified under conditions: */
390 /* - voltage maximum transition (lowest to highest value) */
391 /* - until voltage reaches final value +-1LSB */
392 /* - DAC channel output buffer enabled */
393 /* - load impedance of 5kOhm min, 50pF max */
394 /* Literal set to maximum value (refer to device datasheet, */
395 /* parameter "tSETTLING"). */
396 /* Unit: us */
397 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
398 /**
399 * @}
400 */
401
402 /**
403 * @}
404 */
405
406 /* Exported macro ------------------------------------------------------------*/
407 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
408 * @{
409 */
410
411 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
412 * @{
413 */
414
415 /**
416 * @brief Write a value in DAC register
417 * @param __INSTANCE__ DAC Instance
418 * @param __REG__ Register to be written
419 * @param __VALUE__ Value to be written in the register
420 * @retval None
421 */
422 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
423
424 /**
425 * @brief Read a value in DAC register
426 * @param __INSTANCE__ DAC Instance
427 * @param __REG__ Register to be read
428 * @retval Register value
429 */
430 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
431
432 /**
433 * @}
434 */
435
436 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
437 * @{
438 */
439
440 /**
441 * @brief Helper macro to get DAC channel number in decimal format
442 * from literals LL_DAC_CHANNEL_x.
443 * Example:
444 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
445 * will return decimal number "1".
446 * @note The input can be a value from functions where a channel
447 * number is returned.
448 * @param __CHANNEL__ This parameter can be one of the following values:
449 * @arg @ref LL_DAC_CHANNEL_1
450 * @arg @ref LL_DAC_CHANNEL_2 (1)
451 *
452 * (1) On this STM32 series, parameter not available on all devices.
453 * Refer to device datasheet for channels availability.
454 * @retval 1...2 (value "2" depending on DAC channel 2 availability)
455 */
456 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
457 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
458
459 /**
460 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
461 * from number in decimal format.
462 * Example:
463 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
464 * will return a data equivalent to "LL_DAC_CHANNEL_1".
465 * @note If the input parameter does not correspond to a DAC channel,
466 * this macro returns value '0'.
467 * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
468 * @retval Returned value can be one of the following values:
469 * @arg @ref LL_DAC_CHANNEL_1
470 * @arg @ref LL_DAC_CHANNEL_2 (1)
471 *
472 * (1) On this STM32 series, parameter not available on all devices.
473 * Refer to device datasheet for channels availability.
474 */
475 #if defined(DAC_CHANNEL2_SUPPORT)
476 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
477 (((__DECIMAL_NB__) == 1U) \
478 ? ( \
479 LL_DAC_CHANNEL_1 \
480 ) \
481 : \
482 (((__DECIMAL_NB__) == 2U) \
483 ? ( \
484 LL_DAC_CHANNEL_2 \
485 ) \
486 : \
487 ( \
488 0 \
489 ) \
490 ) \
491 )
492 #else
493 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
494 (((__DECIMAL_NB__) == 1U) \
495 ? ( \
496 LL_DAC_CHANNEL_1 \
497 ) \
498 : \
499 ( \
500 0 \
501 ) \
502 )
503 #endif /* DAC_CHANNEL2_SUPPORT */
504
505 /**
506 * @brief Helper macro to define the DAC conversion data full-scale digital
507 * value corresponding to the selected DAC resolution.
508 * @note DAC conversion data full-scale corresponds to voltage range
509 * determined by analog voltage references Vref+ and Vref-
510 * (refer to reference manual).
511 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
512 * @arg @ref LL_DAC_RESOLUTION_12B
513 * @arg @ref LL_DAC_RESOLUTION_8B
514 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
515 */
516 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
517 ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
518
519 /**
520 * @brief Helper macro to calculate the DAC conversion data (unit: digital
521 * value) corresponding to a voltage (unit: mVolt).
522 * @note This helper macro is intended to provide input data in voltage
523 * rather than digital value,
524 * to be used with LL DAC functions such as
525 * @ref LL_DAC_ConvertData12RightAligned().
526 * @note Analog reference voltage (Vref+) must be either known from
527 * user board environment or can be calculated using ADC measurement
528 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
529 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
530 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
531 * (unit: mVolt).
532 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
533 * @arg @ref LL_DAC_RESOLUTION_12B
534 * @arg @ref LL_DAC_RESOLUTION_8B
535 * @retval DAC conversion data (unit: digital value)
536 */
537 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
538 __DAC_VOLTAGE__,\
539 __DAC_RESOLUTION__) \
540 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
541 / (__VREFANALOG_VOLTAGE__) \
542 )
543
544 /**
545 * @}
546 */
547
548 /**
549 * @}
550 */
551
552
553 /* Exported functions --------------------------------------------------------*/
554 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
555 * @{
556 */
557 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
558 * @{
559 */
560
561 /**
562 * @brief Set the conversion trigger source for the selected DAC channel.
563 * @note For conversion trigger source to be effective, DAC trigger
564 * must be enabled using function @ref LL_DAC_EnableTrigger().
565 * @note To set conversion trigger source, DAC channel must be disabled.
566 * Otherwise, the setting is discarded.
567 * @note Availability of parameters of trigger sources from timer
568 * depends on timers availability on the selected device.
569 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
570 * CR TSEL2 LL_DAC_SetTriggerSource
571 * @param DACx DAC instance
572 * @param DAC_Channel This parameter can be one of the following values:
573 * @arg @ref LL_DAC_CHANNEL_1
574 * @arg @ref LL_DAC_CHANNEL_2 (1)
575 *
576 * (1) On this STM32 series, parameter not available on all devices.
577 * Refer to device datasheet for channels availability.
578 * @param TriggerSource This parameter can be one of the following values:
579 * @arg @ref LL_DAC_TRIG_SOFTWARE
580 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
581 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO (1)
582 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO (1)
583 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO (1)
584 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
585 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO (1)
586 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (1)
587 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO (1)
588 * @arg @ref LL_DAC_TRIG_EXT_TIM18_TRGO (1)
589 * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG1 (1)
590 * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG2 (1)(2)
591 * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG3 (1) (3)
592 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
593 *
594 * (1) On STM32F3, parameter not available on all devices
595 * (2) On STM32F3, parameter not available on all DAC instances: DAC1 (for DAC instances DACx available on the selected device).\n
596 * (3) On STM32F3, parameter not available on all DAC instances: DAC2 (for DAC instances DACx available on the selected device).
597 * @retval None
598 */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)599 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
600 {
601 MODIFY_REG(DACx->CR,
602 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
603 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
604 }
605
606 /**
607 * @brief Get the conversion trigger source for the selected DAC channel.
608 * @note For conversion trigger source to be effective, DAC trigger
609 * must be enabled using function @ref LL_DAC_EnableTrigger().
610 * @note Availability of parameters of trigger sources from timer
611 * depends on timers availability on the selected device.
612 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
613 * CR TSEL2 LL_DAC_GetTriggerSource
614 * @param DACx DAC instance
615 * @param DAC_Channel This parameter can be one of the following values:
616 * @arg @ref LL_DAC_CHANNEL_1
617 * @arg @ref LL_DAC_CHANNEL_2 (1)
618 *
619 * (1) On this STM32 series, parameter not available on all devices.
620 * Refer to device datasheet for channels availability.
621 * @retval Returned value can be one of the following values:
622 * @arg @ref LL_DAC_TRIG_SOFTWARE
623 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
624 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO (1)
625 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO (1)
626 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO (1)
627 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
628 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO (1)
629 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (1)
630 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO (1)
631 * @arg @ref LL_DAC_TRIG_EXT_TIM18_TRGO (1)
632 * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG1 (1)
633 * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG2 (1)(2)
634 * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG3 (1) (3)
635 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
636 *
637 * (1) On STM32F3, parameter not available on all devices
638 * (2) On STM32F3, parameter not available on all DAC instances: DAC1 (for DAC instances DACx available on the selected device).\n
639 * (3) On STM32F3, parameter not available on all DAC instances: DAC2 (for DAC instances DACx available on the selected device).
640 */
LL_DAC_GetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel)641 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
642 {
643 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
644 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
645 );
646 }
647
648 /**
649 * @brief Set the waveform automatic generation mode
650 * for the selected DAC channel.
651 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
652 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
653 * @param DACx DAC instance
654 * @param DAC_Channel This parameter can be one of the following values:
655 * @arg @ref LL_DAC_CHANNEL_1
656 * @arg @ref LL_DAC_CHANNEL_2 (1)
657 *
658 * (1) On this STM32 series, parameter not available on all devices.
659 * Refer to device datasheet for channels availability.
660 * @param WaveAutoGeneration This parameter can be one of the following values:
661 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
662 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
663 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
664 * @retval None
665 */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)666 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
667 {
668 MODIFY_REG(DACx->CR,
669 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
670 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
671 }
672
673 /**
674 * @brief Get the waveform automatic generation mode
675 * for the selected DAC channel.
676 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
677 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
678 * @param DACx DAC instance
679 * @param DAC_Channel This parameter can be one of the following values:
680 * @arg @ref LL_DAC_CHANNEL_1
681 * @arg @ref LL_DAC_CHANNEL_2 (1)
682 *
683 * (1) On this STM32 series, parameter not available on all devices.
684 * Refer to device datasheet for channels availability.
685 * @retval Returned value can be one of the following values:
686 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
687 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
688 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
689 */
LL_DAC_GetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel)690 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
691 {
692 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
693 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
694 );
695 }
696
697 /**
698 * @brief Set the noise waveform generation for the selected DAC channel:
699 * Noise mode and parameters LFSR (linear feedback shift register).
700 * @note For wave generation to be effective, DAC channel
701 * wave generation mode must be enabled using
702 * function @ref LL_DAC_SetWaveAutoGeneration().
703 * @note This setting can be set when the selected DAC channel is disabled
704 * (otherwise, the setting operation is ignored).
705 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
706 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
707 * @param DACx DAC instance
708 * @param DAC_Channel This parameter can be one of the following values:
709 * @arg @ref LL_DAC_CHANNEL_1
710 * @arg @ref LL_DAC_CHANNEL_2 (1)
711 *
712 * (1) On this STM32 series, parameter not available on all devices.
713 * Refer to device datasheet for channels availability.
714 * @param NoiseLFSRMask This parameter can be one of the following values:
715 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
716 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
717 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
718 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
719 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
720 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
721 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
722 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
723 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
724 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
725 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
726 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
727 * @retval None
728 */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)729 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
730 {
731 MODIFY_REG(DACx->CR,
732 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
733 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
734 }
735
736 /**
737 * @brief Set the noise waveform generation for the selected DAC channel:
738 * Noise mode and parameters LFSR (linear feedback shift register).
739 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
740 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
741 * @param DACx DAC instance
742 * @param DAC_Channel This parameter can be one of the following values:
743 * @arg @ref LL_DAC_CHANNEL_1
744 * @arg @ref LL_DAC_CHANNEL_2 (1)
745 *
746 * (1) On this STM32 series, parameter not available on all devices.
747 * Refer to device datasheet for channels availability.
748 * @retval Returned value can be one of the following values:
749 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
750 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
751 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
752 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
753 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
754 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
755 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
756 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
757 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
758 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
759 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
760 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
761 */
LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel)762 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
763 {
764 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
765 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
766 );
767 }
768
769 /**
770 * @brief Set the triangle waveform generation for the selected DAC channel:
771 * triangle mode and amplitude.
772 * @note For wave generation to be effective, DAC channel
773 * wave generation mode must be enabled using
774 * function @ref LL_DAC_SetWaveAutoGeneration().
775 * @note This setting can be set when the selected DAC channel is disabled
776 * (otherwise, the setting operation is ignored).
777 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
778 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
779 * @param DACx DAC instance
780 * @param DAC_Channel This parameter can be one of the following values:
781 * @arg @ref LL_DAC_CHANNEL_1
782 * @arg @ref LL_DAC_CHANNEL_2 (1)
783 *
784 * (1) On this STM32 series, parameter not available on all devices.
785 * Refer to device datasheet for channels availability.
786 * @param TriangleAmplitude This parameter can be one of the following values:
787 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
788 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
789 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
790 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
791 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
792 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
793 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
794 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
795 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
796 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
797 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
798 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
799 * @retval None
800 */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)801 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
802 {
803 MODIFY_REG(DACx->CR,
804 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
805 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
806 }
807
808 /**
809 * @brief Set the triangle waveform generation for the selected DAC channel:
810 * triangle mode and amplitude.
811 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
812 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
813 * @param DACx DAC instance
814 * @param DAC_Channel This parameter can be one of the following values:
815 * @arg @ref LL_DAC_CHANNEL_1
816 * @arg @ref LL_DAC_CHANNEL_2 (1)
817 *
818 * (1) On this STM32 series, parameter not available on all devices.
819 * Refer to device datasheet for channels availability.
820 * @retval Returned value can be one of the following values:
821 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
822 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
823 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
824 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
825 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
826 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
827 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
828 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
829 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
830 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
831 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
832 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
833 */
LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel)834 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
835 {
836 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
837 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
838 );
839 }
840
841 /**
842 * @brief Set the output buffer for the selected DAC channel.
843 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
844 * CR BOFF2 LL_DAC_SetOutputBuffer
845 * @param DACx DAC instance
846 * @param DAC_Channel This parameter can be one of the following values:
847 * @arg @ref LL_DAC_CHANNEL_1
848 * @arg @ref LL_DAC_CHANNEL_2 (1)
849 *
850 * (1) On this STM32 series, parameter not available on all devices.
851 * Refer to device datasheet for channels availability.
852 * @param OutputBuffer This parameter can be one of the following values:
853 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
854 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
855 * @arg @ref LL_DAC_OUTPUT_SWITCH_DISABLE (1)
856 * @arg @ref LL_DAC_OUTPUT_SWITCH_ENABLE (1)
857 *
858 * (1) Feature specific to STM32F303x6/8 and STM32F328:
859 * On DAC1 channel 2, output buffer is replaced by a switch
860 * to connect DAC channel output to pin PA5.
861 * On DAC2 channel 1, output buffer is replaced by a switch
862 * to connect DAC channel output to pin PA6.
863 * @retval None
864 */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)865 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
866 {
867 MODIFY_REG(DACx->CR,
868 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
869 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
870 }
871
872 /**
873 * @brief Get the output buffer state for the selected DAC channel.
874 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
875 * CR BOFF2 LL_DAC_GetOutputBuffer
876 * @param DACx DAC instance
877 * @param DAC_Channel This parameter can be one of the following values:
878 * @arg @ref LL_DAC_CHANNEL_1
879 * @arg @ref LL_DAC_CHANNEL_2 (1)
880 *
881 * (1) On this STM32 series, parameter not available on all devices.
882 * Refer to device datasheet for channels availability.
883 * @retval Returned value can be one of the following values:
884 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
885 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
886 * @arg @ref LL_DAC_OUTPUT_SWITCH_DISABLE (1)
887 * @arg @ref LL_DAC_OUTPUT_SWITCH_ENABLE (1)
888 *
889 * (1) Feature specific to STM32F303x6/8 and STM32F328:
890 * On DAC1 channel 2, output buffer is replaced by a switch
891 * to connect DAC channel output to pin PA5.
892 * On DAC2 channel 1, output buffer is replaced by a switch
893 * to connect DAC channel output to pin PA6.
894 */
LL_DAC_GetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel)895 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
896 {
897 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
898 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
899 );
900 }
901
902 /**
903 * @}
904 */
905
906 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
907 * @{
908 */
909
910 /**
911 * @brief Enable DAC DMA transfer request of the selected channel.
912 * @note To configure DMA source address (peripheral address),
913 * use function @ref LL_DAC_DMA_GetRegAddr().
914 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
915 * CR DMAEN2 LL_DAC_EnableDMAReq
916 * @param DACx DAC instance
917 * @param DAC_Channel This parameter can be one of the following values:
918 * @arg @ref LL_DAC_CHANNEL_1
919 * @arg @ref LL_DAC_CHANNEL_2 (1)
920 *
921 * (1) On this STM32 series, parameter not available on all devices.
922 * Refer to device datasheet for channels availability.
923 * @retval None
924 */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)925 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
926 {
927 SET_BIT(DACx->CR,
928 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
929 }
930
931 /**
932 * @brief Disable DAC DMA transfer request of the selected channel.
933 * @note To configure DMA source address (peripheral address),
934 * use function @ref LL_DAC_DMA_GetRegAddr().
935 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
936 * CR DMAEN2 LL_DAC_DisableDMAReq
937 * @param DACx DAC instance
938 * @param DAC_Channel This parameter can be one of the following values:
939 * @arg @ref LL_DAC_CHANNEL_1
940 * @arg @ref LL_DAC_CHANNEL_2 (1)
941 *
942 * (1) On this STM32 series, parameter not available on all devices.
943 * Refer to device datasheet for channels availability.
944 * @retval None
945 */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)946 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
947 {
948 CLEAR_BIT(DACx->CR,
949 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
950 }
951
952 /**
953 * @brief Get DAC DMA transfer request state of the selected channel.
954 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
955 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
956 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
957 * @param DACx DAC instance
958 * @param DAC_Channel This parameter can be one of the following values:
959 * @arg @ref LL_DAC_CHANNEL_1
960 * @arg @ref LL_DAC_CHANNEL_2 (1)
961 *
962 * (1) On this STM32 series, parameter not available on all devices.
963 * Refer to device datasheet for channels availability.
964 * @retval State of bit (1 or 0).
965 */
LL_DAC_IsDMAReqEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)966 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
967 {
968 return (READ_BIT(DACx->CR,
969 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
970 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
971 }
972
973 /**
974 * @brief Function to help to configure DMA transfer to DAC: retrieve the
975 * DAC register address from DAC instance and a list of DAC registers
976 * intended to be used (most commonly) with DMA transfer.
977 * @note These DAC registers are data holding registers:
978 * when DAC conversion is requested, DAC generates a DMA transfer
979 * request to have data available in DAC data holding registers.
980 * @note This macro is intended to be used with LL DMA driver, refer to
981 * function "LL_DMA_ConfigAddresses()".
982 * Example:
983 * LL_DMA_ConfigAddresses(DMA1,
984 * LL_DMA_CHANNEL_1,
985 * (uint32_t)&< array or variable >,
986 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
987 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
988 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
989 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
990 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
991 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
992 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
993 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
994 * @param DACx DAC instance
995 * @param DAC_Channel This parameter can be one of the following values:
996 * @arg @ref LL_DAC_CHANNEL_1
997 * @arg @ref LL_DAC_CHANNEL_2 (1)
998 *
999 * (1) On this STM32 series, parameter not available on all devices.
1000 * Refer to device datasheet for channels availability.
1001 * @param Register This parameter can be one of the following values:
1002 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
1003 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
1004 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
1005 * @retval DAC register address
1006 */
LL_DAC_DMA_GetRegAddr(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)1007 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
1008 {
1009 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
1010 /* DAC channel selected. */
1011 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
1012 }
1013 /**
1014 * @}
1015 */
1016
1017 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
1018 * @{
1019 */
1020
1021 /**
1022 * @brief Enable DAC selected channel.
1023 * @rmtoll CR EN1 LL_DAC_Enable\n
1024 * CR EN2 LL_DAC_Enable
1025 * @note After enable from off state, DAC channel requires a delay
1026 * for output voltage to reach accuracy +/- 1 LSB.
1027 * Refer to device datasheet, parameter "tWAKEUP".
1028 * @param DACx DAC instance
1029 * @param DAC_Channel This parameter can be one of the following values:
1030 * @arg @ref LL_DAC_CHANNEL_1
1031 * @arg @ref LL_DAC_CHANNEL_2 (1)
1032 *
1033 * (1) On this STM32 series, parameter not available on all devices.
1034 * Refer to device datasheet for channels availability.
1035 * @retval None
1036 */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1037 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1038 {
1039 SET_BIT(DACx->CR,
1040 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1041 }
1042
1043 /**
1044 * @brief Disable DAC selected channel.
1045 * @rmtoll CR EN1 LL_DAC_Disable\n
1046 * CR EN2 LL_DAC_Disable
1047 * @param DACx DAC instance
1048 * @param DAC_Channel This parameter can be one of the following values:
1049 * @arg @ref LL_DAC_CHANNEL_1
1050 * @arg @ref LL_DAC_CHANNEL_2 (1)
1051 *
1052 * (1) On this STM32 series, parameter not available on all devices.
1053 * Refer to device datasheet for channels availability.
1054 * @retval None
1055 */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1056 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1057 {
1058 CLEAR_BIT(DACx->CR,
1059 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1060 }
1061
1062 /**
1063 * @brief Get DAC enable state of the selected channel.
1064 * (0: DAC channel is disabled, 1: DAC channel is enabled)
1065 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
1066 * CR EN2 LL_DAC_IsEnabled
1067 * @param DACx DAC instance
1068 * @param DAC_Channel This parameter can be one of the following values:
1069 * @arg @ref LL_DAC_CHANNEL_1
1070 * @arg @ref LL_DAC_CHANNEL_2 (1)
1071 *
1072 * (1) On this STM32 series, parameter not available on all devices.
1073 * Refer to device datasheet for channels availability.
1074 * @retval State of bit (1 or 0).
1075 */
LL_DAC_IsEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)1076 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1077 {
1078 return (READ_BIT(DACx->CR,
1079 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1080 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
1081 }
1082
1083 /**
1084 * @brief Enable DAC trigger of the selected channel.
1085 * @note - If DAC trigger is disabled, DAC conversion is performed
1086 * automatically once the data holding register is updated,
1087 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1088 * @ref LL_DAC_ConvertData12RightAligned(), ...
1089 * - If DAC trigger is enabled, DAC conversion is performed
1090 * only when a hardware of software trigger event is occurring.
1091 * Select trigger source using
1092 * function @ref LL_DAC_SetTriggerSource().
1093 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
1094 * CR TEN2 LL_DAC_EnableTrigger
1095 * @param DACx DAC instance
1096 * @param DAC_Channel This parameter can be one of the following values:
1097 * @arg @ref LL_DAC_CHANNEL_1
1098 * @arg @ref LL_DAC_CHANNEL_2 (1)
1099 *
1100 * (1) On this STM32 series, parameter not available on all devices.
1101 * Refer to device datasheet for channels availability.
1102 * @retval None
1103 */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1104 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1105 {
1106 SET_BIT(DACx->CR,
1107 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1108 }
1109
1110 /**
1111 * @brief Disable DAC trigger of the selected channel.
1112 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
1113 * CR TEN2 LL_DAC_DisableTrigger
1114 * @param DACx DAC instance
1115 * @param DAC_Channel This parameter can be one of the following values:
1116 * @arg @ref LL_DAC_CHANNEL_1
1117 * @arg @ref LL_DAC_CHANNEL_2 (1)
1118 *
1119 * (1) On this STM32 series, parameter not available on all devices.
1120 * Refer to device datasheet for channels availability.
1121 * @retval None
1122 */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1123 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1124 {
1125 CLEAR_BIT(DACx->CR,
1126 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1127 }
1128
1129 /**
1130 * @brief Get DAC trigger state of the selected channel.
1131 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1132 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
1133 * CR TEN2 LL_DAC_IsTriggerEnabled
1134 * @param DACx DAC instance
1135 * @param DAC_Channel This parameter can be one of the following values:
1136 * @arg @ref LL_DAC_CHANNEL_1
1137 * @arg @ref LL_DAC_CHANNEL_2 (1)
1138 *
1139 * (1) On this STM32 series, parameter not available on all devices.
1140 * Refer to device datasheet for channels availability.
1141 * @retval State of bit (1 or 0).
1142 */
LL_DAC_IsTriggerEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)1143 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1144 {
1145 return (READ_BIT(DACx->CR,
1146 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1147 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
1148 }
1149
1150 /**
1151 * @brief Trig DAC conversion by software for the selected DAC channel.
1152 * @note Preliminarily, DAC trigger must be set to software trigger
1153 * using function @ref LL_DAC_SetTriggerSource()
1154 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
1155 * and DAC trigger must be enabled using
1156 * function @ref LL_DAC_EnableTrigger().
1157 * @note For devices featuring DAC with 2 channels: this function
1158 * can perform a SW start of both DAC channels simultaneously.
1159 * Two channels can be selected as parameter.
1160 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1161 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1162 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1163 * @param DACx DAC instance
1164 * @param DAC_Channel This parameter can a combination of the following values:
1165 * @arg @ref LL_DAC_CHANNEL_1
1166 * @arg @ref LL_DAC_CHANNEL_2 (1)
1167 *
1168 * (1) On this STM32 series, parameter not available on all devices.
1169 * Refer to device datasheet for channels availability.
1170 * @retval None
1171 */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)1172 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1173 {
1174 SET_BIT(DACx->SWTRIGR,
1175 (DAC_Channel & DAC_SWTR_CHX_MASK));
1176 }
1177
1178 /**
1179 * @brief Set the data to be loaded in the data holding register
1180 * in format 12 bits left alignment (LSB aligned on bit 0),
1181 * for the selected DAC channel.
1182 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1183 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1184 * @param DACx DAC instance
1185 * @param DAC_Channel This parameter can be one of the following values:
1186 * @arg @ref LL_DAC_CHANNEL_1
1187 * @arg @ref LL_DAC_CHANNEL_2 (1)
1188 *
1189 * (1) On this STM32 series, parameter not available on all devices.
1190 * Refer to device datasheet for channels availability.
1191 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1192 * @retval None
1193 */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1194 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1195 {
1196 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
1197
1198 MODIFY_REG(*preg,
1199 DAC_DHR12R1_DACC1DHR,
1200 Data);
1201 }
1202
1203 /**
1204 * @brief Set the data to be loaded in the data holding register
1205 * in format 12 bits left alignment (MSB aligned on bit 15),
1206 * for the selected DAC channel.
1207 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1208 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1209 * @param DACx DAC instance
1210 * @param DAC_Channel This parameter can be one of the following values:
1211 * @arg @ref LL_DAC_CHANNEL_1
1212 * @arg @ref LL_DAC_CHANNEL_2 (1)
1213 *
1214 * (1) On this STM32 series, parameter not available on all devices.
1215 * Refer to device datasheet for channels availability.
1216 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1217 * @retval None
1218 */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1219 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1220 {
1221 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
1222
1223 MODIFY_REG(*preg,
1224 DAC_DHR12L1_DACC1DHR,
1225 Data);
1226 }
1227
1228 /**
1229 * @brief Set the data to be loaded in the data holding register
1230 * in format 8 bits left alignment (LSB aligned on bit 0),
1231 * for the selected DAC channel.
1232 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1233 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1234 * @param DACx DAC instance
1235 * @param DAC_Channel This parameter can be one of the following values:
1236 * @arg @ref LL_DAC_CHANNEL_1
1237 * @arg @ref LL_DAC_CHANNEL_2 (1)
1238 *
1239 * (1) On this STM32 series, parameter not available on all devices.
1240 * Refer to device datasheet for channels availability.
1241 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1242 * @retval None
1243 */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1244 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1245 {
1246 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
1247
1248 MODIFY_REG(*preg,
1249 DAC_DHR8R1_DACC1DHR,
1250 Data);
1251 }
1252
1253 #if defined(DAC_CHANNEL2_SUPPORT)
1254 /**
1255 * @brief Set the data to be loaded in the data holding register
1256 * in format 12 bits left alignment (LSB aligned on bit 0),
1257 * for both DAC channels.
1258 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1259 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1260 * @param DACx DAC instance
1261 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1262 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1263 * @retval None
1264 */
LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1265 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1266 {
1267 MODIFY_REG(DACx->DHR12RD,
1268 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1269 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1270 }
1271
1272 /**
1273 * @brief Set the data to be loaded in the data holding register
1274 * in format 12 bits left alignment (MSB aligned on bit 15),
1275 * for both DAC channels.
1276 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1277 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1278 * @param DACx DAC instance
1279 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1280 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1281 * @retval None
1282 */
LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1283 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1284 {
1285 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1286 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1287 /* the 4 LSB must be taken into account for the shift value. */
1288 MODIFY_REG(DACx->DHR12LD,
1289 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1290 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1291 }
1292
1293 /**
1294 * @brief Set the data to be loaded in the data holding register
1295 * in format 8 bits left alignment (LSB aligned on bit 0),
1296 * for both DAC channels.
1297 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1298 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1299 * @param DACx DAC instance
1300 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1301 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1302 * @retval None
1303 */
LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1304 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1305 {
1306 MODIFY_REG(DACx->DHR8RD,
1307 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1308 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1309 }
1310
1311 #endif /* DAC_CHANNEL2_SUPPORT */
1312 /**
1313 * @brief Retrieve output data currently generated for the selected DAC channel.
1314 * @note Whatever alignment and resolution settings
1315 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1316 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1317 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1318 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1319 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1320 * @param DACx DAC instance
1321 * @param DAC_Channel This parameter can be one of the following values:
1322 * @arg @ref LL_DAC_CHANNEL_1
1323 * @arg @ref LL_DAC_CHANNEL_2 (1)
1324 *
1325 * (1) On this STM32 series, parameter not available on all devices.
1326 * Refer to device datasheet for channels availability.
1327 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1328 */
LL_DAC_RetrieveOutputData(DAC_TypeDef * DACx,uint32_t DAC_Channel)1329 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1330 {
1331 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
1332
1333 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1334 }
1335
1336 /**
1337 * @}
1338 */
1339
1340 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1341 * @{
1342 */
1343 /**
1344 * @brief Get DAC underrun flag for DAC channel 1
1345 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1346 * @param DACx DAC instance
1347 * @retval State of bit (1 or 0).
1348 */
LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef * DACx)1349 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
1350 {
1351 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
1352 }
1353
1354 #if defined(DAC_CHANNEL2_SUPPORT)
1355 /**
1356 * @brief Get DAC underrun flag for DAC channel 2
1357 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1358 * @param DACx DAC instance
1359 * @retval State of bit (1 or 0).
1360 */
LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef * DACx)1361 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
1362 {
1363 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
1364 }
1365 #endif /* DAC_CHANNEL2_SUPPORT */
1366
1367 /**
1368 * @brief Clear DAC underrun flag for DAC channel 1
1369 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1370 * @param DACx DAC instance
1371 * @retval None
1372 */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)1373 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1374 {
1375 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1376 }
1377
1378 #if defined(DAC_CHANNEL2_SUPPORT)
1379 /**
1380 * @brief Clear DAC underrun flag for DAC channel 2
1381 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1382 * @param DACx DAC instance
1383 * @retval None
1384 */
LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef * DACx)1385 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1386 {
1387 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1388 }
1389 #endif /* DAC_CHANNEL2_SUPPORT */
1390
1391 /**
1392 * @}
1393 */
1394
1395 /** @defgroup DAC_LL_EF_IT_Management IT management
1396 * @{
1397 */
1398
1399 /**
1400 * @brief Enable DMA underrun interrupt for DAC channel 1
1401 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1402 * @param DACx DAC instance
1403 * @retval None
1404 */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)1405 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1406 {
1407 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1408 }
1409
1410 #if defined(DAC_CHANNEL2_SUPPORT)
1411 /**
1412 * @brief Enable DMA underrun interrupt for DAC channel 2
1413 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1414 * @param DACx DAC instance
1415 * @retval None
1416 */
LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef * DACx)1417 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1418 {
1419 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1420 }
1421 #endif /* DAC_CHANNEL2_SUPPORT */
1422
1423 /**
1424 * @brief Disable DMA underrun interrupt for DAC channel 1
1425 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1426 * @param DACx DAC instance
1427 * @retval None
1428 */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)1429 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1430 {
1431 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1432 }
1433
1434 #if defined(DAC_CHANNEL2_SUPPORT)
1435 /**
1436 * @brief Disable DMA underrun interrupt for DAC channel 2
1437 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1438 * @param DACx DAC instance
1439 * @retval None
1440 */
LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef * DACx)1441 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1442 {
1443 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1444 }
1445 #endif /* DAC_CHANNEL2_SUPPORT */
1446
1447 /**
1448 * @brief Get DMA underrun interrupt for DAC channel 1
1449 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1450 * @param DACx DAC instance
1451 * @retval State of bit (1 or 0).
1452 */
LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef * DACx)1453 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
1454 {
1455 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
1456 }
1457
1458 #if defined(DAC_CHANNEL2_SUPPORT)
1459 /**
1460 * @brief Get DMA underrun interrupt for DAC channel 2
1461 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1462 * @param DACx DAC instance
1463 * @retval State of bit (1 or 0).
1464 */
LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef * DACx)1465 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
1466 {
1467 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
1468 }
1469 #endif /* DAC_CHANNEL2_SUPPORT */
1470
1471 /**
1472 * @}
1473 */
1474
1475 #if defined(USE_FULL_LL_DRIVER)
1476 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1477 * @{
1478 */
1479
1480 ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
1481 ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
1482 void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
1483
1484 /**
1485 * @}
1486 */
1487 #endif /* USE_FULL_LL_DRIVER */
1488
1489 /**
1490 * @}
1491 */
1492
1493 /**
1494 * @}
1495 */
1496
1497 #endif /* DAC1 || DAC2 */
1498
1499 /**
1500 * @}
1501 */
1502
1503 #ifdef __cplusplus
1504 }
1505 #endif
1506
1507 #endif /* __STM32F3xx_LL_DAC_H */
1508
1509
