1 /*
2  * Copyright (c) 2019 Linaro Limited
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 /**
8  * @file
9  * @brief System/hardware module for STM32H7 CM7 processor
10  */
11 
12 #include <zephyr/kernel.h>
13 #include <zephyr/device.h>
14 #include <zephyr/init.h>
15 #include <zephyr/cache.h>
16 #include <soc.h>
17 #include <stm32_ll_bus.h>
18 #include <stm32_ll_pwr.h>
19 #include <stm32_ll_rcc.h>
20 #include <stm32_ll_system.h>
21 #include "stm32_hsem.h"
22 
23 #include <cmsis_core.h>
24 
25 #if defined(CONFIG_STM32H7_DUAL_CORE)
stm32h7_m4_wakeup(void)26 static int stm32h7_m4_wakeup(void)
27 {
28 
29 	/* HW semaphore and SysCfg Clock enable */
30 	LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_HSEM);
31 	LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_SYSCFG);
32 
33 	if (READ_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4)) {
34 		/* Cortex-M4 is waiting for end of system initialization made by
35 		 * Cortex-M7. This initialization is now finished,
36 		 * then Cortex-M7 takes HSEM so that CM4 can continue running.
37 		 */
38 		LL_HSEM_1StepLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID);
39 	} else if (IS_ENABLED(CONFIG_STM32H7_BOOT_M4_AT_INIT)) {
40 		/* CM4 is not started at boot, start it now */
41 		LL_RCC_ForceCM4Boot();
42 	}
43 
44 	return 0;
45 }
46 #endif /* CONFIG_STM32H7_DUAL_CORE */
47 
48 /**
49  * @brief Perform basic hardware initialization at boot.
50  *
51  * This needs to be run from the very beginning.
52  */
soc_early_init_hook(void)53 void soc_early_init_hook(void)
54 {
55 	sys_cache_instr_enable();
56 	sys_cache_data_enable();
57 
58 	/* Update CMSIS SystemCoreClock variable (HCLK) */
59 	/* At reset, system core clock is set to 64 MHz from HSI */
60 	SystemCoreClock = 64000000;
61 
62 	/* Power Configuration */
63 #if !defined(SMPS) && \
64 		(defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS) || \
65 		defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO) || \
66 		defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO) || \
67 		defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || \
68 		defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || \
69 		defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT) || \
70 		defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT))
71 #error Unsupported configuration: Selected SoC do not support SMPS
72 #endif
73 #if defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS)
74 	LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY);
75 #elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO)
76 	LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_LDO);
77 #elif defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO)
78 	LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_LDO);
79 #elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO)
80 	LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO);
81 #elif defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO)
82 	LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO);
83 #elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT)
84 	LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT);
85 #elif defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT)
86 	LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT);
87 #elif defined(CONFIG_POWER_SUPPLY_EXTERNAL_SOURCE)
88 	LL_PWR_ConfigSupply(LL_PWR_EXTERNAL_SOURCE_SUPPLY);
89 #else
90 	LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
91 #endif
92 	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
93 	while (LL_PWR_IsActiveFlag_VOS() == 0) {
94 	}
95 
96 	/* Errata ES0392 Rev 8:
97 	 * 2.2.9: Reading from AXI SRAM may lead to data read corruption
98 	 * Workaround: Set the READ_ISS_OVERRIDE bit in the AXI_TARG7_FN_MOD
99 	 * register.
100 	 * Applicable only to RevY (REV_ID 0x1003)
101 	 */
102 	if (LL_DBGMCU_GetRevisionID() == 0x1003) {
103 		MODIFY_REG(GPV->AXI_TARG7_FN_MOD, 0x1, 0x1);
104 	}
105 }
106 
107 #if defined(CONFIG_STM32H7_DUAL_CORE)
108 /* Unlock M4 once system configuration has been done */
109 SYS_INIT(stm32h7_m4_wakeup, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY);
110 #endif /* CONFIG_STM32H7_DUAL_CORE */
111