Searched refs:TIM4_OR1_OCREF_CLR_Pos (Results 1 – 3 of 3) sorted by relevance
7859 #define TIM4_OR1_OCREF_CLR_Pos (0U) macro7860 #define TIM4_OR1_OCREF_CLR_Msk (0x3UL << TIM4_OR1_OCREF_CLR_Pos) /*!< 0x00000003 */7862 #define TIM4_OR1_OCREF_CLR_0 (0x1UL << TIM4_OR1_OCREF_CLR_Pos) /*!< 0x00000001 */7863 #define TIM4_OR1_OCREF_CLR_1 (0x2UL << TIM4_OR1_OCREF_CLR_Pos) /*!< 0x00000002 */
9092 #define TIM4_OR1_OCREF_CLR_Pos (0U) macro9093 #define TIM4_OR1_OCREF_CLR_Msk (0x3UL << TIM4_OR1_OCREF_CLR_Pos) /*!< 0x00000003 */9095 #define TIM4_OR1_OCREF_CLR_0 (0x1UL << TIM4_OR1_OCREF_CLR_Pos) /*!< 0x00000001 */9096 #define TIM4_OR1_OCREF_CLR_1 (0x2UL << TIM4_OR1_OCREF_CLR_Pos) /*!< 0x00000002 */
9396 #define TIM4_OR1_OCREF_CLR_Pos (0U) macro9397 #define TIM4_OR1_OCREF_CLR_Msk (0x3UL << TIM4_OR1_OCREF_CLR_Pos) /*!< 0x00000003 */9399 #define TIM4_OR1_OCREF_CLR_0 (0x1UL << TIM4_OR1_OCREF_CLR_Pos) /*!< 0x00000001 */9400 #define TIM4_OR1_OCREF_CLR_1 (0x2UL << TIM4_OR1_OCREF_CLR_Pos) /*!< 0x00000002 */
